X86 Target
Instructions
ADC16i16
adc{w} {src, %ax|ax, src}
ADC16mi
adc{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ADC16mi8
adc{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ADC16mr
adc{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ADC32i32
adc{l} {src, %eax|eax, src}
ADC32mi
adc{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ADC32mi8
adc{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ADC32mr
adc{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ADC64i32
adc{q} {src, %rax|rax, src}
ADC64mr
adc{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ADC8i8
adc{b} {src, %al|al, src}
ADC8mi
adc{b} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ADC8mr
adc{b} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ADCX32rm
adcx{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
ADCX32rr
adcx{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ADCX64rm
adcx{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
ADCX64rr
adcx{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ADD16i16
add{w} {src, %ax|ax, src}
ADD16mi
add{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ADD16mi8
add{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ADD16mr
add{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ADD32i32
add{l} {src, %eax|eax, src}
ADD32mi
add{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ADD32mi8
add{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ADD32mr
add{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ADD64i32
add{q} {src, %rax|rax, src}
ADD64mr
add{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ADD8i8
add{b} {src, %al|al, src}
ADD8mi
add{b} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ADD8mr
add{b} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ADOX32rm
adox{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
ADOX32rr
adox{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ADOX64rm
adox{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
ADOX64rr
adox{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
AND16i16
and{w} {src, %ax|ax, src}
AND16mi
and{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
AND16mi8
and{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
AND16mr
and{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
AND32i32
and{l} {src, %eax|eax, src}
AND32mi
and{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
AND32mi8
and{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
AND32mr
and{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
AND64i32
and{q} {src, %rax|rax, src}
AND64mr
and{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
AND8i8
and{b} {src, %al|al, src}
AND8mi
and{b} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
AND8mr
and{b} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
BLSI32rm
blsi{l} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
BLSI32rr
blsi{l} {src1, dst|dst, src1}
BLSI64rm
blsi{q} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
BLSI64rr
blsi{q} {src1, dst|dst, src1}
BLSMSK32rm
blsmsk{l} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
BLSMSK32rr
blsmsk{l} {src1, dst|dst, src1}
BLSMSK64rm
blsmsk{q} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
BLSMSK64rr
blsmsk{q} {src1, dst|dst, src1}
BLSR32rm
blsr{l} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
BLSR32rr
blsr{l} {src1, dst|dst, src1}
BLSR64rm
blsr{q} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
BLSR64rr
blsr{q} {src1, dst|dst, src1}
BSF16rm
bsf{w} {src, dst|dst, src}
|
Note
|
Constraints: fallback = dst |
BSF16rr
bsf{w} {src, dst|dst, src}
|
Note
|
Constraints: fallback = dst |
BSF32rm
bsf{l} {src, dst|dst, src}
|
Note
|
Constraints: fallback = dst |
BSF32rr
bsf{l} {src, dst|dst, src}
|
Note
|
Constraints: fallback = dst |
BSF64rm
bsf{q} {src, dst|dst, src}
|
Note
|
Constraints: fallback = dst |
BSF64rr
bsf{q} {src, dst|dst, src}
|
Note
|
Constraints: fallback = dst |
BSR16rm
bsr{w} {src, dst|dst, src}
|
Note
|
Constraints: fallback = dst |
BSR16rr
bsr{w} {src, dst|dst, src}
|
Note
|
Constraints: fallback = dst |
BSR32rm
bsr{l} {src, dst|dst, src}
|
Note
|
Constraints: fallback = dst |
BSR32rr
bsr{l} {src, dst|dst, src}
|
Note
|
Constraints: fallback = dst |
BSR64rm
bsr{q} {src, dst|dst, src}
|
Note
|
Constraints: fallback = dst |
BSR64rr
bsr{q} {src, dst|dst, src}
|
Note
|
Constraints: fallback = dst |
BT16mi8
bt{w} {src2, src1|src1, src2}
BT16mr
bt{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
BT16ri8
bt{w} {src2, src1|src1, src2}
BT16rr
bt{w} {src2, src1|src1, src2}
BT32mi8
bt{l} {src2, src1|src1, src2}
BT32mr
bt{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
BT32ri8
bt{l} {src2, src1|src1, src2}
BT32rr
bt{l} {src2, src1|src1, src2}
BT64mr
bt{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
BT64ri8
bt{q} {src2, src1|src1, src2}
BT64rr
bt{q} {src2, src1|src1, src2}
BTC16mi8
btc{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
BTC16mr
btc{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
BTC16ri8
btc{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
BTC16rr
btc{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
BTC32mi8
btc{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
BTC32mr
btc{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
BTC32ri8
btc{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
BTC32rr
btc{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
BTC64mr
btc{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
BTC64ri8
btc{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
BTC64rr
btc{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
BTR16mi8
btr{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
BTR16mr
btr{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
BTR16ri8
btr{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
BTR16rr
btr{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
BTR32mi8
btr{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
BTR32mr
btr{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
BTR32ri8
btr{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
BTR32rr
btr{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
BTR64mr
btr{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
BTR64ri8
btr{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
BTR64rr
btr{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
BTS16mi8
bts{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
BTS16mr
bts{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
BTS16ri8
bts{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
BTS16rr
bts{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
BTS32mi8
bts{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
BTS32mr
bts{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
BTS32ri8
bts{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
BTS32rr
bts{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
BTS64mr
bts{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
BTS64ri8
bts{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
BTS64rr
bts{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
CBW
{cbtw|cbw}
CDQ
{cltd|cdq}
CLAC
clac
CLC
clc
CLD
cld
CLGI
clgi
CLI
cli
CLRSSBSY
clrssbsy src
CLTS
clts
CMC
cmc
CMP16i16
cmp{w} {src, %ax|ax, src}
|
Note
|
Properties: isCompare |
CMP16mi
cmp{w} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare, mayLoad |
CMP16mi8
cmp{w} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare, mayLoad |
CMP16mr
cmp{w} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare, mayLoad |
CMP16ri
cmp{w} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare |
CMP16ri8
cmp{w} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare |
CMP16rm
cmp{w} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare, mayLoad |
CMP16rr
cmp{w} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare |
CMP32i32
cmp{l} {src, %eax|eax, src}
|
Note
|
Properties: isCompare |
CMP32mi
cmp{l} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare, mayLoad |
CMP32mi8
cmp{l} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare, mayLoad |
CMP32mr
cmp{l} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare, mayLoad |
CMP32ri
cmp{l} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare |
CMP32ri8
cmp{l} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare |
CMP32rm
cmp{l} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare, mayLoad |
CMP32rr
cmp{l} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare |
CMP64i32
cmp{q} {src, %rax|rax, src}
|
Note
|
Properties: isCompare |
CMP64mr
cmp{q} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare, mayLoad |
CMP64ri32
cmp{q} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare |
CMP64ri8
cmp{q} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare |
CMP64rm
cmp{q} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare, mayLoad |
CMP64rr
cmp{q} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare |
CMP8i8
cmp{b} {src, %al|al, src}
|
Note
|
Properties: isCompare |
CMP8mi
cmp{b} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare, mayLoad |
CMP8mr
cmp{b} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare, mayLoad |
CMP8ri
cmp{b} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare |
CMP8rm
cmp{b} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare, mayLoad |
CMP8rr
cmp{b} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare |
CMPSB
cmpsb {dst, src|src, dst}
CMPSL
cmps{l|d} {dst, src|src, dst}
CMPSW
cmpsw {dst, src|src, dst}
CMPXCHG16rm
cmpxchg{w} {src, dst|dst, src}
|
Note
|
Properties: mayLoad, mayStore |
CMPXCHG16rr
cmpxchg{w} {src, dst|dst, src}
CMPXCHG32rm
cmpxchg{l} {src, dst|dst, src}
|
Note
|
Properties: mayLoad, mayStore |
CMPXCHG32rr
cmpxchg{l} {src, dst|dst, src}
CMPXCHG64rm
cmpxchg{q} {src, dst|dst, src}
|
Note
|
Properties: mayLoad, mayStore |
CMPXCHG64rr
cmpxchg{q} {src, dst|dst, src}
CMPXCHG8rm
cmpxchg{b} {src, dst|dst, src}
|
Note
|
Properties: mayLoad, mayStore |
CMPXCHG8rr
cmpxchg{b} {src, dst|dst, src}
CPUID
cpuid
CS_PREFIX
cs
CWD
{cwtd|cwd}
CWDE
{cwtl|cwde}
DATA16_PREFIX
data16
DIV16m
div{w} src1
|
Note
|
Properties: hasSideEffects, mayLoad |
DIV16r
div{w} src1
|
Note
|
Properties: hasSideEffects |
DIV32m
div{l} src1
|
Note
|
Properties: hasSideEffects, mayLoad |
DIV32r
div{l} src1
|
Note
|
Properties: hasSideEffects |
DIV64r
div{q} src1
|
Note
|
Properties: hasSideEffects |
DIV8m
div{b} src1
|
Note
|
Properties: hasSideEffects, mayLoad |
DIV8r
div{b} src1
|
Note
|
Properties: hasSideEffects |
DS_PREFIX
ds
ENDBR32
endbr32
ENDBR64
endbr64
ENTER
enter len, lvl
ES_PREFIX
es
F2XM1
f2xm1
|
Note
|
Properties: mayRaiseFPException |
FARCALL16m
lcall{w} {*}dst
|
Note
|
Properties: isCall, mayLoad |
FARCALL32m
{l}call{l} {*}dst
|
Note
|
Properties: isCall, mayLoad |
FARCALL64m
lcall{q} {*}dst
|
Note
|
Properties: isCall, mayLoad |
FARJMP16m
ljmp{w} {*}dst
|
Note
|
Properties: isBarrier, isBranch, isIndirectBranch, isTerminator, mayLoad |
FARJMP32m
{l}jmp{l} {*}dst
|
Note
|
Properties: isBarrier, isBranch, isIndirectBranch, isTerminator, mayLoad |
FCOMPP
fcompp
|
Note
|
Properties: mayRaiseFPException |
FCOS
fcos
|
Note
|
Properties: mayRaiseFPException |
FDECSTP
fdecstp
FEMMS
femms
|
Note
|
Properties: hasSideEffects, mayLoad, mayStore |
FINCSTP
fincstp
FLDCW16m
fldcw dst
|
Note
|
Properties: mayLoad |
FLDL2E
fldl2e
FLDL2T
fldl2t
FLDLG2
fldlg2
FLDLN2
fldln2
FLDPI
fldpi
FNCLEX
fnclex
FNINIT
fninit
FNOP
fnop
FNSTCW16m
fnstcw dst
FNSTSW16r
fnstsw {%ax|ax}
FPATAN
fpatan
|
Note
|
Properties: mayRaiseFPException |
FPREM
fprem
|
Note
|
Properties: mayRaiseFPException |
FPREM1
fprem1
|
Note
|
Properties: mayRaiseFPException |
FPTAN
fptan
|
Note
|
Properties: mayRaiseFPException |
FRNDINT
frndint
|
Note
|
Properties: mayRaiseFPException |
FSCALE
fscale
|
Note
|
Properties: mayRaiseFPException |
FSIN
fsin
|
Note
|
Properties: mayRaiseFPException |
FSINCOS
fsincos
|
Note
|
Properties: mayRaiseFPException |
FS_PREFIX
fs
FXTRACT
fxtract
|
Note
|
Properties: mayRaiseFPException |
FYL2X
fyl2x
|
Note
|
Properties: mayRaiseFPException |
FYL2XP1
fyl2xp1
|
Note
|
Properties: mayRaiseFPException |
GETSEC
getsec
GS_PREFIX
gs
HLT
hlt
|
Note
|
Properties: isTerminator |
IDIV16m
idiv{w} src1
|
Note
|
Properties: hasSideEffects, mayLoad |
IDIV16r
idiv{w} src1
|
Note
|
Properties: hasSideEffects |
IDIV32m
idiv{l} src1
|
Note
|
Properties: hasSideEffects, mayLoad |
IDIV32r
idiv{l} src1
|
Note
|
Properties: hasSideEffects |
IDIV64r
idiv{q} src1
|
Note
|
Properties: hasSideEffects |
IDIV8m
idiv{b} src1
|
Note
|
Properties: hasSideEffects, mayLoad |
IDIV8r
idiv{b} src1
|
Note
|
Properties: hasSideEffects |
IMUL16m
imul{w} src1
|
Note
|
Properties: mayLoad |
IMUL16r
imul{w} src1
IMUL16rmi
imul{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
IMUL16rmi8
imul{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
IMUL16rri
imul{w} {src2, src1, dst|dst, src1, src2}
IMUL16rri8
imul{w} {src2, src1, dst|dst, src1, src2}
IMUL32m
imul{l} src1
|
Note
|
Properties: mayLoad |
IMUL32r
imul{l} src1
IMUL32rmi
imul{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
IMUL32rmi8
imul{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
IMUL32rri
imul{l} {src2, src1, dst|dst, src1, src2}
IMUL32rri8
imul{l} {src2, src1, dst|dst, src1, src2}
IMUL64r
imul{q} src1
IMUL64rmi32
imul{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
IMUL64rmi8
imul{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
IMUL64rri32
imul{q} {src2, src1, dst|dst, src1, src2}
IMUL64rri8
imul{q} {src2, src1, dst|dst, src1, src2}
IMUL8m
imul{b} src1
|
Note
|
Properties: mayLoad |
IMUL8r
imul{b} src1
IN16ri
in{w} {port, %ax|ax, port}
IN16rr
in{w} {%dx, %ax|ax, dx}
IN32ri
in{l} {port, %eax|eax, port}
IN32rr
in{l} {%dx, %eax|eax, dx}
IN8ri
in{b} {port, %al|al, port}
IN8rr
in{b} {%dx, %al|al, dx}
INCSSPD
incsspd src
INCSSPQ
incsspq src
INSB
insb {%dx, dst|dst, dx}
INSL
ins{l|d} {%dx, dst|dst, dx}
INSW
insw {%dx, dst|dst, dx}
INT
int trap
INT3
int3
INVD
invd
INVLPG
invlpg addr
IRET16
iret{w}
|
Note
|
Properties: hasCtrlDep, isBarrier, isReturn, isTerminator |
IRET32
iret{l|d}
|
Note
|
Properties: hasCtrlDep, isBarrier, isReturn, isTerminator |
JECXZ
jecxz dst
|
Note
|
Properties: isBranch, isTerminator |
JMP_1
jmp dst
|
Note
|
Properties: isBarrier, isBranch, isTerminator |
LAR16rm
lar{w} {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
LAR16rr
lar{w} {src, dst|dst, src}
LAR32rm
lar{l} {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
LAR32rr
lar{l} {src, dst|dst, src}
LAR64rm
lar{q} {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
LAR64rr
lar{q} {src, dst|dst, src}
LDMXCSR
ldmxcsr src
|
Note
|
Properties: hasSideEffects, mayLoad |
LEA16r
lea{w} {src|dst}, {dst|src}
LEA64r
lea{q} {src|dst}, {dst|src}
LFS16rm
lfs{w} {src, dst|dst, src}
LFS32rm
lfs{l} {src, dst|dst, src}
LFS64rm
lfs{q} {src, dst|dst, src}
LGS16rm
lgs{w} {src, dst|dst, src}
LGS32rm
lgs{l} {src, dst|dst, src}
LGS64rm
lgs{q} {src, dst|dst, src}
LLDT16m
lldt{w} src
|
Note
|
Properties: mayLoad |
LLDT16r
lldt{w} src
LMSW16m
lmsw{w} src
|
Note
|
Properties: mayLoad |
LMSW16r
lmsw{w} src
LOCK_PREFIX
lock
LODSB
lodsb {src, %al|al, src}
LODSL
lods{l|d} {src, %eax|eax, src}
LODSW
lodsw {src, %ax|ax, src}
LOOP
loop dst
|
Note
|
Properties: isBranch, isTerminator |
LOOPE
loope dst
|
Note
|
Properties: isBranch, isTerminator |
LOOPNE
loopne dst
|
Note
|
Properties: isBranch, isTerminator |
LRET16
{l}ret{w|f}
|
Note
|
Properties: hasCtrlDep, isBarrier, isReturn, isTerminator |
LRET32
{l}ret{l|f}
|
Note
|
Properties: hasCtrlDep, isBarrier, isReturn, isTerminator |
LRETI16
{l}ret{w|f} amt
|
Note
|
Properties: hasCtrlDep, isBarrier, isReturn, isTerminator |
LRETI32
{l}ret{l|f} amt
|
Note
|
Properties: hasCtrlDep, isBarrier, isReturn, isTerminator |
LSL16rm
lsl{w} {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
LSL16rr
lsl{w} {src, dst|dst, src}
LSL32rm
lsl{l} {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
LSL32rr
lsl{l} {src, dst|dst, src}
LSL64rm
lsl{q} {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
LSL64rr
lsl{q} {src, dst|dst, src}
LSS16rm
lss{w} {src, dst|dst, src}
LSS32rm
lss{l} {src, dst|dst, src}
LSS64rm
lss{q} {src, dst|dst, src}
LTRm
ltr{w} src
|
Note
|
Properties: mayLoad |
LTRr
ltr{w} src
LZCNT16rm_NF
lzcnt{w} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
LZCNT16rr_NF
lzcnt{w} {src1, dst|dst, src1}
LZCNT32rm_NF
lzcnt{l} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
LZCNT32rr_NF
lzcnt{l} {src1, dst|dst, src1}
LZCNT64rm_NF
lzcnt{q} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
LZCNT64rr_NF
lzcnt{q} {src1, dst|dst, src1}
MONTMUL
montmul
MOV16ao16
mov{w} {src, %ax|ax, src}
|
Note
|
Properties: mayLoad |
MOV16ao32
mov{w} {src, %ax|ax, src}
|
Note
|
Properties: mayLoad |
MOV16ao64
movabs{w} {src, %ax|ax, src}
|
Note
|
Properties: mayLoad |
MOV16mi
mov{w} {src, dst|dst, src}
MOV16mr
mov{w} {src, dst|dst, src}
MOV16ms
mov{w} {src, dst|dst, src}
|
Note
|
Properties: mayStore |
MOV16o16a
mov{w} {%ax, dst|dst, ax}
|
Note
|
Properties: mayStore |
MOV16o32a
mov{w} {%ax, dst|dst, ax}
|
Note
|
Properties: mayStore |
MOV16o64a
movabs{w} {%ax, dst|dst, ax}
|
Note
|
Properties: mayStore |
MOV16ri
mov{w} {src, dst|dst, src}
|
Note
|
Properties: isAsCheapAsAMove, isMoveImm |
MOV16rm
mov{w} {src, dst|dst, src}
MOV16rr
mov{w} {src, dst|dst, src}
|
Note
|
Properties: isMoveReg |
MOV16rs
mov{w} {src, dst|dst, src}
MOV16sm
mov{w} {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
MOV16sr
mov{w} {src, dst|dst, src}
MOV32ao16
mov{l} {src, %eax|eax, src}
|
Note
|
Properties: mayLoad |
MOV32ao32
mov{l} {src, %eax|eax, src}
|
Note
|
Properties: mayLoad |
MOV32ao64
movabs{l} {src, %eax|eax, src}
|
Note
|
Properties: mayLoad |
MOV32mi
mov{l} {src, dst|dst, src}
MOV32mr
mov{l} {src, dst|dst, src}
MOV32o16a
mov{l} {%eax, dst|dst, eax}
|
Note
|
Properties: mayStore |
MOV32o32a
mov{l} {%eax, dst|dst, eax}
|
Note
|
Properties: mayStore |
MOV32o64a
movabs{l} {%eax, dst|dst, eax}
|
Note
|
Properties: mayStore |
MOV32ri
mov{l} {src, dst|dst, src}
|
Note
|
Properties: isAsCheapAsAMove, isMoveImm |
MOV32rm
mov{l} {src, dst|dst, src}
MOV32rr
mov{l} {src, dst|dst, src}
|
Note
|
Properties: isMoveReg |
MOV32rs
mov{l} {src, dst|dst, src}
MOV32sr
mov{l} {src, dst|dst, src}
MOV64ao32
mov{q} {src, %rax|rax, src}
|
Note
|
Properties: mayLoad |
MOV64ao64
movabs{q} {src, %rax|rax, src}
|
Note
|
Properties: mayLoad |
MOV64mr
mov{q} {src, dst|dst, src}
MOV64o32a
mov{q} {%rax, dst|dst, rax}
|
Note
|
Properties: mayStore |
MOV64o64a
movabs{q} {%rax, dst|dst, rax}
|
Note
|
Properties: mayStore |
MOV64ri
movabs{q} {src, dst|dst, src}
|
Note
|
Properties: isMoveImm |
MOV64ri32
mov{q} {src, dst|dst, src}
|
Note
|
Properties: isAsCheapAsAMove, isMoveImm |
MOV64rm
mov{q} {src, dst|dst, src}
MOV64rr
mov{q} {src, dst|dst, src}
|
Note
|
Properties: isMoveReg |
MOV64rs
mov{q} {src, dst|dst, src}
MOV64sr
mov{q} {src, dst|dst, src}
MOV8ao16
mov{b} {src, %al|al, src}
|
Note
|
Properties: mayLoad |
MOV8ao32
mov{b} {src, %al|al, src}
|
Note
|
Properties: mayLoad |
MOV8ao64
movabs{b} {src, %al|al, src}
|
Note
|
Properties: mayLoad |
MOV8mi
mov{b} {src, dst|dst, src}
MOV8mr
mov{b} {src, dst|dst, src}
MOV8o16a
mov{b} {%al, dst|dst, al}
|
Note
|
Properties: mayStore |
MOV8o32a
mov{b} {%al, dst|dst, al}
|
Note
|
Properties: mayStore |
MOV8o64a
movabs{b} {%al, dst|dst, al}
|
Note
|
Properties: mayStore |
MOV8ri
mov{b} {src, dst|dst, src}
|
Note
|
Properties: isAsCheapAsAMove, isMoveImm |
MOV8rm
mov{b} {src, dst|dst, src}
MOV8rr
mov{b} {src, dst|dst, src}
|
Note
|
Properties: isMoveReg |
MOVSB
movsb {src, dst|dst, src}
MOVSL
movs{l|d} {src, dst|dst, src}
MOVSW
movsw {src, dst|dst, src}
MOVSX16rm8
movs{bw|x} {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
MOVSX16rr8
movs{bw|x} {src, dst|dst, src}
MOVSX32rm16
movs{wl|x} {src, dst|dst, src}
MOVSX32rm8
movs{bl|x} {src, dst|dst, src}
MOVSX32rr16
movs{wl|x} {src, dst|dst, src}
MOVSX32rr8
movs{bl|x} {src, dst|dst, src}
MOVSX64rm16
movs{wq|x} {src, dst|dst, src}
MOVSX64rm8
movs{bq|x} {src, dst|dst, src}
MOVSX64rr16
movs{wq|x} {src, dst|dst, src}
MOVSX64rr8
movs{bq|x} {src, dst|dst, src}
MOVZX16rm8
movz{bw|x} {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
MOVZX16rr8
movz{bw|x} {src, dst|dst, src}
MOVZX32rm16
movz{wl|x} {src, dst|dst, src}
MOVZX32rm8
movz{bl|x} {src, dst|dst, src}
MOVZX32rr16
movz{wl|x} {src, dst|dst, src}
MOVZX32rr8
movz{bl|x} {src, dst|dst, src}
MOVZX64rm16
movz{wq|x} {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
MOVZX64rm8
movz{bq|x} {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
MOVZX64rr16
movz{wq|x} {src, dst|dst, src}
MOVZX64rr8
movz{bq|x} {src, dst|dst, src}
MUL16m
mul{w} src1
|
Note
|
Properties: mayLoad |
MUL16r
mul{w} src1
MUL32m
mul{l} src1
|
Note
|
Properties: mayLoad |
MUL32r
mul{l} src1
MUL64r
mul{q} src1
MUL8m
mul{b} src1
|
Note
|
Properties: mayLoad |
MUL8r
mul{b} src1
MULX32rm
mulx{l} {src, dst2, dst1|dst1, dst2, src}
|
Note
|
Properties: mayLoad |
MULX32rr
mulx{l} {src, dst2, dst1|dst1, dst2, src}
MULX64rm
mulx{q} {src, dst2, dst1|dst1, dst2, src}
|
Note
|
Properties: mayLoad |
MULX64rr
mulx{q} {src, dst2, dst1|dst1, dst2, src}
NEG16m
neg{w} src1
|
Note
|
Properties: mayLoad, mayStore |
NEG32m
neg{l} src1
|
Note
|
Properties: mayLoad, mayStore |
NEG8m
neg{b} src1
|
Note
|
Properties: mayLoad, mayStore |
NOOP
nop
NOOPL
nop{l} zero
NOOPLr
nop{l} zero
NOOPW
nop{w} zero
NOOPWr
nop{w} zero
NOT16m
not{w} src1
|
Note
|
Properties: mayLoad, mayStore |
NOT32m
not{l} src1
|
Note
|
Properties: mayLoad, mayStore |
NOT8m
not{b} src1
|
Note
|
Properties: mayLoad, mayStore |
OR16i16
or{w} {src, %ax|ax, src}
OR16mi
or{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
OR16mi8
or{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
OR16mr
or{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
OR32i32
or{l} {src, %eax|eax, src}
OR32mi
or{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
OR32mi8
or{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
OR32mr
or{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
OR64i32
or{q} {src, %rax|rax, src}
OR64mr
or{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
OR8i8
or{b} {src, %al|al, src}
OR8mi
or{b} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
OR8mr
or{b} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
OUT16ir
out{w} {%ax, port|port, ax}
OUT16rr
out{w} {%ax, %dx|dx, ax}
OUT32ir
out{l} {%eax, port|port, eax}
OUT32rr
out{l} {%eax, %dx|dx, eax}
OUT8ir
out{b} {%al, port|port, al}
OUT8rr
out{b} {%al, %dx|dx, al}
OUTSB
outsb {src, %dx|dx, src}
OUTSL
outs{l|d} {src, %dx|dx, src}
OUTSW
outsw {src, %dx|dx, src}
PAUSE
pause
PAVGUSBrm
pavgusb {src2, dst|dst, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
PAVGUSBrr
pavgusb {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PF2IDrm
pf2id {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
PF2IDrr
pf2id {src, dst|dst, src}
PF2IWrm
pf2iw {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
PF2IWrr
pf2iw {src, dst|dst, src}
PFACCrm
pfacc {src2, dst|dst, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
PFACCrr
pfacc {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PFADDrm
pfadd {src2, dst|dst, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
PFADDrr
pfadd {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PFCMPEQrm
pfcmpeq {src2, dst|dst, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
PFCMPEQrr
pfcmpeq {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PFCMPGErm
pfcmpge {src2, dst|dst, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
PFCMPGErr
pfcmpge {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PFCMPGTrm
pfcmpgt {src2, dst|dst, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
PFCMPGTrr
pfcmpgt {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PFMAXrm
pfmax {src2, dst|dst, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
PFMAXrr
pfmax {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PFMINrm
pfmin {src2, dst|dst, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
PFMINrr
pfmin {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PFMULrm
pfmul {src2, dst|dst, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
PFMULrr
pfmul {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PFNACCrm
pfnacc {src2, dst|dst, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
PFNACCrr
pfnacc {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PFPNACCrm
pfpnacc {src2, dst|dst, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
PFPNACCrr
pfpnacc {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PFRCPIT1rm
pfrcpit1 {src2, dst|dst, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
PFRCPIT1rr
pfrcpit1 {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PFRCPIT2rm
pfrcpit2 {src2, dst|dst, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
PFRCPIT2rr
pfrcpit2 {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PFRCPrm
pfrcp {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
PFRCPrr
pfrcp {src, dst|dst, src}
PFRSQIT1rm
pfrsqit1 {src2, dst|dst, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
PFRSQIT1rr
pfrsqit1 {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PFRSQRTrm
pfrsqrt {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
PFRSQRTrr
pfrsqrt {src, dst|dst, src}
PFSUBRrm
pfsubr {src2, dst|dst, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
PFSUBRrr
pfsubr {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PFSUBrm
pfsub {src2, dst|dst, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
PFSUBrr
pfsub {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PI2FDrm
pi2fd {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
PI2FDrr
pi2fd {src, dst|dst, src}
PI2FWrm
pi2fw {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
PI2FWrr
pi2fw {src, dst|dst, src}
PMULHRWrm
pmulhrw {src2, dst|dst, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
PMULHRWrr
pmulhrw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
POP16r
pop{w} reg
|
Note
|
Properties: mayLoad |
POP16rmm
pop{w} dst
|
Note
|
Properties: mayLoad, mayStore |
POP2
pop2 {reg2, reg1|reg1, reg2}
|
Note
|
Properties: mayLoad |
POP2P
pop2p {reg2, reg1|reg1, reg2}
|
Note
|
Properties: mayLoad |
POPCNT16rm_NF
popcnt{w} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
POPCNT16rr_NF
popcnt{w} {src1, dst|dst, src1}
POPCNT32rm_NF
popcnt{l} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
POPCNT32rr_NF
popcnt{l} {src1, dst|dst, src1}
POPCNT64rm_NF
popcnt{q} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
POPCNT64rr_NF
popcnt{q} {src1, dst|dst, src1}
POPF16
popf{w}
|
Note
|
Properties: mayLoad |
POPFS16
pop{w} {%fs|fs}
POPGS16
pop{w} {%gs|gs}
PREFETCH
prefetch addr
|
Note
|
Properties: mayLoad, mayStore |
PREFETCHWT1
prefetchwt1 addr
|
Note
|
Properties: mayLoad, mayStore |
PSWAPDrm
pswapd {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
PSWAPDrr
pswapd {src, dst|dst, src}
PUSH16i
push{w} imm
|
Note
|
Properties: mayStore |
PUSH16i8
push{w} imm
|
Note
|
Properties: mayStore |
PUSH16r
push{w} reg
|
Note
|
Properties: mayStore |
PUSH16rmm
push{w} src
|
Note
|
Properties: mayLoad, mayStore |
PUSH2
push2 {reg2, reg1|reg1, reg2}
|
Note
|
Properties: mayStore |
PUSH2P
push2p {reg2, reg1|reg1, reg2}
|
Note
|
Properties: mayStore |
PUSHF16
pushf{w}
|
Note
|
Properties: mayStore |
PUSHFS16
push{w} {%fs|fs}
PUSHGS16
push{w} {%gs|gs}
RCL16m1
rcl{w} src1
|
Note
|
Properties: mayLoad, mayStore |
RCL16mCL
rcl{w} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
RCL16mi
rcl{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
RCL16r1
rcl{w} src1
|
Note
|
Constraints: src1 = dst |
RCL32m1
rcl{l} src1
|
Note
|
Properties: mayLoad, mayStore |
RCL32mCL
rcl{l} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
RCL32mi
rcl{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
RCL32r1
rcl{l} src1
|
Note
|
Constraints: src1 = dst |
RCL64r1
rcl{q} src1
|
Note
|
Constraints: src1 = dst |
RCL8m1
rcl{b} src1
|
Note
|
Properties: mayLoad, mayStore |
RCL8mCL
rcl{b} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
RCL8mi
rcl{b} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
RCL8r1
rcl{b} src1
|
Note
|
Constraints: src1 = dst |
RCPSSm_Int
rcpss {src2, dst|dst, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
RCPSSr_Int
rcpss {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
RCR16m1
rcr{w} src1
|
Note
|
Properties: mayLoad, mayStore |
RCR16mCL
rcr{w} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
RCR16mi
rcr{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
RCR16r1
rcr{w} src1
|
Note
|
Constraints: src1 = dst |
RCR32m1
rcr{l} src1
|
Note
|
Properties: mayLoad, mayStore |
RCR32mCL
rcr{l} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
RCR32mi
rcr{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
RCR32r1
rcr{l} src1
|
Note
|
Constraints: src1 = dst |
RCR64r1
rcr{q} src1
|
Note
|
Constraints: src1 = dst |
RCR8m1
rcr{b} src1
|
Note
|
Properties: mayLoad, mayStore |
RCR8mCL
rcr{b} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
RCR8mi
rcr{b} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
RCR8r1
rcr{b} src1
|
Note
|
Constraints: src1 = dst |
RDMSR
rdmsr
RDPKRUr
rdpkru
RDPMC
rdpmc
RDSSPD
rdsspd dst
|
Note
|
Constraints: src = dst |
RDSSPQ
rdsspq dst
|
Note
|
Constraints: src = dst |
RDTSC
rdtsc
RDTSCP
rdtscp
REPNE_PREFIX
repne
REP_PREFIX
rep
RET16
ret{w}
|
Note
|
Properties: hasCtrlDep, isBarrier, isReturn, isTerminator |
RETI16
ret{w} amt
|
Note
|
Properties: hasCtrlDep, isBarrier, isReturn, isTerminator |
ROL16m1
rol{w} src1
|
Note
|
Properties: mayLoad, mayStore |
ROL16mCL
rol{w} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
ROL16mi
rol{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ROL16r1
rol{w} src1
|
Note
|
Constraints: src1 = dst |
ROL32m1
rol{l} src1
|
Note
|
Properties: mayLoad, mayStore |
ROL32mCL
rol{l} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
ROL32mi
rol{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ROL32r1
rol{l} src1
|
Note
|
Constraints: src1 = dst |
ROL64r1
rol{q} src1
|
Note
|
Constraints: src1 = dst |
ROL8m1
rol{b} src1
|
Note
|
Properties: mayLoad, mayStore |
ROL8mCL
rol{b} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
ROL8mi
rol{b} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ROL8r1
rol{b} src1
|
Note
|
Constraints: src1 = dst |
ROR16m1
ror{w} src1
|
Note
|
Properties: mayLoad, mayStore |
ROR16mCL
ror{w} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
ROR16mi
ror{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ROR16r1
ror{w} src1
|
Note
|
Constraints: src1 = dst |
ROR32m1
ror{l} src1
|
Note
|
Properties: mayLoad, mayStore |
ROR32mCL
ror{l} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
ROR32mi
ror{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ROR32r1
ror{l} src1
|
Note
|
Constraints: src1 = dst |
ROR64r1
ror{q} src1
|
Note
|
Constraints: src1 = dst |
ROR8m1
ror{b} src1
|
Note
|
Properties: mayLoad, mayStore |
ROR8mCL
ror{b} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
ROR8mi
ror{b} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ROR8r1
ror{b} src1
|
Note
|
Constraints: src1 = dst |
RSM
rsm
RSQRTSSm_Int
rsqrtss {src2, dst|dst, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
RSQRTSSr_Int
rsqrtss {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
RSTORSSP
rstorssp src
SAR16m1
sar{w} src1
|
Note
|
Properties: mayLoad, mayStore |
SAR16mCL
sar{w} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
SAR16mi
sar{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
SAR16r1
sar{w} src1
|
Note
|
Constraints: src1 = dst |
SAR32m1
sar{l} src1
|
Note
|
Properties: mayLoad, mayStore |
SAR32mCL
sar{l} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
SAR32mi
sar{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
SAR32r1
sar{l} src1
|
Note
|
Constraints: src1 = dst |
SAR64r1
sar{q} src1
|
Note
|
Constraints: src1 = dst |
SAR8m1
sar{b} src1
|
Note
|
Properties: mayLoad, mayStore |
SAR8mCL
sar{b} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
SAR8mi
sar{b} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
SAR8r1
sar{b} src1
|
Note
|
Constraints: src1 = dst |
SAVEPREVSSP
saveprevssp
SBB16i16
sbb{w} {src, %ax|ax, src}
SBB16mi
sbb{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
SBB16mi8
sbb{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
SBB16mr
sbb{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
SBB32i32
sbb{l} {src, %eax|eax, src}
SBB32mi
sbb{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
SBB32mi8
sbb{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
SBB32mr
sbb{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
SBB64i32
sbb{q} {src, %rax|rax, src}
SBB64mr
sbb{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
SBB8i8
sbb{b} {src, %al|al, src}
SBB8mi
sbb{b} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
SBB8mr
sbb{b} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
SCASB
scasb {dst, %al|al, dst}
SCASL
scas{l|d} {dst, %eax|eax, dst}
SCASW
scasw {dst, %ax|ax, dst}
SETSSBSY
setssbsy
SHL16m1
shl{w} src1
|
Note
|
Properties: mayLoad, mayStore |
SHL16mCL
shl{w} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
SHL16mi
shl{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
SHL16r1
shl{w} src1
|
Note
|
Constraints: src1 = dst |
SHL32m1
shl{l} src1
|
Note
|
Properties: mayLoad, mayStore |
SHL32mCL
shl{l} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
SHL32mi
shl{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
SHL32r1
shl{l} src1
|
Note
|
Constraints: src1 = dst |
SHL64r1
shl{q} src1
|
Note
|
Constraints: src1 = dst |
SHL8m1
shl{b} src1
|
Note
|
Properties: mayLoad, mayStore |
SHL8mCL
shl{b} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
SHL8mi
shl{b} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
SHL8r1
shl{b} src1
|
Note
|
Constraints: src1 = dst |
SHLD16mrCL
shld{w} {%cl, src2, src1|src1, src2, cl}
|
Note
|
Properties: mayLoad, mayStore |
SHLD16mri8
shld{w} {src3, src2, src1|src1, src2, src3}
|
Note
|
Properties: mayLoad, mayStore |
SHLD32mrCL
shld{l} {%cl, src2, src1|src1, src2, cl}
|
Note
|
Properties: mayLoad, mayStore |
SHLD32mri8
shld{l} {src3, src2, src1|src1, src2, src3}
|
Note
|
Properties: mayLoad, mayStore |
SHLD64mrCL
shld{q} {%cl, src2, src1|src1, src2, cl}
|
Note
|
Properties: mayLoad, mayStore |
SHLD64mri8
shld{q} {src3, src2, src1|src1, src2, src3}
|
Note
|
Properties: mayLoad, mayStore |
SHR16m1
shr{w} src1
|
Note
|
Properties: mayLoad, mayStore |
SHR16mCL
shr{w} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
SHR16mi
shr{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
SHR16r1
shr{w} src1
|
Note
|
Constraints: src1 = dst |
SHR32m1
shr{l} src1
|
Note
|
Properties: mayLoad, mayStore |
SHR32mCL
shr{l} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
SHR32mi
shr{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
SHR32r1
shr{l} src1
|
Note
|
Constraints: src1 = dst |
SHR64r1
shr{q} src1
|
Note
|
Constraints: src1 = dst |
SHR8m1
shr{b} src1
|
Note
|
Properties: mayLoad, mayStore |
SHR8mCL
shr{b} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
SHR8mi
shr{b} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
SHR8r1
shr{b} src1
|
Note
|
Constraints: src1 = dst |
SHRD16mrCL
shrd{w} {%cl, src2, src1|src1, src2, cl}
|
Note
|
Properties: mayLoad, mayStore |
SHRD16mri8
shrd{w} {src3, src2, src1|src1, src2, src3}
|
Note
|
Properties: mayLoad, mayStore |
SHRD32mrCL
shrd{l} {%cl, src2, src1|src1, src2, cl}
|
Note
|
Properties: mayLoad, mayStore |
SHRD32mri8
shrd{l} {src3, src2, src1|src1, src2, src3}
|
Note
|
Properties: mayLoad, mayStore |
SHRD64mrCL
shrd{q} {%cl, src2, src1|src1, src2, cl}
|
Note
|
Properties: mayLoad, mayStore |
SHRD64mri8
shrd{q} {src3, src2, src1|src1, src2, src3}
|
Note
|
Properties: mayLoad, mayStore |
SKINIT
skinit
SLDT16m
sldt{w} dst
|
Note
|
Properties: mayStore |
SLDT16r
sldt{w} dst
SLDT32r
sldt{l} dst
SMSW16m
smsw{w} dst
SMSW16r
smsw{w} dst
SMSW32r
smsw{l} dst
SMSW64r
smsw{q} dst
SQRTSDm_Int
sqrtsd {src2, dst|dst, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
SQRTSDr_Int
sqrtsd {src2, dst|dst, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
SQRTSSm_Int
sqrtss {src2, dst|dst, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
SQRTSSr_Int
sqrtss {src2, dst|dst, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
SS_PREFIX
ss
STAC
stac
STC
stc
STD
std
STGI
stgi
STI
sti
STMXCSR
stmxcsr dst
|
Note
|
Properties: hasSideEffects, mayStore |
STOSB
stosb {%al, dst|dst, al}
STOSL
stos{l|d} {%eax, dst|dst, eax}
STOSW
stosw {%ax, dst|dst, ax}
STR16r
str{w} dst
STR32r
str{l} dst
STR64r
str{q} dst
STRm
str{w} dst
|
Note
|
Properties: mayStore |
SUB16i16
sub{w} {src, %ax|ax, src}
|
Note
|
Properties: isCompare |
SUB16mi
sub{w} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare, mayLoad, mayStore |
SUB16mi8
sub{w} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare, mayLoad, mayStore |
SUB16mr
sub{w} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare, mayLoad, mayStore |
SUB32i32
sub{l} {src, %eax|eax, src}
|
Note
|
Properties: isCompare |
SUB32mi
sub{l} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare, mayLoad, mayStore |
SUB32mi8
sub{l} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare, mayLoad, mayStore |
SUB32mr
sub{l} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare, mayLoad, mayStore |
SUB64i32
sub{q} {src, %rax|rax, src}
|
Note
|
Properties: isCompare |
SUB64mr
sub{q} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare, mayLoad, mayStore |
SUB8i8
sub{b} {src, %al|al, src}
|
Note
|
Properties: isCompare |
SUB8mi
sub{b} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare, mayLoad, mayStore |
SUB8mr
sub{b} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare, mayLoad, mayStore |
SWAPGS
swapgs
SYSCALL
syscall
SYSENTER
sysenter
SYSEXIT
sysexit{l}
SYSRET
sysret{l}
TDCALL
tdcall
TEST16i16
test{w} {src, %ax|ax, src}
|
Note
|
Properties: isCompare |
TEST16mi
test{w} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare, mayLoad |
TEST16mr
test{w} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare, mayLoad |
TEST16ri
test{w} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare |
TEST16rr
test{w} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare |
TEST32i32
test{l} {src, %eax|eax, src}
|
Note
|
Properties: isCompare |
TEST32mi
test{l} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare, mayLoad |
TEST32mr
test{l} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare, mayLoad |
TEST32ri
test{l} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare |
TEST32rr
test{l} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare |
TEST64i32
test{q} {src, %rax|rax, src}
|
Note
|
Properties: isCompare |
TEST64mr
test{q} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare, mayLoad |
TEST64ri32
test{q} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare |
TEST64rr
test{q} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare |
TEST8i8
test{b} {src, %al|al, src}
|
Note
|
Properties: isCompare |
TEST8mi
test{b} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare, mayLoad |
TEST8mr
test{b} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare, mayLoad |
TEST8ri
test{b} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare |
TEST8rr
test{b} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare |
TLBSYNC
tlbsync
TRAP
ud2
|
Note
|
Properties: hasSideEffects, isTrap, mayLoad |
TZCNT16rm_NF
tzcnt{w} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
TZCNT16rr_NF
tzcnt{w} {src1, dst|dst, src1}
TZCNT32rm_NF
tzcnt{l} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
TZCNT32rr_NF
tzcnt{l} {src1, dst|dst, src1}
TZCNT64rm_NF
tzcnt{q} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
TZCNT64rr_NF
tzcnt{q} {src1, dst|dst, src1}
UD1Lm
ud1{l} {src2, src1|src1, src2}
|
Note
|
Properties: hasSideEffects, isTrap, mayLoad |
UD1Lr
ud1{l} {src2, src1|src1, src2}
|
Note
|
Properties: hasSideEffects, isTrap, mayLoad |
UD1Qm
ud1{q} {src2, src1|src1, src2}
|
Note
|
Properties: hasSideEffects, isTrap, mayLoad |
UD1Qr
ud1{q} {src2, src1|src1, src2}
|
Note
|
Properties: hasSideEffects, isTrap, mayLoad |
UD1Wm
ud1{w} {src2, src1|src1, src2}
|
Note
|
Properties: hasSideEffects, isTrap, mayLoad |
UD1Wr
ud1{w} {src2, src1|src1, src2}
|
Note
|
Properties: hasSideEffects, isTrap, mayLoad |
VERRm
verr seg
|
Note
|
Properties: mayLoad |
VERRr
verr seg
VERWm
verw seg
|
Note
|
Properties: mayLoad |
VERWr
verw seg
VMCALL
vmcall
VMCLEARm
vmclear vmcs
VMFUNC
vmfunc
VMLAUNCH
vmlaunch
VMMCALL
vmmcall
VMPTRLDm
vmptrld vmcs
VMPTRSTm
vmptrst vmcs
VMRESUME
vmresume
VMXOFF
vmxoff
VMXON
vmxon vmxon
VRCPSSm_Int
vrcpss {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VRCPSSr_Int
vrcpss {src2, src1, dst|dst, src1, src2}
VRSQRTSSm_Int
vrsqrtss {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VRSQRTSSr_Int
vrsqrtss {src2, src1, dst|dst, src1, src2}
VSQRTSDm_Int
vsqrtsd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VSQRTSDr_Int
vsqrtsd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSQRTSSm_Int
vsqrtss {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VSQRTSSr_Int
vsqrtss {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
WAIT
wait
WBINVD
wbinvd
WRMSR
wrmsr
WRMSRNS
wrmsrns
WRPKRUr
wrpkru
XACQUIRE_PREFIX
xacquire
XADD16rm
xadd{w} {val, ptr|ptr, val}
|
Note
|
Properties: mayLoad, mayStore |
|
Note
|
Constraints: val = dst |
XADD16rr
xadd{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst1, src2 = dst2 |
XADD32rm
xadd{l} {val, ptr|ptr, val}
|
Note
|
Properties: mayLoad, mayStore |
|
Note
|
Constraints: val = dst |
XADD32rr
xadd{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst1, src2 = dst2 |
XADD64rm
xadd{q} {val, ptr|ptr, val}
|
Note
|
Properties: mayLoad, mayStore |
|
Note
|
Constraints: val = dst |
XADD64rr
xadd{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst1, src2 = dst2 |
XADD8rm
xadd{b} {val, ptr|ptr, val}
|
Note
|
Properties: mayLoad, mayStore |
|
Note
|
Constraints: val = dst |
XADD8rr
xadd{b} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst1, src2 = dst2 |
XBEGIN_2
xbegin dst
|
Note
|
Properties: isBranch, isTerminator |
XBEGIN_4
xbegin dst
|
Note
|
Properties: isBranch, isTerminator |
XCHG16ar
xchg{w} {src, %ax|ax, src}
|
Note
|
Constraints: src = dst |
XCHG16rm
xchg{w} {val, ptr|ptr, val}
|
Note
|
Constraints: val = dst |
XCHG16rr
xchg{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst1, src2 = dst2 |
XCHG32ar
xchg{l} {src, %eax|eax, src}
|
Note
|
Constraints: src = dst |
XCHG32rm
xchg{l} {val, ptr|ptr, val}
|
Note
|
Constraints: val = dst |
XCHG32rr
xchg{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst1, src2 = dst2 |
XCHG64ar
xchg{q} {src, %rax|rax, src}
|
Note
|
Constraints: src = dst |
XCHG64rm
xchg{q} {val, ptr|ptr, val}
|
Note
|
Constraints: val = dst |
XCHG64rr
xchg{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst1, src2 = dst2 |
XCHG8rm
xchg{b} {val, ptr|ptr, val}
|
Note
|
Constraints: val = dst |
XCHG8rr
xchg{b} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst1, src2 = dst2 |
XCRYPTCBC
xcryptcbc
XCRYPTCFB
xcryptcfb
XCRYPTCTR
xcryptctr
XCRYPTECB
xcryptecb
XCRYPTOFB
xcryptofb
XGETBV
xgetbv
XLAT
xlatb
|
Note
|
Properties: mayLoad |
XOR16i16
xor{w} {src, %ax|ax, src}
XOR16mi
xor{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
XOR16mi8
xor{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
XOR16mr
xor{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
XOR32i32
xor{l} {src, %eax|eax, src}
XOR32mi
xor{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
XOR32mi8
xor{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
XOR32mr
xor{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
XOR64i32
xor{q} {src, %rax|rax, src}
XOR64mr
xor{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
XOR8i8
xor{b} {src, %al|al, src}
XOR8mi
xor{b} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
XOR8mr
xor{b} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
XRELEASE_PREFIX
xrelease
XSETBV
xsetbv
XSHA1
xsha1
XSHA256
xsha256
XSTORE
xstore
VBLENDMPDZ128rm [HasVLX]
vblendmpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VBLENDMPDZ128rmb [HasVLX]
vblendmpd {src2{1to2}, src1, dst|dst, src1, src2{1to2}}
|
Note
|
Properties: mayLoad |
VBLENDMPDZ128rmbk [HasVLX]
vblendmpd {src2{1to2}, src1, dst {mask}|dst {mask}, src1, src2{1to2}}
|
Note
|
Properties: mayLoad |
VBLENDMPDZ128rmbkz [HasVLX]
vblendmpd {src2{1to2}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to2}}
|
Note
|
Properties: mayLoad |
VBLENDMPDZ128rmk [HasVLX]
vblendmpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
VBLENDMPDZ128rmkz [HasVLX]
vblendmpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VBLENDMPDZ128rr [HasVLX]
vblendmpd {src2, src1, dst|dst, src1, src2}
VBLENDMPDZ128rrk [HasVLX]
vblendmpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
VBLENDMPDZ128rrkz [HasVLX]
vblendmpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VBLENDMPDZ256rm [HasVLX]
vblendmpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VBLENDMPDZ256rmb [HasVLX]
vblendmpd {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
|
Note
|
Properties: mayLoad |
VBLENDMPDZ256rmbk [HasVLX]
vblendmpd {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Properties: mayLoad |
VBLENDMPDZ256rmbkz [HasVLX]
vblendmpd {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
|
Note
|
Properties: mayLoad |
VBLENDMPDZ256rmk [HasVLX]
vblendmpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
VBLENDMPDZ256rmkz [HasVLX]
vblendmpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VBLENDMPDZ256rr [HasVLX]
vblendmpd {src2, src1, dst|dst, src1, src2}
VBLENDMPDZ256rrk [HasVLX]
vblendmpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
VBLENDMPDZ256rrkz [HasVLX]
vblendmpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VBLENDMPSZ128rm [HasVLX]
vblendmps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VBLENDMPSZ128rmb [HasVLX]
vblendmps {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
|
Note
|
Properties: mayLoad |
VBLENDMPSZ128rmbk [HasVLX]
vblendmps {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Properties: mayLoad |
VBLENDMPSZ128rmbkz [HasVLX]
vblendmps {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
|
Note
|
Properties: mayLoad |
VBLENDMPSZ128rmk [HasVLX]
vblendmps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
VBLENDMPSZ128rmkz [HasVLX]
vblendmps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VBLENDMPSZ128rr [HasVLX]
vblendmps {src2, src1, dst|dst, src1, src2}
VBLENDMPSZ128rrk [HasVLX]
vblendmps {src2, src1, dst {mask}|dst {mask}, src1, src2}
VBLENDMPSZ128rrkz [HasVLX]
vblendmps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VBLENDMPSZ256rm [HasVLX]
vblendmps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VBLENDMPSZ256rmb [HasVLX]
vblendmps {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
VBLENDMPSZ256rmbk [HasVLX]
vblendmps {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
VBLENDMPSZ256rmbkz [HasVLX]
vblendmps {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
VBLENDMPSZ256rmk [HasVLX]
vblendmps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
VBLENDMPSZ256rmkz [HasVLX]
vblendmps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VBLENDMPSZ256rr [HasVLX]
vblendmps {src2, src1, dst|dst, src1, src2}
VBLENDMPSZ256rrk [HasVLX]
vblendmps {src2, src1, dst {mask}|dst {mask}, src1, src2}
VBLENDMPSZ256rrkz [HasVLX]
vblendmps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VBROADCASTF32X4Z256rm [HasVLX]
vbroadcastf32x4 {src, dst|dst, src}
VBROADCASTF32X4Z256rmk [HasVLX]
vbroadcastf32x4 {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VBROADCASTF32X4Z256rmkz [HasVLX]
vbroadcastf32x4 {src, dst {mask} {z}|dst {mask} {z}, src}
VBROADCASTI32X4Z256rm [HasVLX]
vbroadcasti32x4 {src, dst|dst, src}
VBROADCASTI32X4Z256rmk [HasVLX]
vbroadcasti32x4 {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VBROADCASTI32X4Z256rmkz [HasVLX]
vbroadcasti32x4 {src, dst {mask} {z}|dst {mask} {z}, src}
VBROADCASTSDZ256rm [HasVLX]
vbroadcastsd {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
VBROADCASTSDZ256rmk [HasVLX]
vbroadcastsd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VBROADCASTSDZ256rmkz [HasVLX]
vbroadcastsd {src, dst {mask} {z}|dst {mask} {z}, src}
VBROADCASTSDZ256rr [HasVLX]
vbroadcastsd {src, dst|dst, src}
VBROADCASTSDZ256rrk [HasVLX]
vbroadcastsd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VBROADCASTSDZ256rrkz [HasVLX]
vbroadcastsd {src, dst {mask} {z}|dst {mask} {z}, src}
VBROADCASTSSZ128rm [HasVLX]
vbroadcastss {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
VBROADCASTSSZ128rmk [HasVLX]
vbroadcastss {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VBROADCASTSSZ128rmkz [HasVLX]
vbroadcastss {src, dst {mask} {z}|dst {mask} {z}, src}
VBROADCASTSSZ128rr [HasVLX]
vbroadcastss {src, dst|dst, src}
VBROADCASTSSZ128rrk [HasVLX]
vbroadcastss {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VBROADCASTSSZ128rrkz [HasVLX]
vbroadcastss {src, dst {mask} {z}|dst {mask} {z}, src}
VBROADCASTSSZ256rm [HasVLX]
vbroadcastss {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
VBROADCASTSSZ256rmk [HasVLX]
vbroadcastss {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VBROADCASTSSZ256rmkz [HasVLX]
vbroadcastss {src, dst {mask} {z}|dst {mask} {z}, src}
VBROADCASTSSZ256rr [HasVLX]
vbroadcastss {src, dst|dst, src}
VBROADCASTSSZ256rrk [HasVLX]
vbroadcastss {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VBROADCASTSSZ256rrkz [HasVLX]
vbroadcastss {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTDQ2PDZ128rm [HasVLX]
vcvtdq2pd {src, dst|dst, src}
VCVTDQ2PDZ128rmb [HasVLX]
vcvtdq2pd {src{1to2}, dst|dst, src{1to2}}
VCVTDQ2PDZ128rmbk [HasVLX]
vcvtdq2pd {src{1to2}, dst {mask}|dst {mask}, src{1to2}}
|
Note
|
Constraints: src0 = dst |
VCVTDQ2PDZ128rmbkz [HasVLX]
vcvtdq2pd {src{1to2}, dst {mask} {z}|dst {mask} {z}, src{1to2}}
VCVTDQ2PDZ128rmk [HasVLX]
vcvtdq2pd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTDQ2PDZ128rmkz [HasVLX]
vcvtdq2pd {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTDQ2PDZ128rr [HasVLX]
vcvtdq2pd {src, dst|dst, src}
VCVTDQ2PDZ128rrk [HasVLX]
vcvtdq2pd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTDQ2PDZ128rrkz [HasVLX]
vcvtdq2pd {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTDQ2PDZ256rm [HasVLX]
vcvtdq2pd {src, dst|dst, src}
VCVTDQ2PDZ256rmb [HasVLX]
vcvtdq2pd {src{1to4}, dst|dst, src{1to4}}
VCVTDQ2PDZ256rmbk [HasVLX]
vcvtdq2pd {src{1to4}, dst {mask}|dst {mask}, src{1to4}}
|
Note
|
Constraints: src0 = dst |
VCVTDQ2PDZ256rmbkz [HasVLX]
vcvtdq2pd {src{1to4}, dst {mask} {z}|dst {mask} {z}, src{1to4}}
VCVTDQ2PDZ256rmk [HasVLX]
vcvtdq2pd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTDQ2PDZ256rmkz [HasVLX]
vcvtdq2pd {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTDQ2PDZ256rr [HasVLX]
vcvtdq2pd {src, dst|dst, src}
VCVTDQ2PDZ256rrk [HasVLX]
vcvtdq2pd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTDQ2PDZ256rrkz [HasVLX]
vcvtdq2pd {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTDQ2PSZ128rm [HasVLX]
vcvtdq2ps {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTDQ2PSZ128rmb [HasVLX]
vcvtdq2ps {src{1to4}, dst|dst, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTDQ2PSZ128rmbk [HasVLX]
vcvtdq2ps {src{1to4}, dst {mask}|dst {mask}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTDQ2PSZ128rmbkz [HasVLX]
vcvtdq2ps {src{1to4}, dst {mask} {z}|dst {mask} {z}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTDQ2PSZ128rmk [HasVLX]
vcvtdq2ps {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTDQ2PSZ128rmkz [HasVLX]
vcvtdq2ps {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTDQ2PSZ128rr [HasVLX]
vcvtdq2ps {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTDQ2PSZ128rrk [HasVLX]
vcvtdq2ps {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTDQ2PSZ128rrkz [HasVLX]
vcvtdq2ps {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTDQ2PSZ256rm [HasVLX]
vcvtdq2ps {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTDQ2PSZ256rmb [HasVLX]
vcvtdq2ps {src{1to8}, dst|dst, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTDQ2PSZ256rmbk [HasVLX]
vcvtdq2ps {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTDQ2PSZ256rmbkz [HasVLX]
vcvtdq2ps {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTDQ2PSZ256rmk [HasVLX]
vcvtdq2ps {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTDQ2PSZ256rmkz [HasVLX]
vcvtdq2ps {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTDQ2PSZ256rr [HasVLX]
vcvtdq2ps {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTDQ2PSZ256rrk [HasVLX]
vcvtdq2ps {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTDQ2PSZ256rrkz [HasVLX]
vcvtdq2ps {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2DQZ128rm [HasVLX]
vcvtpd2dq{x} {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2DQZ128rmb [HasVLX]
vcvtpd2dq {src{1to2}, dst|dst, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2DQZ128rmbk [HasVLX]
vcvtpd2dq {src{1to2}, dst {mask}|dst {mask}, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPD2DQZ128rmbkz [HasVLX]
vcvtpd2dq {src{1to2}, dst {mask} {z}|dst {mask} {z}, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2DQZ128rmk [HasVLX]
vcvtpd2dq{x} {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPD2DQZ128rmkz [HasVLX]
vcvtpd2dq{x} {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2DQZ128rr [HasVLX]
vcvtpd2dq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2DQZ128rrk [HasVLX]
vcvtpd2dq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPD2DQZ128rrkz [HasVLX]
vcvtpd2dq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2DQZ256rm [HasVLX]
vcvtpd2dq{y} {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2DQZ256rmb [HasVLX]
vcvtpd2dq {src{1to4}, dst|dst, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2DQZ256rmbk [HasVLX]
vcvtpd2dq {src{1to4}, dst {mask}|dst {mask}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPD2DQZ256rmbkz [HasVLX]
vcvtpd2dq {src{1to4}, dst {mask} {z}|dst {mask} {z}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2DQZ256rmk [HasVLX]
vcvtpd2dq{y} {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPD2DQZ256rmkz [HasVLX]
vcvtpd2dq{y} {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2DQZ256rr [HasVLX]
vcvtpd2dq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2DQZ256rrk [HasVLX]
vcvtpd2dq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPD2DQZ256rrkz [HasVLX]
vcvtpd2dq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2UDQZ128rm [HasVLX]
vcvtpd2udq{x} {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2UDQZ128rmb [HasVLX]
vcvtpd2udq {src{1to2}, dst|dst, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2UDQZ128rmbk [HasVLX]
vcvtpd2udq {src{1to2}, dst {mask}|dst {mask}, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPD2UDQZ128rmbkz [HasVLX]
vcvtpd2udq {src{1to2}, dst {mask} {z}|dst {mask} {z}, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2UDQZ128rmk [HasVLX]
vcvtpd2udq{x} {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPD2UDQZ128rmkz [HasVLX]
vcvtpd2udq{x} {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2UDQZ128rr [HasVLX]
vcvtpd2udq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2UDQZ128rrk [HasVLX]
vcvtpd2udq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPD2UDQZ128rrkz [HasVLX]
vcvtpd2udq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2UDQZ256rm [HasVLX]
vcvtpd2udq{y} {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2UDQZ256rmb [HasVLX]
vcvtpd2udq {src{1to4}, dst|dst, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2UDQZ256rmbk [HasVLX]
vcvtpd2udq {src{1to4}, dst {mask}|dst {mask}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPD2UDQZ256rmbkz [HasVLX]
vcvtpd2udq {src{1to4}, dst {mask} {z}|dst {mask} {z}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2UDQZ256rmk [HasVLX]
vcvtpd2udq{y} {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPD2UDQZ256rmkz [HasVLX]
vcvtpd2udq{y} {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2UDQZ256rr [HasVLX]
vcvtpd2udq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2UDQZ256rrk [HasVLX]
vcvtpd2udq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPD2UDQZ256rrkz [HasVLX]
vcvtpd2udq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2PSZ128rm [HasVLX]
vcvtph2ps {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2PSZ128rmk [HasVLX]
vcvtph2ps {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2PSZ128rmkz [HasVLX]
vcvtph2ps {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2PSZ128rr [HasVLX]
vcvtph2ps {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2PSZ128rrk [HasVLX]
vcvtph2ps {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2PSZ128rrkz [HasVLX]
vcvtph2ps {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2PSZ256rm [HasVLX]
vcvtph2ps {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2PSZ256rmk [HasVLX]
vcvtph2ps {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2PSZ256rmkz [HasVLX]
vcvtph2ps {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2PSZ256rr [HasVLX]
vcvtph2ps {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2PSZ256rrk [HasVLX]
vcvtph2ps {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2PSZ256rrkz [HasVLX]
vcvtph2ps {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2DQZ128rm [HasVLX]
vcvtps2dq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2DQZ128rmb [HasVLX]
vcvtps2dq {src{1to4}, dst|dst, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2DQZ128rmbk [HasVLX]
vcvtps2dq {src{1to4}, dst {mask}|dst {mask}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPS2DQZ128rmbkz [HasVLX]
vcvtps2dq {src{1to4}, dst {mask} {z}|dst {mask} {z}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2DQZ128rmk [HasVLX]
vcvtps2dq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPS2DQZ128rmkz [HasVLX]
vcvtps2dq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2DQZ128rr [HasVLX]
vcvtps2dq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2DQZ128rrk [HasVLX]
vcvtps2dq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPS2DQZ128rrkz [HasVLX]
vcvtps2dq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2DQZ256rm [HasVLX]
vcvtps2dq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2DQZ256rmb [HasVLX]
vcvtps2dq {src{1to8}, dst|dst, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2DQZ256rmbk [HasVLX]
vcvtps2dq {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPS2DQZ256rmbkz [HasVLX]
vcvtps2dq {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2DQZ256rmk [HasVLX]
vcvtps2dq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPS2DQZ256rmkz [HasVLX]
vcvtps2dq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2DQZ256rr [HasVLX]
vcvtps2dq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2DQZ256rrk [HasVLX]
vcvtps2dq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPS2DQZ256rrkz [HasVLX]
vcvtps2dq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2PHZ128mr [HasVLX]
vcvtps2ph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException, mayStore |
VCVTPS2PHZ128mrk [HasVLX]
vcvtps2ph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException, mayStore |
VCVTPS2PHZ128rr [HasVLX]
vcvtps2ph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2PHZ128rrk [HasVLX]
vcvtps2ph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPS2PHZ128rrkz [HasVLX]
vcvtps2ph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2PHZ256mr [HasVLX]
vcvtps2ph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException, mayStore |
VCVTPS2PHZ256mrk [HasVLX]
vcvtps2ph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException, mayStore |
VCVTPS2PHZ256rr [HasVLX]
vcvtps2ph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2PHZ256rrk [HasVLX]
vcvtps2ph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPS2PHZ256rrkz [HasVLX]
vcvtps2ph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2UDQZ128rm [HasVLX]
vcvtps2udq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2UDQZ128rmb [HasVLX]
vcvtps2udq {src{1to4}, dst|dst, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2UDQZ128rmbk [HasVLX]
vcvtps2udq {src{1to4}, dst {mask}|dst {mask}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPS2UDQZ128rmbkz [HasVLX]
vcvtps2udq {src{1to4}, dst {mask} {z}|dst {mask} {z}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2UDQZ128rmk [HasVLX]
vcvtps2udq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPS2UDQZ128rmkz [HasVLX]
vcvtps2udq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2UDQZ128rr [HasVLX]
vcvtps2udq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2UDQZ128rrk [HasVLX]
vcvtps2udq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPS2UDQZ128rrkz [HasVLX]
vcvtps2udq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2UDQZ256rm [HasVLX]
vcvtps2udq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2UDQZ256rmb [HasVLX]
vcvtps2udq {src{1to8}, dst|dst, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2UDQZ256rmbk [HasVLX]
vcvtps2udq {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPS2UDQZ256rmbkz [HasVLX]
vcvtps2udq {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2UDQZ256rmk [HasVLX]
vcvtps2udq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPS2UDQZ256rmkz [HasVLX]
vcvtps2udq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2UDQZ256rr [HasVLX]
vcvtps2udq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2UDQZ256rrk [HasVLX]
vcvtps2udq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPS2UDQZ256rrkz [HasVLX]
vcvtps2udq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2DQZ128rm [HasVLX]
vcvttpd2dq{x} {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2DQZ128rmb [HasVLX]
vcvttpd2dq {src{1to2}, dst|dst, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2DQZ128rmbk [HasVLX]
vcvttpd2dq {src{1to2}, dst {mask}|dst {mask}, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPD2DQZ128rmbkz [HasVLX]
vcvttpd2dq {src{1to2}, dst {mask} {z}|dst {mask} {z}, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2DQZ128rmk [HasVLX]
vcvttpd2dq{x} {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPD2DQZ128rmkz [HasVLX]
vcvttpd2dq{x} {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2DQZ128rr [HasVLX]
vcvttpd2dq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2DQZ128rrk [HasVLX]
vcvttpd2dq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPD2DQZ128rrkz [HasVLX]
vcvttpd2dq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2DQZ256rm [HasVLX]
vcvttpd2dq{y} {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2DQZ256rmb [HasVLX]
vcvttpd2dq {src{1to4}, dst|dst, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2DQZ256rmbk [HasVLX]
vcvttpd2dq {src{1to4}, dst {mask}|dst {mask}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPD2DQZ256rmbkz [HasVLX]
vcvttpd2dq {src{1to4}, dst {mask} {z}|dst {mask} {z}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2DQZ256rmk [HasVLX]
vcvttpd2dq{y} {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPD2DQZ256rmkz [HasVLX]
vcvttpd2dq{y} {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2DQZ256rr [HasVLX]
vcvttpd2dq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2DQZ256rrk [HasVLX]
vcvttpd2dq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPD2DQZ256rrkz [HasVLX]
vcvttpd2dq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2UDQZ128rm [HasVLX]
vcvttpd2udq{x} {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2UDQZ128rmb [HasVLX]
vcvttpd2udq {src{1to2}, dst|dst, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2UDQZ128rmbk [HasVLX]
vcvttpd2udq {src{1to2}, dst {mask}|dst {mask}, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPD2UDQZ128rmbkz [HasVLX]
vcvttpd2udq {src{1to2}, dst {mask} {z}|dst {mask} {z}, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2UDQZ128rmk [HasVLX]
vcvttpd2udq{x} {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPD2UDQZ128rmkz [HasVLX]
vcvttpd2udq{x} {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2UDQZ128rr [HasVLX]
vcvttpd2udq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2UDQZ128rrk [HasVLX]
vcvttpd2udq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPD2UDQZ128rrkz [HasVLX]
vcvttpd2udq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2UDQZ256rm [HasVLX]
vcvttpd2udq{y} {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2UDQZ256rmb [HasVLX]
vcvttpd2udq {src{1to4}, dst|dst, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2UDQZ256rmbk [HasVLX]
vcvttpd2udq {src{1to4}, dst {mask}|dst {mask}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPD2UDQZ256rmbkz [HasVLX]
vcvttpd2udq {src{1to4}, dst {mask} {z}|dst {mask} {z}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2UDQZ256rmk [HasVLX]
vcvttpd2udq{y} {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPD2UDQZ256rmkz [HasVLX]
vcvttpd2udq{y} {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2UDQZ256rr [HasVLX]
vcvttpd2udq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2UDQZ256rrk [HasVLX]
vcvttpd2udq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPD2UDQZ256rrkz [HasVLX]
vcvttpd2udq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2DQZ128rm [HasVLX]
vcvttps2dq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2DQZ128rmb [HasVLX]
vcvttps2dq {src{1to4}, dst|dst, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2DQZ128rmbk [HasVLX]
vcvttps2dq {src{1to4}, dst {mask}|dst {mask}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPS2DQZ128rmbkz [HasVLX]
vcvttps2dq {src{1to4}, dst {mask} {z}|dst {mask} {z}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2DQZ128rmk [HasVLX]
vcvttps2dq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPS2DQZ128rmkz [HasVLX]
vcvttps2dq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2DQZ128rr [HasVLX]
vcvttps2dq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2DQZ128rrk [HasVLX]
vcvttps2dq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPS2DQZ128rrkz [HasVLX]
vcvttps2dq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2DQZ256rm [HasVLX]
vcvttps2dq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2DQZ256rmb [HasVLX]
vcvttps2dq {src{1to8}, dst|dst, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2DQZ256rmbk [HasVLX]
vcvttps2dq {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPS2DQZ256rmbkz [HasVLX]
vcvttps2dq {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2DQZ256rmk [HasVLX]
vcvttps2dq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPS2DQZ256rmkz [HasVLX]
vcvttps2dq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2DQZ256rr [HasVLX]
vcvttps2dq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2DQZ256rrk [HasVLX]
vcvttps2dq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPS2DQZ256rrkz [HasVLX]
vcvttps2dq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2UDQZ128rm [HasVLX]
vcvttps2udq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2UDQZ128rmb [HasVLX]
vcvttps2udq {src{1to4}, dst|dst, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2UDQZ128rmbk [HasVLX]
vcvttps2udq {src{1to4}, dst {mask}|dst {mask}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPS2UDQZ128rmbkz [HasVLX]
vcvttps2udq {src{1to4}, dst {mask} {z}|dst {mask} {z}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2UDQZ128rmk [HasVLX]
vcvttps2udq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPS2UDQZ128rmkz [HasVLX]
vcvttps2udq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2UDQZ128rr [HasVLX]
vcvttps2udq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2UDQZ128rrk [HasVLX]
vcvttps2udq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPS2UDQZ128rrkz [HasVLX]
vcvttps2udq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2UDQZ256rm [HasVLX]
vcvttps2udq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2UDQZ256rmb [HasVLX]
vcvttps2udq {src{1to8}, dst|dst, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2UDQZ256rmbk [HasVLX]
vcvttps2udq {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPS2UDQZ256rmbkz [HasVLX]
vcvttps2udq {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2UDQZ256rmk [HasVLX]
vcvttps2udq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPS2UDQZ256rmkz [HasVLX]
vcvttps2udq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2UDQZ256rr [HasVLX]
vcvttps2udq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2UDQZ256rrk [HasVLX]
vcvttps2udq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPS2UDQZ256rrkz [HasVLX]
vcvttps2udq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTUDQ2PDZ128rm [HasVLX]
vcvtudq2pd {src, dst|dst, src}
VCVTUDQ2PDZ128rmb [HasVLX]
vcvtudq2pd {src{1to2}, dst|dst, src{1to2}}
VCVTUDQ2PDZ128rmbk [HasVLX]
vcvtudq2pd {src{1to2}, dst {mask}|dst {mask}, src{1to2}}
|
Note
|
Constraints: src0 = dst |
VCVTUDQ2PDZ128rmbkz [HasVLX]
vcvtudq2pd {src{1to2}, dst {mask} {z}|dst {mask} {z}, src{1to2}}
VCVTUDQ2PDZ128rmk [HasVLX]
vcvtudq2pd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTUDQ2PDZ128rmkz [HasVLX]
vcvtudq2pd {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTUDQ2PDZ128rr [HasVLX]
vcvtudq2pd {src, dst|dst, src}
VCVTUDQ2PDZ128rrk [HasVLX]
vcvtudq2pd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTUDQ2PDZ128rrkz [HasVLX]
vcvtudq2pd {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTUDQ2PDZ256rm [HasVLX]
vcvtudq2pd {src, dst|dst, src}
VCVTUDQ2PDZ256rmb [HasVLX]
vcvtudq2pd {src{1to4}, dst|dst, src{1to4}}
VCVTUDQ2PDZ256rmbk [HasVLX]
vcvtudq2pd {src{1to4}, dst {mask}|dst {mask}, src{1to4}}
|
Note
|
Constraints: src0 = dst |
VCVTUDQ2PDZ256rmbkz [HasVLX]
vcvtudq2pd {src{1to4}, dst {mask} {z}|dst {mask} {z}, src{1to4}}
VCVTUDQ2PDZ256rmk [HasVLX]
vcvtudq2pd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTUDQ2PDZ256rmkz [HasVLX]
vcvtudq2pd {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTUDQ2PDZ256rr [HasVLX]
vcvtudq2pd {src, dst|dst, src}
VCVTUDQ2PDZ256rrk [HasVLX]
vcvtudq2pd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTUDQ2PDZ256rrkz [HasVLX]
vcvtudq2pd {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTUDQ2PSZ128rm [HasVLX]
vcvtudq2ps {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTUDQ2PSZ128rmb [HasVLX]
vcvtudq2ps {src{1to4}, dst|dst, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTUDQ2PSZ128rmbk [HasVLX]
vcvtudq2ps {src{1to4}, dst {mask}|dst {mask}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTUDQ2PSZ128rmbkz [HasVLX]
vcvtudq2ps {src{1to4}, dst {mask} {z}|dst {mask} {z}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTUDQ2PSZ128rmk [HasVLX]
vcvtudq2ps {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTUDQ2PSZ128rmkz [HasVLX]
vcvtudq2ps {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTUDQ2PSZ128rr [HasVLX]
vcvtudq2ps {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTUDQ2PSZ128rrk [HasVLX]
vcvtudq2ps {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTUDQ2PSZ128rrkz [HasVLX]
vcvtudq2ps {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTUDQ2PSZ256rm [HasVLX]
vcvtudq2ps {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTUDQ2PSZ256rmb [HasVLX]
vcvtudq2ps {src{1to8}, dst|dst, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTUDQ2PSZ256rmbk [HasVLX]
vcvtudq2ps {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTUDQ2PSZ256rmbkz [HasVLX]
vcvtudq2ps {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTUDQ2PSZ256rmk [HasVLX]
vcvtudq2ps {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTUDQ2PSZ256rmkz [HasVLX]
vcvtudq2ps {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTUDQ2PSZ256rr [HasVLX]
vcvtudq2ps {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTUDQ2PSZ256rrk [HasVLX]
vcvtudq2ps {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTUDQ2PSZ256rrkz [HasVLX]
vcvtudq2ps {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VEXTRACTF32X4Z256mri [HasVLX]
vextractf32x4 {idx, src1, dst|dst, src1, idx}
VEXTRACTF32X4Z256mrik [HasVLX]
vextractf32x4 {idx, src1, dst {mask}|dst {mask}, src1, idx}
|
Note
|
Properties: mayStore |
VEXTRACTF32X4Z256rri [HasVLX]
vextractf32x4 {idx, src1, dst|dst, src1, idx}
VEXTRACTF32X4Z256rrik [HasVLX]
vextractf32x4 {idx, src1, dst {mask}|dst {mask}, src1, idx}
|
Note
|
Constraints: src0 = dst |
VEXTRACTF32X4Z256rrikz [HasVLX]
vextractf32x4 {idx, src1, dst {mask} {z}|dst {mask} {z}, src1, idx}
VEXTRACTI32X4Z256mri [HasVLX]
vextracti32x4 {idx, src1, dst|dst, src1, idx}
VEXTRACTI32X4Z256mrik [HasVLX]
vextracti32x4 {idx, src1, dst {mask}|dst {mask}, src1, idx}
|
Note
|
Properties: mayStore |
VEXTRACTI32X4Z256rri [HasVLX]
vextracti32x4 {idx, src1, dst|dst, src1, idx}
VEXTRACTI32X4Z256rrik [HasVLX]
vextracti32x4 {idx, src1, dst {mask}|dst {mask}, src1, idx}
|
Note
|
Constraints: src0 = dst |
VEXTRACTI32X4Z256rrikz [HasVLX]
vextracti32x4 {idx, src1, dst {mask} {z}|dst {mask} {z}, src1, idx}
VGATHERDPDZ128rm [HasVLX]
vgatherdpd {src2, dst {mask}|dst {mask}, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst, src1 = dst, mask = mask_wb |
VGATHERDPDZ256rm [HasVLX]
vgatherdpd {src2, dst {mask}|dst {mask}, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst, src1 = dst, mask = mask_wb |
VGATHERDPSZ128rm [HasVLX]
vgatherdps {src2, dst {mask}|dst {mask}, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst, src1 = dst, mask = mask_wb |
VGATHERDPSZ256rm [HasVLX]
vgatherdps {src2, dst {mask}|dst {mask}, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst, src1 = dst, mask = mask_wb |
VGATHERQPDZ128rm [HasVLX]
vgatherqpd {src2, dst {mask}|dst {mask}, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst, src1 = dst, mask = mask_wb |
VGATHERQPDZ256rm [HasVLX]
vgatherqpd {src2, dst {mask}|dst {mask}, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst, src1 = dst, mask = mask_wb |
VGATHERQPSZ128rm [HasVLX]
vgatherqps {src2, dst {mask}|dst {mask}, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst, src1 = dst, mask = mask_wb |
VGATHERQPSZ256rm [HasVLX]
vgatherqps {src2, dst {mask}|dst {mask}, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst, src1 = dst, mask = mask_wb |
VGETEXPPDZ128m [HasVLX]
vgetexppd {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VGETEXPPDZ128mb [HasVLX]
vgetexppd {src{1to2}, dst|dst, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
VGETEXPPDZ128mbk [HasVLX]
vgetexppd {src{1to2}, dst {mask}|dst {mask}, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VGETEXPPDZ128mbkz [HasVLX]
vgetexppd {src{1to2}, dst {mask} {z}|dst {mask} {z}, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
VGETEXPPDZ128mk [HasVLX]
vgetexppd {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VGETEXPPDZ128mkz [HasVLX]
vgetexppd {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VGETEXPPDZ128r [HasVLX]
vgetexppd {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VGETEXPPDZ128rk [HasVLX]
vgetexppd {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VGETEXPPDZ128rkz [HasVLX]
vgetexppd {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VGETEXPPDZ256m [HasVLX]
vgetexppd {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VGETEXPPDZ256mb [HasVLX]
vgetexppd {src{1to4}, dst|dst, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VGETEXPPDZ256mbk [HasVLX]
vgetexppd {src{1to4}, dst {mask}|dst {mask}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VGETEXPPDZ256mbkz [HasVLX]
vgetexppd {src{1to4}, dst {mask} {z}|dst {mask} {z}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VGETEXPPDZ256mk [HasVLX]
vgetexppd {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VGETEXPPDZ256mkz [HasVLX]
vgetexppd {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VGETEXPPDZ256r [HasVLX]
vgetexppd {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VGETEXPPDZ256rk [HasVLX]
vgetexppd {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VGETEXPPDZ256rkz [HasVLX]
vgetexppd {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VGETEXPPSZ128m [HasVLX]
vgetexpps {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VGETEXPPSZ128mb [HasVLX]
vgetexpps {src{1to4}, dst|dst, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VGETEXPPSZ128mbk [HasVLX]
vgetexpps {src{1to4}, dst {mask}|dst {mask}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VGETEXPPSZ128mbkz [HasVLX]
vgetexpps {src{1to4}, dst {mask} {z}|dst {mask} {z}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VGETEXPPSZ128mk [HasVLX]
vgetexpps {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VGETEXPPSZ128mkz [HasVLX]
vgetexpps {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VGETEXPPSZ128r [HasVLX]
vgetexpps {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VGETEXPPSZ128rk [HasVLX]
vgetexpps {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VGETEXPPSZ128rkz [HasVLX]
vgetexpps {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VGETEXPPSZ256m [HasVLX]
vgetexpps {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VGETEXPPSZ256mb [HasVLX]
vgetexpps {src{1to8}, dst|dst, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VGETEXPPSZ256mbk [HasVLX]
vgetexpps {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VGETEXPPSZ256mbkz [HasVLX]
vgetexpps {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VGETEXPPSZ256mk [HasVLX]
vgetexpps {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VGETEXPPSZ256mkz [HasVLX]
vgetexpps {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VGETEXPPSZ256r [HasVLX]
vgetexpps {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VGETEXPPSZ256rk [HasVLX]
vgetexpps {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VGETEXPPSZ256rkz [HasVLX]
vgetexpps {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VINSERTF32X4Z256rmi [HasVLX]
vinsertf32x4 {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayLoad |
VINSERTF32X4Z256rmik [HasVLX]
vinsertf32x4 {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VINSERTF32X4Z256rmikz [HasVLX]
vinsertf32x4 {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
|
Note
|
Properties: mayLoad |
VINSERTF32X4Z256rri [HasVLX]
vinsertf32x4 {src3, src2, src1, dst|dst, src1, src2, src3}
VINSERTF32X4Z256rrik [HasVLX]
vinsertf32x4 {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VINSERTF32X4Z256rrikz [HasVLX]
vinsertf32x4 {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VINSERTI32X4Z256rmi [HasVLX]
vinserti32x4 {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayLoad |
VINSERTI32X4Z256rmik [HasVLX]
vinserti32x4 {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VINSERTI32X4Z256rmikz [HasVLX]
vinserti32x4 {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
|
Note
|
Properties: mayLoad |
VINSERTI32X4Z256rri [HasVLX]
vinserti32x4 {src3, src2, src1, dst|dst, src1, src2, src3}
VINSERTI32X4Z256rrik [HasVLX]
vinserti32x4 {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VINSERTI32X4Z256rrikz [HasVLX]
vinserti32x4 {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VMOVNTDQAZ128rm [HasVLX]
vmovntdqa {src, dst|dst, src}
VMOVNTDQAZ256rm [HasVLX]
vmovntdqa {src, dst|dst, src}
VPBLENDMDZ128rm [HasVLX]
vpblendmd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VPBLENDMDZ128rmb [HasVLX]
vpblendmd {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
|
Note
|
Properties: mayLoad |
VPBLENDMDZ128rmbk [HasVLX]
vpblendmd {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Properties: mayLoad |
VPBLENDMDZ128rmbkz [HasVLX]
vpblendmd {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
|
Note
|
Properties: mayLoad |
VPBLENDMDZ128rmk [HasVLX]
vpblendmd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
VPBLENDMDZ128rmkz [HasVLX]
vpblendmd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VPBLENDMDZ128rr [HasVLX]
vpblendmd {src2, src1, dst|dst, src1, src2}
VPBLENDMDZ128rrk [HasVLX]
vpblendmd {src2, src1, dst {mask}|dst {mask}, src1, src2}
VPBLENDMDZ128rrkz [HasVLX]
vpblendmd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPBLENDMDZ256rm [HasVLX]
vpblendmd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VPBLENDMDZ256rmb [HasVLX]
vpblendmd {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
VPBLENDMDZ256rmbk [HasVLX]
vpblendmd {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
VPBLENDMDZ256rmbkz [HasVLX]
vpblendmd {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
VPBLENDMDZ256rmk [HasVLX]
vpblendmd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
VPBLENDMDZ256rmkz [HasVLX]
vpblendmd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VPBLENDMDZ256rr [HasVLX]
vpblendmd {src2, src1, dst|dst, src1, src2}
VPBLENDMDZ256rrk [HasVLX]
vpblendmd {src2, src1, dst {mask}|dst {mask}, src1, src2}
VPBLENDMDZ256rrkz [HasVLX]
vpblendmd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPBLENDMQZ128rm [HasVLX]
vpblendmq {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VPBLENDMQZ128rmb [HasVLX]
vpblendmq {src2{1to2}, src1, dst|dst, src1, src2{1to2}}
|
Note
|
Properties: mayLoad |
VPBLENDMQZ128rmbk [HasVLX]
vpblendmq {src2{1to2}, src1, dst {mask}|dst {mask}, src1, src2{1to2}}
|
Note
|
Properties: mayLoad |
VPBLENDMQZ128rmbkz [HasVLX]
vpblendmq {src2{1to2}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to2}}
|
Note
|
Properties: mayLoad |
VPBLENDMQZ128rmk [HasVLX]
vpblendmq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
VPBLENDMQZ128rmkz [HasVLX]
vpblendmq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VPBLENDMQZ128rr [HasVLX]
vpblendmq {src2, src1, dst|dst, src1, src2}
VPBLENDMQZ128rrk [HasVLX]
vpblendmq {src2, src1, dst {mask}|dst {mask}, src1, src2}
VPBLENDMQZ128rrkz [HasVLX]
vpblendmq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPBLENDMQZ256rm [HasVLX]
vpblendmq {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VPBLENDMQZ256rmb [HasVLX]
vpblendmq {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
|
Note
|
Properties: mayLoad |
VPBLENDMQZ256rmbk [HasVLX]
vpblendmq {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Properties: mayLoad |
VPBLENDMQZ256rmbkz [HasVLX]
vpblendmq {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
|
Note
|
Properties: mayLoad |
VPBLENDMQZ256rmk [HasVLX]
vpblendmq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
VPBLENDMQZ256rmkz [HasVLX]
vpblendmq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VPBLENDMQZ256rr [HasVLX]
vpblendmq {src2, src1, dst|dst, src1, src2}
VPBLENDMQZ256rrk [HasVLX]
vpblendmq {src2, src1, dst {mask}|dst {mask}, src1, src2}
VPBLENDMQZ256rrkz [HasVLX]
vpblendmq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPERMI2DZ128rm [HasVLX]
vpermi2d {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2DZ128rmb [HasVLX]
vpermi2d {src3{1to4}, src2, dst|dst, src2, src3{1to4}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2DZ128rmbk [HasVLX]
vpermi2d {src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2DZ128rmbkz [HasVLX]
vpermi2d {src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2DZ128rmk [HasVLX]
vpermi2d {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2DZ128rmkz [HasVLX]
vpermi2d {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2DZ128rr [HasVLX]
vpermi2d {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMI2DZ128rrk [HasVLX]
vpermi2d {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMI2DZ128rrkz [HasVLX]
vpermi2d {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMI2DZ256rm [HasVLX]
vpermi2d {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2DZ256rmb [HasVLX]
vpermi2d {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2DZ256rmbk [HasVLX]
vpermi2d {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2DZ256rmbkz [HasVLX]
vpermi2d {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2DZ256rmk [HasVLX]
vpermi2d {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2DZ256rmkz [HasVLX]
vpermi2d {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2DZ256rr [HasVLX]
vpermi2d {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMI2DZ256rrk [HasVLX]
vpermi2d {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMI2DZ256rrkz [HasVLX]
vpermi2d {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMI2PDZ128rm [HasVLX]
vpermi2pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2PDZ128rmb [HasVLX]
vpermi2pd {src3{1to2}, src2, dst|dst, src2, src3{1to2}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2PDZ128rmbk [HasVLX]
vpermi2pd {src3{1to2}, src2, dst {mask}|dst {mask}, src2, src3{1to2}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2PDZ128rmbkz [HasVLX]
vpermi2pd {src3{1to2}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to2}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2PDZ128rmk [HasVLX]
vpermi2pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2PDZ128rmkz [HasVLX]
vpermi2pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2PDZ128rr [HasVLX]
vpermi2pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMI2PDZ128rrk [HasVLX]
vpermi2pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMI2PDZ128rrkz [HasVLX]
vpermi2pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMI2PDZ256rm [HasVLX]
vpermi2pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2PDZ256rmb [HasVLX]
vpermi2pd {src3{1to4}, src2, dst|dst, src2, src3{1to4}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2PDZ256rmbk [HasVLX]
vpermi2pd {src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2PDZ256rmbkz [HasVLX]
vpermi2pd {src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2PDZ256rmk [HasVLX]
vpermi2pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2PDZ256rmkz [HasVLX]
vpermi2pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2PDZ256rr [HasVLX]
vpermi2pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMI2PDZ256rrk [HasVLX]
vpermi2pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMI2PDZ256rrkz [HasVLX]
vpermi2pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMI2PSZ128rm [HasVLX]
vpermi2ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2PSZ128rmb [HasVLX]
vpermi2ps {src3{1to4}, src2, dst|dst, src2, src3{1to4}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2PSZ128rmbk [HasVLX]
vpermi2ps {src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2PSZ128rmbkz [HasVLX]
vpermi2ps {src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2PSZ128rmk [HasVLX]
vpermi2ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2PSZ128rmkz [HasVLX]
vpermi2ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2PSZ128rr [HasVLX]
vpermi2ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMI2PSZ128rrk [HasVLX]
vpermi2ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMI2PSZ128rrkz [HasVLX]
vpermi2ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMI2PSZ256rm [HasVLX]
vpermi2ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2PSZ256rmb [HasVLX]
vpermi2ps {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2PSZ256rmbk [HasVLX]
vpermi2ps {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2PSZ256rmbkz [HasVLX]
vpermi2ps {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2PSZ256rmk [HasVLX]
vpermi2ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2PSZ256rmkz [HasVLX]
vpermi2ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2PSZ256rr [HasVLX]
vpermi2ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMI2PSZ256rrk [HasVLX]
vpermi2ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMI2PSZ256rrkz [HasVLX]
vpermi2ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMI2QZ128rm [HasVLX]
vpermi2q {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2QZ128rmb [HasVLX]
vpermi2q {src3{1to2}, src2, dst|dst, src2, src3{1to2}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2QZ128rmbk [HasVLX]
vpermi2q {src3{1to2}, src2, dst {mask}|dst {mask}, src2, src3{1to2}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2QZ128rmbkz [HasVLX]
vpermi2q {src3{1to2}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to2}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2QZ128rmk [HasVLX]
vpermi2q {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2QZ128rmkz [HasVLX]
vpermi2q {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2QZ128rr [HasVLX]
vpermi2q {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMI2QZ128rrk [HasVLX]
vpermi2q {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMI2QZ128rrkz [HasVLX]
vpermi2q {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMI2QZ256rm [HasVLX]
vpermi2q {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2QZ256rmb [HasVLX]
vpermi2q {src3{1to4}, src2, dst|dst, src2, src3{1to4}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2QZ256rmbk [HasVLX]
vpermi2q {src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2QZ256rmbkz [HasVLX]
vpermi2q {src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2QZ256rmk [HasVLX]
vpermi2q {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2QZ256rmkz [HasVLX]
vpermi2q {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2QZ256rr [HasVLX]
vpermi2q {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMI2QZ256rrk [HasVLX]
vpermi2q {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMI2QZ256rrkz [HasVLX]
vpermi2q {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2DZ128rm [HasVLX]
vpermt2d {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2DZ128rmb [HasVLX]
vpermt2d {src3{1to4}, src2, dst|dst, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPERMT2DZ128rmbk [HasVLX]
vpermt2d {src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPERMT2DZ128rmbkz [HasVLX]
vpermt2d {src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPERMT2DZ128rmk [HasVLX]
vpermt2d {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2DZ128rmkz [HasVLX]
vpermt2d {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2DZ128rr [HasVLX]
vpermt2d {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2DZ128rrk [HasVLX]
vpermt2d {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2DZ128rrkz [HasVLX]
vpermt2d {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2DZ256rm [HasVLX]
vpermt2d {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2DZ256rmb [HasVLX]
vpermt2d {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPERMT2DZ256rmbk [HasVLX]
vpermt2d {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPERMT2DZ256rmbkz [HasVLX]
vpermt2d {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPERMT2DZ256rmk [HasVLX]
vpermt2d {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2DZ256rmkz [HasVLX]
vpermt2d {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2DZ256rr [HasVLX]
vpermt2d {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2DZ256rrk [HasVLX]
vpermt2d {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2DZ256rrkz [HasVLX]
vpermt2d {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2PDZ128rm [HasVLX]
vpermt2pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2PDZ128rmb [HasVLX]
vpermt2pd {src3{1to2}, src2, dst|dst, src2, src3{1to2}}
|
Note
|
Constraints: src1 = dst |
VPERMT2PDZ128rmbk [HasVLX]
vpermt2pd {src3{1to2}, src2, dst {mask}|dst {mask}, src2, src3{1to2}}
|
Note
|
Constraints: src1 = dst |
VPERMT2PDZ128rmbkz [HasVLX]
vpermt2pd {src3{1to2}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to2}}
|
Note
|
Constraints: src1 = dst |
VPERMT2PDZ128rmk [HasVLX]
vpermt2pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2PDZ128rmkz [HasVLX]
vpermt2pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2PDZ128rr [HasVLX]
vpermt2pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2PDZ128rrk [HasVLX]
vpermt2pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2PDZ128rrkz [HasVLX]
vpermt2pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2PDZ256rm [HasVLX]
vpermt2pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2PDZ256rmb [HasVLX]
vpermt2pd {src3{1to4}, src2, dst|dst, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPERMT2PDZ256rmbk [HasVLX]
vpermt2pd {src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPERMT2PDZ256rmbkz [HasVLX]
vpermt2pd {src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPERMT2PDZ256rmk [HasVLX]
vpermt2pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2PDZ256rmkz [HasVLX]
vpermt2pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2PDZ256rr [HasVLX]
vpermt2pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2PDZ256rrk [HasVLX]
vpermt2pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2PDZ256rrkz [HasVLX]
vpermt2pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2PSZ128rm [HasVLX]
vpermt2ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2PSZ128rmb [HasVLX]
vpermt2ps {src3{1to4}, src2, dst|dst, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPERMT2PSZ128rmbk [HasVLX]
vpermt2ps {src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPERMT2PSZ128rmbkz [HasVLX]
vpermt2ps {src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPERMT2PSZ128rmk [HasVLX]
vpermt2ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2PSZ128rmkz [HasVLX]
vpermt2ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2PSZ128rr [HasVLX]
vpermt2ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2PSZ128rrk [HasVLX]
vpermt2ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2PSZ128rrkz [HasVLX]
vpermt2ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2PSZ256rm [HasVLX]
vpermt2ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2PSZ256rmb [HasVLX]
vpermt2ps {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPERMT2PSZ256rmbk [HasVLX]
vpermt2ps {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPERMT2PSZ256rmbkz [HasVLX]
vpermt2ps {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPERMT2PSZ256rmk [HasVLX]
vpermt2ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2PSZ256rmkz [HasVLX]
vpermt2ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2PSZ256rr [HasVLX]
vpermt2ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2PSZ256rrk [HasVLX]
vpermt2ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2PSZ256rrkz [HasVLX]
vpermt2ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2QZ128rm [HasVLX]
vpermt2q {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2QZ128rmb [HasVLX]
vpermt2q {src3{1to2}, src2, dst|dst, src2, src3{1to2}}
|
Note
|
Constraints: src1 = dst |
VPERMT2QZ128rmbk [HasVLX]
vpermt2q {src3{1to2}, src2, dst {mask}|dst {mask}, src2, src3{1to2}}
|
Note
|
Constraints: src1 = dst |
VPERMT2QZ128rmbkz [HasVLX]
vpermt2q {src3{1to2}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to2}}
|
Note
|
Constraints: src1 = dst |
VPERMT2QZ128rmk [HasVLX]
vpermt2q {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2QZ128rmkz [HasVLX]
vpermt2q {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2QZ128rr [HasVLX]
vpermt2q {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2QZ128rrk [HasVLX]
vpermt2q {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2QZ128rrkz [HasVLX]
vpermt2q {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2QZ256rm [HasVLX]
vpermt2q {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2QZ256rmb [HasVLX]
vpermt2q {src3{1to4}, src2, dst|dst, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPERMT2QZ256rmbk [HasVLX]
vpermt2q {src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPERMT2QZ256rmbkz [HasVLX]
vpermt2q {src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPERMT2QZ256rmk [HasVLX]
vpermt2q {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2QZ256rmkz [HasVLX]
vpermt2q {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2QZ256rr [HasVLX]
vpermt2q {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2QZ256rrk [HasVLX]
vpermt2q {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2QZ256rrkz [HasVLX]
vpermt2q {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPGATHERDDZ128rm [HasVLX]
vpgatherdd {src2, dst {mask}|dst {mask}, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst, src1 = dst, mask = mask_wb |
VPGATHERDDZ256rm [HasVLX]
vpgatherdd {src2, dst {mask}|dst {mask}, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst, src1 = dst, mask = mask_wb |
VPGATHERDQZ128rm [HasVLX]
vpgatherdq {src2, dst {mask}|dst {mask}, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst, src1 = dst, mask = mask_wb |
VPGATHERDQZ256rm [HasVLX]
vpgatherdq {src2, dst {mask}|dst {mask}, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst, src1 = dst, mask = mask_wb |
VPGATHERQDZ128rm [HasVLX]
vpgatherqd {src2, dst {mask}|dst {mask}, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst, src1 = dst, mask = mask_wb |
VPGATHERQDZ256rm [HasVLX]
vpgatherqd {src2, dst {mask}|dst {mask}, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst, src1 = dst, mask = mask_wb |
VPGATHERQQZ128rm [HasVLX]
vpgatherqq {src2, dst {mask}|dst {mask}, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst, src1 = dst, mask = mask_wb |
VPGATHERQQZ256rm [HasVLX]
vpgatherqq {src2, dst {mask}|dst {mask}, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst, src1 = dst, mask = mask_wb |
VPSCATTERDDZ128mr [HasVLX]
vpscatterdd {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
|
Note
|
Constraints: mask = mask_wb |
VPSCATTERDDZ256mr [HasVLX]
vpscatterdd {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
|
Note
|
Constraints: mask = mask_wb |
VPSCATTERDQZ128mr [HasVLX]
vpscatterdq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
|
Note
|
Constraints: mask = mask_wb |
VPSCATTERDQZ256mr [HasVLX]
vpscatterdq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
|
Note
|
Constraints: mask = mask_wb |
VPSCATTERQDZ128mr [HasVLX]
vpscatterqd {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
|
Note
|
Constraints: mask = mask_wb |
VPSCATTERQDZ256mr [HasVLX]
vpscatterqd {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
|
Note
|
Constraints: mask = mask_wb |
VPSCATTERQQZ128mr [HasVLX]
vpscatterqq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
|
Note
|
Constraints: mask = mask_wb |
VPSCATTERQQZ256mr [HasVLX]
vpscatterqq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
|
Note
|
Constraints: mask = mask_wb |
VRCP14PDZ128m [HasVLX]
vrcp14pd {src, dst|dst, src}
VRCP14PDZ128mb [HasVLX]
vrcp14pd {src{1to2}, dst|dst, src{1to2}}
VRCP14PDZ128mbk [HasVLX]
vrcp14pd {src{1to2}, dst {mask}|dst {mask}, src{1to2}}
|
Note
|
Constraints: src0 = dst |
VRCP14PDZ128mbkz [HasVLX]
vrcp14pd {src{1to2}, dst {mask} {z}|dst {mask} {z}, src{1to2}}
VRCP14PDZ128mk [HasVLX]
vrcp14pd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VRCP14PDZ128mkz [HasVLX]
vrcp14pd {src, dst {mask} {z}|dst {mask} {z}, src}
VRCP14PDZ128r [HasVLX]
vrcp14pd {src, dst|dst, src}
VRCP14PDZ128rk [HasVLX]
vrcp14pd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VRCP14PDZ128rkz [HasVLX]
vrcp14pd {src, dst {mask} {z}|dst {mask} {z}, src}
VRCP14PDZ256m [HasVLX]
vrcp14pd {src, dst|dst, src}
VRCP14PDZ256mb [HasVLX]
vrcp14pd {src{1to4}, dst|dst, src{1to4}}
VRCP14PDZ256mbk [HasVLX]
vrcp14pd {src{1to4}, dst {mask}|dst {mask}, src{1to4}}
|
Note
|
Constraints: src0 = dst |
VRCP14PDZ256mbkz [HasVLX]
vrcp14pd {src{1to4}, dst {mask} {z}|dst {mask} {z}, src{1to4}}
VRCP14PDZ256mk [HasVLX]
vrcp14pd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VRCP14PDZ256mkz [HasVLX]
vrcp14pd {src, dst {mask} {z}|dst {mask} {z}, src}
VRCP14PDZ256r [HasVLX]
vrcp14pd {src, dst|dst, src}
VRCP14PDZ256rk [HasVLX]
vrcp14pd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VRCP14PDZ256rkz [HasVLX]
vrcp14pd {src, dst {mask} {z}|dst {mask} {z}, src}
VRCP14PSZ128m [HasVLX]
vrcp14ps {src, dst|dst, src}
VRCP14PSZ128mb [HasVLX]
vrcp14ps {src{1to4}, dst|dst, src{1to4}}
VRCP14PSZ128mbk [HasVLX]
vrcp14ps {src{1to4}, dst {mask}|dst {mask}, src{1to4}}
|
Note
|
Constraints: src0 = dst |
VRCP14PSZ128mbkz [HasVLX]
vrcp14ps {src{1to4}, dst {mask} {z}|dst {mask} {z}, src{1to4}}
VRCP14PSZ128mk [HasVLX]
vrcp14ps {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VRCP14PSZ128mkz [HasVLX]
vrcp14ps {src, dst {mask} {z}|dst {mask} {z}, src}
VRCP14PSZ128r [HasVLX]
vrcp14ps {src, dst|dst, src}
VRCP14PSZ128rk [HasVLX]
vrcp14ps {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VRCP14PSZ128rkz [HasVLX]
vrcp14ps {src, dst {mask} {z}|dst {mask} {z}, src}
VRCP14PSZ256m [HasVLX]
vrcp14ps {src, dst|dst, src}
VRCP14PSZ256mb [HasVLX]
vrcp14ps {src{1to8}, dst|dst, src{1to8}}
VRCP14PSZ256mbk [HasVLX]
vrcp14ps {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Constraints: src0 = dst |
VRCP14PSZ256mbkz [HasVLX]
vrcp14ps {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
VRCP14PSZ256mk [HasVLX]
vrcp14ps {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VRCP14PSZ256mkz [HasVLX]
vrcp14ps {src, dst {mask} {z}|dst {mask} {z}, src}
VRCP14PSZ256r [HasVLX]
vrcp14ps {src, dst|dst, src}
VRCP14PSZ256rk [HasVLX]
vrcp14ps {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VRCP14PSZ256rkz [HasVLX]
vrcp14ps {src, dst {mask} {z}|dst {mask} {z}, src}
VRSQRT14PDZ128m [HasVLX]
vrsqrt14pd {src, dst|dst, src}
VRSQRT14PDZ128mb [HasVLX]
vrsqrt14pd {src{1to2}, dst|dst, src{1to2}}
VRSQRT14PDZ128mbk [HasVLX]
vrsqrt14pd {src{1to2}, dst {mask}|dst {mask}, src{1to2}}
|
Note
|
Constraints: src0 = dst |
VRSQRT14PDZ128mbkz [HasVLX]
vrsqrt14pd {src{1to2}, dst {mask} {z}|dst {mask} {z}, src{1to2}}
VRSQRT14PDZ128mk [HasVLX]
vrsqrt14pd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VRSQRT14PDZ128mkz [HasVLX]
vrsqrt14pd {src, dst {mask} {z}|dst {mask} {z}, src}
VRSQRT14PDZ128r [HasVLX]
vrsqrt14pd {src, dst|dst, src}
VRSQRT14PDZ128rk [HasVLX]
vrsqrt14pd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VRSQRT14PDZ128rkz [HasVLX]
vrsqrt14pd {src, dst {mask} {z}|dst {mask} {z}, src}
VRSQRT14PDZ256m [HasVLX]
vrsqrt14pd {src, dst|dst, src}
VRSQRT14PDZ256mb [HasVLX]
vrsqrt14pd {src{1to4}, dst|dst, src{1to4}}
VRSQRT14PDZ256mbk [HasVLX]
vrsqrt14pd {src{1to4}, dst {mask}|dst {mask}, src{1to4}}
|
Note
|
Constraints: src0 = dst |
VRSQRT14PDZ256mbkz [HasVLX]
vrsqrt14pd {src{1to4}, dst {mask} {z}|dst {mask} {z}, src{1to4}}
VRSQRT14PDZ256mk [HasVLX]
vrsqrt14pd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VRSQRT14PDZ256mkz [HasVLX]
vrsqrt14pd {src, dst {mask} {z}|dst {mask} {z}, src}
VRSQRT14PDZ256r [HasVLX]
vrsqrt14pd {src, dst|dst, src}
VRSQRT14PDZ256rk [HasVLX]
vrsqrt14pd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VRSQRT14PDZ256rkz [HasVLX]
vrsqrt14pd {src, dst {mask} {z}|dst {mask} {z}, src}
VRSQRT14PSZ128m [HasVLX]
vrsqrt14ps {src, dst|dst, src}
VRSQRT14PSZ128mb [HasVLX]
vrsqrt14ps {src{1to4}, dst|dst, src{1to4}}
VRSQRT14PSZ128mbk [HasVLX]
vrsqrt14ps {src{1to4}, dst {mask}|dst {mask}, src{1to4}}
|
Note
|
Constraints: src0 = dst |
VRSQRT14PSZ128mbkz [HasVLX]
vrsqrt14ps {src{1to4}, dst {mask} {z}|dst {mask} {z}, src{1to4}}
VRSQRT14PSZ128mk [HasVLX]
vrsqrt14ps {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VRSQRT14PSZ128mkz [HasVLX]
vrsqrt14ps {src, dst {mask} {z}|dst {mask} {z}, src}
VRSQRT14PSZ128r [HasVLX]
vrsqrt14ps {src, dst|dst, src}
VRSQRT14PSZ128rk [HasVLX]
vrsqrt14ps {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VRSQRT14PSZ128rkz [HasVLX]
vrsqrt14ps {src, dst {mask} {z}|dst {mask} {z}, src}
VRSQRT14PSZ256m [HasVLX]
vrsqrt14ps {src, dst|dst, src}
VRSQRT14PSZ256mb [HasVLX]
vrsqrt14ps {src{1to8}, dst|dst, src{1to8}}
VRSQRT14PSZ256mbk [HasVLX]
vrsqrt14ps {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Constraints: src0 = dst |
VRSQRT14PSZ256mbkz [HasVLX]
vrsqrt14ps {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
VRSQRT14PSZ256mk [HasVLX]
vrsqrt14ps {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VRSQRT14PSZ256mkz [HasVLX]
vrsqrt14ps {src, dst {mask} {z}|dst {mask} {z}, src}
VRSQRT14PSZ256r [HasVLX]
vrsqrt14ps {src, dst|dst, src}
VRSQRT14PSZ256rk [HasVLX]
vrsqrt14ps {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VRSQRT14PSZ256rkz [HasVLX]
vrsqrt14ps {src, dst {mask} {z}|dst {mask} {z}, src}
VSCALEFPDZ128rm [HasVLX]
vscalefpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSCALEFPDZ128rmb [HasVLX]
vscalefpd {src2{1to2}, src1, dst|dst, src1, src2{1to2}}
|
Note
|
Properties: mayRaiseFPException |
VSCALEFPDZ128rmbk [HasVLX]
vscalefpd {src2{1to2}, src1, dst {mask}|dst {mask}, src1, src2{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSCALEFPDZ128rmbkz [HasVLX]
vscalefpd {src2{1to2}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to2}}
|
Note
|
Properties: mayRaiseFPException |
VSCALEFPDZ128rmk [HasVLX]
vscalefpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSCALEFPDZ128rmkz [HasVLX]
vscalefpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSCALEFPDZ128rr [HasVLX]
vscalefpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSCALEFPDZ128rrk [HasVLX]
vscalefpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSCALEFPDZ128rrkz [HasVLX]
vscalefpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSCALEFPDZ256rm [HasVLX]
vscalefpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSCALEFPDZ256rmb [HasVLX]
vscalefpd {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VSCALEFPDZ256rmbk [HasVLX]
vscalefpd {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSCALEFPDZ256rmbkz [HasVLX]
vscalefpd {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VSCALEFPDZ256rmk [HasVLX]
vscalefpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSCALEFPDZ256rmkz [HasVLX]
vscalefpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSCALEFPDZ256rr [HasVLX]
vscalefpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSCALEFPDZ256rrk [HasVLX]
vscalefpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSCALEFPDZ256rrkz [HasVLX]
vscalefpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSCALEFPSZ128rm [HasVLX]
vscalefps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSCALEFPSZ128rmb [HasVLX]
vscalefps {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VSCALEFPSZ128rmbk [HasVLX]
vscalefps {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSCALEFPSZ128rmbkz [HasVLX]
vscalefps {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VSCALEFPSZ128rmk [HasVLX]
vscalefps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSCALEFPSZ128rmkz [HasVLX]
vscalefps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSCALEFPSZ128rr [HasVLX]
vscalefps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSCALEFPSZ128rrk [HasVLX]
vscalefps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSCALEFPSZ128rrkz [HasVLX]
vscalefps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSCALEFPSZ256rm [HasVLX]
vscalefps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSCALEFPSZ256rmb [HasVLX]
vscalefps {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VSCALEFPSZ256rmbk [HasVLX]
vscalefps {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSCALEFPSZ256rmbkz [HasVLX]
vscalefps {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VSCALEFPSZ256rmk [HasVLX]
vscalefps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSCALEFPSZ256rmkz [HasVLX]
vscalefps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSCALEFPSZ256rr [HasVLX]
vscalefps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSCALEFPSZ256rrk [HasVLX]
vscalefps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSCALEFPSZ256rrkz [HasVLX]
vscalefps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSCATTERDPDZ128mr [HasVLX]
vscatterdpd {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
|
Note
|
Constraints: mask = mask_wb |
VSCATTERDPDZ256mr [HasVLX]
vscatterdpd {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
|
Note
|
Constraints: mask = mask_wb |
VSCATTERDPSZ128mr [HasVLX]
vscatterdps {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
|
Note
|
Constraints: mask = mask_wb |
VSCATTERDPSZ256mr [HasVLX]
vscatterdps {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
|
Note
|
Constraints: mask = mask_wb |
VSCATTERQPDZ128mr [HasVLX]
vscatterqpd {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
|
Note
|
Constraints: mask = mask_wb |
VSCATTERQPDZ256mr [HasVLX]
vscatterqpd {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
|
Note
|
Constraints: mask = mask_wb |
VSCATTERQPSZ128mr [HasVLX]
vscatterqps {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
|
Note
|
Constraints: mask = mask_wb |
VSCATTERQPSZ256mr [HasVLX]
vscatterqps {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
|
Note
|
Constraints: mask = mask_wb |
VSQRTPDZ128m [HasVLX]
vsqrtpd {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VSQRTPDZ128mb [HasVLX]
vsqrtpd {src{1to2}, dst|dst, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
VSQRTPDZ128mbk [HasVLX]
vsqrtpd {src{1to2}, dst {mask}|dst {mask}, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSQRTPDZ128mbkz [HasVLX]
vsqrtpd {src{1to2}, dst {mask} {z}|dst {mask} {z}, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
VSQRTPDZ128mk [HasVLX]
vsqrtpd {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSQRTPDZ128mkz [HasVLX]
vsqrtpd {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VSQRTPDZ128r [HasVLX]
vsqrtpd {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VSQRTPDZ128rk [HasVLX]
vsqrtpd {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSQRTPDZ128rkz [HasVLX]
vsqrtpd {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VSQRTPDZ256m [HasVLX]
vsqrtpd {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VSQRTPDZ256mb [HasVLX]
vsqrtpd {src{1to4}, dst|dst, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VSQRTPDZ256mbk [HasVLX]
vsqrtpd {src{1to4}, dst {mask}|dst {mask}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSQRTPDZ256mbkz [HasVLX]
vsqrtpd {src{1to4}, dst {mask} {z}|dst {mask} {z}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VSQRTPDZ256mk [HasVLX]
vsqrtpd {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSQRTPDZ256mkz [HasVLX]
vsqrtpd {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VSQRTPDZ256r [HasVLX]
vsqrtpd {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VSQRTPDZ256rk [HasVLX]
vsqrtpd {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSQRTPDZ256rkz [HasVLX]
vsqrtpd {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VSQRTPSZ128m [HasVLX]
vsqrtps {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VSQRTPSZ128mb [HasVLX]
vsqrtps {src{1to4}, dst|dst, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VSQRTPSZ128mbk [HasVLX]
vsqrtps {src{1to4}, dst {mask}|dst {mask}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSQRTPSZ128mbkz [HasVLX]
vsqrtps {src{1to4}, dst {mask} {z}|dst {mask} {z}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VSQRTPSZ128mk [HasVLX]
vsqrtps {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSQRTPSZ128mkz [HasVLX]
vsqrtps {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VSQRTPSZ128r [HasVLX]
vsqrtps {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VSQRTPSZ128rk [HasVLX]
vsqrtps {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSQRTPSZ128rkz [HasVLX]
vsqrtps {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VSQRTPSZ256m [HasVLX]
vsqrtps {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VSQRTPSZ256mb [HasVLX]
vsqrtps {src{1to8}, dst|dst, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VSQRTPSZ256mbk [HasVLX]
vsqrtps {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSQRTPSZ256mbkz [HasVLX]
vsqrtps {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VSQRTPSZ256mk [HasVLX]
vsqrtps {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSQRTPSZ256mkz [HasVLX]
vsqrtps {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VSQRTPSZ256r [HasVLX]
vsqrtps {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VSQRTPSZ256rk [HasVLX]
vsqrtps {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSQRTPSZ256rkz [HasVLX]
vsqrtps {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VADDPDZ128rm [HasVLX, HasAVX512]
vaddpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VADDPDZ128rmb [HasVLX, HasAVX512]
vaddpd {src2{1to2}, src1, dst|dst, src1, src2{1to2}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VADDPDZ128rmbk [HasVLX, HasAVX512]
vaddpd {src2{1to2}, src1, dst {mask}|dst {mask}, src1, src2{1to2}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VADDPDZ128rmbkz [HasVLX, HasAVX512]
vaddpd {src2{1to2}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to2}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VADDPDZ128rmk [HasVLX, HasAVX512]
vaddpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VADDPDZ128rmkz [HasVLX, HasAVX512]
vaddpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VADDPDZ128rr [HasVLX, HasAVX512]
vaddpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VADDPDZ128rrk [HasVLX, HasAVX512]
vaddpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VADDPDZ128rrkz [HasVLX, HasAVX512]
vaddpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VADDPDZ256rm [HasVLX, HasAVX512]
vaddpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VADDPDZ256rmb [HasVLX, HasAVX512]
vaddpd {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VADDPDZ256rmbk [HasVLX, HasAVX512]
vaddpd {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VADDPDZ256rmbkz [HasVLX, HasAVX512]
vaddpd {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VADDPDZ256rmk [HasVLX, HasAVX512]
vaddpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VADDPDZ256rmkz [HasVLX, HasAVX512]
vaddpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VADDPDZ256rr [HasVLX, HasAVX512]
vaddpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VADDPDZ256rrk [HasVLX, HasAVX512]
vaddpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VADDPDZ256rrkz [HasVLX, HasAVX512]
vaddpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VADDPSZ128rm [HasVLX, HasAVX512]
vaddps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VADDPSZ128rmb [HasVLX, HasAVX512]
vaddps {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VADDPSZ128rmbk [HasVLX, HasAVX512]
vaddps {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VADDPSZ128rmbkz [HasVLX, HasAVX512]
vaddps {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VADDPSZ128rmk [HasVLX, HasAVX512]
vaddps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VADDPSZ128rmkz [HasVLX, HasAVX512]
vaddps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VADDPSZ128rr [HasVLX, HasAVX512]
vaddps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VADDPSZ128rrk [HasVLX, HasAVX512]
vaddps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VADDPSZ128rrkz [HasVLX, HasAVX512]
vaddps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VADDPSZ256rm [HasVLX, HasAVX512]
vaddps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VADDPSZ256rmb [HasVLX, HasAVX512]
vaddps {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VADDPSZ256rmbk [HasVLX, HasAVX512]
vaddps {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VADDPSZ256rmbkz [HasVLX, HasAVX512]
vaddps {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VADDPSZ256rmk [HasVLX, HasAVX512]
vaddps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VADDPSZ256rmkz [HasVLX, HasAVX512]
vaddps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VADDPSZ256rr [HasVLX, HasAVX512]
vaddps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VADDPSZ256rrk [HasVLX, HasAVX512]
vaddps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VADDPSZ256rrkz [HasVLX, HasAVX512]
vaddps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VALIGNDZ128rmbi [HasVLX, HasAVX512]
valignd {src3, src2{1to4}, src1, dst|dst, src1, src2{1to4}, src3}
VALIGNDZ128rmbik [HasVLX, HasAVX512]
valignd {src3, src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}, src3}
|
Note
|
Constraints: src0 = dst |
VALIGNDZ128rmbikz [HasVLX, HasAVX512]
valignd {src3, src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}, src3}
VALIGNDZ128rmi [HasVLX, HasAVX512]
valignd {src3, src2, src1, dst|dst, src1, src2, src3}
VALIGNDZ128rmik [HasVLX, HasAVX512]
valignd {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VALIGNDZ128rmikz [HasVLX, HasAVX512]
valignd {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VALIGNDZ128rri [HasVLX, HasAVX512]
valignd {src3, src2, src1, dst|dst, src1, src2, src3}
VALIGNDZ128rrik [HasVLX, HasAVX512]
valignd {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VALIGNDZ128rrikz [HasVLX, HasAVX512]
valignd {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VALIGNDZ256rmbi [HasVLX, HasAVX512]
valignd {src3, src2{1to8}, src1, dst|dst, src1, src2{1to8}, src3}
VALIGNDZ256rmbik [HasVLX, HasAVX512]
valignd {src3, src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}, src3}
|
Note
|
Constraints: src0 = dst |
VALIGNDZ256rmbikz [HasVLX, HasAVX512]
valignd {src3, src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}, src3}
VALIGNDZ256rmi [HasVLX, HasAVX512]
valignd {src3, src2, src1, dst|dst, src1, src2, src3}
VALIGNDZ256rmik [HasVLX, HasAVX512]
valignd {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VALIGNDZ256rmikz [HasVLX, HasAVX512]
valignd {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VALIGNDZ256rri [HasVLX, HasAVX512]
valignd {src3, src2, src1, dst|dst, src1, src2, src3}
VALIGNDZ256rrik [HasVLX, HasAVX512]
valignd {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VALIGNDZ256rrikz [HasVLX, HasAVX512]
valignd {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VALIGNQZ128rmbi [HasVLX, HasAVX512]
valignq {src3, src2{1to2}, src1, dst|dst, src1, src2{1to2}, src3}
VALIGNQZ128rmbik [HasVLX, HasAVX512]
valignq {src3, src2{1to2}, src1, dst {mask}|dst {mask}, src1, src2{1to2}, src3}
|
Note
|
Constraints: src0 = dst |
VALIGNQZ128rmbikz [HasVLX, HasAVX512]
valignq {src3, src2{1to2}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to2}, src3}
VALIGNQZ128rmi [HasVLX, HasAVX512]
valignq {src3, src2, src1, dst|dst, src1, src2, src3}
VALIGNQZ128rmik [HasVLX, HasAVX512]
valignq {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VALIGNQZ128rmikz [HasVLX, HasAVX512]
valignq {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VALIGNQZ128rri [HasVLX, HasAVX512]
valignq {src3, src2, src1, dst|dst, src1, src2, src3}
VALIGNQZ128rrik [HasVLX, HasAVX512]
valignq {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VALIGNQZ128rrikz [HasVLX, HasAVX512]
valignq {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VALIGNQZ256rmbi [HasVLX, HasAVX512]
valignq {src3, src2{1to4}, src1, dst|dst, src1, src2{1to4}, src3}
VALIGNQZ256rmbik [HasVLX, HasAVX512]
valignq {src3, src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}, src3}
|
Note
|
Constraints: src0 = dst |
VALIGNQZ256rmbikz [HasVLX, HasAVX512]
valignq {src3, src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}, src3}
VALIGNQZ256rmi [HasVLX, HasAVX512]
valignq {src3, src2, src1, dst|dst, src1, src2, src3}
VALIGNQZ256rmik [HasVLX, HasAVX512]
valignq {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VALIGNQZ256rmikz [HasVLX, HasAVX512]
valignq {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VALIGNQZ256rri [HasVLX, HasAVX512]
valignq {src3, src2, src1, dst|dst, src1, src2, src3}
VALIGNQZ256rrik [HasVLX, HasAVX512]
valignq {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VALIGNQZ256rrikz [HasVLX, HasAVX512]
valignq {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VCMPPDZ128rmbi [HasVLX, HasAVX512]
vcmppd {cc, src2{1to2}, src1, dst|dst, src1, src2{1to2}, cc}
|
Note
|
Properties: mayRaiseFPException |
VCMPPDZ128rmbik [HasVLX, HasAVX512]
vcmppd {cc, src2{1to2}, src1, dst {mask}|dst {mask}, src1, src2{1to2}, cc}
|
Note
|
Properties: mayRaiseFPException |
VCMPPDZ128rmi [HasVLX, HasAVX512]
vcmppd {cc, src2, src1, dst|dst, src1, src2, cc}
|
Note
|
Properties: mayRaiseFPException |
VCMPPDZ128rmik [HasVLX, HasAVX512]
vcmppd {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
|
Note
|
Properties: mayRaiseFPException |
VCMPPDZ128rri [HasVLX, HasAVX512]
vcmppd {cc, src2, src1, dst|dst, src1, src2, cc}
|
Note
|
Properties: mayRaiseFPException |
VCMPPDZ128rrik [HasVLX, HasAVX512]
vcmppd {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
|
Note
|
Properties: mayRaiseFPException |
VCMPPDZ256rmbi [HasVLX, HasAVX512]
vcmppd {cc, src2{1to4}, src1, dst|dst, src1, src2{1to4}, cc}
|
Note
|
Properties: mayRaiseFPException |
VCMPPDZ256rmbik [HasVLX, HasAVX512]
vcmppd {cc, src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}, cc}
|
Note
|
Properties: mayRaiseFPException |
VCMPPDZ256rmi [HasVLX, HasAVX512]
vcmppd {cc, src2, src1, dst|dst, src1, src2, cc}
|
Note
|
Properties: mayRaiseFPException |
VCMPPDZ256rmik [HasVLX, HasAVX512]
vcmppd {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
|
Note
|
Properties: mayRaiseFPException |
VCMPPDZ256rri [HasVLX, HasAVX512]
vcmppd {cc, src2, src1, dst|dst, src1, src2, cc}
|
Note
|
Properties: mayRaiseFPException |
VCMPPDZ256rrik [HasVLX, HasAVX512]
vcmppd {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
|
Note
|
Properties: mayRaiseFPException |
VCMPPSZ128rmbi [HasVLX, HasAVX512]
vcmpps {cc, src2{1to4}, src1, dst|dst, src1, src2{1to4}, cc}
|
Note
|
Properties: mayRaiseFPException |
VCMPPSZ128rmbik [HasVLX, HasAVX512]
vcmpps {cc, src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}, cc}
|
Note
|
Properties: mayRaiseFPException |
VCMPPSZ128rmi [HasVLX, HasAVX512]
vcmpps {cc, src2, src1, dst|dst, src1, src2, cc}
|
Note
|
Properties: mayRaiseFPException |
VCMPPSZ128rmik [HasVLX, HasAVX512]
vcmpps {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
|
Note
|
Properties: mayRaiseFPException |
VCMPPSZ128rri [HasVLX, HasAVX512]
vcmpps {cc, src2, src1, dst|dst, src1, src2, cc}
|
Note
|
Properties: mayRaiseFPException |
VCMPPSZ128rrik [HasVLX, HasAVX512]
vcmpps {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
|
Note
|
Properties: mayRaiseFPException |
VCMPPSZ256rmbi [HasVLX, HasAVX512]
vcmpps {cc, src2{1to8}, src1, dst|dst, src1, src2{1to8}, cc}
|
Note
|
Properties: mayRaiseFPException |
VCMPPSZ256rmbik [HasVLX, HasAVX512]
vcmpps {cc, src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}, cc}
|
Note
|
Properties: mayRaiseFPException |
VCMPPSZ256rmi [HasVLX, HasAVX512]
vcmpps {cc, src2, src1, dst|dst, src1, src2, cc}
|
Note
|
Properties: mayRaiseFPException |
VCMPPSZ256rmik [HasVLX, HasAVX512]
vcmpps {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
|
Note
|
Properties: mayRaiseFPException |
VCMPPSZ256rri [HasVLX, HasAVX512]
vcmpps {cc, src2, src1, dst|dst, src1, src2, cc}
|
Note
|
Properties: mayRaiseFPException |
VCMPPSZ256rrik [HasVLX, HasAVX512]
vcmpps {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
|
Note
|
Properties: mayRaiseFPException |
VCOMPRESSPDZ128mr [HasVLX, HasAVX512]
vcompresspd {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VCOMPRESSPDZ128mrk [HasVLX, HasAVX512]
vcompresspd {src, dst {mask}|dst {mask}, src}
VCOMPRESSPDZ128rr [HasVLX, HasAVX512]
vcompresspd {src1, dst|dst, src1}
VCOMPRESSPDZ128rrk [HasVLX, HasAVX512]
vcompresspd {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VCOMPRESSPDZ128rrkz [HasVLX, HasAVX512]
vcompresspd {src1, dst {mask} {z}|dst {mask} {z}, src1}
VCOMPRESSPDZ256mr [HasVLX, HasAVX512]
vcompresspd {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VCOMPRESSPDZ256mrk [HasVLX, HasAVX512]
vcompresspd {src, dst {mask}|dst {mask}, src}
VCOMPRESSPDZ256rr [HasVLX, HasAVX512]
vcompresspd {src1, dst|dst, src1}
VCOMPRESSPDZ256rrk [HasVLX, HasAVX512]
vcompresspd {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VCOMPRESSPDZ256rrkz [HasVLX, HasAVX512]
vcompresspd {src1, dst {mask} {z}|dst {mask} {z}, src1}
VCOMPRESSPSZ128mr [HasVLX, HasAVX512]
vcompressps {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VCOMPRESSPSZ128mrk [HasVLX, HasAVX512]
vcompressps {src, dst {mask}|dst {mask}, src}
VCOMPRESSPSZ128rr [HasVLX, HasAVX512]
vcompressps {src1, dst|dst, src1}
VCOMPRESSPSZ128rrk [HasVLX, HasAVX512]
vcompressps {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VCOMPRESSPSZ128rrkz [HasVLX, HasAVX512]
vcompressps {src1, dst {mask} {z}|dst {mask} {z}, src1}
VCOMPRESSPSZ256mr [HasVLX, HasAVX512]
vcompressps {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VCOMPRESSPSZ256mrk [HasVLX, HasAVX512]
vcompressps {src, dst {mask}|dst {mask}, src}
VCOMPRESSPSZ256rr [HasVLX, HasAVX512]
vcompressps {src1, dst|dst, src1}
VCOMPRESSPSZ256rrk [HasVLX, HasAVX512]
vcompressps {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VCOMPRESSPSZ256rrkz [HasVLX, HasAVX512]
vcompressps {src1, dst {mask} {z}|dst {mask} {z}, src1}
VCVTPD2PSZ128rm [HasVLX, HasAVX512]
vcvtpd2ps{x} {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2PSZ128rmb [HasVLX, HasAVX512]
vcvtpd2ps {src{1to2}, dst|dst, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2PSZ128rmbk [HasVLX, HasAVX512]
vcvtpd2ps {src{1to2}, dst {mask}|dst {mask}, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPD2PSZ128rmbkz [HasVLX, HasAVX512]
vcvtpd2ps {src{1to2}, dst {mask} {z}|dst {mask} {z}, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2PSZ128rmk [HasVLX, HasAVX512]
vcvtpd2ps{x} {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPD2PSZ128rmkz [HasVLX, HasAVX512]
vcvtpd2ps{x} {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2PSZ128rr [HasVLX, HasAVX512]
vcvtpd2ps {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2PSZ128rrk [HasVLX, HasAVX512]
vcvtpd2ps {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPD2PSZ128rrkz [HasVLX, HasAVX512]
vcvtpd2ps {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2PSZ256rm [HasVLX, HasAVX512]
vcvtpd2ps{y} {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2PSZ256rmb [HasVLX, HasAVX512]
vcvtpd2ps {src{1to4}, dst|dst, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2PSZ256rmbk [HasVLX, HasAVX512]
vcvtpd2ps {src{1to4}, dst {mask}|dst {mask}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPD2PSZ256rmbkz [HasVLX, HasAVX512]
vcvtpd2ps {src{1to4}, dst {mask} {z}|dst {mask} {z}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2PSZ256rmk [HasVLX, HasAVX512]
vcvtpd2ps{y} {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPD2PSZ256rmkz [HasVLX, HasAVX512]
vcvtpd2ps{y} {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2PSZ256rr [HasVLX, HasAVX512]
vcvtpd2ps {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2PSZ256rrk [HasVLX, HasAVX512]
vcvtpd2ps {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPD2PSZ256rrkz [HasVLX, HasAVX512]
vcvtpd2ps {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2PDZ128rm [HasVLX, HasAVX512]
vcvtps2pd {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2PDZ128rmb [HasVLX, HasAVX512]
vcvtps2pd {src{1to2}, dst|dst, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2PDZ128rmbk [HasVLX, HasAVX512]
vcvtps2pd {src{1to2}, dst {mask}|dst {mask}, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPS2PDZ128rmbkz [HasVLX, HasAVX512]
vcvtps2pd {src{1to2}, dst {mask} {z}|dst {mask} {z}, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2PDZ128rmk [HasVLX, HasAVX512]
vcvtps2pd {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPS2PDZ128rmkz [HasVLX, HasAVX512]
vcvtps2pd {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2PDZ128rr [HasVLX, HasAVX512]
vcvtps2pd {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2PDZ128rrk [HasVLX, HasAVX512]
vcvtps2pd {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPS2PDZ128rrkz [HasVLX, HasAVX512]
vcvtps2pd {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2PDZ256rm [HasVLX, HasAVX512]
vcvtps2pd {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2PDZ256rmb [HasVLX, HasAVX512]
vcvtps2pd {src{1to4}, dst|dst, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2PDZ256rmbk [HasVLX, HasAVX512]
vcvtps2pd {src{1to4}, dst {mask}|dst {mask}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPS2PDZ256rmbkz [HasVLX, HasAVX512]
vcvtps2pd {src{1to4}, dst {mask} {z}|dst {mask} {z}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2PDZ256rmk [HasVLX, HasAVX512]
vcvtps2pd {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPS2PDZ256rmkz [HasVLX, HasAVX512]
vcvtps2pd {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2PDZ256rr [HasVLX, HasAVX512]
vcvtps2pd {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2PDZ256rrk [HasVLX, HasAVX512]
vcvtps2pd {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPS2PDZ256rrkz [HasVLX, HasAVX512]
vcvtps2pd {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VDIVPDZ128rm [HasVLX, HasAVX512]
vdivpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VDIVPDZ128rmb [HasVLX, HasAVX512]
vdivpd {src2{1to2}, src1, dst|dst, src1, src2{1to2}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VDIVPDZ128rmbk [HasVLX, HasAVX512]
vdivpd {src2{1to2}, src1, dst {mask}|dst {mask}, src1, src2{1to2}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VDIVPDZ128rmbkz [HasVLX, HasAVX512]
vdivpd {src2{1to2}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to2}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VDIVPDZ128rmk [HasVLX, HasAVX512]
vdivpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VDIVPDZ128rmkz [HasVLX, HasAVX512]
vdivpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VDIVPDZ128rr [HasVLX, HasAVX512]
vdivpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VDIVPDZ128rrk [HasVLX, HasAVX512]
vdivpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VDIVPDZ128rrkz [HasVLX, HasAVX512]
vdivpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VDIVPDZ256rm [HasVLX, HasAVX512]
vdivpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VDIVPDZ256rmb [HasVLX, HasAVX512]
vdivpd {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VDIVPDZ256rmbk [HasVLX, HasAVX512]
vdivpd {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VDIVPDZ256rmbkz [HasVLX, HasAVX512]
vdivpd {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VDIVPDZ256rmk [HasVLX, HasAVX512]
vdivpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VDIVPDZ256rmkz [HasVLX, HasAVX512]
vdivpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VDIVPDZ256rr [HasVLX, HasAVX512]
vdivpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VDIVPDZ256rrk [HasVLX, HasAVX512]
vdivpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VDIVPDZ256rrkz [HasVLX, HasAVX512]
vdivpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VDIVPSZ128rm [HasVLX, HasAVX512]
vdivps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VDIVPSZ128rmb [HasVLX, HasAVX512]
vdivps {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VDIVPSZ128rmbk [HasVLX, HasAVX512]
vdivps {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VDIVPSZ128rmbkz [HasVLX, HasAVX512]
vdivps {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VDIVPSZ128rmk [HasVLX, HasAVX512]
vdivps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VDIVPSZ128rmkz [HasVLX, HasAVX512]
vdivps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VDIVPSZ128rr [HasVLX, HasAVX512]
vdivps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VDIVPSZ128rrk [HasVLX, HasAVX512]
vdivps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VDIVPSZ128rrkz [HasVLX, HasAVX512]
vdivps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VDIVPSZ256rm [HasVLX, HasAVX512]
vdivps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VDIVPSZ256rmb [HasVLX, HasAVX512]
vdivps {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VDIVPSZ256rmbk [HasVLX, HasAVX512]
vdivps {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VDIVPSZ256rmbkz [HasVLX, HasAVX512]
vdivps {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VDIVPSZ256rmk [HasVLX, HasAVX512]
vdivps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VDIVPSZ256rmkz [HasVLX, HasAVX512]
vdivps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VDIVPSZ256rr [HasVLX, HasAVX512]
vdivps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VDIVPSZ256rrk [HasVLX, HasAVX512]
vdivps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VDIVPSZ256rrkz [HasVLX, HasAVX512]
vdivps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VEXPANDPDZ128rm [HasVLX, HasAVX512]
vexpandpd {src1, dst|dst, src1}
VEXPANDPDZ128rmk [HasVLX, HasAVX512]
vexpandpd {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VEXPANDPDZ128rmkz [HasVLX, HasAVX512]
vexpandpd {src1, dst {mask} {z}|dst {mask} {z}, src1}
VEXPANDPDZ128rr [HasVLX, HasAVX512]
vexpandpd {src1, dst|dst, src1}
VEXPANDPDZ128rrk [HasVLX, HasAVX512]
vexpandpd {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VEXPANDPDZ128rrkz [HasVLX, HasAVX512]
vexpandpd {src1, dst {mask} {z}|dst {mask} {z}, src1}
VEXPANDPDZ256rm [HasVLX, HasAVX512]
vexpandpd {src1, dst|dst, src1}
VEXPANDPDZ256rmk [HasVLX, HasAVX512]
vexpandpd {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VEXPANDPDZ256rmkz [HasVLX, HasAVX512]
vexpandpd {src1, dst {mask} {z}|dst {mask} {z}, src1}
VEXPANDPDZ256rr [HasVLX, HasAVX512]
vexpandpd {src1, dst|dst, src1}
VEXPANDPDZ256rrk [HasVLX, HasAVX512]
vexpandpd {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VEXPANDPDZ256rrkz [HasVLX, HasAVX512]
vexpandpd {src1, dst {mask} {z}|dst {mask} {z}, src1}
VEXPANDPSZ128rm [HasVLX, HasAVX512]
vexpandps {src1, dst|dst, src1}
VEXPANDPSZ128rmk [HasVLX, HasAVX512]
vexpandps {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VEXPANDPSZ128rmkz [HasVLX, HasAVX512]
vexpandps {src1, dst {mask} {z}|dst {mask} {z}, src1}
VEXPANDPSZ128rr [HasVLX, HasAVX512]
vexpandps {src1, dst|dst, src1}
VEXPANDPSZ128rrk [HasVLX, HasAVX512]
vexpandps {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VEXPANDPSZ128rrkz [HasVLX, HasAVX512]
vexpandps {src1, dst {mask} {z}|dst {mask} {z}, src1}
VEXPANDPSZ256rm [HasVLX, HasAVX512]
vexpandps {src1, dst|dst, src1}
VEXPANDPSZ256rmk [HasVLX, HasAVX512]
vexpandps {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VEXPANDPSZ256rmkz [HasVLX, HasAVX512]
vexpandps {src1, dst {mask} {z}|dst {mask} {z}, src1}
VEXPANDPSZ256rr [HasVLX, HasAVX512]
vexpandps {src1, dst|dst, src1}
VEXPANDPSZ256rrk [HasVLX, HasAVX512]
vexpandps {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VEXPANDPSZ256rrkz [HasVLX, HasAVX512]
vexpandps {src1, dst {mask} {z}|dst {mask} {z}, src1}
VFIXUPIMMPDZ128rmbi [HasVLX, HasAVX512]
vfixupimmpd {src4, src3{1to2}, src2, dst|dst, src2, src3{1to2}, src4}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMPDZ128rmbik [HasVLX, HasAVX512]
vfixupimmpd {src4, src3{1to2}, src2, dst {mask}|dst {mask}, src2, src3{1to2}, src4}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMPDZ128rmbikz [HasVLX, HasAVX512]
vfixupimmpd {src4, src3{1to2}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to2}, src4}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMPDZ128rmi [HasVLX, HasAVX512]
vfixupimmpd {src4, src3, src2, dst|dst, src2, src3, src4}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMPDZ128rmik [HasVLX, HasAVX512]
vfixupimmpd {src4, src3, src2, dst {mask}|dst {mask}, src2, src3, src4}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMPDZ128rmikz [HasVLX, HasAVX512]
vfixupimmpd {src4, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, src4}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMPDZ128rri [HasVLX, HasAVX512]
vfixupimmpd {src4, src3, src2, dst|dst, src2, src3, src4}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMPDZ128rrik [HasVLX, HasAVX512]
vfixupimmpd {src4, src3, src2, dst {mask}|dst {mask}, src2, src3, src4}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMPDZ128rrikz [HasVLX, HasAVX512]
vfixupimmpd {src4, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, src4}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMPDZ256rmbi [HasVLX, HasAVX512]
vfixupimmpd {src4, src3{1to4}, src2, dst|dst, src2, src3{1to4}, src4}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMPDZ256rmbik [HasVLX, HasAVX512]
vfixupimmpd {src4, src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}, src4}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMPDZ256rmbikz [HasVLX, HasAVX512]
vfixupimmpd {src4, src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}, src4}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMPDZ256rmi [HasVLX, HasAVX512]
vfixupimmpd {src4, src3, src2, dst|dst, src2, src3, src4}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMPDZ256rmik [HasVLX, HasAVX512]
vfixupimmpd {src4, src3, src2, dst {mask}|dst {mask}, src2, src3, src4}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMPDZ256rmikz [HasVLX, HasAVX512]
vfixupimmpd {src4, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, src4}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMPDZ256rri [HasVLX, HasAVX512]
vfixupimmpd {src4, src3, src2, dst|dst, src2, src3, src4}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMPDZ256rrik [HasVLX, HasAVX512]
vfixupimmpd {src4, src3, src2, dst {mask}|dst {mask}, src2, src3, src4}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMPDZ256rrikz [HasVLX, HasAVX512]
vfixupimmpd {src4, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, src4}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMPSZ128rmbi [HasVLX, HasAVX512]
vfixupimmps {src4, src3{1to4}, src2, dst|dst, src2, src3{1to4}, src4}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMPSZ128rmbik [HasVLX, HasAVX512]
vfixupimmps {src4, src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}, src4}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMPSZ128rmbikz [HasVLX, HasAVX512]
vfixupimmps {src4, src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}, src4}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMPSZ128rmi [HasVLX, HasAVX512]
vfixupimmps {src4, src3, src2, dst|dst, src2, src3, src4}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMPSZ128rmik [HasVLX, HasAVX512]
vfixupimmps {src4, src3, src2, dst {mask}|dst {mask}, src2, src3, src4}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMPSZ128rmikz [HasVLX, HasAVX512]
vfixupimmps {src4, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, src4}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMPSZ128rri [HasVLX, HasAVX512]
vfixupimmps {src4, src3, src2, dst|dst, src2, src3, src4}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMPSZ128rrik [HasVLX, HasAVX512]
vfixupimmps {src4, src3, src2, dst {mask}|dst {mask}, src2, src3, src4}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMPSZ128rrikz [HasVLX, HasAVX512]
vfixupimmps {src4, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, src4}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMPSZ256rmbi [HasVLX, HasAVX512]
vfixupimmps {src4, src3{1to8}, src2, dst|dst, src2, src3{1to8}, src4}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMPSZ256rmbik [HasVLX, HasAVX512]
vfixupimmps {src4, src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}, src4}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMPSZ256rmbikz [HasVLX, HasAVX512]
vfixupimmps {src4, src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}, src4}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMPSZ256rmi [HasVLX, HasAVX512]
vfixupimmps {src4, src3, src2, dst|dst, src2, src3, src4}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMPSZ256rmik [HasVLX, HasAVX512]
vfixupimmps {src4, src3, src2, dst {mask}|dst {mask}, src2, src3, src4}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMPSZ256rmikz [HasVLX, HasAVX512]
vfixupimmps {src4, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, src4}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMPSZ256rri [HasVLX, HasAVX512]
vfixupimmps {src4, src3, src2, dst|dst, src2, src3, src4}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMPSZ256rrik [HasVLX, HasAVX512]
vfixupimmps {src4, src3, src2, dst {mask}|dst {mask}, src2, src3, src4}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMPSZ256rrikz [HasVLX, HasAVX512]
vfixupimmps {src4, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, src4}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PDZ128m [HasVLX, HasAVX512]
vfmadd132pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PDZ128mb [HasVLX, HasAVX512]
vfmadd132pd {src3{1to2}, src2, dst|dst, src2, src3{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PDZ128mbk [HasVLX, HasAVX512]
vfmadd132pd {src3{1to2}, src2, dst {mask}|dst {mask}, src2, src3{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PDZ128mbkz [HasVLX, HasAVX512]
vfmadd132pd {src3{1to2}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PDZ128mk [HasVLX, HasAVX512]
vfmadd132pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PDZ128mkz [HasVLX, HasAVX512]
vfmadd132pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PDZ128r [HasVLX, HasAVX512]
vfmadd132pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PDZ128rk [HasVLX, HasAVX512]
vfmadd132pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PDZ128rkz [HasVLX, HasAVX512]
vfmadd132pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PDZ256m [HasVLX, HasAVX512]
vfmadd132pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PDZ256mb [HasVLX, HasAVX512]
vfmadd132pd {src3{1to4}, src2, dst|dst, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PDZ256mbk [HasVLX, HasAVX512]
vfmadd132pd {src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PDZ256mbkz [HasVLX, HasAVX512]
vfmadd132pd {src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PDZ256mk [HasVLX, HasAVX512]
vfmadd132pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PDZ256mkz [HasVLX, HasAVX512]
vfmadd132pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PDZ256r [HasVLX, HasAVX512]
vfmadd132pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PDZ256rk [HasVLX, HasAVX512]
vfmadd132pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PDZ256rkz [HasVLX, HasAVX512]
vfmadd132pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PSZ128m [HasVLX, HasAVX512]
vfmadd132ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PSZ128mb [HasVLX, HasAVX512]
vfmadd132ps {src3{1to4}, src2, dst|dst, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PSZ128mbk [HasVLX, HasAVX512]
vfmadd132ps {src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PSZ128mbkz [HasVLX, HasAVX512]
vfmadd132ps {src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PSZ128mk [HasVLX, HasAVX512]
vfmadd132ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PSZ128mkz [HasVLX, HasAVX512]
vfmadd132ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PSZ128r [HasVLX, HasAVX512]
vfmadd132ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PSZ128rk [HasVLX, HasAVX512]
vfmadd132ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PSZ128rkz [HasVLX, HasAVX512]
vfmadd132ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PSZ256m [HasVLX, HasAVX512]
vfmadd132ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PSZ256mb [HasVLX, HasAVX512]
vfmadd132ps {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PSZ256mbk [HasVLX, HasAVX512]
vfmadd132ps {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PSZ256mbkz [HasVLX, HasAVX512]
vfmadd132ps {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PSZ256mk [HasVLX, HasAVX512]
vfmadd132ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PSZ256mkz [HasVLX, HasAVX512]
vfmadd132ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PSZ256r [HasVLX, HasAVX512]
vfmadd132ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PSZ256rk [HasVLX, HasAVX512]
vfmadd132ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PSZ256rkz [HasVLX, HasAVX512]
vfmadd132ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PDZ128m [HasVLX, HasAVX512]
vfmadd213pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PDZ128mb [HasVLX, HasAVX512]
vfmadd213pd {src3{1to2}, src2, dst|dst, src2, src3{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PDZ128mbk [HasVLX, HasAVX512]
vfmadd213pd {src3{1to2}, src2, dst {mask}|dst {mask}, src2, src3{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PDZ128mbkz [HasVLX, HasAVX512]
vfmadd213pd {src3{1to2}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PDZ128mk [HasVLX, HasAVX512]
vfmadd213pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PDZ128mkz [HasVLX, HasAVX512]
vfmadd213pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PDZ128r [HasVLX, HasAVX512]
vfmadd213pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PDZ128rk [HasVLX, HasAVX512]
vfmadd213pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PDZ128rkz [HasVLX, HasAVX512]
vfmadd213pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PDZ256m [HasVLX, HasAVX512]
vfmadd213pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PDZ256mb [HasVLX, HasAVX512]
vfmadd213pd {src3{1to4}, src2, dst|dst, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PDZ256mbk [HasVLX, HasAVX512]
vfmadd213pd {src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PDZ256mbkz [HasVLX, HasAVX512]
vfmadd213pd {src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PDZ256mk [HasVLX, HasAVX512]
vfmadd213pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PDZ256mkz [HasVLX, HasAVX512]
vfmadd213pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PDZ256r [HasVLX, HasAVX512]
vfmadd213pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PDZ256rk [HasVLX, HasAVX512]
vfmadd213pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PDZ256rkz [HasVLX, HasAVX512]
vfmadd213pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PSZ128m [HasVLX, HasAVX512]
vfmadd213ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PSZ128mb [HasVLX, HasAVX512]
vfmadd213ps {src3{1to4}, src2, dst|dst, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PSZ128mbk [HasVLX, HasAVX512]
vfmadd213ps {src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PSZ128mbkz [HasVLX, HasAVX512]
vfmadd213ps {src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PSZ128mk [HasVLX, HasAVX512]
vfmadd213ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PSZ128mkz [HasVLX, HasAVX512]
vfmadd213ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PSZ128r [HasVLX, HasAVX512]
vfmadd213ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PSZ128rk [HasVLX, HasAVX512]
vfmadd213ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PSZ128rkz [HasVLX, HasAVX512]
vfmadd213ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PSZ256m [HasVLX, HasAVX512]
vfmadd213ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PSZ256mb [HasVLX, HasAVX512]
vfmadd213ps {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PSZ256mbk [HasVLX, HasAVX512]
vfmadd213ps {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PSZ256mbkz [HasVLX, HasAVX512]
vfmadd213ps {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PSZ256mk [HasVLX, HasAVX512]
vfmadd213ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PSZ256mkz [HasVLX, HasAVX512]
vfmadd213ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PSZ256r [HasVLX, HasAVX512]
vfmadd213ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PSZ256rk [HasVLX, HasAVX512]
vfmadd213ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PSZ256rkz [HasVLX, HasAVX512]
vfmadd213ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PDZ128m [HasVLX, HasAVX512]
vfmadd231pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PDZ128mb [HasVLX, HasAVX512]
vfmadd231pd {src3{1to2}, src2, dst|dst, src2, src3{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PDZ128mbk [HasVLX, HasAVX512]
vfmadd231pd {src3{1to2}, src2, dst {mask}|dst {mask}, src2, src3{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PDZ128mbkz [HasVLX, HasAVX512]
vfmadd231pd {src3{1to2}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PDZ128mk [HasVLX, HasAVX512]
vfmadd231pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PDZ128mkz [HasVLX, HasAVX512]
vfmadd231pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PDZ128r [HasVLX, HasAVX512]
vfmadd231pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PDZ128rk [HasVLX, HasAVX512]
vfmadd231pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PDZ128rkz [HasVLX, HasAVX512]
vfmadd231pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PDZ256m [HasVLX, HasAVX512]
vfmadd231pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PDZ256mb [HasVLX, HasAVX512]
vfmadd231pd {src3{1to4}, src2, dst|dst, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PDZ256mbk [HasVLX, HasAVX512]
vfmadd231pd {src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PDZ256mbkz [HasVLX, HasAVX512]
vfmadd231pd {src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PDZ256mk [HasVLX, HasAVX512]
vfmadd231pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PDZ256mkz [HasVLX, HasAVX512]
vfmadd231pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PDZ256r [HasVLX, HasAVX512]
vfmadd231pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PDZ256rk [HasVLX, HasAVX512]
vfmadd231pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PDZ256rkz [HasVLX, HasAVX512]
vfmadd231pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PSZ128m [HasVLX, HasAVX512]
vfmadd231ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PSZ128mb [HasVLX, HasAVX512]
vfmadd231ps {src3{1to4}, src2, dst|dst, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PSZ128mbk [HasVLX, HasAVX512]
vfmadd231ps {src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PSZ128mbkz [HasVLX, HasAVX512]
vfmadd231ps {src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PSZ128mk [HasVLX, HasAVX512]
vfmadd231ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PSZ128mkz [HasVLX, HasAVX512]
vfmadd231ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PSZ128r [HasVLX, HasAVX512]
vfmadd231ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PSZ128rk [HasVLX, HasAVX512]
vfmadd231ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PSZ128rkz [HasVLX, HasAVX512]
vfmadd231ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PSZ256m [HasVLX, HasAVX512]
vfmadd231ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PSZ256mb [HasVLX, HasAVX512]
vfmadd231ps {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PSZ256mbk [HasVLX, HasAVX512]
vfmadd231ps {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PSZ256mbkz [HasVLX, HasAVX512]
vfmadd231ps {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PSZ256mk [HasVLX, HasAVX512]
vfmadd231ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PSZ256mkz [HasVLX, HasAVX512]
vfmadd231ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PSZ256r [HasVLX, HasAVX512]
vfmadd231ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PSZ256rk [HasVLX, HasAVX512]
vfmadd231ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PSZ256rkz [HasVLX, HasAVX512]
vfmadd231ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PDZ128m [HasVLX, HasAVX512]
vfmaddsub132pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PDZ128mb [HasVLX, HasAVX512]
vfmaddsub132pd {src3{1to2}, src2, dst|dst, src2, src3{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PDZ128mbk [HasVLX, HasAVX512]
vfmaddsub132pd {src3{1to2}, src2, dst {mask}|dst {mask}, src2, src3{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PDZ128mbkz [HasVLX, HasAVX512]
vfmaddsub132pd {src3{1to2}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PDZ128mk [HasVLX, HasAVX512]
vfmaddsub132pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PDZ128mkz [HasVLX, HasAVX512]
vfmaddsub132pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PDZ128r [HasVLX, HasAVX512]
vfmaddsub132pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PDZ128rk [HasVLX, HasAVX512]
vfmaddsub132pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PDZ128rkz [HasVLX, HasAVX512]
vfmaddsub132pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PDZ256m [HasVLX, HasAVX512]
vfmaddsub132pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PDZ256mb [HasVLX, HasAVX512]
vfmaddsub132pd {src3{1to4}, src2, dst|dst, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PDZ256mbk [HasVLX, HasAVX512]
vfmaddsub132pd {src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PDZ256mbkz [HasVLX, HasAVX512]
vfmaddsub132pd {src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PDZ256mk [HasVLX, HasAVX512]
vfmaddsub132pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PDZ256mkz [HasVLX, HasAVX512]
vfmaddsub132pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PDZ256r [HasVLX, HasAVX512]
vfmaddsub132pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PDZ256rk [HasVLX, HasAVX512]
vfmaddsub132pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PDZ256rkz [HasVLX, HasAVX512]
vfmaddsub132pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PSZ128m [HasVLX, HasAVX512]
vfmaddsub132ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PSZ128mb [HasVLX, HasAVX512]
vfmaddsub132ps {src3{1to4}, src2, dst|dst, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PSZ128mbk [HasVLX, HasAVX512]
vfmaddsub132ps {src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PSZ128mbkz [HasVLX, HasAVX512]
vfmaddsub132ps {src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PSZ128mk [HasVLX, HasAVX512]
vfmaddsub132ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PSZ128mkz [HasVLX, HasAVX512]
vfmaddsub132ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PSZ128r [HasVLX, HasAVX512]
vfmaddsub132ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PSZ128rk [HasVLX, HasAVX512]
vfmaddsub132ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PSZ128rkz [HasVLX, HasAVX512]
vfmaddsub132ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PSZ256m [HasVLX, HasAVX512]
vfmaddsub132ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PSZ256mb [HasVLX, HasAVX512]
vfmaddsub132ps {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PSZ256mbk [HasVLX, HasAVX512]
vfmaddsub132ps {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PSZ256mbkz [HasVLX, HasAVX512]
vfmaddsub132ps {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PSZ256mk [HasVLX, HasAVX512]
vfmaddsub132ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PSZ256mkz [HasVLX, HasAVX512]
vfmaddsub132ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PSZ256r [HasVLX, HasAVX512]
vfmaddsub132ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PSZ256rk [HasVLX, HasAVX512]
vfmaddsub132ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PSZ256rkz [HasVLX, HasAVX512]
vfmaddsub132ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PDZ128m [HasVLX, HasAVX512]
vfmaddsub213pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PDZ128mb [HasVLX, HasAVX512]
vfmaddsub213pd {src3{1to2}, src2, dst|dst, src2, src3{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PDZ128mbk [HasVLX, HasAVX512]
vfmaddsub213pd {src3{1to2}, src2, dst {mask}|dst {mask}, src2, src3{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PDZ128mbkz [HasVLX, HasAVX512]
vfmaddsub213pd {src3{1to2}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PDZ128mk [HasVLX, HasAVX512]
vfmaddsub213pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PDZ128mkz [HasVLX, HasAVX512]
vfmaddsub213pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PDZ128r [HasVLX, HasAVX512]
vfmaddsub213pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PDZ128rk [HasVLX, HasAVX512]
vfmaddsub213pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PDZ128rkz [HasVLX, HasAVX512]
vfmaddsub213pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PDZ256m [HasVLX, HasAVX512]
vfmaddsub213pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PDZ256mb [HasVLX, HasAVX512]
vfmaddsub213pd {src3{1to4}, src2, dst|dst, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PDZ256mbk [HasVLX, HasAVX512]
vfmaddsub213pd {src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PDZ256mbkz [HasVLX, HasAVX512]
vfmaddsub213pd {src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PDZ256mk [HasVLX, HasAVX512]
vfmaddsub213pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PDZ256mkz [HasVLX, HasAVX512]
vfmaddsub213pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PDZ256r [HasVLX, HasAVX512]
vfmaddsub213pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PDZ256rk [HasVLX, HasAVX512]
vfmaddsub213pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PDZ256rkz [HasVLX, HasAVX512]
vfmaddsub213pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PSZ128m [HasVLX, HasAVX512]
vfmaddsub213ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PSZ128mb [HasVLX, HasAVX512]
vfmaddsub213ps {src3{1to4}, src2, dst|dst, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PSZ128mbk [HasVLX, HasAVX512]
vfmaddsub213ps {src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PSZ128mbkz [HasVLX, HasAVX512]
vfmaddsub213ps {src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PSZ128mk [HasVLX, HasAVX512]
vfmaddsub213ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PSZ128mkz [HasVLX, HasAVX512]
vfmaddsub213ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PSZ128r [HasVLX, HasAVX512]
vfmaddsub213ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PSZ128rk [HasVLX, HasAVX512]
vfmaddsub213ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PSZ128rkz [HasVLX, HasAVX512]
vfmaddsub213ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PSZ256m [HasVLX, HasAVX512]
vfmaddsub213ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PSZ256mb [HasVLX, HasAVX512]
vfmaddsub213ps {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PSZ256mbk [HasVLX, HasAVX512]
vfmaddsub213ps {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PSZ256mbkz [HasVLX, HasAVX512]
vfmaddsub213ps {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PSZ256mk [HasVLX, HasAVX512]
vfmaddsub213ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PSZ256mkz [HasVLX, HasAVX512]
vfmaddsub213ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PSZ256r [HasVLX, HasAVX512]
vfmaddsub213ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PSZ256rk [HasVLX, HasAVX512]
vfmaddsub213ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PSZ256rkz [HasVLX, HasAVX512]
vfmaddsub213ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PDZ128m [HasVLX, HasAVX512]
vfmaddsub231pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PDZ128mb [HasVLX, HasAVX512]
vfmaddsub231pd {src3{1to2}, src2, dst|dst, src2, src3{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PDZ128mbk [HasVLX, HasAVX512]
vfmaddsub231pd {src3{1to2}, src2, dst {mask}|dst {mask}, src2, src3{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PDZ128mbkz [HasVLX, HasAVX512]
vfmaddsub231pd {src3{1to2}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PDZ128mk [HasVLX, HasAVX512]
vfmaddsub231pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PDZ128mkz [HasVLX, HasAVX512]
vfmaddsub231pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PDZ128r [HasVLX, HasAVX512]
vfmaddsub231pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PDZ128rk [HasVLX, HasAVX512]
vfmaddsub231pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PDZ128rkz [HasVLX, HasAVX512]
vfmaddsub231pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PDZ256m [HasVLX, HasAVX512]
vfmaddsub231pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PDZ256mb [HasVLX, HasAVX512]
vfmaddsub231pd {src3{1to4}, src2, dst|dst, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PDZ256mbk [HasVLX, HasAVX512]
vfmaddsub231pd {src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PDZ256mbkz [HasVLX, HasAVX512]
vfmaddsub231pd {src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PDZ256mk [HasVLX, HasAVX512]
vfmaddsub231pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PDZ256mkz [HasVLX, HasAVX512]
vfmaddsub231pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PDZ256r [HasVLX, HasAVX512]
vfmaddsub231pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PDZ256rk [HasVLX, HasAVX512]
vfmaddsub231pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PDZ256rkz [HasVLX, HasAVX512]
vfmaddsub231pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PSZ128m [HasVLX, HasAVX512]
vfmaddsub231ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PSZ128mb [HasVLX, HasAVX512]
vfmaddsub231ps {src3{1to4}, src2, dst|dst, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PSZ128mbk [HasVLX, HasAVX512]
vfmaddsub231ps {src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PSZ128mbkz [HasVLX, HasAVX512]
vfmaddsub231ps {src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PSZ128mk [HasVLX, HasAVX512]
vfmaddsub231ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PSZ128mkz [HasVLX, HasAVX512]
vfmaddsub231ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PSZ128r [HasVLX, HasAVX512]
vfmaddsub231ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PSZ128rk [HasVLX, HasAVX512]
vfmaddsub231ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PSZ128rkz [HasVLX, HasAVX512]
vfmaddsub231ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PSZ256m [HasVLX, HasAVX512]
vfmaddsub231ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PSZ256mb [HasVLX, HasAVX512]
vfmaddsub231ps {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PSZ256mbk [HasVLX, HasAVX512]
vfmaddsub231ps {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PSZ256mbkz [HasVLX, HasAVX512]
vfmaddsub231ps {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PSZ256mk [HasVLX, HasAVX512]
vfmaddsub231ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PSZ256mkz [HasVLX, HasAVX512]
vfmaddsub231ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PSZ256r [HasVLX, HasAVX512]
vfmaddsub231ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PSZ256rk [HasVLX, HasAVX512]
vfmaddsub231ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PSZ256rkz [HasVLX, HasAVX512]
vfmaddsub231ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PDZ128m [HasVLX, HasAVX512]
vfmsub132pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PDZ128mb [HasVLX, HasAVX512]
vfmsub132pd {src3{1to2}, src2, dst|dst, src2, src3{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PDZ128mbk [HasVLX, HasAVX512]
vfmsub132pd {src3{1to2}, src2, dst {mask}|dst {mask}, src2, src3{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PDZ128mbkz [HasVLX, HasAVX512]
vfmsub132pd {src3{1to2}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PDZ128mk [HasVLX, HasAVX512]
vfmsub132pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PDZ128mkz [HasVLX, HasAVX512]
vfmsub132pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PDZ128r [HasVLX, HasAVX512]
vfmsub132pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PDZ128rk [HasVLX, HasAVX512]
vfmsub132pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PDZ128rkz [HasVLX, HasAVX512]
vfmsub132pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PDZ256m [HasVLX, HasAVX512]
vfmsub132pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PDZ256mb [HasVLX, HasAVX512]
vfmsub132pd {src3{1to4}, src2, dst|dst, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PDZ256mbk [HasVLX, HasAVX512]
vfmsub132pd {src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PDZ256mbkz [HasVLX, HasAVX512]
vfmsub132pd {src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PDZ256mk [HasVLX, HasAVX512]
vfmsub132pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PDZ256mkz [HasVLX, HasAVX512]
vfmsub132pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PDZ256r [HasVLX, HasAVX512]
vfmsub132pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PDZ256rk [HasVLX, HasAVX512]
vfmsub132pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PDZ256rkz [HasVLX, HasAVX512]
vfmsub132pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PSZ128m [HasVLX, HasAVX512]
vfmsub132ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PSZ128mb [HasVLX, HasAVX512]
vfmsub132ps {src3{1to4}, src2, dst|dst, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PSZ128mbk [HasVLX, HasAVX512]
vfmsub132ps {src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PSZ128mbkz [HasVLX, HasAVX512]
vfmsub132ps {src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PSZ128mk [HasVLX, HasAVX512]
vfmsub132ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PSZ128mkz [HasVLX, HasAVX512]
vfmsub132ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PSZ128r [HasVLX, HasAVX512]
vfmsub132ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PSZ128rk [HasVLX, HasAVX512]
vfmsub132ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PSZ128rkz [HasVLX, HasAVX512]
vfmsub132ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PSZ256m [HasVLX, HasAVX512]
vfmsub132ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PSZ256mb [HasVLX, HasAVX512]
vfmsub132ps {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PSZ256mbk [HasVLX, HasAVX512]
vfmsub132ps {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PSZ256mbkz [HasVLX, HasAVX512]
vfmsub132ps {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PSZ256mk [HasVLX, HasAVX512]
vfmsub132ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PSZ256mkz [HasVLX, HasAVX512]
vfmsub132ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PSZ256r [HasVLX, HasAVX512]
vfmsub132ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PSZ256rk [HasVLX, HasAVX512]
vfmsub132ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PSZ256rkz [HasVLX, HasAVX512]
vfmsub132ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PDZ128m [HasVLX, HasAVX512]
vfmsub213pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PDZ128mb [HasVLX, HasAVX512]
vfmsub213pd {src3{1to2}, src2, dst|dst, src2, src3{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PDZ128mbk [HasVLX, HasAVX512]
vfmsub213pd {src3{1to2}, src2, dst {mask}|dst {mask}, src2, src3{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PDZ128mbkz [HasVLX, HasAVX512]
vfmsub213pd {src3{1to2}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PDZ128mk [HasVLX, HasAVX512]
vfmsub213pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PDZ128mkz [HasVLX, HasAVX512]
vfmsub213pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PDZ128r [HasVLX, HasAVX512]
vfmsub213pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PDZ128rk [HasVLX, HasAVX512]
vfmsub213pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PDZ128rkz [HasVLX, HasAVX512]
vfmsub213pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PDZ256m [HasVLX, HasAVX512]
vfmsub213pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PDZ256mb [HasVLX, HasAVX512]
vfmsub213pd {src3{1to4}, src2, dst|dst, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PDZ256mbk [HasVLX, HasAVX512]
vfmsub213pd {src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PDZ256mbkz [HasVLX, HasAVX512]
vfmsub213pd {src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PDZ256mk [HasVLX, HasAVX512]
vfmsub213pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PDZ256mkz [HasVLX, HasAVX512]
vfmsub213pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PDZ256r [HasVLX, HasAVX512]
vfmsub213pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PDZ256rk [HasVLX, HasAVX512]
vfmsub213pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PDZ256rkz [HasVLX, HasAVX512]
vfmsub213pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PSZ128m [HasVLX, HasAVX512]
vfmsub213ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PSZ128mb [HasVLX, HasAVX512]
vfmsub213ps {src3{1to4}, src2, dst|dst, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PSZ128mbk [HasVLX, HasAVX512]
vfmsub213ps {src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PSZ128mbkz [HasVLX, HasAVX512]
vfmsub213ps {src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PSZ128mk [HasVLX, HasAVX512]
vfmsub213ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PSZ128mkz [HasVLX, HasAVX512]
vfmsub213ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PSZ128r [HasVLX, HasAVX512]
vfmsub213ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PSZ128rk [HasVLX, HasAVX512]
vfmsub213ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PSZ128rkz [HasVLX, HasAVX512]
vfmsub213ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PSZ256m [HasVLX, HasAVX512]
vfmsub213ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PSZ256mb [HasVLX, HasAVX512]
vfmsub213ps {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PSZ256mbk [HasVLX, HasAVX512]
vfmsub213ps {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PSZ256mbkz [HasVLX, HasAVX512]
vfmsub213ps {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PSZ256mk [HasVLX, HasAVX512]
vfmsub213ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PSZ256mkz [HasVLX, HasAVX512]
vfmsub213ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PSZ256r [HasVLX, HasAVX512]
vfmsub213ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PSZ256rk [HasVLX, HasAVX512]
vfmsub213ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PSZ256rkz [HasVLX, HasAVX512]
vfmsub213ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PDZ128m [HasVLX, HasAVX512]
vfmsub231pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PDZ128mb [HasVLX, HasAVX512]
vfmsub231pd {src3{1to2}, src2, dst|dst, src2, src3{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PDZ128mbk [HasVLX, HasAVX512]
vfmsub231pd {src3{1to2}, src2, dst {mask}|dst {mask}, src2, src3{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PDZ128mbkz [HasVLX, HasAVX512]
vfmsub231pd {src3{1to2}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PDZ128mk [HasVLX, HasAVX512]
vfmsub231pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PDZ128mkz [HasVLX, HasAVX512]
vfmsub231pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PDZ128r [HasVLX, HasAVX512]
vfmsub231pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PDZ128rk [HasVLX, HasAVX512]
vfmsub231pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PDZ128rkz [HasVLX, HasAVX512]
vfmsub231pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PDZ256m [HasVLX, HasAVX512]
vfmsub231pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PDZ256mb [HasVLX, HasAVX512]
vfmsub231pd {src3{1to4}, src2, dst|dst, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PDZ256mbk [HasVLX, HasAVX512]
vfmsub231pd {src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PDZ256mbkz [HasVLX, HasAVX512]
vfmsub231pd {src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PDZ256mk [HasVLX, HasAVX512]
vfmsub231pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PDZ256mkz [HasVLX, HasAVX512]
vfmsub231pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PDZ256r [HasVLX, HasAVX512]
vfmsub231pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PDZ256rk [HasVLX, HasAVX512]
vfmsub231pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PDZ256rkz [HasVLX, HasAVX512]
vfmsub231pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PSZ128m [HasVLX, HasAVX512]
vfmsub231ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PSZ128mb [HasVLX, HasAVX512]
vfmsub231ps {src3{1to4}, src2, dst|dst, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PSZ128mbk [HasVLX, HasAVX512]
vfmsub231ps {src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PSZ128mbkz [HasVLX, HasAVX512]
vfmsub231ps {src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PSZ128mk [HasVLX, HasAVX512]
vfmsub231ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PSZ128mkz [HasVLX, HasAVX512]
vfmsub231ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PSZ128r [HasVLX, HasAVX512]
vfmsub231ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PSZ128rk [HasVLX, HasAVX512]
vfmsub231ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PSZ128rkz [HasVLX, HasAVX512]
vfmsub231ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PSZ256m [HasVLX, HasAVX512]
vfmsub231ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PSZ256mb [HasVLX, HasAVX512]
vfmsub231ps {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PSZ256mbk [HasVLX, HasAVX512]
vfmsub231ps {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PSZ256mbkz [HasVLX, HasAVX512]
vfmsub231ps {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PSZ256mk [HasVLX, HasAVX512]
vfmsub231ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PSZ256mkz [HasVLX, HasAVX512]
vfmsub231ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PSZ256r [HasVLX, HasAVX512]
vfmsub231ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PSZ256rk [HasVLX, HasAVX512]
vfmsub231ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PSZ256rkz [HasVLX, HasAVX512]
vfmsub231ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PDZ128m [HasVLX, HasAVX512]
vfmsubadd132pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PDZ128mb [HasVLX, HasAVX512]
vfmsubadd132pd {src3{1to2}, src2, dst|dst, src2, src3{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PDZ128mbk [HasVLX, HasAVX512]
vfmsubadd132pd {src3{1to2}, src2, dst {mask}|dst {mask}, src2, src3{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PDZ128mbkz [HasVLX, HasAVX512]
vfmsubadd132pd {src3{1to2}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PDZ128mk [HasVLX, HasAVX512]
vfmsubadd132pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PDZ128mkz [HasVLX, HasAVX512]
vfmsubadd132pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PDZ128r [HasVLX, HasAVX512]
vfmsubadd132pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PDZ128rk [HasVLX, HasAVX512]
vfmsubadd132pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PDZ128rkz [HasVLX, HasAVX512]
vfmsubadd132pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PDZ256m [HasVLX, HasAVX512]
vfmsubadd132pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PDZ256mb [HasVLX, HasAVX512]
vfmsubadd132pd {src3{1to4}, src2, dst|dst, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PDZ256mbk [HasVLX, HasAVX512]
vfmsubadd132pd {src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PDZ256mbkz [HasVLX, HasAVX512]
vfmsubadd132pd {src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PDZ256mk [HasVLX, HasAVX512]
vfmsubadd132pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PDZ256mkz [HasVLX, HasAVX512]
vfmsubadd132pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PDZ256r [HasVLX, HasAVX512]
vfmsubadd132pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PDZ256rk [HasVLX, HasAVX512]
vfmsubadd132pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PDZ256rkz [HasVLX, HasAVX512]
vfmsubadd132pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PSZ128m [HasVLX, HasAVX512]
vfmsubadd132ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PSZ128mb [HasVLX, HasAVX512]
vfmsubadd132ps {src3{1to4}, src2, dst|dst, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PSZ128mbk [HasVLX, HasAVX512]
vfmsubadd132ps {src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PSZ128mbkz [HasVLX, HasAVX512]
vfmsubadd132ps {src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PSZ128mk [HasVLX, HasAVX512]
vfmsubadd132ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PSZ128mkz [HasVLX, HasAVX512]
vfmsubadd132ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PSZ128r [HasVLX, HasAVX512]
vfmsubadd132ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PSZ128rk [HasVLX, HasAVX512]
vfmsubadd132ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PSZ128rkz [HasVLX, HasAVX512]
vfmsubadd132ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PSZ256m [HasVLX, HasAVX512]
vfmsubadd132ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PSZ256mb [HasVLX, HasAVX512]
vfmsubadd132ps {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PSZ256mbk [HasVLX, HasAVX512]
vfmsubadd132ps {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PSZ256mbkz [HasVLX, HasAVX512]
vfmsubadd132ps {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PSZ256mk [HasVLX, HasAVX512]
vfmsubadd132ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PSZ256mkz [HasVLX, HasAVX512]
vfmsubadd132ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PSZ256r [HasVLX, HasAVX512]
vfmsubadd132ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PSZ256rk [HasVLX, HasAVX512]
vfmsubadd132ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PSZ256rkz [HasVLX, HasAVX512]
vfmsubadd132ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PDZ128m [HasVLX, HasAVX512]
vfmsubadd213pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PDZ128mb [HasVLX, HasAVX512]
vfmsubadd213pd {src3{1to2}, src2, dst|dst, src2, src3{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PDZ128mbk [HasVLX, HasAVX512]
vfmsubadd213pd {src3{1to2}, src2, dst {mask}|dst {mask}, src2, src3{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PDZ128mbkz [HasVLX, HasAVX512]
vfmsubadd213pd {src3{1to2}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PDZ128mk [HasVLX, HasAVX512]
vfmsubadd213pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PDZ128mkz [HasVLX, HasAVX512]
vfmsubadd213pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PDZ128r [HasVLX, HasAVX512]
vfmsubadd213pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PDZ128rk [HasVLX, HasAVX512]
vfmsubadd213pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PDZ128rkz [HasVLX, HasAVX512]
vfmsubadd213pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PDZ256m [HasVLX, HasAVX512]
vfmsubadd213pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PDZ256mb [HasVLX, HasAVX512]
vfmsubadd213pd {src3{1to4}, src2, dst|dst, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PDZ256mbk [HasVLX, HasAVX512]
vfmsubadd213pd {src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PDZ256mbkz [HasVLX, HasAVX512]
vfmsubadd213pd {src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PDZ256mk [HasVLX, HasAVX512]
vfmsubadd213pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PDZ256mkz [HasVLX, HasAVX512]
vfmsubadd213pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PDZ256r [HasVLX, HasAVX512]
vfmsubadd213pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PDZ256rk [HasVLX, HasAVX512]
vfmsubadd213pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PDZ256rkz [HasVLX, HasAVX512]
vfmsubadd213pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PSZ128m [HasVLX, HasAVX512]
vfmsubadd213ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PSZ128mb [HasVLX, HasAVX512]
vfmsubadd213ps {src3{1to4}, src2, dst|dst, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PSZ128mbk [HasVLX, HasAVX512]
vfmsubadd213ps {src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PSZ128mbkz [HasVLX, HasAVX512]
vfmsubadd213ps {src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PSZ128mk [HasVLX, HasAVX512]
vfmsubadd213ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PSZ128mkz [HasVLX, HasAVX512]
vfmsubadd213ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PSZ128r [HasVLX, HasAVX512]
vfmsubadd213ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PSZ128rk [HasVLX, HasAVX512]
vfmsubadd213ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PSZ128rkz [HasVLX, HasAVX512]
vfmsubadd213ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PSZ256m [HasVLX, HasAVX512]
vfmsubadd213ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PSZ256mb [HasVLX, HasAVX512]
vfmsubadd213ps {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PSZ256mbk [HasVLX, HasAVX512]
vfmsubadd213ps {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PSZ256mbkz [HasVLX, HasAVX512]
vfmsubadd213ps {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PSZ256mk [HasVLX, HasAVX512]
vfmsubadd213ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PSZ256mkz [HasVLX, HasAVX512]
vfmsubadd213ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PSZ256r [HasVLX, HasAVX512]
vfmsubadd213ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PSZ256rk [HasVLX, HasAVX512]
vfmsubadd213ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PSZ256rkz [HasVLX, HasAVX512]
vfmsubadd213ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PDZ128m [HasVLX, HasAVX512]
vfmsubadd231pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PDZ128mb [HasVLX, HasAVX512]
vfmsubadd231pd {src3{1to2}, src2, dst|dst, src2, src3{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PDZ128mbk [HasVLX, HasAVX512]
vfmsubadd231pd {src3{1to2}, src2, dst {mask}|dst {mask}, src2, src3{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PDZ128mbkz [HasVLX, HasAVX512]
vfmsubadd231pd {src3{1to2}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PDZ128mk [HasVLX, HasAVX512]
vfmsubadd231pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PDZ128mkz [HasVLX, HasAVX512]
vfmsubadd231pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PDZ128r [HasVLX, HasAVX512]
vfmsubadd231pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PDZ128rk [HasVLX, HasAVX512]
vfmsubadd231pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PDZ128rkz [HasVLX, HasAVX512]
vfmsubadd231pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PDZ256m [HasVLX, HasAVX512]
vfmsubadd231pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PDZ256mb [HasVLX, HasAVX512]
vfmsubadd231pd {src3{1to4}, src2, dst|dst, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PDZ256mbk [HasVLX, HasAVX512]
vfmsubadd231pd {src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PDZ256mbkz [HasVLX, HasAVX512]
vfmsubadd231pd {src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PDZ256mk [HasVLX, HasAVX512]
vfmsubadd231pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PDZ256mkz [HasVLX, HasAVX512]
vfmsubadd231pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PDZ256r [HasVLX, HasAVX512]
vfmsubadd231pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PDZ256rk [HasVLX, HasAVX512]
vfmsubadd231pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PDZ256rkz [HasVLX, HasAVX512]
vfmsubadd231pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PSZ128m [HasVLX, HasAVX512]
vfmsubadd231ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PSZ128mb [HasVLX, HasAVX512]
vfmsubadd231ps {src3{1to4}, src2, dst|dst, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PSZ128mbk [HasVLX, HasAVX512]
vfmsubadd231ps {src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PSZ128mbkz [HasVLX, HasAVX512]
vfmsubadd231ps {src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PSZ128mk [HasVLX, HasAVX512]
vfmsubadd231ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PSZ128mkz [HasVLX, HasAVX512]
vfmsubadd231ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PSZ128r [HasVLX, HasAVX512]
vfmsubadd231ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PSZ128rk [HasVLX, HasAVX512]
vfmsubadd231ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PSZ128rkz [HasVLX, HasAVX512]
vfmsubadd231ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PSZ256m [HasVLX, HasAVX512]
vfmsubadd231ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PSZ256mb [HasVLX, HasAVX512]
vfmsubadd231ps {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PSZ256mbk [HasVLX, HasAVX512]
vfmsubadd231ps {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PSZ256mbkz [HasVLX, HasAVX512]
vfmsubadd231ps {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PSZ256mk [HasVLX, HasAVX512]
vfmsubadd231ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PSZ256mkz [HasVLX, HasAVX512]
vfmsubadd231ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PSZ256r [HasVLX, HasAVX512]
vfmsubadd231ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PSZ256rk [HasVLX, HasAVX512]
vfmsubadd231ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PSZ256rkz [HasVLX, HasAVX512]
vfmsubadd231ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PDZ128m [HasVLX, HasAVX512]
vfnmadd132pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PDZ128mb [HasVLX, HasAVX512]
vfnmadd132pd {src3{1to2}, src2, dst|dst, src2, src3{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PDZ128mbk [HasVLX, HasAVX512]
vfnmadd132pd {src3{1to2}, src2, dst {mask}|dst {mask}, src2, src3{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PDZ128mbkz [HasVLX, HasAVX512]
vfnmadd132pd {src3{1to2}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PDZ128mk [HasVLX, HasAVX512]
vfnmadd132pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PDZ128mkz [HasVLX, HasAVX512]
vfnmadd132pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PDZ128r [HasVLX, HasAVX512]
vfnmadd132pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PDZ128rk [HasVLX, HasAVX512]
vfnmadd132pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PDZ128rkz [HasVLX, HasAVX512]
vfnmadd132pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PDZ256m [HasVLX, HasAVX512]
vfnmadd132pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PDZ256mb [HasVLX, HasAVX512]
vfnmadd132pd {src3{1to4}, src2, dst|dst, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PDZ256mbk [HasVLX, HasAVX512]
vfnmadd132pd {src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PDZ256mbkz [HasVLX, HasAVX512]
vfnmadd132pd {src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PDZ256mk [HasVLX, HasAVX512]
vfnmadd132pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PDZ256mkz [HasVLX, HasAVX512]
vfnmadd132pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PDZ256r [HasVLX, HasAVX512]
vfnmadd132pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PDZ256rk [HasVLX, HasAVX512]
vfnmadd132pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PDZ256rkz [HasVLX, HasAVX512]
vfnmadd132pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PSZ128m [HasVLX, HasAVX512]
vfnmadd132ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PSZ128mb [HasVLX, HasAVX512]
vfnmadd132ps {src3{1to4}, src2, dst|dst, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PSZ128mbk [HasVLX, HasAVX512]
vfnmadd132ps {src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PSZ128mbkz [HasVLX, HasAVX512]
vfnmadd132ps {src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PSZ128mk [HasVLX, HasAVX512]
vfnmadd132ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PSZ128mkz [HasVLX, HasAVX512]
vfnmadd132ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PSZ128r [HasVLX, HasAVX512]
vfnmadd132ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PSZ128rk [HasVLX, HasAVX512]
vfnmadd132ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PSZ128rkz [HasVLX, HasAVX512]
vfnmadd132ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PSZ256m [HasVLX, HasAVX512]
vfnmadd132ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PSZ256mb [HasVLX, HasAVX512]
vfnmadd132ps {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PSZ256mbk [HasVLX, HasAVX512]
vfnmadd132ps {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PSZ256mbkz [HasVLX, HasAVX512]
vfnmadd132ps {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PSZ256mk [HasVLX, HasAVX512]
vfnmadd132ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PSZ256mkz [HasVLX, HasAVX512]
vfnmadd132ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PSZ256r [HasVLX, HasAVX512]
vfnmadd132ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PSZ256rk [HasVLX, HasAVX512]
vfnmadd132ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PSZ256rkz [HasVLX, HasAVX512]
vfnmadd132ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PDZ128m [HasVLX, HasAVX512]
vfnmadd213pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PDZ128mb [HasVLX, HasAVX512]
vfnmadd213pd {src3{1to2}, src2, dst|dst, src2, src3{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PDZ128mbk [HasVLX, HasAVX512]
vfnmadd213pd {src3{1to2}, src2, dst {mask}|dst {mask}, src2, src3{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PDZ128mbkz [HasVLX, HasAVX512]
vfnmadd213pd {src3{1to2}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PDZ128mk [HasVLX, HasAVX512]
vfnmadd213pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PDZ128mkz [HasVLX, HasAVX512]
vfnmadd213pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PDZ128r [HasVLX, HasAVX512]
vfnmadd213pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PDZ128rk [HasVLX, HasAVX512]
vfnmadd213pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PDZ128rkz [HasVLX, HasAVX512]
vfnmadd213pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PDZ256m [HasVLX, HasAVX512]
vfnmadd213pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PDZ256mb [HasVLX, HasAVX512]
vfnmadd213pd {src3{1to4}, src2, dst|dst, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PDZ256mbk [HasVLX, HasAVX512]
vfnmadd213pd {src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PDZ256mbkz [HasVLX, HasAVX512]
vfnmadd213pd {src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PDZ256mk [HasVLX, HasAVX512]
vfnmadd213pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PDZ256mkz [HasVLX, HasAVX512]
vfnmadd213pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PDZ256r [HasVLX, HasAVX512]
vfnmadd213pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PDZ256rk [HasVLX, HasAVX512]
vfnmadd213pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PDZ256rkz [HasVLX, HasAVX512]
vfnmadd213pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PSZ128m [HasVLX, HasAVX512]
vfnmadd213ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PSZ128mb [HasVLX, HasAVX512]
vfnmadd213ps {src3{1to4}, src2, dst|dst, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PSZ128mbk [HasVLX, HasAVX512]
vfnmadd213ps {src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PSZ128mbkz [HasVLX, HasAVX512]
vfnmadd213ps {src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PSZ128mk [HasVLX, HasAVX512]
vfnmadd213ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PSZ128mkz [HasVLX, HasAVX512]
vfnmadd213ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PSZ128r [HasVLX, HasAVX512]
vfnmadd213ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PSZ128rk [HasVLX, HasAVX512]
vfnmadd213ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PSZ128rkz [HasVLX, HasAVX512]
vfnmadd213ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PSZ256m [HasVLX, HasAVX512]
vfnmadd213ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PSZ256mb [HasVLX, HasAVX512]
vfnmadd213ps {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PSZ256mbk [HasVLX, HasAVX512]
vfnmadd213ps {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PSZ256mbkz [HasVLX, HasAVX512]
vfnmadd213ps {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PSZ256mk [HasVLX, HasAVX512]
vfnmadd213ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PSZ256mkz [HasVLX, HasAVX512]
vfnmadd213ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PSZ256r [HasVLX, HasAVX512]
vfnmadd213ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PSZ256rk [HasVLX, HasAVX512]
vfnmadd213ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PSZ256rkz [HasVLX, HasAVX512]
vfnmadd213ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PDZ128m [HasVLX, HasAVX512]
vfnmadd231pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PDZ128mb [HasVLX, HasAVX512]
vfnmadd231pd {src3{1to2}, src2, dst|dst, src2, src3{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PDZ128mbk [HasVLX, HasAVX512]
vfnmadd231pd {src3{1to2}, src2, dst {mask}|dst {mask}, src2, src3{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PDZ128mbkz [HasVLX, HasAVX512]
vfnmadd231pd {src3{1to2}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PDZ128mk [HasVLX, HasAVX512]
vfnmadd231pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PDZ128mkz [HasVLX, HasAVX512]
vfnmadd231pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PDZ128r [HasVLX, HasAVX512]
vfnmadd231pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PDZ128rk [HasVLX, HasAVX512]
vfnmadd231pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PDZ128rkz [HasVLX, HasAVX512]
vfnmadd231pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PDZ256m [HasVLX, HasAVX512]
vfnmadd231pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PDZ256mb [HasVLX, HasAVX512]
vfnmadd231pd {src3{1to4}, src2, dst|dst, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PDZ256mbk [HasVLX, HasAVX512]
vfnmadd231pd {src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PDZ256mbkz [HasVLX, HasAVX512]
vfnmadd231pd {src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PDZ256mk [HasVLX, HasAVX512]
vfnmadd231pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PDZ256mkz [HasVLX, HasAVX512]
vfnmadd231pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PDZ256r [HasVLX, HasAVX512]
vfnmadd231pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PDZ256rk [HasVLX, HasAVX512]
vfnmadd231pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PDZ256rkz [HasVLX, HasAVX512]
vfnmadd231pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PSZ128m [HasVLX, HasAVX512]
vfnmadd231ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PSZ128mb [HasVLX, HasAVX512]
vfnmadd231ps {src3{1to4}, src2, dst|dst, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PSZ128mbk [HasVLX, HasAVX512]
vfnmadd231ps {src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PSZ128mbkz [HasVLX, HasAVX512]
vfnmadd231ps {src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PSZ128mk [HasVLX, HasAVX512]
vfnmadd231ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PSZ128mkz [HasVLX, HasAVX512]
vfnmadd231ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PSZ128r [HasVLX, HasAVX512]
vfnmadd231ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PSZ128rk [HasVLX, HasAVX512]
vfnmadd231ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PSZ128rkz [HasVLX, HasAVX512]
vfnmadd231ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PSZ256m [HasVLX, HasAVX512]
vfnmadd231ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PSZ256mb [HasVLX, HasAVX512]
vfnmadd231ps {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PSZ256mbk [HasVLX, HasAVX512]
vfnmadd231ps {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PSZ256mbkz [HasVLX, HasAVX512]
vfnmadd231ps {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PSZ256mk [HasVLX, HasAVX512]
vfnmadd231ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PSZ256mkz [HasVLX, HasAVX512]
vfnmadd231ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PSZ256r [HasVLX, HasAVX512]
vfnmadd231ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PSZ256rk [HasVLX, HasAVX512]
vfnmadd231ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PSZ256rkz [HasVLX, HasAVX512]
vfnmadd231ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PDZ128m [HasVLX, HasAVX512]
vfnmsub132pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PDZ128mb [HasVLX, HasAVX512]
vfnmsub132pd {src3{1to2}, src2, dst|dst, src2, src3{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PDZ128mbk [HasVLX, HasAVX512]
vfnmsub132pd {src3{1to2}, src2, dst {mask}|dst {mask}, src2, src3{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PDZ128mbkz [HasVLX, HasAVX512]
vfnmsub132pd {src3{1to2}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PDZ128mk [HasVLX, HasAVX512]
vfnmsub132pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PDZ128mkz [HasVLX, HasAVX512]
vfnmsub132pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PDZ128r [HasVLX, HasAVX512]
vfnmsub132pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PDZ128rk [HasVLX, HasAVX512]
vfnmsub132pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PDZ128rkz [HasVLX, HasAVX512]
vfnmsub132pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PDZ256m [HasVLX, HasAVX512]
vfnmsub132pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PDZ256mb [HasVLX, HasAVX512]
vfnmsub132pd {src3{1to4}, src2, dst|dst, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PDZ256mbk [HasVLX, HasAVX512]
vfnmsub132pd {src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PDZ256mbkz [HasVLX, HasAVX512]
vfnmsub132pd {src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PDZ256mk [HasVLX, HasAVX512]
vfnmsub132pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PDZ256mkz [HasVLX, HasAVX512]
vfnmsub132pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PDZ256r [HasVLX, HasAVX512]
vfnmsub132pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PDZ256rk [HasVLX, HasAVX512]
vfnmsub132pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PDZ256rkz [HasVLX, HasAVX512]
vfnmsub132pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PSZ128m [HasVLX, HasAVX512]
vfnmsub132ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PSZ128mb [HasVLX, HasAVX512]
vfnmsub132ps {src3{1to4}, src2, dst|dst, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PSZ128mbk [HasVLX, HasAVX512]
vfnmsub132ps {src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PSZ128mbkz [HasVLX, HasAVX512]
vfnmsub132ps {src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PSZ128mk [HasVLX, HasAVX512]
vfnmsub132ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PSZ128mkz [HasVLX, HasAVX512]
vfnmsub132ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PSZ128r [HasVLX, HasAVX512]
vfnmsub132ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PSZ128rk [HasVLX, HasAVX512]
vfnmsub132ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PSZ128rkz [HasVLX, HasAVX512]
vfnmsub132ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PSZ256m [HasVLX, HasAVX512]
vfnmsub132ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PSZ256mb [HasVLX, HasAVX512]
vfnmsub132ps {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PSZ256mbk [HasVLX, HasAVX512]
vfnmsub132ps {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PSZ256mbkz [HasVLX, HasAVX512]
vfnmsub132ps {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PSZ256mk [HasVLX, HasAVX512]
vfnmsub132ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PSZ256mkz [HasVLX, HasAVX512]
vfnmsub132ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PSZ256r [HasVLX, HasAVX512]
vfnmsub132ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PSZ256rk [HasVLX, HasAVX512]
vfnmsub132ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PSZ256rkz [HasVLX, HasAVX512]
vfnmsub132ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PDZ128m [HasVLX, HasAVX512]
vfnmsub213pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PDZ128mb [HasVLX, HasAVX512]
vfnmsub213pd {src3{1to2}, src2, dst|dst, src2, src3{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PDZ128mbk [HasVLX, HasAVX512]
vfnmsub213pd {src3{1to2}, src2, dst {mask}|dst {mask}, src2, src3{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PDZ128mbkz [HasVLX, HasAVX512]
vfnmsub213pd {src3{1to2}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PDZ128mk [HasVLX, HasAVX512]
vfnmsub213pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PDZ128mkz [HasVLX, HasAVX512]
vfnmsub213pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PDZ128r [HasVLX, HasAVX512]
vfnmsub213pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PDZ128rk [HasVLX, HasAVX512]
vfnmsub213pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PDZ128rkz [HasVLX, HasAVX512]
vfnmsub213pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PDZ256m [HasVLX, HasAVX512]
vfnmsub213pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PDZ256mb [HasVLX, HasAVX512]
vfnmsub213pd {src3{1to4}, src2, dst|dst, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PDZ256mbk [HasVLX, HasAVX512]
vfnmsub213pd {src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PDZ256mbkz [HasVLX, HasAVX512]
vfnmsub213pd {src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PDZ256mk [HasVLX, HasAVX512]
vfnmsub213pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PDZ256mkz [HasVLX, HasAVX512]
vfnmsub213pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PDZ256r [HasVLX, HasAVX512]
vfnmsub213pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PDZ256rk [HasVLX, HasAVX512]
vfnmsub213pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PDZ256rkz [HasVLX, HasAVX512]
vfnmsub213pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PSZ128m [HasVLX, HasAVX512]
vfnmsub213ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PSZ128mb [HasVLX, HasAVX512]
vfnmsub213ps {src3{1to4}, src2, dst|dst, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PSZ128mbk [HasVLX, HasAVX512]
vfnmsub213ps {src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PSZ128mbkz [HasVLX, HasAVX512]
vfnmsub213ps {src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PSZ128mk [HasVLX, HasAVX512]
vfnmsub213ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PSZ128mkz [HasVLX, HasAVX512]
vfnmsub213ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PSZ128r [HasVLX, HasAVX512]
vfnmsub213ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PSZ128rk [HasVLX, HasAVX512]
vfnmsub213ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PSZ128rkz [HasVLX, HasAVX512]
vfnmsub213ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PSZ256m [HasVLX, HasAVX512]
vfnmsub213ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PSZ256mb [HasVLX, HasAVX512]
vfnmsub213ps {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PSZ256mbk [HasVLX, HasAVX512]
vfnmsub213ps {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PSZ256mbkz [HasVLX, HasAVX512]
vfnmsub213ps {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PSZ256mk [HasVLX, HasAVX512]
vfnmsub213ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PSZ256mkz [HasVLX, HasAVX512]
vfnmsub213ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PSZ256r [HasVLX, HasAVX512]
vfnmsub213ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PSZ256rk [HasVLX, HasAVX512]
vfnmsub213ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PSZ256rkz [HasVLX, HasAVX512]
vfnmsub213ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PDZ128m [HasVLX, HasAVX512]
vfnmsub231pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PDZ128mb [HasVLX, HasAVX512]
vfnmsub231pd {src3{1to2}, src2, dst|dst, src2, src3{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PDZ128mbk [HasVLX, HasAVX512]
vfnmsub231pd {src3{1to2}, src2, dst {mask}|dst {mask}, src2, src3{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PDZ128mbkz [HasVLX, HasAVX512]
vfnmsub231pd {src3{1to2}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PDZ128mk [HasVLX, HasAVX512]
vfnmsub231pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PDZ128mkz [HasVLX, HasAVX512]
vfnmsub231pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PDZ128r [HasVLX, HasAVX512]
vfnmsub231pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PDZ128rk [HasVLX, HasAVX512]
vfnmsub231pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PDZ128rkz [HasVLX, HasAVX512]
vfnmsub231pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PDZ256m [HasVLX, HasAVX512]
vfnmsub231pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PDZ256mb [HasVLX, HasAVX512]
vfnmsub231pd {src3{1to4}, src2, dst|dst, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PDZ256mbk [HasVLX, HasAVX512]
vfnmsub231pd {src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PDZ256mbkz [HasVLX, HasAVX512]
vfnmsub231pd {src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PDZ256mk [HasVLX, HasAVX512]
vfnmsub231pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PDZ256mkz [HasVLX, HasAVX512]
vfnmsub231pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PDZ256r [HasVLX, HasAVX512]
vfnmsub231pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PDZ256rk [HasVLX, HasAVX512]
vfnmsub231pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PDZ256rkz [HasVLX, HasAVX512]
vfnmsub231pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PSZ128m [HasVLX, HasAVX512]
vfnmsub231ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PSZ128mb [HasVLX, HasAVX512]
vfnmsub231ps {src3{1to4}, src2, dst|dst, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PSZ128mbk [HasVLX, HasAVX512]
vfnmsub231ps {src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PSZ128mbkz [HasVLX, HasAVX512]
vfnmsub231ps {src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PSZ128mk [HasVLX, HasAVX512]
vfnmsub231ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PSZ128mkz [HasVLX, HasAVX512]
vfnmsub231ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PSZ128r [HasVLX, HasAVX512]
vfnmsub231ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PSZ128rk [HasVLX, HasAVX512]
vfnmsub231ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PSZ128rkz [HasVLX, HasAVX512]
vfnmsub231ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PSZ256m [HasVLX, HasAVX512]
vfnmsub231ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PSZ256mb [HasVLX, HasAVX512]
vfnmsub231ps {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PSZ256mbk [HasVLX, HasAVX512]
vfnmsub231ps {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PSZ256mbkz [HasVLX, HasAVX512]
vfnmsub231ps {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PSZ256mk [HasVLX, HasAVX512]
vfnmsub231ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PSZ256mkz [HasVLX, HasAVX512]
vfnmsub231ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PSZ256r [HasVLX, HasAVX512]
vfnmsub231ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PSZ256rk [HasVLX, HasAVX512]
vfnmsub231ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PSZ256rkz [HasVLX, HasAVX512]
vfnmsub231ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VGETMANTPDZ128rmbi [HasVLX, HasAVX512]
vgetmantpd {src2, src1{1to2}, dst|dst, src1{1to2}, src2}
|
Note
|
Properties: mayRaiseFPException |
VGETMANTPDZ128rmbik [HasVLX, HasAVX512]
vgetmantpd {src2, src1{1to2}, dst {mask}|dst {mask}, src1{1to2}, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VGETMANTPDZ128rmbikz [HasVLX, HasAVX512]
vgetmantpd {src2, src1{1to2}, dst {mask} {z}|dst {mask} {z}, src1{1to2}, src2}
|
Note
|
Properties: mayRaiseFPException |
VGETMANTPDZ128rmi [HasVLX, HasAVX512]
vgetmantpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VGETMANTPDZ128rmik [HasVLX, HasAVX512]
vgetmantpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VGETMANTPDZ128rmikz [HasVLX, HasAVX512]
vgetmantpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VGETMANTPDZ128rri [HasVLX, HasAVX512]
vgetmantpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VGETMANTPDZ128rrik [HasVLX, HasAVX512]
vgetmantpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VGETMANTPDZ128rrikz [HasVLX, HasAVX512]
vgetmantpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VGETMANTPDZ256rmbi [HasVLX, HasAVX512]
vgetmantpd {src2, src1{1to4}, dst|dst, src1{1to4}, src2}
|
Note
|
Properties: mayRaiseFPException |
VGETMANTPDZ256rmbik [HasVLX, HasAVX512]
vgetmantpd {src2, src1{1to4}, dst {mask}|dst {mask}, src1{1to4}, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VGETMANTPDZ256rmbikz [HasVLX, HasAVX512]
vgetmantpd {src2, src1{1to4}, dst {mask} {z}|dst {mask} {z}, src1{1to4}, src2}
|
Note
|
Properties: mayRaiseFPException |
VGETMANTPDZ256rmi [HasVLX, HasAVX512]
vgetmantpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VGETMANTPDZ256rmik [HasVLX, HasAVX512]
vgetmantpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VGETMANTPDZ256rmikz [HasVLX, HasAVX512]
vgetmantpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VGETMANTPDZ256rri [HasVLX, HasAVX512]
vgetmantpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VGETMANTPDZ256rrik [HasVLX, HasAVX512]
vgetmantpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VGETMANTPDZ256rrikz [HasVLX, HasAVX512]
vgetmantpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VGETMANTPSZ128rmbi [HasVLX, HasAVX512]
vgetmantps {src2, src1{1to4}, dst|dst, src1{1to4}, src2}
|
Note
|
Properties: mayRaiseFPException |
VGETMANTPSZ128rmbik [HasVLX, HasAVX512]
vgetmantps {src2, src1{1to4}, dst {mask}|dst {mask}, src1{1to4}, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VGETMANTPSZ128rmbikz [HasVLX, HasAVX512]
vgetmantps {src2, src1{1to4}, dst {mask} {z}|dst {mask} {z}, src1{1to4}, src2}
|
Note
|
Properties: mayRaiseFPException |
VGETMANTPSZ128rmi [HasVLX, HasAVX512]
vgetmantps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VGETMANTPSZ128rmik [HasVLX, HasAVX512]
vgetmantps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VGETMANTPSZ128rmikz [HasVLX, HasAVX512]
vgetmantps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VGETMANTPSZ128rri [HasVLX, HasAVX512]
vgetmantps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VGETMANTPSZ128rrik [HasVLX, HasAVX512]
vgetmantps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VGETMANTPSZ128rrikz [HasVLX, HasAVX512]
vgetmantps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VGETMANTPSZ256rmbi [HasVLX, HasAVX512]
vgetmantps {src2, src1{1to8}, dst|dst, src1{1to8}, src2}
|
Note
|
Properties: mayRaiseFPException |
VGETMANTPSZ256rmbik [HasVLX, HasAVX512]
vgetmantps {src2, src1{1to8}, dst {mask}|dst {mask}, src1{1to8}, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VGETMANTPSZ256rmbikz [HasVLX, HasAVX512]
vgetmantps {src2, src1{1to8}, dst {mask} {z}|dst {mask} {z}, src1{1to8}, src2}
|
Note
|
Properties: mayRaiseFPException |
VGETMANTPSZ256rmi [HasVLX, HasAVX512]
vgetmantps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VGETMANTPSZ256rmik [HasVLX, HasAVX512]
vgetmantps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VGETMANTPSZ256rmikz [HasVLX, HasAVX512]
vgetmantps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VGETMANTPSZ256rri [HasVLX, HasAVX512]
vgetmantps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VGETMANTPSZ256rrik [HasVLX, HasAVX512]
vgetmantps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VGETMANTPSZ256rrikz [HasVLX, HasAVX512]
vgetmantps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMAXPDZ128rm [HasVLX, HasAVX512]
vmaxpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMAXPDZ128rmb [HasVLX, HasAVX512]
vmaxpd {src2{1to2}, src1, dst|dst, src1, src2{1to2}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMAXPDZ128rmbk [HasVLX, HasAVX512]
vmaxpd {src2{1to2}, src1, dst {mask}|dst {mask}, src1, src2{1to2}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMAXPDZ128rmbkz [HasVLX, HasAVX512]
vmaxpd {src2{1to2}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to2}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMAXPDZ128rmk [HasVLX, HasAVX512]
vmaxpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMAXPDZ128rmkz [HasVLX, HasAVX512]
vmaxpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMAXPDZ128rr [HasVLX, HasAVX512]
vmaxpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMAXPDZ128rrk [HasVLX, HasAVX512]
vmaxpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMAXPDZ128rrkz [HasVLX, HasAVX512]
vmaxpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMAXPDZ256rm [HasVLX, HasAVX512]
vmaxpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMAXPDZ256rmb [HasVLX, HasAVX512]
vmaxpd {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMAXPDZ256rmbk [HasVLX, HasAVX512]
vmaxpd {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMAXPDZ256rmbkz [HasVLX, HasAVX512]
vmaxpd {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMAXPDZ256rmk [HasVLX, HasAVX512]
vmaxpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMAXPDZ256rmkz [HasVLX, HasAVX512]
vmaxpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMAXPDZ256rr [HasVLX, HasAVX512]
vmaxpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMAXPDZ256rrk [HasVLX, HasAVX512]
vmaxpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMAXPDZ256rrkz [HasVLX, HasAVX512]
vmaxpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMAXPSZ128rm [HasVLX, HasAVX512]
vmaxps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMAXPSZ128rmb [HasVLX, HasAVX512]
vmaxps {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMAXPSZ128rmbk [HasVLX, HasAVX512]
vmaxps {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMAXPSZ128rmbkz [HasVLX, HasAVX512]
vmaxps {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMAXPSZ128rmk [HasVLX, HasAVX512]
vmaxps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMAXPSZ128rmkz [HasVLX, HasAVX512]
vmaxps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMAXPSZ128rr [HasVLX, HasAVX512]
vmaxps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMAXPSZ128rrk [HasVLX, HasAVX512]
vmaxps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMAXPSZ128rrkz [HasVLX, HasAVX512]
vmaxps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMAXPSZ256rm [HasVLX, HasAVX512]
vmaxps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMAXPSZ256rmb [HasVLX, HasAVX512]
vmaxps {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMAXPSZ256rmbk [HasVLX, HasAVX512]
vmaxps {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMAXPSZ256rmbkz [HasVLX, HasAVX512]
vmaxps {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMAXPSZ256rmk [HasVLX, HasAVX512]
vmaxps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMAXPSZ256rmkz [HasVLX, HasAVX512]
vmaxps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMAXPSZ256rr [HasVLX, HasAVX512]
vmaxps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMAXPSZ256rrk [HasVLX, HasAVX512]
vmaxps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMAXPSZ256rrkz [HasVLX, HasAVX512]
vmaxps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMINPDZ128rm [HasVLX, HasAVX512]
vminpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMINPDZ128rmb [HasVLX, HasAVX512]
vminpd {src2{1to2}, src1, dst|dst, src1, src2{1to2}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMINPDZ128rmbk [HasVLX, HasAVX512]
vminpd {src2{1to2}, src1, dst {mask}|dst {mask}, src1, src2{1to2}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMINPDZ128rmbkz [HasVLX, HasAVX512]
vminpd {src2{1to2}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to2}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMINPDZ128rmk [HasVLX, HasAVX512]
vminpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMINPDZ128rmkz [HasVLX, HasAVX512]
vminpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMINPDZ128rr [HasVLX, HasAVX512]
vminpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMINPDZ128rrk [HasVLX, HasAVX512]
vminpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMINPDZ128rrkz [HasVLX, HasAVX512]
vminpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMINPDZ256rm [HasVLX, HasAVX512]
vminpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMINPDZ256rmb [HasVLX, HasAVX512]
vminpd {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMINPDZ256rmbk [HasVLX, HasAVX512]
vminpd {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMINPDZ256rmbkz [HasVLX, HasAVX512]
vminpd {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMINPDZ256rmk [HasVLX, HasAVX512]
vminpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMINPDZ256rmkz [HasVLX, HasAVX512]
vminpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMINPDZ256rr [HasVLX, HasAVX512]
vminpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMINPDZ256rrk [HasVLX, HasAVX512]
vminpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMINPDZ256rrkz [HasVLX, HasAVX512]
vminpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMINPSZ128rm [HasVLX, HasAVX512]
vminps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMINPSZ128rmb [HasVLX, HasAVX512]
vminps {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMINPSZ128rmbk [HasVLX, HasAVX512]
vminps {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMINPSZ128rmbkz [HasVLX, HasAVX512]
vminps {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMINPSZ128rmk [HasVLX, HasAVX512]
vminps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMINPSZ128rmkz [HasVLX, HasAVX512]
vminps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMINPSZ128rr [HasVLX, HasAVX512]
vminps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMINPSZ128rrk [HasVLX, HasAVX512]
vminps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMINPSZ128rrkz [HasVLX, HasAVX512]
vminps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMINPSZ256rm [HasVLX, HasAVX512]
vminps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMINPSZ256rmb [HasVLX, HasAVX512]
vminps {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMINPSZ256rmbk [HasVLX, HasAVX512]
vminps {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMINPSZ256rmbkz [HasVLX, HasAVX512]
vminps {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMINPSZ256rmk [HasVLX, HasAVX512]
vminps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMINPSZ256rmkz [HasVLX, HasAVX512]
vminps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMINPSZ256rr [HasVLX, HasAVX512]
vminps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMINPSZ256rrk [HasVLX, HasAVX512]
vminps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMINPSZ256rrkz [HasVLX, HasAVX512]
vminps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMOVAPDZ128mr [HasVLX, HasAVX512]
vmovapd {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VMOVAPDZ128mrk [HasVLX, HasAVX512]
vmovapd {src, dst {mask}|dst {mask}, src}
VMOVAPDZ128rm [HasVLX, HasAVX512]
vmovapd {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
VMOVAPDZ128rmk [HasVLX, HasAVX512]
vmovapd {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVAPDZ128rmkz [HasVLX, HasAVX512]
vmovapd {src, dst {mask} {z}|dst {mask} {z}, src}
VMOVAPDZ128rr [HasVLX, HasAVX512]
vmovapd {src, dst|dst, src}
|
Note
|
Properties: isMoveReg |
VMOVAPDZ128rrk [HasVLX, HasAVX512]
vmovapd {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVAPDZ128rrkz [HasVLX, HasAVX512]
vmovapd {src, dst {mask} {z}|dst {mask} {z}, src}
VMOVAPDZ256mr [HasVLX, HasAVX512]
vmovapd {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VMOVAPDZ256mrk [HasVLX, HasAVX512]
vmovapd {src, dst {mask}|dst {mask}, src}
VMOVAPDZ256rm [HasVLX, HasAVX512]
vmovapd {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
VMOVAPDZ256rmk [HasVLX, HasAVX512]
vmovapd {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVAPDZ256rmkz [HasVLX, HasAVX512]
vmovapd {src, dst {mask} {z}|dst {mask} {z}, src}
VMOVAPDZ256rr [HasVLX, HasAVX512]
vmovapd {src, dst|dst, src}
|
Note
|
Properties: isMoveReg |
VMOVAPDZ256rrk [HasVLX, HasAVX512]
vmovapd {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVAPDZ256rrkz [HasVLX, HasAVX512]
vmovapd {src, dst {mask} {z}|dst {mask} {z}, src}
VMOVAPSZ128mr [HasVLX, HasAVX512]
vmovaps {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VMOVAPSZ128mrk [HasVLX, HasAVX512]
vmovaps {src, dst {mask}|dst {mask}, src}
VMOVAPSZ128rm [HasVLX, HasAVX512]
vmovaps {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
VMOVAPSZ128rmk [HasVLX, HasAVX512]
vmovaps {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVAPSZ128rmkz [HasVLX, HasAVX512]
vmovaps {src, dst {mask} {z}|dst {mask} {z}, src}
VMOVAPSZ128rr [HasVLX, HasAVX512]
vmovaps {src, dst|dst, src}
|
Note
|
Properties: isMoveReg |
VMOVAPSZ128rrk [HasVLX, HasAVX512]
vmovaps {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVAPSZ128rrkz [HasVLX, HasAVX512]
vmovaps {src, dst {mask} {z}|dst {mask} {z}, src}
VMOVAPSZ256mr [HasVLX, HasAVX512]
vmovaps {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VMOVAPSZ256mrk [HasVLX, HasAVX512]
vmovaps {src, dst {mask}|dst {mask}, src}
VMOVAPSZ256rm [HasVLX, HasAVX512]
vmovaps {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
VMOVAPSZ256rmk [HasVLX, HasAVX512]
vmovaps {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVAPSZ256rmkz [HasVLX, HasAVX512]
vmovaps {src, dst {mask} {z}|dst {mask} {z}, src}
VMOVAPSZ256rr [HasVLX, HasAVX512]
vmovaps {src, dst|dst, src}
|
Note
|
Properties: isMoveReg |
VMOVAPSZ256rrk [HasVLX, HasAVX512]
vmovaps {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVAPSZ256rrkz [HasVLX, HasAVX512]
vmovaps {src, dst {mask} {z}|dst {mask} {z}, src}
VMOVDDUPZ128rm [HasVLX, HasAVX512]
vmovddup {src, dst|dst, src}
VMOVDDUPZ128rmk [HasVLX, HasAVX512]
vmovddup {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VMOVDDUPZ128rmkz [HasVLX, HasAVX512]
vmovddup {src, dst {mask} {z}|dst {mask} {z}, src}
VMOVDDUPZ128rr [HasVLX, HasAVX512]
vmovddup {src, dst|dst, src}
VMOVDDUPZ128rrk [HasVLX, HasAVX512]
vmovddup {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VMOVDDUPZ128rrkz [HasVLX, HasAVX512]
vmovddup {src, dst {mask} {z}|dst {mask} {z}, src}
VMOVDDUPZ256rm [HasVLX, HasAVX512]
vmovddup {src1, dst|dst, src1}
VMOVDDUPZ256rmk [HasVLX, HasAVX512]
vmovddup {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVDDUPZ256rmkz [HasVLX, HasAVX512]
vmovddup {src1, dst {mask} {z}|dst {mask} {z}, src1}
VMOVDDUPZ256rr [HasVLX, HasAVX512]
vmovddup {src1, dst|dst, src1}
VMOVDDUPZ256rrk [HasVLX, HasAVX512]
vmovddup {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVDDUPZ256rrkz [HasVLX, HasAVX512]
vmovddup {src1, dst {mask} {z}|dst {mask} {z}, src1}
VMOVDQA32Z128mr [HasVLX, HasAVX512]
vmovdqa32 {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VMOVDQA32Z128mrk [HasVLX, HasAVX512]
vmovdqa32 {src, dst {mask}|dst {mask}, src}
VMOVDQA32Z128rm [HasVLX, HasAVX512]
vmovdqa32 {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
VMOVDQA32Z128rmk [HasVLX, HasAVX512]
vmovdqa32 {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVDQA32Z128rmkz [HasVLX, HasAVX512]
vmovdqa32 {src, dst {mask} {z}|dst {mask} {z}, src}
VMOVDQA32Z128rr [HasVLX, HasAVX512]
vmovdqa32 {src, dst|dst, src}
|
Note
|
Properties: isMoveReg |
VMOVDQA32Z128rrk [HasVLX, HasAVX512]
vmovdqa32 {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVDQA32Z128rrkz [HasVLX, HasAVX512]
vmovdqa32 {src, dst {mask} {z}|dst {mask} {z}, src}
VMOVDQA32Z256mr [HasVLX, HasAVX512]
vmovdqa32 {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VMOVDQA32Z256mrk [HasVLX, HasAVX512]
vmovdqa32 {src, dst {mask}|dst {mask}, src}
VMOVDQA32Z256rm [HasVLX, HasAVX512]
vmovdqa32 {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
VMOVDQA32Z256rmk [HasVLX, HasAVX512]
vmovdqa32 {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVDQA32Z256rmkz [HasVLX, HasAVX512]
vmovdqa32 {src, dst {mask} {z}|dst {mask} {z}, src}
VMOVDQA32Z256rr [HasVLX, HasAVX512]
vmovdqa32 {src, dst|dst, src}
|
Note
|
Properties: isMoveReg |
VMOVDQA32Z256rrk [HasVLX, HasAVX512]
vmovdqa32 {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVDQA32Z256rrkz [HasVLX, HasAVX512]
vmovdqa32 {src, dst {mask} {z}|dst {mask} {z}, src}
VMOVDQA64Z128mr [HasVLX, HasAVX512]
vmovdqa64 {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VMOVDQA64Z128mrk [HasVLX, HasAVX512]
vmovdqa64 {src, dst {mask}|dst {mask}, src}
VMOVDQA64Z128rm [HasVLX, HasAVX512]
vmovdqa64 {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
VMOVDQA64Z128rmk [HasVLX, HasAVX512]
vmovdqa64 {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVDQA64Z128rmkz [HasVLX, HasAVX512]
vmovdqa64 {src, dst {mask} {z}|dst {mask} {z}, src}
VMOVDQA64Z128rr [HasVLX, HasAVX512]
vmovdqa64 {src, dst|dst, src}
|
Note
|
Properties: isMoveReg |
VMOVDQA64Z128rrk [HasVLX, HasAVX512]
vmovdqa64 {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVDQA64Z128rrkz [HasVLX, HasAVX512]
vmovdqa64 {src, dst {mask} {z}|dst {mask} {z}, src}
VMOVDQA64Z256mr [HasVLX, HasAVX512]
vmovdqa64 {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VMOVDQA64Z256mrk [HasVLX, HasAVX512]
vmovdqa64 {src, dst {mask}|dst {mask}, src}
VMOVDQA64Z256rm [HasVLX, HasAVX512]
vmovdqa64 {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
VMOVDQA64Z256rmk [HasVLX, HasAVX512]
vmovdqa64 {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVDQA64Z256rmkz [HasVLX, HasAVX512]
vmovdqa64 {src, dst {mask} {z}|dst {mask} {z}, src}
VMOVDQA64Z256rr [HasVLX, HasAVX512]
vmovdqa64 {src, dst|dst, src}
|
Note
|
Properties: isMoveReg |
VMOVDQA64Z256rrk [HasVLX, HasAVX512]
vmovdqa64 {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVDQA64Z256rrkz [HasVLX, HasAVX512]
vmovdqa64 {src, dst {mask} {z}|dst {mask} {z}, src}
VMOVDQU32Z128mr [HasVLX, HasAVX512]
vmovdqu32 {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VMOVDQU32Z128mrk [HasVLX, HasAVX512]
vmovdqu32 {src, dst {mask}|dst {mask}, src}
VMOVDQU32Z128rm [HasVLX, HasAVX512]
vmovdqu32 {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
VMOVDQU32Z128rmk [HasVLX, HasAVX512]
vmovdqu32 {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVDQU32Z128rmkz [HasVLX, HasAVX512]
vmovdqu32 {src, dst {mask} {z}|dst {mask} {z}, src}
VMOVDQU32Z128rr [HasVLX, HasAVX512]
vmovdqu32 {src, dst|dst, src}
|
Note
|
Properties: isMoveReg |
VMOVDQU32Z128rrk [HasVLX, HasAVX512]
vmovdqu32 {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVDQU32Z128rrkz [HasVLX, HasAVX512]
vmovdqu32 {src, dst {mask} {z}|dst {mask} {z}, src}
VMOVDQU32Z256mr [HasVLX, HasAVX512]
vmovdqu32 {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VMOVDQU32Z256mrk [HasVLX, HasAVX512]
vmovdqu32 {src, dst {mask}|dst {mask}, src}
VMOVDQU32Z256rm [HasVLX, HasAVX512]
vmovdqu32 {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
VMOVDQU32Z256rmk [HasVLX, HasAVX512]
vmovdqu32 {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVDQU32Z256rmkz [HasVLX, HasAVX512]
vmovdqu32 {src, dst {mask} {z}|dst {mask} {z}, src}
VMOVDQU32Z256rr [HasVLX, HasAVX512]
vmovdqu32 {src, dst|dst, src}
|
Note
|
Properties: isMoveReg |
VMOVDQU32Z256rrk [HasVLX, HasAVX512]
vmovdqu32 {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVDQU32Z256rrkz [HasVLX, HasAVX512]
vmovdqu32 {src, dst {mask} {z}|dst {mask} {z}, src}
VMOVDQU64Z128mr [HasVLX, HasAVX512]
vmovdqu64 {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VMOVDQU64Z128mrk [HasVLX, HasAVX512]
vmovdqu64 {src, dst {mask}|dst {mask}, src}
VMOVDQU64Z128rm [HasVLX, HasAVX512]
vmovdqu64 {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
VMOVDQU64Z128rmk [HasVLX, HasAVX512]
vmovdqu64 {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVDQU64Z128rmkz [HasVLX, HasAVX512]
vmovdqu64 {src, dst {mask} {z}|dst {mask} {z}, src}
VMOVDQU64Z128rr [HasVLX, HasAVX512]
vmovdqu64 {src, dst|dst, src}
|
Note
|
Properties: isMoveReg |
VMOVDQU64Z128rrk [HasVLX, HasAVX512]
vmovdqu64 {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVDQU64Z128rrkz [HasVLX, HasAVX512]
vmovdqu64 {src, dst {mask} {z}|dst {mask} {z}, src}
VMOVDQU64Z256mr [HasVLX, HasAVX512]
vmovdqu64 {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VMOVDQU64Z256mrk [HasVLX, HasAVX512]
vmovdqu64 {src, dst {mask}|dst {mask}, src}
VMOVDQU64Z256rm [HasVLX, HasAVX512]
vmovdqu64 {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
VMOVDQU64Z256rmk [HasVLX, HasAVX512]
vmovdqu64 {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVDQU64Z256rmkz [HasVLX, HasAVX512]
vmovdqu64 {src, dst {mask} {z}|dst {mask} {z}, src}
VMOVDQU64Z256rr [HasVLX, HasAVX512]
vmovdqu64 {src, dst|dst, src}
|
Note
|
Properties: isMoveReg |
VMOVDQU64Z256rrk [HasVLX, HasAVX512]
vmovdqu64 {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVDQU64Z256rrkz [HasVLX, HasAVX512]
vmovdqu64 {src, dst {mask} {z}|dst {mask} {z}, src}
VMOVNTDQZ128mr [HasVLX, HasAVX512]
vmovntdq {src, dst|dst, src}
VMOVNTDQZ256mr [HasVLX, HasAVX512]
vmovntdq {src, dst|dst, src}
VMOVNTPDZ128mr [HasVLX, HasAVX512]
vmovntpd {src, dst|dst, src}
VMOVNTPDZ256mr [HasVLX, HasAVX512]
vmovntpd {src, dst|dst, src}
VMOVNTPSZ128mr [HasVLX, HasAVX512]
vmovntps {src, dst|dst, src}
VMOVNTPSZ256mr [HasVLX, HasAVX512]
vmovntps {src, dst|dst, src}
VMOVSHDUPZ128rm [HasVLX, HasAVX512]
vmovshdup {src1, dst|dst, src1}
VMOVSHDUPZ128rmk [HasVLX, HasAVX512]
vmovshdup {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVSHDUPZ128rmkz [HasVLX, HasAVX512]
vmovshdup {src1, dst {mask} {z}|dst {mask} {z}, src1}
VMOVSHDUPZ128rr [HasVLX, HasAVX512]
vmovshdup {src1, dst|dst, src1}
VMOVSHDUPZ128rrk [HasVLX, HasAVX512]
vmovshdup {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVSHDUPZ128rrkz [HasVLX, HasAVX512]
vmovshdup {src1, dst {mask} {z}|dst {mask} {z}, src1}
VMOVSHDUPZ256rm [HasVLX, HasAVX512]
vmovshdup {src1, dst|dst, src1}
VMOVSHDUPZ256rmk [HasVLX, HasAVX512]
vmovshdup {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVSHDUPZ256rmkz [HasVLX, HasAVX512]
vmovshdup {src1, dst {mask} {z}|dst {mask} {z}, src1}
VMOVSHDUPZ256rr [HasVLX, HasAVX512]
vmovshdup {src1, dst|dst, src1}
VMOVSHDUPZ256rrk [HasVLX, HasAVX512]
vmovshdup {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVSHDUPZ256rrkz [HasVLX, HasAVX512]
vmovshdup {src1, dst {mask} {z}|dst {mask} {z}, src1}
VMOVSLDUPZ128rm [HasVLX, HasAVX512]
vmovsldup {src1, dst|dst, src1}
VMOVSLDUPZ128rmk [HasVLX, HasAVX512]
vmovsldup {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVSLDUPZ128rmkz [HasVLX, HasAVX512]
vmovsldup {src1, dst {mask} {z}|dst {mask} {z}, src1}
VMOVSLDUPZ128rr [HasVLX, HasAVX512]
vmovsldup {src1, dst|dst, src1}
VMOVSLDUPZ128rrk [HasVLX, HasAVX512]
vmovsldup {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVSLDUPZ128rrkz [HasVLX, HasAVX512]
vmovsldup {src1, dst {mask} {z}|dst {mask} {z}, src1}
VMOVSLDUPZ256rm [HasVLX, HasAVX512]
vmovsldup {src1, dst|dst, src1}
VMOVSLDUPZ256rmk [HasVLX, HasAVX512]
vmovsldup {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVSLDUPZ256rmkz [HasVLX, HasAVX512]
vmovsldup {src1, dst {mask} {z}|dst {mask} {z}, src1}
VMOVSLDUPZ256rr [HasVLX, HasAVX512]
vmovsldup {src1, dst|dst, src1}
VMOVSLDUPZ256rrk [HasVLX, HasAVX512]
vmovsldup {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVSLDUPZ256rrkz [HasVLX, HasAVX512]
vmovsldup {src1, dst {mask} {z}|dst {mask} {z}, src1}
VMOVUPDZ128mr [HasVLX, HasAVX512]
vmovupd {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VMOVUPDZ128mrk [HasVLX, HasAVX512]
vmovupd {src, dst {mask}|dst {mask}, src}
VMOVUPDZ128rm [HasVLX, HasAVX512]
vmovupd {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
VMOVUPDZ128rmk [HasVLX, HasAVX512]
vmovupd {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVUPDZ128rmkz [HasVLX, HasAVX512]
vmovupd {src, dst {mask} {z}|dst {mask} {z}, src}
VMOVUPDZ128rr [HasVLX, HasAVX512]
vmovupd {src, dst|dst, src}
|
Note
|
Properties: isMoveReg |
VMOVUPDZ128rrk [HasVLX, HasAVX512]
vmovupd {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVUPDZ128rrkz [HasVLX, HasAVX512]
vmovupd {src, dst {mask} {z}|dst {mask} {z}, src}
VMOVUPDZ256mr [HasVLX, HasAVX512]
vmovupd {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VMOVUPDZ256mrk [HasVLX, HasAVX512]
vmovupd {src, dst {mask}|dst {mask}, src}
VMOVUPDZ256rm [HasVLX, HasAVX512]
vmovupd {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
VMOVUPDZ256rmk [HasVLX, HasAVX512]
vmovupd {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVUPDZ256rmkz [HasVLX, HasAVX512]
vmovupd {src, dst {mask} {z}|dst {mask} {z}, src}
VMOVUPDZ256rr [HasVLX, HasAVX512]
vmovupd {src, dst|dst, src}
|
Note
|
Properties: isMoveReg |
VMOVUPDZ256rrk [HasVLX, HasAVX512]
vmovupd {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVUPDZ256rrkz [HasVLX, HasAVX512]
vmovupd {src, dst {mask} {z}|dst {mask} {z}, src}
VMOVUPSZ128mr [HasVLX, HasAVX512]
vmovups {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VMOVUPSZ128mrk [HasVLX, HasAVX512]
vmovups {src, dst {mask}|dst {mask}, src}
VMOVUPSZ128rm [HasVLX, HasAVX512]
vmovups {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
VMOVUPSZ128rmk [HasVLX, HasAVX512]
vmovups {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVUPSZ128rmkz [HasVLX, HasAVX512]
vmovups {src, dst {mask} {z}|dst {mask} {z}, src}
VMOVUPSZ128rr [HasVLX, HasAVX512]
vmovups {src, dst|dst, src}
|
Note
|
Properties: isMoveReg |
VMOVUPSZ128rrk [HasVLX, HasAVX512]
vmovups {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVUPSZ128rrkz [HasVLX, HasAVX512]
vmovups {src, dst {mask} {z}|dst {mask} {z}, src}
VMOVUPSZ256mr [HasVLX, HasAVX512]
vmovups {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VMOVUPSZ256mrk [HasVLX, HasAVX512]
vmovups {src, dst {mask}|dst {mask}, src}
VMOVUPSZ256rm [HasVLX, HasAVX512]
vmovups {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
VMOVUPSZ256rmk [HasVLX, HasAVX512]
vmovups {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVUPSZ256rmkz [HasVLX, HasAVX512]
vmovups {src, dst {mask} {z}|dst {mask} {z}, src}
VMOVUPSZ256rr [HasVLX, HasAVX512]
vmovups {src, dst|dst, src}
|
Note
|
Properties: isMoveReg |
VMOVUPSZ256rrk [HasVLX, HasAVX512]
vmovups {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVUPSZ256rrkz [HasVLX, HasAVX512]
vmovups {src, dst {mask} {z}|dst {mask} {z}, src}
VMULPDZ128rm [HasVLX, HasAVX512]
vmulpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMULPDZ128rmb [HasVLX, HasAVX512]
vmulpd {src2{1to2}, src1, dst|dst, src1, src2{1to2}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMULPDZ128rmbk [HasVLX, HasAVX512]
vmulpd {src2{1to2}, src1, dst {mask}|dst {mask}, src1, src2{1to2}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMULPDZ128rmbkz [HasVLX, HasAVX512]
vmulpd {src2{1to2}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to2}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMULPDZ128rmk [HasVLX, HasAVX512]
vmulpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMULPDZ128rmkz [HasVLX, HasAVX512]
vmulpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMULPDZ128rr [HasVLX, HasAVX512]
vmulpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMULPDZ128rrk [HasVLX, HasAVX512]
vmulpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMULPDZ128rrkz [HasVLX, HasAVX512]
vmulpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMULPDZ256rm [HasVLX, HasAVX512]
vmulpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMULPDZ256rmb [HasVLX, HasAVX512]
vmulpd {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMULPDZ256rmbk [HasVLX, HasAVX512]
vmulpd {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMULPDZ256rmbkz [HasVLX, HasAVX512]
vmulpd {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMULPDZ256rmk [HasVLX, HasAVX512]
vmulpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMULPDZ256rmkz [HasVLX, HasAVX512]
vmulpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMULPDZ256rr [HasVLX, HasAVX512]
vmulpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMULPDZ256rrk [HasVLX, HasAVX512]
vmulpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMULPDZ256rrkz [HasVLX, HasAVX512]
vmulpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMULPSZ128rm [HasVLX, HasAVX512]
vmulps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMULPSZ128rmb [HasVLX, HasAVX512]
vmulps {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMULPSZ128rmbk [HasVLX, HasAVX512]
vmulps {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMULPSZ128rmbkz [HasVLX, HasAVX512]
vmulps {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMULPSZ128rmk [HasVLX, HasAVX512]
vmulps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMULPSZ128rmkz [HasVLX, HasAVX512]
vmulps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMULPSZ128rr [HasVLX, HasAVX512]
vmulps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMULPSZ128rrk [HasVLX, HasAVX512]
vmulps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMULPSZ128rrkz [HasVLX, HasAVX512]
vmulps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMULPSZ256rm [HasVLX, HasAVX512]
vmulps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMULPSZ256rmb [HasVLX, HasAVX512]
vmulps {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMULPSZ256rmbk [HasVLX, HasAVX512]
vmulps {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMULPSZ256rmbkz [HasVLX, HasAVX512]
vmulps {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMULPSZ256rmk [HasVLX, HasAVX512]
vmulps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMULPSZ256rmkz [HasVLX, HasAVX512]
vmulps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMULPSZ256rr [HasVLX, HasAVX512]
vmulps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMULPSZ256rrk [HasVLX, HasAVX512]
vmulps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMULPSZ256rrkz [HasVLX, HasAVX512]
vmulps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VPABSDZ128rm [HasVLX, HasAVX512]
vpabsd {src1, dst|dst, src1}
VPABSDZ128rmb [HasVLX, HasAVX512]
vpabsd {src1{1to4}, dst|dst, src1{1to4}}
VPABSDZ128rmbk [HasVLX, HasAVX512]
vpabsd {src1{1to4}, dst {mask}|dst {mask}, src1{1to4}}
|
Note
|
Constraints: src0 = dst |
VPABSDZ128rmbkz [HasVLX, HasAVX512]
vpabsd {src1{1to4}, dst {mask} {z}|dst {mask} {z}, src1{1to4}}
VPABSDZ128rmk [HasVLX, HasAVX512]
vpabsd {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPABSDZ128rmkz [HasVLX, HasAVX512]
vpabsd {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPABSDZ128rr [HasVLX, HasAVX512]
vpabsd {src1, dst|dst, src1}
VPABSDZ128rrk [HasVLX, HasAVX512]
vpabsd {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPABSDZ128rrkz [HasVLX, HasAVX512]
vpabsd {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPABSDZ256rm [HasVLX, HasAVX512]
vpabsd {src1, dst|dst, src1}
VPABSDZ256rmb [HasVLX, HasAVX512]
vpabsd {src1{1to8}, dst|dst, src1{1to8}}
VPABSDZ256rmbk [HasVLX, HasAVX512]
vpabsd {src1{1to8}, dst {mask}|dst {mask}, src1{1to8}}
|
Note
|
Constraints: src0 = dst |
VPABSDZ256rmbkz [HasVLX, HasAVX512]
vpabsd {src1{1to8}, dst {mask} {z}|dst {mask} {z}, src1{1to8}}
VPABSDZ256rmk [HasVLX, HasAVX512]
vpabsd {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPABSDZ256rmkz [HasVLX, HasAVX512]
vpabsd {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPABSDZ256rr [HasVLX, HasAVX512]
vpabsd {src1, dst|dst, src1}
VPABSDZ256rrk [HasVLX, HasAVX512]
vpabsd {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPABSDZ256rrkz [HasVLX, HasAVX512]
vpabsd {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPABSQZ128rm [HasVLX, HasAVX512]
vpabsq {src1, dst|dst, src1}
VPABSQZ128rmb [HasVLX, HasAVX512]
vpabsq {src1{1to2}, dst|dst, src1{1to2}}
VPABSQZ128rmbk [HasVLX, HasAVX512]
vpabsq {src1{1to2}, dst {mask}|dst {mask}, src1{1to2}}
|
Note
|
Constraints: src0 = dst |
VPABSQZ128rmbkz [HasVLX, HasAVX512]
vpabsq {src1{1to2}, dst {mask} {z}|dst {mask} {z}, src1{1to2}}
VPABSQZ128rmk [HasVLX, HasAVX512]
vpabsq {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPABSQZ128rmkz [HasVLX, HasAVX512]
vpabsq {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPABSQZ128rr [HasVLX, HasAVX512]
vpabsq {src1, dst|dst, src1}
VPABSQZ128rrk [HasVLX, HasAVX512]
vpabsq {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPABSQZ128rrkz [HasVLX, HasAVX512]
vpabsq {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPABSQZ256rm [HasVLX, HasAVX512]
vpabsq {src1, dst|dst, src1}
VPABSQZ256rmb [HasVLX, HasAVX512]
vpabsq {src1{1to4}, dst|dst, src1{1to4}}
VPABSQZ256rmbk [HasVLX, HasAVX512]
vpabsq {src1{1to4}, dst {mask}|dst {mask}, src1{1to4}}
|
Note
|
Constraints: src0 = dst |
VPABSQZ256rmbkz [HasVLX, HasAVX512]
vpabsq {src1{1to4}, dst {mask} {z}|dst {mask} {z}, src1{1to4}}
VPABSQZ256rmk [HasVLX, HasAVX512]
vpabsq {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPABSQZ256rmkz [HasVLX, HasAVX512]
vpabsq {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPABSQZ256rr [HasVLX, HasAVX512]
vpabsq {src1, dst|dst, src1}
VPABSQZ256rrk [HasVLX, HasAVX512]
vpabsq {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPABSQZ256rrkz [HasVLX, HasAVX512]
vpabsq {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPADDDZ128rm [HasVLX, HasAVX512]
vpaddd {src2, src1, dst|dst, src1, src2}
VPADDDZ128rmb [HasVLX, HasAVX512]
vpaddd {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
VPADDDZ128rmbk [HasVLX, HasAVX512]
vpaddd {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Constraints: src0 = dst |
VPADDDZ128rmbkz [HasVLX, HasAVX512]
vpaddd {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
VPADDDZ128rmk [HasVLX, HasAVX512]
vpaddd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPADDDZ128rmkz [HasVLX, HasAVX512]
vpaddd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPADDDZ128rr [HasVLX, HasAVX512]
vpaddd {src2, src1, dst|dst, src1, src2}
VPADDDZ128rrk [HasVLX, HasAVX512]
vpaddd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPADDDZ128rrkz [HasVLX, HasAVX512]
vpaddd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPADDDZ256rm [HasVLX, HasAVX512]
vpaddd {src2, src1, dst|dst, src1, src2}
VPADDDZ256rmb [HasVLX, HasAVX512]
vpaddd {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
VPADDDZ256rmbk [HasVLX, HasAVX512]
vpaddd {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Constraints: src0 = dst |
VPADDDZ256rmbkz [HasVLX, HasAVX512]
vpaddd {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
VPADDDZ256rmk [HasVLX, HasAVX512]
vpaddd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPADDDZ256rmkz [HasVLX, HasAVX512]
vpaddd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPADDDZ256rr [HasVLX, HasAVX512]
vpaddd {src2, src1, dst|dst, src1, src2}
VPADDDZ256rrk [HasVLX, HasAVX512]
vpaddd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPADDDZ256rrkz [HasVLX, HasAVX512]
vpaddd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPADDQZ128rm [HasVLX, HasAVX512]
vpaddq {src2, src1, dst|dst, src1, src2}
VPADDQZ128rmb [HasVLX, HasAVX512]
vpaddq {src2{1to2}, src1, dst|dst, src1, src2{1to2}}
VPADDQZ128rmbk [HasVLX, HasAVX512]
vpaddq {src2{1to2}, src1, dst {mask}|dst {mask}, src1, src2{1to2}}
|
Note
|
Constraints: src0 = dst |
VPADDQZ128rmbkz [HasVLX, HasAVX512]
vpaddq {src2{1to2}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to2}}
VPADDQZ128rmk [HasVLX, HasAVX512]
vpaddq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPADDQZ128rmkz [HasVLX, HasAVX512]
vpaddq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPADDQZ128rr [HasVLX, HasAVX512]
vpaddq {src2, src1, dst|dst, src1, src2}
VPADDQZ128rrk [HasVLX, HasAVX512]
vpaddq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPADDQZ128rrkz [HasVLX, HasAVX512]
vpaddq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPADDQZ256rm [HasVLX, HasAVX512]
vpaddq {src2, src1, dst|dst, src1, src2}
VPADDQZ256rmb [HasVLX, HasAVX512]
vpaddq {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
VPADDQZ256rmbk [HasVLX, HasAVX512]
vpaddq {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Constraints: src0 = dst |
VPADDQZ256rmbkz [HasVLX, HasAVX512]
vpaddq {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
VPADDQZ256rmk [HasVLX, HasAVX512]
vpaddq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPADDQZ256rmkz [HasVLX, HasAVX512]
vpaddq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPADDQZ256rr [HasVLX, HasAVX512]
vpaddq {src2, src1, dst|dst, src1, src2}
VPADDQZ256rrk [HasVLX, HasAVX512]
vpaddq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPADDQZ256rrkz [HasVLX, HasAVX512]
vpaddq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPANDDZ128rm [HasVLX, HasAVX512]
vpandd {src2, src1, dst|dst, src1, src2}
VPANDDZ128rmb [HasVLX, HasAVX512]
vpandd {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
VPANDDZ128rmbk [HasVLX, HasAVX512]
vpandd {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Constraints: src0 = dst |
VPANDDZ128rmbkz [HasVLX, HasAVX512]
vpandd {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
VPANDDZ128rmk [HasVLX, HasAVX512]
vpandd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPANDDZ128rmkz [HasVLX, HasAVX512]
vpandd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPANDDZ128rr [HasVLX, HasAVX512]
vpandd {src2, src1, dst|dst, src1, src2}
VPANDDZ128rrk [HasVLX, HasAVX512]
vpandd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPANDDZ128rrkz [HasVLX, HasAVX512]
vpandd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPANDDZ256rm [HasVLX, HasAVX512]
vpandd {src2, src1, dst|dst, src1, src2}
VPANDDZ256rmb [HasVLX, HasAVX512]
vpandd {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
VPANDDZ256rmbk [HasVLX, HasAVX512]
vpandd {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Constraints: src0 = dst |
VPANDDZ256rmbkz [HasVLX, HasAVX512]
vpandd {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
VPANDDZ256rmk [HasVLX, HasAVX512]
vpandd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPANDDZ256rmkz [HasVLX, HasAVX512]
vpandd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPANDDZ256rr [HasVLX, HasAVX512]
vpandd {src2, src1, dst|dst, src1, src2}
VPANDDZ256rrk [HasVLX, HasAVX512]
vpandd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPANDDZ256rrkz [HasVLX, HasAVX512]
vpandd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPANDNDZ128rm [HasVLX, HasAVX512]
vpandnd {src2, src1, dst|dst, src1, src2}
VPANDNDZ128rmb [HasVLX, HasAVX512]
vpandnd {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
VPANDNDZ128rmbk [HasVLX, HasAVX512]
vpandnd {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Constraints: src0 = dst |
VPANDNDZ128rmbkz [HasVLX, HasAVX512]
vpandnd {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
VPANDNDZ128rmk [HasVLX, HasAVX512]
vpandnd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPANDNDZ128rmkz [HasVLX, HasAVX512]
vpandnd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPANDNDZ128rr [HasVLX, HasAVX512]
vpandnd {src2, src1, dst|dst, src1, src2}
VPANDNDZ128rrk [HasVLX, HasAVX512]
vpandnd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPANDNDZ128rrkz [HasVLX, HasAVX512]
vpandnd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPANDNDZ256rm [HasVLX, HasAVX512]
vpandnd {src2, src1, dst|dst, src1, src2}
VPANDNDZ256rmb [HasVLX, HasAVX512]
vpandnd {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
VPANDNDZ256rmbk [HasVLX, HasAVX512]
vpandnd {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Constraints: src0 = dst |
VPANDNDZ256rmbkz [HasVLX, HasAVX512]
vpandnd {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
VPANDNDZ256rmk [HasVLX, HasAVX512]
vpandnd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPANDNDZ256rmkz [HasVLX, HasAVX512]
vpandnd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPANDNDZ256rr [HasVLX, HasAVX512]
vpandnd {src2, src1, dst|dst, src1, src2}
VPANDNDZ256rrk [HasVLX, HasAVX512]
vpandnd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPANDNDZ256rrkz [HasVLX, HasAVX512]
vpandnd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPANDNQZ128rm [HasVLX, HasAVX512]
vpandnq {src2, src1, dst|dst, src1, src2}
VPANDNQZ128rmb [HasVLX, HasAVX512]
vpandnq {src2{1to2}, src1, dst|dst, src1, src2{1to2}}
VPANDNQZ128rmbk [HasVLX, HasAVX512]
vpandnq {src2{1to2}, src1, dst {mask}|dst {mask}, src1, src2{1to2}}
|
Note
|
Constraints: src0 = dst |
VPANDNQZ128rmbkz [HasVLX, HasAVX512]
vpandnq {src2{1to2}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to2}}
VPANDNQZ128rmk [HasVLX, HasAVX512]
vpandnq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPANDNQZ128rmkz [HasVLX, HasAVX512]
vpandnq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPANDNQZ128rr [HasVLX, HasAVX512]
vpandnq {src2, src1, dst|dst, src1, src2}
VPANDNQZ128rrk [HasVLX, HasAVX512]
vpandnq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPANDNQZ128rrkz [HasVLX, HasAVX512]
vpandnq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPANDNQZ256rm [HasVLX, HasAVX512]
vpandnq {src2, src1, dst|dst, src1, src2}
VPANDNQZ256rmb [HasVLX, HasAVX512]
vpandnq {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
VPANDNQZ256rmbk [HasVLX, HasAVX512]
vpandnq {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Constraints: src0 = dst |
VPANDNQZ256rmbkz [HasVLX, HasAVX512]
vpandnq {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
VPANDNQZ256rmk [HasVLX, HasAVX512]
vpandnq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPANDNQZ256rmkz [HasVLX, HasAVX512]
vpandnq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPANDNQZ256rr [HasVLX, HasAVX512]
vpandnq {src2, src1, dst|dst, src1, src2}
VPANDNQZ256rrk [HasVLX, HasAVX512]
vpandnq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPANDNQZ256rrkz [HasVLX, HasAVX512]
vpandnq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPANDQZ128rm [HasVLX, HasAVX512]
vpandq {src2, src1, dst|dst, src1, src2}
VPANDQZ128rmb [HasVLX, HasAVX512]
vpandq {src2{1to2}, src1, dst|dst, src1, src2{1to2}}
VPANDQZ128rmbk [HasVLX, HasAVX512]
vpandq {src2{1to2}, src1, dst {mask}|dst {mask}, src1, src2{1to2}}
|
Note
|
Constraints: src0 = dst |
VPANDQZ128rmbkz [HasVLX, HasAVX512]
vpandq {src2{1to2}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to2}}
VPANDQZ128rmk [HasVLX, HasAVX512]
vpandq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPANDQZ128rmkz [HasVLX, HasAVX512]
vpandq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPANDQZ128rr [HasVLX, HasAVX512]
vpandq {src2, src1, dst|dst, src1, src2}
VPANDQZ128rrk [HasVLX, HasAVX512]
vpandq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPANDQZ128rrkz [HasVLX, HasAVX512]
vpandq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPANDQZ256rm [HasVLX, HasAVX512]
vpandq {src2, src1, dst|dst, src1, src2}
VPANDQZ256rmb [HasVLX, HasAVX512]
vpandq {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
VPANDQZ256rmbk [HasVLX, HasAVX512]
vpandq {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Constraints: src0 = dst |
VPANDQZ256rmbkz [HasVLX, HasAVX512]
vpandq {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
VPANDQZ256rmk [HasVLX, HasAVX512]
vpandq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPANDQZ256rmkz [HasVLX, HasAVX512]
vpandq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPANDQZ256rr [HasVLX, HasAVX512]
vpandq {src2, src1, dst|dst, src1, src2}
VPANDQZ256rrk [HasVLX, HasAVX512]
vpandq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPANDQZ256rrkz [HasVLX, HasAVX512]
vpandq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPBROADCASTDZ128rm [HasVLX, HasAVX512]
vpbroadcastd {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
VPBROADCASTDZ128rmk [HasVLX, HasAVX512]
vpbroadcastd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPBROADCASTDZ128rmkz [HasVLX, HasAVX512]
vpbroadcastd {src, dst {mask} {z}|dst {mask} {z}, src}
VPBROADCASTDZ128rr [HasVLX, HasAVX512]
vpbroadcastd {src, dst|dst, src}
VPBROADCASTDZ128rrk [HasVLX, HasAVX512]
vpbroadcastd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPBROADCASTDZ128rrkz [HasVLX, HasAVX512]
vpbroadcastd {src, dst {mask} {z}|dst {mask} {z}, src}
VPBROADCASTDZ256rm [HasVLX, HasAVX512]
vpbroadcastd {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
VPBROADCASTDZ256rmk [HasVLX, HasAVX512]
vpbroadcastd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPBROADCASTDZ256rmkz [HasVLX, HasAVX512]
vpbroadcastd {src, dst {mask} {z}|dst {mask} {z}, src}
VPBROADCASTDZ256rr [HasVLX, HasAVX512]
vpbroadcastd {src, dst|dst, src}
VPBROADCASTDZ256rrk [HasVLX, HasAVX512]
vpbroadcastd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPBROADCASTDZ256rrkz [HasVLX, HasAVX512]
vpbroadcastd {src, dst {mask} {z}|dst {mask} {z}, src}
VPBROADCASTDrZ128rr [HasVLX, HasAVX512]
vpbroadcastd {src, dst|dst, src}
VPBROADCASTDrZ128rrk [HasVLX, HasAVX512]
vpbroadcastd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPBROADCASTDrZ128rrkz [HasVLX, HasAVX512]
vpbroadcastd {src, dst {mask} {z}|dst {mask} {z}, src}
VPBROADCASTDrZ256rr [HasVLX, HasAVX512]
vpbroadcastd {src, dst|dst, src}
VPBROADCASTDrZ256rrk [HasVLX, HasAVX512]
vpbroadcastd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPBROADCASTDrZ256rrkz [HasVLX, HasAVX512]
vpbroadcastd {src, dst {mask} {z}|dst {mask} {z}, src}
VPBROADCASTQZ128rm [HasVLX, HasAVX512]
vpbroadcastq {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
VPBROADCASTQZ128rmk [HasVLX, HasAVX512]
vpbroadcastq {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPBROADCASTQZ128rmkz [HasVLX, HasAVX512]
vpbroadcastq {src, dst {mask} {z}|dst {mask} {z}, src}
VPBROADCASTQZ128rr [HasVLX, HasAVX512]
vpbroadcastq {src, dst|dst, src}
VPBROADCASTQZ128rrk [HasVLX, HasAVX512]
vpbroadcastq {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPBROADCASTQZ128rrkz [HasVLX, HasAVX512]
vpbroadcastq {src, dst {mask} {z}|dst {mask} {z}, src}
VPBROADCASTQZ256rm [HasVLX, HasAVX512]
vpbroadcastq {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
VPBROADCASTQZ256rmk [HasVLX, HasAVX512]
vpbroadcastq {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPBROADCASTQZ256rmkz [HasVLX, HasAVX512]
vpbroadcastq {src, dst {mask} {z}|dst {mask} {z}, src}
VPBROADCASTQZ256rr [HasVLX, HasAVX512]
vpbroadcastq {src, dst|dst, src}
VPBROADCASTQZ256rrk [HasVLX, HasAVX512]
vpbroadcastq {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPBROADCASTQZ256rrkz [HasVLX, HasAVX512]
vpbroadcastq {src, dst {mask} {z}|dst {mask} {z}, src}
VPBROADCASTQrZ128rr [HasVLX, HasAVX512]
vpbroadcastq {src, dst|dst, src}
VPBROADCASTQrZ128rrk [HasVLX, HasAVX512]
vpbroadcastq {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPBROADCASTQrZ128rrkz [HasVLX, HasAVX512]
vpbroadcastq {src, dst {mask} {z}|dst {mask} {z}, src}
VPBROADCASTQrZ256rr [HasVLX, HasAVX512]
vpbroadcastq {src, dst|dst, src}
VPBROADCASTQrZ256rrk [HasVLX, HasAVX512]
vpbroadcastq {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPBROADCASTQrZ256rrkz [HasVLX, HasAVX512]
vpbroadcastq {src, dst {mask} {z}|dst {mask} {z}, src}
VPCMPDZ128rmbi [HasVLX, HasAVX512]
vpcmpd {cc, src2{1to4}, src1, dst|dst, src1, src2{1to4}, cc}
VPCMPDZ128rmbik [HasVLX, HasAVX512]
vpcmpd {cc, src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}, cc}
VPCMPDZ128rmi [HasVLX, HasAVX512]
vpcmpd {cc, src2, src1, dst|dst, src1, src2, cc}
VPCMPDZ128rmik [HasVLX, HasAVX512]
vpcmpd {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
VPCMPDZ128rri [HasVLX, HasAVX512]
vpcmpd {cc, src2, src1, dst|dst, src1, src2, cc}
VPCMPDZ128rrik [HasVLX, HasAVX512]
vpcmpd {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
VPCMPDZ256rmbi [HasVLX, HasAVX512]
vpcmpd {cc, src2{1to8}, src1, dst|dst, src1, src2{1to8}, cc}
VPCMPDZ256rmbik [HasVLX, HasAVX512]
vpcmpd {cc, src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}, cc}
VPCMPDZ256rmi [HasVLX, HasAVX512]
vpcmpd {cc, src2, src1, dst|dst, src1, src2, cc}
VPCMPDZ256rmik [HasVLX, HasAVX512]
vpcmpd {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
VPCMPDZ256rri [HasVLX, HasAVX512]
vpcmpd {cc, src2, src1, dst|dst, src1, src2, cc}
VPCMPDZ256rrik [HasVLX, HasAVX512]
vpcmpd {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
VPCMPEQDZ128rm [HasVLX, HasAVX512]
vpcmpeqd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VPCMPEQDZ128rmb [HasVLX, HasAVX512]
vpcmpeqd {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
|
Note
|
Properties: mayLoad |
VPCMPEQDZ128rmbk [HasVLX, HasAVX512]
vpcmpeqd {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Properties: mayLoad |
VPCMPEQDZ128rmk [HasVLX, HasAVX512]
vpcmpeqd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
VPCMPEQDZ128rr [HasVLX, HasAVX512]
vpcmpeqd {src2, src1, dst|dst, src1, src2}
VPCMPEQDZ128rrk [HasVLX, HasAVX512]
vpcmpeqd {src2, src1, dst {mask}|dst {mask}, src1, src2}
VPCMPEQDZ256rm [HasVLX, HasAVX512]
vpcmpeqd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VPCMPEQDZ256rmb [HasVLX, HasAVX512]
vpcmpeqd {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
VPCMPEQDZ256rmbk [HasVLX, HasAVX512]
vpcmpeqd {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
VPCMPEQDZ256rmk [HasVLX, HasAVX512]
vpcmpeqd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
VPCMPEQDZ256rr [HasVLX, HasAVX512]
vpcmpeqd {src2, src1, dst|dst, src1, src2}
VPCMPEQDZ256rrk [HasVLX, HasAVX512]
vpcmpeqd {src2, src1, dst {mask}|dst {mask}, src1, src2}
VPCMPEQQZ128rm [HasVLX, HasAVX512]
vpcmpeqq {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VPCMPEQQZ128rmb [HasVLX, HasAVX512]
vpcmpeqq {src2{1to2}, src1, dst|dst, src1, src2{1to2}}
|
Note
|
Properties: mayLoad |
VPCMPEQQZ128rmbk [HasVLX, HasAVX512]
vpcmpeqq {src2{1to2}, src1, dst {mask}|dst {mask}, src1, src2{1to2}}
|
Note
|
Properties: mayLoad |
VPCMPEQQZ128rmk [HasVLX, HasAVX512]
vpcmpeqq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
VPCMPEQQZ128rr [HasVLX, HasAVX512]
vpcmpeqq {src2, src1, dst|dst, src1, src2}
VPCMPEQQZ128rrk [HasVLX, HasAVX512]
vpcmpeqq {src2, src1, dst {mask}|dst {mask}, src1, src2}
VPCMPEQQZ256rm [HasVLX, HasAVX512]
vpcmpeqq {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VPCMPEQQZ256rmb [HasVLX, HasAVX512]
vpcmpeqq {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
|
Note
|
Properties: mayLoad |
VPCMPEQQZ256rmbk [HasVLX, HasAVX512]
vpcmpeqq {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Properties: mayLoad |
VPCMPEQQZ256rmk [HasVLX, HasAVX512]
vpcmpeqq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
VPCMPEQQZ256rr [HasVLX, HasAVX512]
vpcmpeqq {src2, src1, dst|dst, src1, src2}
VPCMPEQQZ256rrk [HasVLX, HasAVX512]
vpcmpeqq {src2, src1, dst {mask}|dst {mask}, src1, src2}
VPCMPGTDZ128rm [HasVLX, HasAVX512]
vpcmpgtd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VPCMPGTDZ128rmb [HasVLX, HasAVX512]
vpcmpgtd {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
|
Note
|
Properties: mayLoad |
VPCMPGTDZ128rmbk [HasVLX, HasAVX512]
vpcmpgtd {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Properties: mayLoad |
VPCMPGTDZ128rmk [HasVLX, HasAVX512]
vpcmpgtd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
VPCMPGTDZ128rr [HasVLX, HasAVX512]
vpcmpgtd {src2, src1, dst|dst, src1, src2}
VPCMPGTDZ128rrk [HasVLX, HasAVX512]
vpcmpgtd {src2, src1, dst {mask}|dst {mask}, src1, src2}
VPCMPGTDZ256rm [HasVLX, HasAVX512]
vpcmpgtd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VPCMPGTDZ256rmb [HasVLX, HasAVX512]
vpcmpgtd {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
VPCMPGTDZ256rmbk [HasVLX, HasAVX512]
vpcmpgtd {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
VPCMPGTDZ256rmk [HasVLX, HasAVX512]
vpcmpgtd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
VPCMPGTDZ256rr [HasVLX, HasAVX512]
vpcmpgtd {src2, src1, dst|dst, src1, src2}
VPCMPGTDZ256rrk [HasVLX, HasAVX512]
vpcmpgtd {src2, src1, dst {mask}|dst {mask}, src1, src2}
VPCMPGTQZ128rm [HasVLX, HasAVX512]
vpcmpgtq {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VPCMPGTQZ128rmb [HasVLX, HasAVX512]
vpcmpgtq {src2{1to2}, src1, dst|dst, src1, src2{1to2}}
|
Note
|
Properties: mayLoad |
VPCMPGTQZ128rmbk [HasVLX, HasAVX512]
vpcmpgtq {src2{1to2}, src1, dst {mask}|dst {mask}, src1, src2{1to2}}
|
Note
|
Properties: mayLoad |
VPCMPGTQZ128rmk [HasVLX, HasAVX512]
vpcmpgtq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
VPCMPGTQZ128rr [HasVLX, HasAVX512]
vpcmpgtq {src2, src1, dst|dst, src1, src2}
VPCMPGTQZ128rrk [HasVLX, HasAVX512]
vpcmpgtq {src2, src1, dst {mask}|dst {mask}, src1, src2}
VPCMPGTQZ256rm [HasVLX, HasAVX512]
vpcmpgtq {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VPCMPGTQZ256rmb [HasVLX, HasAVX512]
vpcmpgtq {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
|
Note
|
Properties: mayLoad |
VPCMPGTQZ256rmbk [HasVLX, HasAVX512]
vpcmpgtq {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Properties: mayLoad |
VPCMPGTQZ256rmk [HasVLX, HasAVX512]
vpcmpgtq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
VPCMPGTQZ256rr [HasVLX, HasAVX512]
vpcmpgtq {src2, src1, dst|dst, src1, src2}
VPCMPGTQZ256rrk [HasVLX, HasAVX512]
vpcmpgtq {src2, src1, dst {mask}|dst {mask}, src1, src2}
VPCMPQZ128rmbi [HasVLX, HasAVX512]
vpcmpq {cc, src2{1to2}, src1, dst|dst, src1, src2{1to2}, cc}
VPCMPQZ128rmbik [HasVLX, HasAVX512]
vpcmpq {cc, src2{1to2}, src1, dst {mask}|dst {mask}, src1, src2{1to2}, cc}
VPCMPQZ128rmi [HasVLX, HasAVX512]
vpcmpq {cc, src2, src1, dst|dst, src1, src2, cc}
VPCMPQZ128rmik [HasVLX, HasAVX512]
vpcmpq {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
VPCMPQZ128rri [HasVLX, HasAVX512]
vpcmpq {cc, src2, src1, dst|dst, src1, src2, cc}
VPCMPQZ128rrik [HasVLX, HasAVX512]
vpcmpq {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
VPCMPQZ256rmbi [HasVLX, HasAVX512]
vpcmpq {cc, src2{1to4}, src1, dst|dst, src1, src2{1to4}, cc}
VPCMPQZ256rmbik [HasVLX, HasAVX512]
vpcmpq {cc, src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}, cc}
VPCMPQZ256rmi [HasVLX, HasAVX512]
vpcmpq {cc, src2, src1, dst|dst, src1, src2, cc}
VPCMPQZ256rmik [HasVLX, HasAVX512]
vpcmpq {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
VPCMPQZ256rri [HasVLX, HasAVX512]
vpcmpq {cc, src2, src1, dst|dst, src1, src2, cc}
VPCMPQZ256rrik [HasVLX, HasAVX512]
vpcmpq {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
VPCMPUDZ128rmbi [HasVLX, HasAVX512]
vpcmpud {cc, src2{1to4}, src1, dst|dst, src1, src2{1to4}, cc}
VPCMPUDZ128rmbik [HasVLX, HasAVX512]
vpcmpud {cc, src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}, cc}
VPCMPUDZ128rmi [HasVLX, HasAVX512]
vpcmpud {cc, src2, src1, dst|dst, src1, src2, cc}
VPCMPUDZ128rmik [HasVLX, HasAVX512]
vpcmpud {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
VPCMPUDZ128rri [HasVLX, HasAVX512]
vpcmpud {cc, src2, src1, dst|dst, src1, src2, cc}
VPCMPUDZ128rrik [HasVLX, HasAVX512]
vpcmpud {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
VPCMPUDZ256rmbi [HasVLX, HasAVX512]
vpcmpud {cc, src2{1to8}, src1, dst|dst, src1, src2{1to8}, cc}
VPCMPUDZ256rmbik [HasVLX, HasAVX512]
vpcmpud {cc, src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}, cc}
VPCMPUDZ256rmi [HasVLX, HasAVX512]
vpcmpud {cc, src2, src1, dst|dst, src1, src2, cc}
VPCMPUDZ256rmik [HasVLX, HasAVX512]
vpcmpud {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
VPCMPUDZ256rri [HasVLX, HasAVX512]
vpcmpud {cc, src2, src1, dst|dst, src1, src2, cc}
VPCMPUDZ256rrik [HasVLX, HasAVX512]
vpcmpud {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
VPCMPUQZ128rmbi [HasVLX, HasAVX512]
vpcmpuq {cc, src2{1to2}, src1, dst|dst, src1, src2{1to2}, cc}
VPCMPUQZ128rmbik [HasVLX, HasAVX512]
vpcmpuq {cc, src2{1to2}, src1, dst {mask}|dst {mask}, src1, src2{1to2}, cc}
VPCMPUQZ128rmi [HasVLX, HasAVX512]
vpcmpuq {cc, src2, src1, dst|dst, src1, src2, cc}
VPCMPUQZ128rmik [HasVLX, HasAVX512]
vpcmpuq {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
VPCMPUQZ128rri [HasVLX, HasAVX512]
vpcmpuq {cc, src2, src1, dst|dst, src1, src2, cc}
VPCMPUQZ128rrik [HasVLX, HasAVX512]
vpcmpuq {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
VPCMPUQZ256rmbi [HasVLX, HasAVX512]
vpcmpuq {cc, src2{1to4}, src1, dst|dst, src1, src2{1to4}, cc}
VPCMPUQZ256rmbik [HasVLX, HasAVX512]
vpcmpuq {cc, src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}, cc}
VPCMPUQZ256rmi [HasVLX, HasAVX512]
vpcmpuq {cc, src2, src1, dst|dst, src1, src2, cc}
VPCMPUQZ256rmik [HasVLX, HasAVX512]
vpcmpuq {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
VPCMPUQZ256rri [HasVLX, HasAVX512]
vpcmpuq {cc, src2, src1, dst|dst, src1, src2, cc}
VPCMPUQZ256rrik [HasVLX, HasAVX512]
vpcmpuq {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
VPCOMPRESSDZ128mr [HasVLX, HasAVX512]
vpcompressd {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VPCOMPRESSDZ128mrk [HasVLX, HasAVX512]
vpcompressd {src, dst {mask}|dst {mask}, src}
VPCOMPRESSDZ128rr [HasVLX, HasAVX512]
vpcompressd {src1, dst|dst, src1}
VPCOMPRESSDZ128rrk [HasVLX, HasAVX512]
vpcompressd {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPCOMPRESSDZ128rrkz [HasVLX, HasAVX512]
vpcompressd {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPCOMPRESSDZ256mr [HasVLX, HasAVX512]
vpcompressd {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VPCOMPRESSDZ256mrk [HasVLX, HasAVX512]
vpcompressd {src, dst {mask}|dst {mask}, src}
VPCOMPRESSDZ256rr [HasVLX, HasAVX512]
vpcompressd {src1, dst|dst, src1}
VPCOMPRESSDZ256rrk [HasVLX, HasAVX512]
vpcompressd {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPCOMPRESSDZ256rrkz [HasVLX, HasAVX512]
vpcompressd {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPCOMPRESSQZ128mr [HasVLX, HasAVX512]
vpcompressq {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VPCOMPRESSQZ128mrk [HasVLX, HasAVX512]
vpcompressq {src, dst {mask}|dst {mask}, src}
VPCOMPRESSQZ128rr [HasVLX, HasAVX512]
vpcompressq {src1, dst|dst, src1}
VPCOMPRESSQZ128rrk [HasVLX, HasAVX512]
vpcompressq {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPCOMPRESSQZ128rrkz [HasVLX, HasAVX512]
vpcompressq {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPCOMPRESSQZ256mr [HasVLX, HasAVX512]
vpcompressq {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VPCOMPRESSQZ256mrk [HasVLX, HasAVX512]
vpcompressq {src, dst {mask}|dst {mask}, src}
VPCOMPRESSQZ256rr [HasVLX, HasAVX512]
vpcompressq {src1, dst|dst, src1}
VPCOMPRESSQZ256rrk [HasVLX, HasAVX512]
vpcompressq {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPCOMPRESSQZ256rrkz [HasVLX, HasAVX512]
vpcompressq {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPERMDZ256rm [HasVLX, HasAVX512]
vpermd {src2, src1, dst|dst, src1, src2}
VPERMDZ256rmb [HasVLX, HasAVX512]
vpermd {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
VPERMDZ256rmbk [HasVLX, HasAVX512]
vpermd {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Constraints: src0 = dst |
VPERMDZ256rmbkz [HasVLX, HasAVX512]
vpermd {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
VPERMDZ256rmk [HasVLX, HasAVX512]
vpermd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPERMDZ256rmkz [HasVLX, HasAVX512]
vpermd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPERMDZ256rr [HasVLX, HasAVX512]
vpermd {src2, src1, dst|dst, src1, src2}
VPERMDZ256rrk [HasVLX, HasAVX512]
vpermd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPERMDZ256rrkz [HasVLX, HasAVX512]
vpermd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPERMILPDZ128mbi [HasVLX, HasAVX512]
vpermilpd {src2, src1{1to2}, dst|dst, src1{1to2}, src2}
VPERMILPDZ128mbik [HasVLX, HasAVX512]
vpermilpd {src2, src1{1to2}, dst {mask}|dst {mask}, src1{1to2}, src2}
|
Note
|
Constraints: src0 = dst |
VPERMILPDZ128mbikz [HasVLX, HasAVX512]
vpermilpd {src2, src1{1to2}, dst {mask} {z}|dst {mask} {z}, src1{1to2}, src2}
VPERMILPDZ128mi [HasVLX, HasAVX512]
vpermilpd {src2, src1, dst|dst, src1, src2}
VPERMILPDZ128mik [HasVLX, HasAVX512]
vpermilpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPERMILPDZ128mikz [HasVLX, HasAVX512]
vpermilpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPERMILPDZ128ri [HasVLX, HasAVX512]
vpermilpd {src2, src1, dst|dst, src1, src2}
VPERMILPDZ128rik [HasVLX, HasAVX512]
vpermilpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPERMILPDZ128rikz [HasVLX, HasAVX512]
vpermilpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPERMILPDZ128rm [HasVLX, HasAVX512]
vpermilpd {src2, src1, dst|dst, src1, src2}
VPERMILPDZ128rmb [HasVLX, HasAVX512]
vpermilpd {src2{1to2}, src1, dst|dst, src1, src2{1to2}}
VPERMILPDZ128rmbk [HasVLX, HasAVX512]
vpermilpd {src2{1to2}, src1, dst {mask}|dst {mask}, src1, src2{1to2}}
|
Note
|
Constraints: src0 = dst |
VPERMILPDZ128rmbkz [HasVLX, HasAVX512]
vpermilpd {src2{1to2}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to2}}
VPERMILPDZ128rmk [HasVLX, HasAVX512]
vpermilpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPERMILPDZ128rmkz [HasVLX, HasAVX512]
vpermilpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPERMILPDZ128rr [HasVLX, HasAVX512]
vpermilpd {src2, src1, dst|dst, src1, src2}
VPERMILPDZ128rrk [HasVLX, HasAVX512]
vpermilpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPERMILPDZ128rrkz [HasVLX, HasAVX512]
vpermilpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPERMILPDZ256mbi [HasVLX, HasAVX512]
vpermilpd {src2, src1{1to4}, dst|dst, src1{1to4}, src2}
VPERMILPDZ256mbik [HasVLX, HasAVX512]
vpermilpd {src2, src1{1to4}, dst {mask}|dst {mask}, src1{1to4}, src2}
|
Note
|
Constraints: src0 = dst |
VPERMILPDZ256mbikz [HasVLX, HasAVX512]
vpermilpd {src2, src1{1to4}, dst {mask} {z}|dst {mask} {z}, src1{1to4}, src2}
VPERMILPDZ256mi [HasVLX, HasAVX512]
vpermilpd {src2, src1, dst|dst, src1, src2}
VPERMILPDZ256mik [HasVLX, HasAVX512]
vpermilpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPERMILPDZ256mikz [HasVLX, HasAVX512]
vpermilpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPERMILPDZ256ri [HasVLX, HasAVX512]
vpermilpd {src2, src1, dst|dst, src1, src2}
VPERMILPDZ256rik [HasVLX, HasAVX512]
vpermilpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPERMILPDZ256rikz [HasVLX, HasAVX512]
vpermilpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPERMILPDZ256rm [HasVLX, HasAVX512]
vpermilpd {src2, src1, dst|dst, src1, src2}
VPERMILPDZ256rmb [HasVLX, HasAVX512]
vpermilpd {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
VPERMILPDZ256rmbk [HasVLX, HasAVX512]
vpermilpd {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Constraints: src0 = dst |
VPERMILPDZ256rmbkz [HasVLX, HasAVX512]
vpermilpd {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
VPERMILPDZ256rmk [HasVLX, HasAVX512]
vpermilpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPERMILPDZ256rmkz [HasVLX, HasAVX512]
vpermilpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPERMILPDZ256rr [HasVLX, HasAVX512]
vpermilpd {src2, src1, dst|dst, src1, src2}
VPERMILPDZ256rrk [HasVLX, HasAVX512]
vpermilpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPERMILPDZ256rrkz [HasVLX, HasAVX512]
vpermilpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPERMILPSZ128mbi [HasVLX, HasAVX512]
vpermilps {src2, src1{1to4}, dst|dst, src1{1to4}, src2}
VPERMILPSZ128mbik [HasVLX, HasAVX512]
vpermilps {src2, src1{1to4}, dst {mask}|dst {mask}, src1{1to4}, src2}
|
Note
|
Constraints: src0 = dst |
VPERMILPSZ128mbikz [HasVLX, HasAVX512]
vpermilps {src2, src1{1to4}, dst {mask} {z}|dst {mask} {z}, src1{1to4}, src2}
VPERMILPSZ128mi [HasVLX, HasAVX512]
vpermilps {src2, src1, dst|dst, src1, src2}
VPERMILPSZ128mik [HasVLX, HasAVX512]
vpermilps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPERMILPSZ128mikz [HasVLX, HasAVX512]
vpermilps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPERMILPSZ128ri [HasVLX, HasAVX512]
vpermilps {src2, src1, dst|dst, src1, src2}
VPERMILPSZ128rik [HasVLX, HasAVX512]
vpermilps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPERMILPSZ128rikz [HasVLX, HasAVX512]
vpermilps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPERMILPSZ128rm [HasVLX, HasAVX512]
vpermilps {src2, src1, dst|dst, src1, src2}
VPERMILPSZ128rmb [HasVLX, HasAVX512]
vpermilps {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
VPERMILPSZ128rmbk [HasVLX, HasAVX512]
vpermilps {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Constraints: src0 = dst |
VPERMILPSZ128rmbkz [HasVLX, HasAVX512]
vpermilps {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
VPERMILPSZ128rmk [HasVLX, HasAVX512]
vpermilps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPERMILPSZ128rmkz [HasVLX, HasAVX512]
vpermilps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPERMILPSZ128rr [HasVLX, HasAVX512]
vpermilps {src2, src1, dst|dst, src1, src2}
VPERMILPSZ128rrk [HasVLX, HasAVX512]
vpermilps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPERMILPSZ128rrkz [HasVLX, HasAVX512]
vpermilps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPERMILPSZ256mbi [HasVLX, HasAVX512]
vpermilps {src2, src1{1to8}, dst|dst, src1{1to8}, src2}
VPERMILPSZ256mbik [HasVLX, HasAVX512]
vpermilps {src2, src1{1to8}, dst {mask}|dst {mask}, src1{1to8}, src2}
|
Note
|
Constraints: src0 = dst |
VPERMILPSZ256mbikz [HasVLX, HasAVX512]
vpermilps {src2, src1{1to8}, dst {mask} {z}|dst {mask} {z}, src1{1to8}, src2}
VPERMILPSZ256mi [HasVLX, HasAVX512]
vpermilps {src2, src1, dst|dst, src1, src2}
VPERMILPSZ256mik [HasVLX, HasAVX512]
vpermilps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPERMILPSZ256mikz [HasVLX, HasAVX512]
vpermilps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPERMILPSZ256ri [HasVLX, HasAVX512]
vpermilps {src2, src1, dst|dst, src1, src2}
VPERMILPSZ256rik [HasVLX, HasAVX512]
vpermilps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPERMILPSZ256rikz [HasVLX, HasAVX512]
vpermilps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPERMILPSZ256rm [HasVLX, HasAVX512]
vpermilps {src2, src1, dst|dst, src1, src2}
VPERMILPSZ256rmb [HasVLX, HasAVX512]
vpermilps {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
VPERMILPSZ256rmbk [HasVLX, HasAVX512]
vpermilps {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Constraints: src0 = dst |
VPERMILPSZ256rmbkz [HasVLX, HasAVX512]
vpermilps {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
VPERMILPSZ256rmk [HasVLX, HasAVX512]
vpermilps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPERMILPSZ256rmkz [HasVLX, HasAVX512]
vpermilps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPERMILPSZ256rr [HasVLX, HasAVX512]
vpermilps {src2, src1, dst|dst, src1, src2}
VPERMILPSZ256rrk [HasVLX, HasAVX512]
vpermilps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPERMILPSZ256rrkz [HasVLX, HasAVX512]
vpermilps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPERMPDZ256mbi [HasVLX, HasAVX512]
vpermpd {src2, src1{1to4}, dst|dst, src1{1to4}, src2}
VPERMPDZ256mbik [HasVLX, HasAVX512]
vpermpd {src2, src1{1to4}, dst {mask}|dst {mask}, src1{1to4}, src2}
|
Note
|
Constraints: src0 = dst |
VPERMPDZ256mbikz [HasVLX, HasAVX512]
vpermpd {src2, src1{1to4}, dst {mask} {z}|dst {mask} {z}, src1{1to4}, src2}
VPERMPDZ256mi [HasVLX, HasAVX512]
vpermpd {src2, src1, dst|dst, src1, src2}
VPERMPDZ256mik [HasVLX, HasAVX512]
vpermpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPERMPDZ256mikz [HasVLX, HasAVX512]
vpermpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPERMPDZ256ri [HasVLX, HasAVX512]
vpermpd {src2, src1, dst|dst, src1, src2}
VPERMPDZ256rik [HasVLX, HasAVX512]
vpermpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPERMPDZ256rikz [HasVLX, HasAVX512]
vpermpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPERMPDZ256rm [HasVLX, HasAVX512]
vpermpd {src2, src1, dst|dst, src1, src2}
VPERMPDZ256rmb [HasVLX, HasAVX512]
vpermpd {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
VPERMPDZ256rmbk [HasVLX, HasAVX512]
vpermpd {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Constraints: src0 = dst |
VPERMPDZ256rmbkz [HasVLX, HasAVX512]
vpermpd {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
VPERMPDZ256rmk [HasVLX, HasAVX512]
vpermpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPERMPDZ256rmkz [HasVLX, HasAVX512]
vpermpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPERMPDZ256rr [HasVLX, HasAVX512]
vpermpd {src2, src1, dst|dst, src1, src2}
VPERMPDZ256rrk [HasVLX, HasAVX512]
vpermpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPERMPDZ256rrkz [HasVLX, HasAVX512]
vpermpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPERMPSZ256rm [HasVLX, HasAVX512]
vpermps {src2, src1, dst|dst, src1, src2}
VPERMPSZ256rmb [HasVLX, HasAVX512]
vpermps {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
VPERMPSZ256rmbk [HasVLX, HasAVX512]
vpermps {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Constraints: src0 = dst |
VPERMPSZ256rmbkz [HasVLX, HasAVX512]
vpermps {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
VPERMPSZ256rmk [HasVLX, HasAVX512]
vpermps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPERMPSZ256rmkz [HasVLX, HasAVX512]
vpermps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPERMPSZ256rr [HasVLX, HasAVX512]
vpermps {src2, src1, dst|dst, src1, src2}
VPERMPSZ256rrk [HasVLX, HasAVX512]
vpermps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPERMPSZ256rrkz [HasVLX, HasAVX512]
vpermps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPERMQZ256mbi [HasVLX, HasAVX512]
vpermq {src2, src1{1to4}, dst|dst, src1{1to4}, src2}
VPERMQZ256mbik [HasVLX, HasAVX512]
vpermq {src2, src1{1to4}, dst {mask}|dst {mask}, src1{1to4}, src2}
|
Note
|
Constraints: src0 = dst |
VPERMQZ256mbikz [HasVLX, HasAVX512]
vpermq {src2, src1{1to4}, dst {mask} {z}|dst {mask} {z}, src1{1to4}, src2}
VPERMQZ256mi [HasVLX, HasAVX512]
vpermq {src2, src1, dst|dst, src1, src2}
VPERMQZ256mik [HasVLX, HasAVX512]
vpermq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPERMQZ256mikz [HasVLX, HasAVX512]
vpermq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPERMQZ256ri [HasVLX, HasAVX512]
vpermq {src2, src1, dst|dst, src1, src2}
VPERMQZ256rik [HasVLX, HasAVX512]
vpermq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPERMQZ256rikz [HasVLX, HasAVX512]
vpermq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPERMQZ256rm [HasVLX, HasAVX512]
vpermq {src2, src1, dst|dst, src1, src2}
VPERMQZ256rmb [HasVLX, HasAVX512]
vpermq {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
VPERMQZ256rmbk [HasVLX, HasAVX512]
vpermq {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Constraints: src0 = dst |
VPERMQZ256rmbkz [HasVLX, HasAVX512]
vpermq {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
VPERMQZ256rmk [HasVLX, HasAVX512]
vpermq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPERMQZ256rmkz [HasVLX, HasAVX512]
vpermq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPERMQZ256rr [HasVLX, HasAVX512]
vpermq {src2, src1, dst|dst, src1, src2}
VPERMQZ256rrk [HasVLX, HasAVX512]
vpermq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPERMQZ256rrkz [HasVLX, HasAVX512]
vpermq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPEXPANDDZ128rm [HasVLX, HasAVX512]
vpexpandd {src1, dst|dst, src1}
VPEXPANDDZ128rmk [HasVLX, HasAVX512]
vpexpandd {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPEXPANDDZ128rmkz [HasVLX, HasAVX512]
vpexpandd {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPEXPANDDZ128rr [HasVLX, HasAVX512]
vpexpandd {src1, dst|dst, src1}
VPEXPANDDZ128rrk [HasVLX, HasAVX512]
vpexpandd {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPEXPANDDZ128rrkz [HasVLX, HasAVX512]
vpexpandd {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPEXPANDDZ256rm [HasVLX, HasAVX512]
vpexpandd {src1, dst|dst, src1}
VPEXPANDDZ256rmk [HasVLX, HasAVX512]
vpexpandd {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPEXPANDDZ256rmkz [HasVLX, HasAVX512]
vpexpandd {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPEXPANDDZ256rr [HasVLX, HasAVX512]
vpexpandd {src1, dst|dst, src1}
VPEXPANDDZ256rrk [HasVLX, HasAVX512]
vpexpandd {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPEXPANDDZ256rrkz [HasVLX, HasAVX512]
vpexpandd {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPEXPANDQZ128rm [HasVLX, HasAVX512]
vpexpandq {src1, dst|dst, src1}
VPEXPANDQZ128rmk [HasVLX, HasAVX512]
vpexpandq {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPEXPANDQZ128rmkz [HasVLX, HasAVX512]
vpexpandq {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPEXPANDQZ128rr [HasVLX, HasAVX512]
vpexpandq {src1, dst|dst, src1}
VPEXPANDQZ128rrk [HasVLX, HasAVX512]
vpexpandq {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPEXPANDQZ128rrkz [HasVLX, HasAVX512]
vpexpandq {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPEXPANDQZ256rm [HasVLX, HasAVX512]
vpexpandq {src1, dst|dst, src1}
VPEXPANDQZ256rmk [HasVLX, HasAVX512]
vpexpandq {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPEXPANDQZ256rmkz [HasVLX, HasAVX512]
vpexpandq {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPEXPANDQZ256rr [HasVLX, HasAVX512]
vpexpandq {src1, dst|dst, src1}
VPEXPANDQZ256rrk [HasVLX, HasAVX512]
vpexpandq {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPEXPANDQZ256rrkz [HasVLX, HasAVX512]
vpexpandq {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPMAXSDZ128rm [HasVLX, HasAVX512]
vpmaxsd {src2, src1, dst|dst, src1, src2}
VPMAXSDZ128rmb [HasVLX, HasAVX512]
vpmaxsd {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
VPMAXSDZ128rmbk [HasVLX, HasAVX512]
vpmaxsd {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Constraints: src0 = dst |
VPMAXSDZ128rmbkz [HasVLX, HasAVX512]
vpmaxsd {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
VPMAXSDZ128rmk [HasVLX, HasAVX512]
vpmaxsd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMAXSDZ128rmkz [HasVLX, HasAVX512]
vpmaxsd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMAXSDZ128rr [HasVLX, HasAVX512]
vpmaxsd {src2, src1, dst|dst, src1, src2}
VPMAXSDZ128rrk [HasVLX, HasAVX512]
vpmaxsd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMAXSDZ128rrkz [HasVLX, HasAVX512]
vpmaxsd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMAXSDZ256rm [HasVLX, HasAVX512]
vpmaxsd {src2, src1, dst|dst, src1, src2}
VPMAXSDZ256rmb [HasVLX, HasAVX512]
vpmaxsd {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
VPMAXSDZ256rmbk [HasVLX, HasAVX512]
vpmaxsd {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Constraints: src0 = dst |
VPMAXSDZ256rmbkz [HasVLX, HasAVX512]
vpmaxsd {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
VPMAXSDZ256rmk [HasVLX, HasAVX512]
vpmaxsd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMAXSDZ256rmkz [HasVLX, HasAVX512]
vpmaxsd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMAXSDZ256rr [HasVLX, HasAVX512]
vpmaxsd {src2, src1, dst|dst, src1, src2}
VPMAXSDZ256rrk [HasVLX, HasAVX512]
vpmaxsd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMAXSDZ256rrkz [HasVLX, HasAVX512]
vpmaxsd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMAXSQZ128rm [HasVLX, HasAVX512]
vpmaxsq {src2, src1, dst|dst, src1, src2}
VPMAXSQZ128rmb [HasVLX, HasAVX512]
vpmaxsq {src2{1to2}, src1, dst|dst, src1, src2{1to2}}
VPMAXSQZ128rmbk [HasVLX, HasAVX512]
vpmaxsq {src2{1to2}, src1, dst {mask}|dst {mask}, src1, src2{1to2}}
|
Note
|
Constraints: src0 = dst |
VPMAXSQZ128rmbkz [HasVLX, HasAVX512]
vpmaxsq {src2{1to2}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to2}}
VPMAXSQZ128rmk [HasVLX, HasAVX512]
vpmaxsq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMAXSQZ128rmkz [HasVLX, HasAVX512]
vpmaxsq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMAXSQZ128rr [HasVLX, HasAVX512]
vpmaxsq {src2, src1, dst|dst, src1, src2}
VPMAXSQZ128rrk [HasVLX, HasAVX512]
vpmaxsq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMAXSQZ128rrkz [HasVLX, HasAVX512]
vpmaxsq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMAXSQZ256rm [HasVLX, HasAVX512]
vpmaxsq {src2, src1, dst|dst, src1, src2}
VPMAXSQZ256rmb [HasVLX, HasAVX512]
vpmaxsq {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
VPMAXSQZ256rmbk [HasVLX, HasAVX512]
vpmaxsq {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Constraints: src0 = dst |
VPMAXSQZ256rmbkz [HasVLX, HasAVX512]
vpmaxsq {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
VPMAXSQZ256rmk [HasVLX, HasAVX512]
vpmaxsq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMAXSQZ256rmkz [HasVLX, HasAVX512]
vpmaxsq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMAXSQZ256rr [HasVLX, HasAVX512]
vpmaxsq {src2, src1, dst|dst, src1, src2}
VPMAXSQZ256rrk [HasVLX, HasAVX512]
vpmaxsq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMAXSQZ256rrkz [HasVLX, HasAVX512]
vpmaxsq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMAXUDZ128rm [HasVLX, HasAVX512]
vpmaxud {src2, src1, dst|dst, src1, src2}
VPMAXUDZ128rmb [HasVLX, HasAVX512]
vpmaxud {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
VPMAXUDZ128rmbk [HasVLX, HasAVX512]
vpmaxud {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Constraints: src0 = dst |
VPMAXUDZ128rmbkz [HasVLX, HasAVX512]
vpmaxud {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
VPMAXUDZ128rmk [HasVLX, HasAVX512]
vpmaxud {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMAXUDZ128rmkz [HasVLX, HasAVX512]
vpmaxud {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMAXUDZ128rr [HasVLX, HasAVX512]
vpmaxud {src2, src1, dst|dst, src1, src2}
VPMAXUDZ128rrk [HasVLX, HasAVX512]
vpmaxud {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMAXUDZ128rrkz [HasVLX, HasAVX512]
vpmaxud {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMAXUDZ256rm [HasVLX, HasAVX512]
vpmaxud {src2, src1, dst|dst, src1, src2}
VPMAXUDZ256rmb [HasVLX, HasAVX512]
vpmaxud {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
VPMAXUDZ256rmbk [HasVLX, HasAVX512]
vpmaxud {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Constraints: src0 = dst |
VPMAXUDZ256rmbkz [HasVLX, HasAVX512]
vpmaxud {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
VPMAXUDZ256rmk [HasVLX, HasAVX512]
vpmaxud {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMAXUDZ256rmkz [HasVLX, HasAVX512]
vpmaxud {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMAXUDZ256rr [HasVLX, HasAVX512]
vpmaxud {src2, src1, dst|dst, src1, src2}
VPMAXUDZ256rrk [HasVLX, HasAVX512]
vpmaxud {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMAXUDZ256rrkz [HasVLX, HasAVX512]
vpmaxud {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMAXUQZ128rm [HasVLX, HasAVX512]
vpmaxuq {src2, src1, dst|dst, src1, src2}
VPMAXUQZ128rmb [HasVLX, HasAVX512]
vpmaxuq {src2{1to2}, src1, dst|dst, src1, src2{1to2}}
VPMAXUQZ128rmbk [HasVLX, HasAVX512]
vpmaxuq {src2{1to2}, src1, dst {mask}|dst {mask}, src1, src2{1to2}}
|
Note
|
Constraints: src0 = dst |
VPMAXUQZ128rmbkz [HasVLX, HasAVX512]
vpmaxuq {src2{1to2}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to2}}
VPMAXUQZ128rmk [HasVLX, HasAVX512]
vpmaxuq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMAXUQZ128rmkz [HasVLX, HasAVX512]
vpmaxuq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMAXUQZ128rr [HasVLX, HasAVX512]
vpmaxuq {src2, src1, dst|dst, src1, src2}
VPMAXUQZ128rrk [HasVLX, HasAVX512]
vpmaxuq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMAXUQZ128rrkz [HasVLX, HasAVX512]
vpmaxuq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMAXUQZ256rm [HasVLX, HasAVX512]
vpmaxuq {src2, src1, dst|dst, src1, src2}
VPMAXUQZ256rmb [HasVLX, HasAVX512]
vpmaxuq {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
VPMAXUQZ256rmbk [HasVLX, HasAVX512]
vpmaxuq {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Constraints: src0 = dst |
VPMAXUQZ256rmbkz [HasVLX, HasAVX512]
vpmaxuq {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
VPMAXUQZ256rmk [HasVLX, HasAVX512]
vpmaxuq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMAXUQZ256rmkz [HasVLX, HasAVX512]
vpmaxuq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMAXUQZ256rr [HasVLX, HasAVX512]
vpmaxuq {src2, src1, dst|dst, src1, src2}
VPMAXUQZ256rrk [HasVLX, HasAVX512]
vpmaxuq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMAXUQZ256rrkz [HasVLX, HasAVX512]
vpmaxuq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMINSDZ128rm [HasVLX, HasAVX512]
vpminsd {src2, src1, dst|dst, src1, src2}
VPMINSDZ128rmb [HasVLX, HasAVX512]
vpminsd {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
VPMINSDZ128rmbk [HasVLX, HasAVX512]
vpminsd {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Constraints: src0 = dst |
VPMINSDZ128rmbkz [HasVLX, HasAVX512]
vpminsd {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
VPMINSDZ128rmk [HasVLX, HasAVX512]
vpminsd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMINSDZ128rmkz [HasVLX, HasAVX512]
vpminsd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMINSDZ128rr [HasVLX, HasAVX512]
vpminsd {src2, src1, dst|dst, src1, src2}
VPMINSDZ128rrk [HasVLX, HasAVX512]
vpminsd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMINSDZ128rrkz [HasVLX, HasAVX512]
vpminsd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMINSDZ256rm [HasVLX, HasAVX512]
vpminsd {src2, src1, dst|dst, src1, src2}
VPMINSDZ256rmb [HasVLX, HasAVX512]
vpminsd {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
VPMINSDZ256rmbk [HasVLX, HasAVX512]
vpminsd {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Constraints: src0 = dst |
VPMINSDZ256rmbkz [HasVLX, HasAVX512]
vpminsd {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
VPMINSDZ256rmk [HasVLX, HasAVX512]
vpminsd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMINSDZ256rmkz [HasVLX, HasAVX512]
vpminsd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMINSDZ256rr [HasVLX, HasAVX512]
vpminsd {src2, src1, dst|dst, src1, src2}
VPMINSDZ256rrk [HasVLX, HasAVX512]
vpminsd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMINSDZ256rrkz [HasVLX, HasAVX512]
vpminsd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMINSQZ128rm [HasVLX, HasAVX512]
vpminsq {src2, src1, dst|dst, src1, src2}
VPMINSQZ128rmb [HasVLX, HasAVX512]
vpminsq {src2{1to2}, src1, dst|dst, src1, src2{1to2}}
VPMINSQZ128rmbk [HasVLX, HasAVX512]
vpminsq {src2{1to2}, src1, dst {mask}|dst {mask}, src1, src2{1to2}}
|
Note
|
Constraints: src0 = dst |
VPMINSQZ128rmbkz [HasVLX, HasAVX512]
vpminsq {src2{1to2}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to2}}
VPMINSQZ128rmk [HasVLX, HasAVX512]
vpminsq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMINSQZ128rmkz [HasVLX, HasAVX512]
vpminsq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMINSQZ128rr [HasVLX, HasAVX512]
vpminsq {src2, src1, dst|dst, src1, src2}
VPMINSQZ128rrk [HasVLX, HasAVX512]
vpminsq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMINSQZ128rrkz [HasVLX, HasAVX512]
vpminsq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMINSQZ256rm [HasVLX, HasAVX512]
vpminsq {src2, src1, dst|dst, src1, src2}
VPMINSQZ256rmb [HasVLX, HasAVX512]
vpminsq {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
VPMINSQZ256rmbk [HasVLX, HasAVX512]
vpminsq {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Constraints: src0 = dst |
VPMINSQZ256rmbkz [HasVLX, HasAVX512]
vpminsq {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
VPMINSQZ256rmk [HasVLX, HasAVX512]
vpminsq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMINSQZ256rmkz [HasVLX, HasAVX512]
vpminsq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMINSQZ256rr [HasVLX, HasAVX512]
vpminsq {src2, src1, dst|dst, src1, src2}
VPMINSQZ256rrk [HasVLX, HasAVX512]
vpminsq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMINSQZ256rrkz [HasVLX, HasAVX512]
vpminsq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMINUDZ128rm [HasVLX, HasAVX512]
vpminud {src2, src1, dst|dst, src1, src2}
VPMINUDZ128rmb [HasVLX, HasAVX512]
vpminud {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
VPMINUDZ128rmbk [HasVLX, HasAVX512]
vpminud {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Constraints: src0 = dst |
VPMINUDZ128rmbkz [HasVLX, HasAVX512]
vpminud {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
VPMINUDZ128rmk [HasVLX, HasAVX512]
vpminud {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMINUDZ128rmkz [HasVLX, HasAVX512]
vpminud {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMINUDZ128rr [HasVLX, HasAVX512]
vpminud {src2, src1, dst|dst, src1, src2}
VPMINUDZ128rrk [HasVLX, HasAVX512]
vpminud {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMINUDZ128rrkz [HasVLX, HasAVX512]
vpminud {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMINUDZ256rm [HasVLX, HasAVX512]
vpminud {src2, src1, dst|dst, src1, src2}
VPMINUDZ256rmb [HasVLX, HasAVX512]
vpminud {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
VPMINUDZ256rmbk [HasVLX, HasAVX512]
vpminud {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Constraints: src0 = dst |
VPMINUDZ256rmbkz [HasVLX, HasAVX512]
vpminud {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
VPMINUDZ256rmk [HasVLX, HasAVX512]
vpminud {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMINUDZ256rmkz [HasVLX, HasAVX512]
vpminud {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMINUDZ256rr [HasVLX, HasAVX512]
vpminud {src2, src1, dst|dst, src1, src2}
VPMINUDZ256rrk [HasVLX, HasAVX512]
vpminud {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMINUDZ256rrkz [HasVLX, HasAVX512]
vpminud {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMINUQZ128rm [HasVLX, HasAVX512]
vpminuq {src2, src1, dst|dst, src1, src2}
VPMINUQZ128rmb [HasVLX, HasAVX512]
vpminuq {src2{1to2}, src1, dst|dst, src1, src2{1to2}}
VPMINUQZ128rmbk [HasVLX, HasAVX512]
vpminuq {src2{1to2}, src1, dst {mask}|dst {mask}, src1, src2{1to2}}
|
Note
|
Constraints: src0 = dst |
VPMINUQZ128rmbkz [HasVLX, HasAVX512]
vpminuq {src2{1to2}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to2}}
VPMINUQZ128rmk [HasVLX, HasAVX512]
vpminuq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMINUQZ128rmkz [HasVLX, HasAVX512]
vpminuq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMINUQZ128rr [HasVLX, HasAVX512]
vpminuq {src2, src1, dst|dst, src1, src2}
VPMINUQZ128rrk [HasVLX, HasAVX512]
vpminuq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMINUQZ128rrkz [HasVLX, HasAVX512]
vpminuq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMINUQZ256rm [HasVLX, HasAVX512]
vpminuq {src2, src1, dst|dst, src1, src2}
VPMINUQZ256rmb [HasVLX, HasAVX512]
vpminuq {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
VPMINUQZ256rmbk [HasVLX, HasAVX512]
vpminuq {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Constraints: src0 = dst |
VPMINUQZ256rmbkz [HasVLX, HasAVX512]
vpminuq {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
VPMINUQZ256rmk [HasVLX, HasAVX512]
vpminuq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMINUQZ256rmkz [HasVLX, HasAVX512]
vpminuq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMINUQZ256rr [HasVLX, HasAVX512]
vpminuq {src2, src1, dst|dst, src1, src2}
VPMINUQZ256rrk [HasVLX, HasAVX512]
vpminuq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMINUQZ256rrkz [HasVLX, HasAVX512]
vpminuq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMOVDBZ128mr [HasVLX, HasAVX512]
vpmovdb {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VPMOVDBZ128mrk [HasVLX, HasAVX512]
vpmovdb {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
VPMOVDBZ128rr [HasVLX, HasAVX512]
vpmovdb {src, dst|dst, src}
VPMOVDBZ128rrk [HasVLX, HasAVX512]
vpmovdb {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVDBZ128rrkz [HasVLX, HasAVX512]
vpmovdb {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVDBZ256mr [HasVLX, HasAVX512]
vpmovdb {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VPMOVDBZ256mrk [HasVLX, HasAVX512]
vpmovdb {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
VPMOVDBZ256rr [HasVLX, HasAVX512]
vpmovdb {src, dst|dst, src}
VPMOVDBZ256rrk [HasVLX, HasAVX512]
vpmovdb {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVDBZ256rrkz [HasVLX, HasAVX512]
vpmovdb {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVDWZ128mr [HasVLX, HasAVX512]
vpmovdw {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VPMOVDWZ128mrk [HasVLX, HasAVX512]
vpmovdw {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
VPMOVDWZ128rr [HasVLX, HasAVX512]
vpmovdw {src, dst|dst, src}
VPMOVDWZ128rrk [HasVLX, HasAVX512]
vpmovdw {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVDWZ128rrkz [HasVLX, HasAVX512]
vpmovdw {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVDWZ256mr [HasVLX, HasAVX512]
vpmovdw {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VPMOVDWZ256mrk [HasVLX, HasAVX512]
vpmovdw {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
VPMOVDWZ256rr [HasVLX, HasAVX512]
vpmovdw {src, dst|dst, src}
VPMOVDWZ256rrk [HasVLX, HasAVX512]
vpmovdw {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVDWZ256rrkz [HasVLX, HasAVX512]
vpmovdw {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVQBZ128mr [HasVLX, HasAVX512]
vpmovqb {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VPMOVQBZ128mrk [HasVLX, HasAVX512]
vpmovqb {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
VPMOVQBZ128rr [HasVLX, HasAVX512]
vpmovqb {src, dst|dst, src}
VPMOVQBZ128rrk [HasVLX, HasAVX512]
vpmovqb {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVQBZ128rrkz [HasVLX, HasAVX512]
vpmovqb {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVQBZ256mr [HasVLX, HasAVX512]
vpmovqb {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VPMOVQBZ256mrk [HasVLX, HasAVX512]
vpmovqb {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
VPMOVQBZ256rr [HasVLX, HasAVX512]
vpmovqb {src, dst|dst, src}
VPMOVQBZ256rrk [HasVLX, HasAVX512]
vpmovqb {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVQBZ256rrkz [HasVLX, HasAVX512]
vpmovqb {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVQDZ128mr [HasVLX, HasAVX512]
vpmovqd {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VPMOVQDZ128mrk [HasVLX, HasAVX512]
vpmovqd {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
VPMOVQDZ128rr [HasVLX, HasAVX512]
vpmovqd {src, dst|dst, src}
VPMOVQDZ128rrk [HasVLX, HasAVX512]
vpmovqd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVQDZ128rrkz [HasVLX, HasAVX512]
vpmovqd {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVQDZ256mr [HasVLX, HasAVX512]
vpmovqd {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VPMOVQDZ256mrk [HasVLX, HasAVX512]
vpmovqd {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
VPMOVQDZ256rr [HasVLX, HasAVX512]
vpmovqd {src, dst|dst, src}
VPMOVQDZ256rrk [HasVLX, HasAVX512]
vpmovqd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVQDZ256rrkz [HasVLX, HasAVX512]
vpmovqd {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVQWZ128mr [HasVLX, HasAVX512]
vpmovqw {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VPMOVQWZ128mrk [HasVLX, HasAVX512]
vpmovqw {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
VPMOVQWZ128rr [HasVLX, HasAVX512]
vpmovqw {src, dst|dst, src}
VPMOVQWZ128rrk [HasVLX, HasAVX512]
vpmovqw {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVQWZ128rrkz [HasVLX, HasAVX512]
vpmovqw {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVQWZ256mr [HasVLX, HasAVX512]
vpmovqw {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VPMOVQWZ256mrk [HasVLX, HasAVX512]
vpmovqw {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
VPMOVQWZ256rr [HasVLX, HasAVX512]
vpmovqw {src, dst|dst, src}
VPMOVQWZ256rrk [HasVLX, HasAVX512]
vpmovqw {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVQWZ256rrkz [HasVLX, HasAVX512]
vpmovqw {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVSDBZ128mr [HasVLX, HasAVX512]
vpmovsdb {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VPMOVSDBZ128mrk [HasVLX, HasAVX512]
vpmovsdb {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
VPMOVSDBZ128rr [HasVLX, HasAVX512]
vpmovsdb {src, dst|dst, src}
VPMOVSDBZ128rrk [HasVLX, HasAVX512]
vpmovsdb {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVSDBZ128rrkz [HasVLX, HasAVX512]
vpmovsdb {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVSDBZ256mr [HasVLX, HasAVX512]
vpmovsdb {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VPMOVSDBZ256mrk [HasVLX, HasAVX512]
vpmovsdb {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
VPMOVSDBZ256rr [HasVLX, HasAVX512]
vpmovsdb {src, dst|dst, src}
VPMOVSDBZ256rrk [HasVLX, HasAVX512]
vpmovsdb {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVSDBZ256rrkz [HasVLX, HasAVX512]
vpmovsdb {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVSDWZ128mr [HasVLX, HasAVX512]
vpmovsdw {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VPMOVSDWZ128mrk [HasVLX, HasAVX512]
vpmovsdw {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
VPMOVSDWZ128rr [HasVLX, HasAVX512]
vpmovsdw {src, dst|dst, src}
VPMOVSDWZ128rrk [HasVLX, HasAVX512]
vpmovsdw {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVSDWZ128rrkz [HasVLX, HasAVX512]
vpmovsdw {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVSDWZ256mr [HasVLX, HasAVX512]
vpmovsdw {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VPMOVSDWZ256mrk [HasVLX, HasAVX512]
vpmovsdw {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
VPMOVSDWZ256rr [HasVLX, HasAVX512]
vpmovsdw {src, dst|dst, src}
VPMOVSDWZ256rrk [HasVLX, HasAVX512]
vpmovsdw {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVSDWZ256rrkz [HasVLX, HasAVX512]
vpmovsdw {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVSQBZ128mr [HasVLX, HasAVX512]
vpmovsqb {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VPMOVSQBZ128mrk [HasVLX, HasAVX512]
vpmovsqb {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
VPMOVSQBZ128rr [HasVLX, HasAVX512]
vpmovsqb {src, dst|dst, src}
VPMOVSQBZ128rrk [HasVLX, HasAVX512]
vpmovsqb {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVSQBZ128rrkz [HasVLX, HasAVX512]
vpmovsqb {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVSQBZ256mr [HasVLX, HasAVX512]
vpmovsqb {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VPMOVSQBZ256mrk [HasVLX, HasAVX512]
vpmovsqb {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
VPMOVSQBZ256rr [HasVLX, HasAVX512]
vpmovsqb {src, dst|dst, src}
VPMOVSQBZ256rrk [HasVLX, HasAVX512]
vpmovsqb {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVSQBZ256rrkz [HasVLX, HasAVX512]
vpmovsqb {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVSQDZ128mr [HasVLX, HasAVX512]
vpmovsqd {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VPMOVSQDZ128mrk [HasVLX, HasAVX512]
vpmovsqd {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
VPMOVSQDZ128rr [HasVLX, HasAVX512]
vpmovsqd {src, dst|dst, src}
VPMOVSQDZ128rrk [HasVLX, HasAVX512]
vpmovsqd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVSQDZ128rrkz [HasVLX, HasAVX512]
vpmovsqd {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVSQDZ256mr [HasVLX, HasAVX512]
vpmovsqd {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VPMOVSQDZ256mrk [HasVLX, HasAVX512]
vpmovsqd {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
VPMOVSQDZ256rr [HasVLX, HasAVX512]
vpmovsqd {src, dst|dst, src}
VPMOVSQDZ256rrk [HasVLX, HasAVX512]
vpmovsqd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVSQDZ256rrkz [HasVLX, HasAVX512]
vpmovsqd {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVSQWZ128mr [HasVLX, HasAVX512]
vpmovsqw {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VPMOVSQWZ128mrk [HasVLX, HasAVX512]
vpmovsqw {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
VPMOVSQWZ128rr [HasVLX, HasAVX512]
vpmovsqw {src, dst|dst, src}
VPMOVSQWZ128rrk [HasVLX, HasAVX512]
vpmovsqw {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVSQWZ128rrkz [HasVLX, HasAVX512]
vpmovsqw {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVSQWZ256mr [HasVLX, HasAVX512]
vpmovsqw {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VPMOVSQWZ256mrk [HasVLX, HasAVX512]
vpmovsqw {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
VPMOVSQWZ256rr [HasVLX, HasAVX512]
vpmovsqw {src, dst|dst, src}
VPMOVSQWZ256rrk [HasVLX, HasAVX512]
vpmovsqw {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVSQWZ256rrkz [HasVLX, HasAVX512]
vpmovsqw {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVSXBDZ128rm [HasVLX, HasAVX512]
vpmovsxbd {src, dst|dst, src}
VPMOVSXBDZ128rmk [HasVLX, HasAVX512]
vpmovsxbd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVSXBDZ128rmkz [HasVLX, HasAVX512]
vpmovsxbd {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVSXBDZ128rr [HasVLX, HasAVX512]
vpmovsxbd {src, dst|dst, src}
VPMOVSXBDZ128rrk [HasVLX, HasAVX512]
vpmovsxbd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVSXBDZ128rrkz [HasVLX, HasAVX512]
vpmovsxbd {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVSXBDZ256rm [HasVLX, HasAVX512]
vpmovsxbd {src, dst|dst, src}
VPMOVSXBDZ256rmk [HasVLX, HasAVX512]
vpmovsxbd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVSXBDZ256rmkz [HasVLX, HasAVX512]
vpmovsxbd {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVSXBDZ256rr [HasVLX, HasAVX512]
vpmovsxbd {src, dst|dst, src}
VPMOVSXBDZ256rrk [HasVLX, HasAVX512]
vpmovsxbd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVSXBDZ256rrkz [HasVLX, HasAVX512]
vpmovsxbd {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVSXBQZ128rm [HasVLX, HasAVX512]
vpmovsxbq {src, dst|dst, src}
VPMOVSXBQZ128rmk [HasVLX, HasAVX512]
vpmovsxbq {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVSXBQZ128rmkz [HasVLX, HasAVX512]
vpmovsxbq {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVSXBQZ128rr [HasVLX, HasAVX512]
vpmovsxbq {src, dst|dst, src}
VPMOVSXBQZ128rrk [HasVLX, HasAVX512]
vpmovsxbq {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVSXBQZ128rrkz [HasVLX, HasAVX512]
vpmovsxbq {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVSXBQZ256rm [HasVLX, HasAVX512]
vpmovsxbq {src, dst|dst, src}
VPMOVSXBQZ256rmk [HasVLX, HasAVX512]
vpmovsxbq {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVSXBQZ256rmkz [HasVLX, HasAVX512]
vpmovsxbq {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVSXBQZ256rr [HasVLX, HasAVX512]
vpmovsxbq {src, dst|dst, src}
VPMOVSXBQZ256rrk [HasVLX, HasAVX512]
vpmovsxbq {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVSXBQZ256rrkz [HasVLX, HasAVX512]
vpmovsxbq {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVSXDQZ128rm [HasVLX, HasAVX512]
vpmovsxdq {src, dst|dst, src}
VPMOVSXDQZ128rmk [HasVLX, HasAVX512]
vpmovsxdq {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVSXDQZ128rmkz [HasVLX, HasAVX512]
vpmovsxdq {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVSXDQZ128rr [HasVLX, HasAVX512]
vpmovsxdq {src, dst|dst, src}
VPMOVSXDQZ128rrk [HasVLX, HasAVX512]
vpmovsxdq {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVSXDQZ128rrkz [HasVLX, HasAVX512]
vpmovsxdq {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVSXDQZ256rm [HasVLX, HasAVX512]
vpmovsxdq {src, dst|dst, src}
VPMOVSXDQZ256rmk [HasVLX, HasAVX512]
vpmovsxdq {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVSXDQZ256rmkz [HasVLX, HasAVX512]
vpmovsxdq {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVSXDQZ256rr [HasVLX, HasAVX512]
vpmovsxdq {src, dst|dst, src}
VPMOVSXDQZ256rrk [HasVLX, HasAVX512]
vpmovsxdq {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVSXDQZ256rrkz [HasVLX, HasAVX512]
vpmovsxdq {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVSXWDZ128rm [HasVLX, HasAVX512]
vpmovsxwd {src, dst|dst, src}
VPMOVSXWDZ128rmk [HasVLX, HasAVX512]
vpmovsxwd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVSXWDZ128rmkz [HasVLX, HasAVX512]
vpmovsxwd {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVSXWDZ128rr [HasVLX, HasAVX512]
vpmovsxwd {src, dst|dst, src}
VPMOVSXWDZ128rrk [HasVLX, HasAVX512]
vpmovsxwd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVSXWDZ128rrkz [HasVLX, HasAVX512]
vpmovsxwd {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVSXWDZ256rm [HasVLX, HasAVX512]
vpmovsxwd {src, dst|dst, src}
VPMOVSXWDZ256rmk [HasVLX, HasAVX512]
vpmovsxwd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVSXWDZ256rmkz [HasVLX, HasAVX512]
vpmovsxwd {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVSXWDZ256rr [HasVLX, HasAVX512]
vpmovsxwd {src, dst|dst, src}
VPMOVSXWDZ256rrk [HasVLX, HasAVX512]
vpmovsxwd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVSXWDZ256rrkz [HasVLX, HasAVX512]
vpmovsxwd {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVSXWQZ128rm [HasVLX, HasAVX512]
vpmovsxwq {src, dst|dst, src}
VPMOVSXWQZ128rmk [HasVLX, HasAVX512]
vpmovsxwq {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVSXWQZ128rmkz [HasVLX, HasAVX512]
vpmovsxwq {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVSXWQZ128rr [HasVLX, HasAVX512]
vpmovsxwq {src, dst|dst, src}
VPMOVSXWQZ128rrk [HasVLX, HasAVX512]
vpmovsxwq {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVSXWQZ128rrkz [HasVLX, HasAVX512]
vpmovsxwq {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVSXWQZ256rm [HasVLX, HasAVX512]
vpmovsxwq {src, dst|dst, src}
VPMOVSXWQZ256rmk [HasVLX, HasAVX512]
vpmovsxwq {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVSXWQZ256rmkz [HasVLX, HasAVX512]
vpmovsxwq {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVSXWQZ256rr [HasVLX, HasAVX512]
vpmovsxwq {src, dst|dst, src}
VPMOVSXWQZ256rrk [HasVLX, HasAVX512]
vpmovsxwq {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVSXWQZ256rrkz [HasVLX, HasAVX512]
vpmovsxwq {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVUSDBZ128mr [HasVLX, HasAVX512]
vpmovusdb {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VPMOVUSDBZ128mrk [HasVLX, HasAVX512]
vpmovusdb {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
VPMOVUSDBZ128rr [HasVLX, HasAVX512]
vpmovusdb {src, dst|dst, src}
VPMOVUSDBZ128rrk [HasVLX, HasAVX512]
vpmovusdb {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVUSDBZ128rrkz [HasVLX, HasAVX512]
vpmovusdb {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVUSDBZ256mr [HasVLX, HasAVX512]
vpmovusdb {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VPMOVUSDBZ256mrk [HasVLX, HasAVX512]
vpmovusdb {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
VPMOVUSDBZ256rr [HasVLX, HasAVX512]
vpmovusdb {src, dst|dst, src}
VPMOVUSDBZ256rrk [HasVLX, HasAVX512]
vpmovusdb {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVUSDBZ256rrkz [HasVLX, HasAVX512]
vpmovusdb {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVUSDWZ128mr [HasVLX, HasAVX512]
vpmovusdw {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VPMOVUSDWZ128mrk [HasVLX, HasAVX512]
vpmovusdw {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
VPMOVUSDWZ128rr [HasVLX, HasAVX512]
vpmovusdw {src, dst|dst, src}
VPMOVUSDWZ128rrk [HasVLX, HasAVX512]
vpmovusdw {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVUSDWZ128rrkz [HasVLX, HasAVX512]
vpmovusdw {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVUSDWZ256mr [HasVLX, HasAVX512]
vpmovusdw {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VPMOVUSDWZ256mrk [HasVLX, HasAVX512]
vpmovusdw {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
VPMOVUSDWZ256rr [HasVLX, HasAVX512]
vpmovusdw {src, dst|dst, src}
VPMOVUSDWZ256rrk [HasVLX, HasAVX512]
vpmovusdw {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVUSDWZ256rrkz [HasVLX, HasAVX512]
vpmovusdw {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVUSQBZ128mr [HasVLX, HasAVX512]
vpmovusqb {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VPMOVUSQBZ128mrk [HasVLX, HasAVX512]
vpmovusqb {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
VPMOVUSQBZ128rr [HasVLX, HasAVX512]
vpmovusqb {src, dst|dst, src}
VPMOVUSQBZ128rrk [HasVLX, HasAVX512]
vpmovusqb {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVUSQBZ128rrkz [HasVLX, HasAVX512]
vpmovusqb {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVUSQBZ256mr [HasVLX, HasAVX512]
vpmovusqb {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VPMOVUSQBZ256mrk [HasVLX, HasAVX512]
vpmovusqb {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
VPMOVUSQBZ256rr [HasVLX, HasAVX512]
vpmovusqb {src, dst|dst, src}
VPMOVUSQBZ256rrk [HasVLX, HasAVX512]
vpmovusqb {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVUSQBZ256rrkz [HasVLX, HasAVX512]
vpmovusqb {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVUSQDZ128mr [HasVLX, HasAVX512]
vpmovusqd {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VPMOVUSQDZ128mrk [HasVLX, HasAVX512]
vpmovusqd {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
VPMOVUSQDZ128rr [HasVLX, HasAVX512]
vpmovusqd {src, dst|dst, src}
VPMOVUSQDZ128rrk [HasVLX, HasAVX512]
vpmovusqd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVUSQDZ128rrkz [HasVLX, HasAVX512]
vpmovusqd {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVUSQDZ256mr [HasVLX, HasAVX512]
vpmovusqd {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VPMOVUSQDZ256mrk [HasVLX, HasAVX512]
vpmovusqd {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
VPMOVUSQDZ256rr [HasVLX, HasAVX512]
vpmovusqd {src, dst|dst, src}
VPMOVUSQDZ256rrk [HasVLX, HasAVX512]
vpmovusqd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVUSQDZ256rrkz [HasVLX, HasAVX512]
vpmovusqd {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVUSQWZ128mr [HasVLX, HasAVX512]
vpmovusqw {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VPMOVUSQWZ128mrk [HasVLX, HasAVX512]
vpmovusqw {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
VPMOVUSQWZ128rr [HasVLX, HasAVX512]
vpmovusqw {src, dst|dst, src}
VPMOVUSQWZ128rrk [HasVLX, HasAVX512]
vpmovusqw {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVUSQWZ128rrkz [HasVLX, HasAVX512]
vpmovusqw {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVUSQWZ256mr [HasVLX, HasAVX512]
vpmovusqw {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VPMOVUSQWZ256mrk [HasVLX, HasAVX512]
vpmovusqw {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
VPMOVUSQWZ256rr [HasVLX, HasAVX512]
vpmovusqw {src, dst|dst, src}
VPMOVUSQWZ256rrk [HasVLX, HasAVX512]
vpmovusqw {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVUSQWZ256rrkz [HasVLX, HasAVX512]
vpmovusqw {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVZXBDZ128rm [HasVLX, HasAVX512]
vpmovzxbd {src, dst|dst, src}
VPMOVZXBDZ128rmk [HasVLX, HasAVX512]
vpmovzxbd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVZXBDZ128rmkz [HasVLX, HasAVX512]
vpmovzxbd {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVZXBDZ128rr [HasVLX, HasAVX512]
vpmovzxbd {src, dst|dst, src}
VPMOVZXBDZ128rrk [HasVLX, HasAVX512]
vpmovzxbd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVZXBDZ128rrkz [HasVLX, HasAVX512]
vpmovzxbd {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVZXBDZ256rm [HasVLX, HasAVX512]
vpmovzxbd {src, dst|dst, src}
VPMOVZXBDZ256rmk [HasVLX, HasAVX512]
vpmovzxbd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVZXBDZ256rmkz [HasVLX, HasAVX512]
vpmovzxbd {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVZXBDZ256rr [HasVLX, HasAVX512]
vpmovzxbd {src, dst|dst, src}
VPMOVZXBDZ256rrk [HasVLX, HasAVX512]
vpmovzxbd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVZXBDZ256rrkz [HasVLX, HasAVX512]
vpmovzxbd {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVZXBQZ128rm [HasVLX, HasAVX512]
vpmovzxbq {src, dst|dst, src}
VPMOVZXBQZ128rmk [HasVLX, HasAVX512]
vpmovzxbq {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVZXBQZ128rmkz [HasVLX, HasAVX512]
vpmovzxbq {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVZXBQZ128rr [HasVLX, HasAVX512]
vpmovzxbq {src, dst|dst, src}
VPMOVZXBQZ128rrk [HasVLX, HasAVX512]
vpmovzxbq {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVZXBQZ128rrkz [HasVLX, HasAVX512]
vpmovzxbq {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVZXBQZ256rm [HasVLX, HasAVX512]
vpmovzxbq {src, dst|dst, src}
VPMOVZXBQZ256rmk [HasVLX, HasAVX512]
vpmovzxbq {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVZXBQZ256rmkz [HasVLX, HasAVX512]
vpmovzxbq {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVZXBQZ256rr [HasVLX, HasAVX512]
vpmovzxbq {src, dst|dst, src}
VPMOVZXBQZ256rrk [HasVLX, HasAVX512]
vpmovzxbq {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVZXBQZ256rrkz [HasVLX, HasAVX512]
vpmovzxbq {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVZXDQZ128rm [HasVLX, HasAVX512]
vpmovzxdq {src, dst|dst, src}
VPMOVZXDQZ128rmk [HasVLX, HasAVX512]
vpmovzxdq {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVZXDQZ128rmkz [HasVLX, HasAVX512]
vpmovzxdq {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVZXDQZ128rr [HasVLX, HasAVX512]
vpmovzxdq {src, dst|dst, src}
VPMOVZXDQZ128rrk [HasVLX, HasAVX512]
vpmovzxdq {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVZXDQZ128rrkz [HasVLX, HasAVX512]
vpmovzxdq {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVZXDQZ256rm [HasVLX, HasAVX512]
vpmovzxdq {src, dst|dst, src}
VPMOVZXDQZ256rmk [HasVLX, HasAVX512]
vpmovzxdq {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVZXDQZ256rmkz [HasVLX, HasAVX512]
vpmovzxdq {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVZXDQZ256rr [HasVLX, HasAVX512]
vpmovzxdq {src, dst|dst, src}
VPMOVZXDQZ256rrk [HasVLX, HasAVX512]
vpmovzxdq {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVZXDQZ256rrkz [HasVLX, HasAVX512]
vpmovzxdq {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVZXWDZ128rm [HasVLX, HasAVX512]
vpmovzxwd {src, dst|dst, src}
VPMOVZXWDZ128rmk [HasVLX, HasAVX512]
vpmovzxwd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVZXWDZ128rmkz [HasVLX, HasAVX512]
vpmovzxwd {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVZXWDZ128rr [HasVLX, HasAVX512]
vpmovzxwd {src, dst|dst, src}
VPMOVZXWDZ128rrk [HasVLX, HasAVX512]
vpmovzxwd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVZXWDZ128rrkz [HasVLX, HasAVX512]
vpmovzxwd {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVZXWDZ256rm [HasVLX, HasAVX512]
vpmovzxwd {src, dst|dst, src}
VPMOVZXWDZ256rmk [HasVLX, HasAVX512]
vpmovzxwd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVZXWDZ256rmkz [HasVLX, HasAVX512]
vpmovzxwd {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVZXWDZ256rr [HasVLX, HasAVX512]
vpmovzxwd {src, dst|dst, src}
VPMOVZXWDZ256rrk [HasVLX, HasAVX512]
vpmovzxwd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVZXWDZ256rrkz [HasVLX, HasAVX512]
vpmovzxwd {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVZXWQZ128rm [HasVLX, HasAVX512]
vpmovzxwq {src, dst|dst, src}
VPMOVZXWQZ128rmk [HasVLX, HasAVX512]
vpmovzxwq {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVZXWQZ128rmkz [HasVLX, HasAVX512]
vpmovzxwq {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVZXWQZ128rr [HasVLX, HasAVX512]
vpmovzxwq {src, dst|dst, src}
VPMOVZXWQZ128rrk [HasVLX, HasAVX512]
vpmovzxwq {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVZXWQZ128rrkz [HasVLX, HasAVX512]
vpmovzxwq {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVZXWQZ256rm [HasVLX, HasAVX512]
vpmovzxwq {src, dst|dst, src}
VPMOVZXWQZ256rmk [HasVLX, HasAVX512]
vpmovzxwq {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVZXWQZ256rmkz [HasVLX, HasAVX512]
vpmovzxwq {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVZXWQZ256rr [HasVLX, HasAVX512]
vpmovzxwq {src, dst|dst, src}
VPMOVZXWQZ256rrk [HasVLX, HasAVX512]
vpmovzxwq {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVZXWQZ256rrkz [HasVLX, HasAVX512]
vpmovzxwq {src, dst {mask} {z}|dst {mask} {z}, src}
VPMULDQZ128rm [HasVLX, HasAVX512]
vpmuldq {src2, src1, dst|dst, src1, src2}
VPMULDQZ128rmb [HasVLX, HasAVX512]
vpmuldq {src2{1to2}, src1, dst|dst, src1, src2{1to2}}
VPMULDQZ128rmbk [HasVLX, HasAVX512]
vpmuldq {src2{1to2}, src1, dst {mask}|dst {mask}, src1, src2{1to2}}
|
Note
|
Constraints: src0 = dst |
VPMULDQZ128rmbkz [HasVLX, HasAVX512]
vpmuldq {src2{1to2}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to2}}
VPMULDQZ128rmk [HasVLX, HasAVX512]
vpmuldq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMULDQZ128rmkz [HasVLX, HasAVX512]
vpmuldq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMULDQZ128rr [HasVLX, HasAVX512]
vpmuldq {src2, src1, dst|dst, src1, src2}
VPMULDQZ128rrk [HasVLX, HasAVX512]
vpmuldq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMULDQZ128rrkz [HasVLX, HasAVX512]
vpmuldq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMULDQZ256rm [HasVLX, HasAVX512]
vpmuldq {src2, src1, dst|dst, src1, src2}
VPMULDQZ256rmb [HasVLX, HasAVX512]
vpmuldq {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
VPMULDQZ256rmbk [HasVLX, HasAVX512]
vpmuldq {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Constraints: src0 = dst |
VPMULDQZ256rmbkz [HasVLX, HasAVX512]
vpmuldq {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
VPMULDQZ256rmk [HasVLX, HasAVX512]
vpmuldq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMULDQZ256rmkz [HasVLX, HasAVX512]
vpmuldq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMULDQZ256rr [HasVLX, HasAVX512]
vpmuldq {src2, src1, dst|dst, src1, src2}
VPMULDQZ256rrk [HasVLX, HasAVX512]
vpmuldq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMULDQZ256rrkz [HasVLX, HasAVX512]
vpmuldq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMULLDZ128rm [HasVLX, HasAVX512]
vpmulld {src2, src1, dst|dst, src1, src2}
VPMULLDZ128rmb [HasVLX, HasAVX512]
vpmulld {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
VPMULLDZ128rmbk [HasVLX, HasAVX512]
vpmulld {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Constraints: src0 = dst |
VPMULLDZ128rmbkz [HasVLX, HasAVX512]
vpmulld {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
VPMULLDZ128rmk [HasVLX, HasAVX512]
vpmulld {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMULLDZ128rmkz [HasVLX, HasAVX512]
vpmulld {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMULLDZ128rr [HasVLX, HasAVX512]
vpmulld {src2, src1, dst|dst, src1, src2}
VPMULLDZ128rrk [HasVLX, HasAVX512]
vpmulld {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMULLDZ128rrkz [HasVLX, HasAVX512]
vpmulld {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMULLDZ256rm [HasVLX, HasAVX512]
vpmulld {src2, src1, dst|dst, src1, src2}
VPMULLDZ256rmb [HasVLX, HasAVX512]
vpmulld {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
VPMULLDZ256rmbk [HasVLX, HasAVX512]
vpmulld {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Constraints: src0 = dst |
VPMULLDZ256rmbkz [HasVLX, HasAVX512]
vpmulld {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
VPMULLDZ256rmk [HasVLX, HasAVX512]
vpmulld {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMULLDZ256rmkz [HasVLX, HasAVX512]
vpmulld {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMULLDZ256rr [HasVLX, HasAVX512]
vpmulld {src2, src1, dst|dst, src1, src2}
VPMULLDZ256rrk [HasVLX, HasAVX512]
vpmulld {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMULLDZ256rrkz [HasVLX, HasAVX512]
vpmulld {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMULUDQZ128rm [HasVLX, HasAVX512]
vpmuludq {src2, src1, dst|dst, src1, src2}
VPMULUDQZ128rmb [HasVLX, HasAVX512]
vpmuludq {src2{1to2}, src1, dst|dst, src1, src2{1to2}}
VPMULUDQZ128rmbk [HasVLX, HasAVX512]
vpmuludq {src2{1to2}, src1, dst {mask}|dst {mask}, src1, src2{1to2}}
|
Note
|
Constraints: src0 = dst |
VPMULUDQZ128rmbkz [HasVLX, HasAVX512]
vpmuludq {src2{1to2}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to2}}
VPMULUDQZ128rmk [HasVLX, HasAVX512]
vpmuludq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMULUDQZ128rmkz [HasVLX, HasAVX512]
vpmuludq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMULUDQZ128rr [HasVLX, HasAVX512]
vpmuludq {src2, src1, dst|dst, src1, src2}
VPMULUDQZ128rrk [HasVLX, HasAVX512]
vpmuludq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMULUDQZ128rrkz [HasVLX, HasAVX512]
vpmuludq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMULUDQZ256rm [HasVLX, HasAVX512]
vpmuludq {src2, src1, dst|dst, src1, src2}
VPMULUDQZ256rmb [HasVLX, HasAVX512]
vpmuludq {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
VPMULUDQZ256rmbk [HasVLX, HasAVX512]
vpmuludq {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Constraints: src0 = dst |
VPMULUDQZ256rmbkz [HasVLX, HasAVX512]
vpmuludq {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
VPMULUDQZ256rmk [HasVLX, HasAVX512]
vpmuludq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMULUDQZ256rmkz [HasVLX, HasAVX512]
vpmuludq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMULUDQZ256rr [HasVLX, HasAVX512]
vpmuludq {src2, src1, dst|dst, src1, src2}
VPMULUDQZ256rrk [HasVLX, HasAVX512]
vpmuludq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMULUDQZ256rrkz [HasVLX, HasAVX512]
vpmuludq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPORDZ128rm [HasVLX, HasAVX512]
vpord {src2, src1, dst|dst, src1, src2}
VPORDZ128rmb [HasVLX, HasAVX512]
vpord {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
VPORDZ128rmbk [HasVLX, HasAVX512]
vpord {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Constraints: src0 = dst |
VPORDZ128rmbkz [HasVLX, HasAVX512]
vpord {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
VPORDZ128rmk [HasVLX, HasAVX512]
vpord {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPORDZ128rmkz [HasVLX, HasAVX512]
vpord {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPORDZ128rr [HasVLX, HasAVX512]
vpord {src2, src1, dst|dst, src1, src2}
VPORDZ128rrk [HasVLX, HasAVX512]
vpord {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPORDZ128rrkz [HasVLX, HasAVX512]
vpord {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPORDZ256rm [HasVLX, HasAVX512]
vpord {src2, src1, dst|dst, src1, src2}
VPORDZ256rmb [HasVLX, HasAVX512]
vpord {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
VPORDZ256rmbk [HasVLX, HasAVX512]
vpord {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Constraints: src0 = dst |
VPORDZ256rmbkz [HasVLX, HasAVX512]
vpord {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
VPORDZ256rmk [HasVLX, HasAVX512]
vpord {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPORDZ256rmkz [HasVLX, HasAVX512]
vpord {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPORDZ256rr [HasVLX, HasAVX512]
vpord {src2, src1, dst|dst, src1, src2}
VPORDZ256rrk [HasVLX, HasAVX512]
vpord {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPORDZ256rrkz [HasVLX, HasAVX512]
vpord {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPORQZ128rm [HasVLX, HasAVX512]
vporq {src2, src1, dst|dst, src1, src2}
VPORQZ128rmb [HasVLX, HasAVX512]
vporq {src2{1to2}, src1, dst|dst, src1, src2{1to2}}
VPORQZ128rmbk [HasVLX, HasAVX512]
vporq {src2{1to2}, src1, dst {mask}|dst {mask}, src1, src2{1to2}}
|
Note
|
Constraints: src0 = dst |
VPORQZ128rmbkz [HasVLX, HasAVX512]
vporq {src2{1to2}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to2}}
VPORQZ128rmk [HasVLX, HasAVX512]
vporq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPORQZ128rmkz [HasVLX, HasAVX512]
vporq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPORQZ128rr [HasVLX, HasAVX512]
vporq {src2, src1, dst|dst, src1, src2}
VPORQZ128rrk [HasVLX, HasAVX512]
vporq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPORQZ128rrkz [HasVLX, HasAVX512]
vporq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPORQZ256rm [HasVLX, HasAVX512]
vporq {src2, src1, dst|dst, src1, src2}
VPORQZ256rmb [HasVLX, HasAVX512]
vporq {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
VPORQZ256rmbk [HasVLX, HasAVX512]
vporq {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Constraints: src0 = dst |
VPORQZ256rmbkz [HasVLX, HasAVX512]
vporq {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
VPORQZ256rmk [HasVLX, HasAVX512]
vporq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPORQZ256rmkz [HasVLX, HasAVX512]
vporq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPORQZ256rr [HasVLX, HasAVX512]
vporq {src2, src1, dst|dst, src1, src2}
VPORQZ256rrk [HasVLX, HasAVX512]
vporq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPORQZ256rrkz [HasVLX, HasAVX512]
vporq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPROLDZ128mbi [HasVLX, HasAVX512]
vprold {src2, src1{1to4}, dst|dst, src1{1to4}, src2}
VPROLDZ128mbik [HasVLX, HasAVX512]
vprold {src2, src1{1to4}, dst {mask}|dst {mask}, src1{1to4}, src2}
|
Note
|
Constraints: src0 = dst |
VPROLDZ128mbikz [HasVLX, HasAVX512]
vprold {src2, src1{1to4}, dst {mask} {z}|dst {mask} {z}, src1{1to4}, src2}
VPROLDZ128mi [HasVLX, HasAVX512]
vprold {src2, src1, dst|dst, src1, src2}
VPROLDZ128mik [HasVLX, HasAVX512]
vprold {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPROLDZ128mikz [HasVLX, HasAVX512]
vprold {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPROLDZ128ri [HasVLX, HasAVX512]
vprold {src2, src1, dst|dst, src1, src2}
VPROLDZ128rik [HasVLX, HasAVX512]
vprold {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPROLDZ128rikz [HasVLX, HasAVX512]
vprold {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPROLDZ256mbi [HasVLX, HasAVX512]
vprold {src2, src1{1to8}, dst|dst, src1{1to8}, src2}
VPROLDZ256mbik [HasVLX, HasAVX512]
vprold {src2, src1{1to8}, dst {mask}|dst {mask}, src1{1to8}, src2}
|
Note
|
Constraints: src0 = dst |
VPROLDZ256mbikz [HasVLX, HasAVX512]
vprold {src2, src1{1to8}, dst {mask} {z}|dst {mask} {z}, src1{1to8}, src2}
VPROLDZ256mi [HasVLX, HasAVX512]
vprold {src2, src1, dst|dst, src1, src2}
VPROLDZ256mik [HasVLX, HasAVX512]
vprold {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPROLDZ256mikz [HasVLX, HasAVX512]
vprold {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPROLDZ256ri [HasVLX, HasAVX512]
vprold {src2, src1, dst|dst, src1, src2}
VPROLDZ256rik [HasVLX, HasAVX512]
vprold {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPROLDZ256rikz [HasVLX, HasAVX512]
vprold {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPROLQZ128mbi [HasVLX, HasAVX512]
vprolq {src2, src1{1to2}, dst|dst, src1{1to2}, src2}
VPROLQZ128mbik [HasVLX, HasAVX512]
vprolq {src2, src1{1to2}, dst {mask}|dst {mask}, src1{1to2}, src2}
|
Note
|
Constraints: src0 = dst |
VPROLQZ128mbikz [HasVLX, HasAVX512]
vprolq {src2, src1{1to2}, dst {mask} {z}|dst {mask} {z}, src1{1to2}, src2}
VPROLQZ128mi [HasVLX, HasAVX512]
vprolq {src2, src1, dst|dst, src1, src2}
VPROLQZ128mik [HasVLX, HasAVX512]
vprolq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPROLQZ128mikz [HasVLX, HasAVX512]
vprolq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPROLQZ128ri [HasVLX, HasAVX512]
vprolq {src2, src1, dst|dst, src1, src2}
VPROLQZ128rik [HasVLX, HasAVX512]
vprolq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPROLQZ128rikz [HasVLX, HasAVX512]
vprolq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPROLQZ256mbi [HasVLX, HasAVX512]
vprolq {src2, src1{1to4}, dst|dst, src1{1to4}, src2}
VPROLQZ256mbik [HasVLX, HasAVX512]
vprolq {src2, src1{1to4}, dst {mask}|dst {mask}, src1{1to4}, src2}
|
Note
|
Constraints: src0 = dst |
VPROLQZ256mbikz [HasVLX, HasAVX512]
vprolq {src2, src1{1to4}, dst {mask} {z}|dst {mask} {z}, src1{1to4}, src2}
VPROLQZ256mi [HasVLX, HasAVX512]
vprolq {src2, src1, dst|dst, src1, src2}
VPROLQZ256mik [HasVLX, HasAVX512]
vprolq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPROLQZ256mikz [HasVLX, HasAVX512]
vprolq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPROLQZ256ri [HasVLX, HasAVX512]
vprolq {src2, src1, dst|dst, src1, src2}
VPROLQZ256rik [HasVLX, HasAVX512]
vprolq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPROLQZ256rikz [HasVLX, HasAVX512]
vprolq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPROLVDZ128rm [HasVLX, HasAVX512]
vprolvd {src2, src1, dst|dst, src1, src2}
VPROLVDZ128rmb [HasVLX, HasAVX512]
vprolvd {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
VPROLVDZ128rmbk [HasVLX, HasAVX512]
vprolvd {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Constraints: src0 = dst |
VPROLVDZ128rmbkz [HasVLX, HasAVX512]
vprolvd {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
VPROLVDZ128rmk [HasVLX, HasAVX512]
vprolvd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPROLVDZ128rmkz [HasVLX, HasAVX512]
vprolvd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPROLVDZ128rr [HasVLX, HasAVX512]
vprolvd {src2, src1, dst|dst, src1, src2}
VPROLVDZ128rrk [HasVLX, HasAVX512]
vprolvd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPROLVDZ128rrkz [HasVLX, HasAVX512]
vprolvd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPROLVDZ256rm [HasVLX, HasAVX512]
vprolvd {src2, src1, dst|dst, src1, src2}
VPROLVDZ256rmb [HasVLX, HasAVX512]
vprolvd {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
VPROLVDZ256rmbk [HasVLX, HasAVX512]
vprolvd {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Constraints: src0 = dst |
VPROLVDZ256rmbkz [HasVLX, HasAVX512]
vprolvd {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
VPROLVDZ256rmk [HasVLX, HasAVX512]
vprolvd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPROLVDZ256rmkz [HasVLX, HasAVX512]
vprolvd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPROLVDZ256rr [HasVLX, HasAVX512]
vprolvd {src2, src1, dst|dst, src1, src2}
VPROLVDZ256rrk [HasVLX, HasAVX512]
vprolvd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPROLVDZ256rrkz [HasVLX, HasAVX512]
vprolvd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPROLVQZ128rm [HasVLX, HasAVX512]
vprolvq {src2, src1, dst|dst, src1, src2}
VPROLVQZ128rmb [HasVLX, HasAVX512]
vprolvq {src2{1to2}, src1, dst|dst, src1, src2{1to2}}
VPROLVQZ128rmbk [HasVLX, HasAVX512]
vprolvq {src2{1to2}, src1, dst {mask}|dst {mask}, src1, src2{1to2}}
|
Note
|
Constraints: src0 = dst |
VPROLVQZ128rmbkz [HasVLX, HasAVX512]
vprolvq {src2{1to2}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to2}}
VPROLVQZ128rmk [HasVLX, HasAVX512]
vprolvq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPROLVQZ128rmkz [HasVLX, HasAVX512]
vprolvq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPROLVQZ128rr [HasVLX, HasAVX512]
vprolvq {src2, src1, dst|dst, src1, src2}
VPROLVQZ128rrk [HasVLX, HasAVX512]
vprolvq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPROLVQZ128rrkz [HasVLX, HasAVX512]
vprolvq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPROLVQZ256rm [HasVLX, HasAVX512]
vprolvq {src2, src1, dst|dst, src1, src2}
VPROLVQZ256rmb [HasVLX, HasAVX512]
vprolvq {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
VPROLVQZ256rmbk [HasVLX, HasAVX512]
vprolvq {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Constraints: src0 = dst |
VPROLVQZ256rmbkz [HasVLX, HasAVX512]
vprolvq {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
VPROLVQZ256rmk [HasVLX, HasAVX512]
vprolvq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPROLVQZ256rmkz [HasVLX, HasAVX512]
vprolvq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPROLVQZ256rr [HasVLX, HasAVX512]
vprolvq {src2, src1, dst|dst, src1, src2}
VPROLVQZ256rrk [HasVLX, HasAVX512]
vprolvq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPROLVQZ256rrkz [HasVLX, HasAVX512]
vprolvq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPRORDZ128mbi [HasVLX, HasAVX512]
vprord {src2, src1{1to4}, dst|dst, src1{1to4}, src2}
VPRORDZ128mbik [HasVLX, HasAVX512]
vprord {src2, src1{1to4}, dst {mask}|dst {mask}, src1{1to4}, src2}
|
Note
|
Constraints: src0 = dst |
VPRORDZ128mbikz [HasVLX, HasAVX512]
vprord {src2, src1{1to4}, dst {mask} {z}|dst {mask} {z}, src1{1to4}, src2}
VPRORDZ128mi [HasVLX, HasAVX512]
vprord {src2, src1, dst|dst, src1, src2}
VPRORDZ128mik [HasVLX, HasAVX512]
vprord {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPRORDZ128mikz [HasVLX, HasAVX512]
vprord {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPRORDZ128ri [HasVLX, HasAVX512]
vprord {src2, src1, dst|dst, src1, src2}
VPRORDZ128rik [HasVLX, HasAVX512]
vprord {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPRORDZ128rikz [HasVLX, HasAVX512]
vprord {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPRORDZ256mbi [HasVLX, HasAVX512]
vprord {src2, src1{1to8}, dst|dst, src1{1to8}, src2}
VPRORDZ256mbik [HasVLX, HasAVX512]
vprord {src2, src1{1to8}, dst {mask}|dst {mask}, src1{1to8}, src2}
|
Note
|
Constraints: src0 = dst |
VPRORDZ256mbikz [HasVLX, HasAVX512]
vprord {src2, src1{1to8}, dst {mask} {z}|dst {mask} {z}, src1{1to8}, src2}
VPRORDZ256mi [HasVLX, HasAVX512]
vprord {src2, src1, dst|dst, src1, src2}
VPRORDZ256mik [HasVLX, HasAVX512]
vprord {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPRORDZ256mikz [HasVLX, HasAVX512]
vprord {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPRORDZ256ri [HasVLX, HasAVX512]
vprord {src2, src1, dst|dst, src1, src2}
VPRORDZ256rik [HasVLX, HasAVX512]
vprord {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPRORDZ256rikz [HasVLX, HasAVX512]
vprord {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPRORQZ128mbi [HasVLX, HasAVX512]
vprorq {src2, src1{1to2}, dst|dst, src1{1to2}, src2}
VPRORQZ128mbik [HasVLX, HasAVX512]
vprorq {src2, src1{1to2}, dst {mask}|dst {mask}, src1{1to2}, src2}
|
Note
|
Constraints: src0 = dst |
VPRORQZ128mbikz [HasVLX, HasAVX512]
vprorq {src2, src1{1to2}, dst {mask} {z}|dst {mask} {z}, src1{1to2}, src2}
VPRORQZ128mi [HasVLX, HasAVX512]
vprorq {src2, src1, dst|dst, src1, src2}
VPRORQZ128mik [HasVLX, HasAVX512]
vprorq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPRORQZ128mikz [HasVLX, HasAVX512]
vprorq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPRORQZ128ri [HasVLX, HasAVX512]
vprorq {src2, src1, dst|dst, src1, src2}
VPRORQZ128rik [HasVLX, HasAVX512]
vprorq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPRORQZ128rikz [HasVLX, HasAVX512]
vprorq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPRORQZ256mbi [HasVLX, HasAVX512]
vprorq {src2, src1{1to4}, dst|dst, src1{1to4}, src2}
VPRORQZ256mbik [HasVLX, HasAVX512]
vprorq {src2, src1{1to4}, dst {mask}|dst {mask}, src1{1to4}, src2}
|
Note
|
Constraints: src0 = dst |
VPRORQZ256mbikz [HasVLX, HasAVX512]
vprorq {src2, src1{1to4}, dst {mask} {z}|dst {mask} {z}, src1{1to4}, src2}
VPRORQZ256mi [HasVLX, HasAVX512]
vprorq {src2, src1, dst|dst, src1, src2}
VPRORQZ256mik [HasVLX, HasAVX512]
vprorq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPRORQZ256mikz [HasVLX, HasAVX512]
vprorq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPRORQZ256ri [HasVLX, HasAVX512]
vprorq {src2, src1, dst|dst, src1, src2}
VPRORQZ256rik [HasVLX, HasAVX512]
vprorq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPRORQZ256rikz [HasVLX, HasAVX512]
vprorq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPRORVDZ128rm [HasVLX, HasAVX512]
vprorvd {src2, src1, dst|dst, src1, src2}
VPRORVDZ128rmb [HasVLX, HasAVX512]
vprorvd {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
VPRORVDZ128rmbk [HasVLX, HasAVX512]
vprorvd {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Constraints: src0 = dst |
VPRORVDZ128rmbkz [HasVLX, HasAVX512]
vprorvd {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
VPRORVDZ128rmk [HasVLX, HasAVX512]
vprorvd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPRORVDZ128rmkz [HasVLX, HasAVX512]
vprorvd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPRORVDZ128rr [HasVLX, HasAVX512]
vprorvd {src2, src1, dst|dst, src1, src2}
VPRORVDZ128rrk [HasVLX, HasAVX512]
vprorvd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPRORVDZ128rrkz [HasVLX, HasAVX512]
vprorvd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPRORVDZ256rm [HasVLX, HasAVX512]
vprorvd {src2, src1, dst|dst, src1, src2}
VPRORVDZ256rmb [HasVLX, HasAVX512]
vprorvd {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
VPRORVDZ256rmbk [HasVLX, HasAVX512]
vprorvd {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Constraints: src0 = dst |
VPRORVDZ256rmbkz [HasVLX, HasAVX512]
vprorvd {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
VPRORVDZ256rmk [HasVLX, HasAVX512]
vprorvd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPRORVDZ256rmkz [HasVLX, HasAVX512]
vprorvd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPRORVDZ256rr [HasVLX, HasAVX512]
vprorvd {src2, src1, dst|dst, src1, src2}
VPRORVDZ256rrk [HasVLX, HasAVX512]
vprorvd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPRORVDZ256rrkz [HasVLX, HasAVX512]
vprorvd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPRORVQZ128rm [HasVLX, HasAVX512]
vprorvq {src2, src1, dst|dst, src1, src2}
VPRORVQZ128rmb [HasVLX, HasAVX512]
vprorvq {src2{1to2}, src1, dst|dst, src1, src2{1to2}}
VPRORVQZ128rmbk [HasVLX, HasAVX512]
vprorvq {src2{1to2}, src1, dst {mask}|dst {mask}, src1, src2{1to2}}
|
Note
|
Constraints: src0 = dst |
VPRORVQZ128rmbkz [HasVLX, HasAVX512]
vprorvq {src2{1to2}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to2}}
VPRORVQZ128rmk [HasVLX, HasAVX512]
vprorvq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPRORVQZ128rmkz [HasVLX, HasAVX512]
vprorvq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPRORVQZ128rr [HasVLX, HasAVX512]
vprorvq {src2, src1, dst|dst, src1, src2}
VPRORVQZ128rrk [HasVLX, HasAVX512]
vprorvq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPRORVQZ128rrkz [HasVLX, HasAVX512]
vprorvq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPRORVQZ256rm [HasVLX, HasAVX512]
vprorvq {src2, src1, dst|dst, src1, src2}
VPRORVQZ256rmb [HasVLX, HasAVX512]
vprorvq {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
VPRORVQZ256rmbk [HasVLX, HasAVX512]
vprorvq {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Constraints: src0 = dst |
VPRORVQZ256rmbkz [HasVLX, HasAVX512]
vprorvq {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
VPRORVQZ256rmk [HasVLX, HasAVX512]
vprorvq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPRORVQZ256rmkz [HasVLX, HasAVX512]
vprorvq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPRORVQZ256rr [HasVLX, HasAVX512]
vprorvq {src2, src1, dst|dst, src1, src2}
VPRORVQZ256rrk [HasVLX, HasAVX512]
vprorvq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPRORVQZ256rrkz [HasVLX, HasAVX512]
vprorvq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSHUFDZ128mbi [HasVLX, HasAVX512]
vpshufd {src2, src1{1to4}, dst|dst, src1{1to4}, src2}
VPSHUFDZ128mbik [HasVLX, HasAVX512]
vpshufd {src2, src1{1to4}, dst {mask}|dst {mask}, src1{1to4}, src2}
|
Note
|
Constraints: src0 = dst |
VPSHUFDZ128mbikz [HasVLX, HasAVX512]
vpshufd {src2, src1{1to4}, dst {mask} {z}|dst {mask} {z}, src1{1to4}, src2}
VPSHUFDZ128mi [HasVLX, HasAVX512]
vpshufd {src2, src1, dst|dst, src1, src2}
VPSHUFDZ128mik [HasVLX, HasAVX512]
vpshufd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSHUFDZ128mikz [HasVLX, HasAVX512]
vpshufd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSHUFDZ128ri [HasVLX, HasAVX512]
vpshufd {src2, src1, dst|dst, src1, src2}
VPSHUFDZ128rik [HasVLX, HasAVX512]
vpshufd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSHUFDZ128rikz [HasVLX, HasAVX512]
vpshufd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSHUFDZ256mbi [HasVLX, HasAVX512]
vpshufd {src2, src1{1to8}, dst|dst, src1{1to8}, src2}
VPSHUFDZ256mbik [HasVLX, HasAVX512]
vpshufd {src2, src1{1to8}, dst {mask}|dst {mask}, src1{1to8}, src2}
|
Note
|
Constraints: src0 = dst |
VPSHUFDZ256mbikz [HasVLX, HasAVX512]
vpshufd {src2, src1{1to8}, dst {mask} {z}|dst {mask} {z}, src1{1to8}, src2}
VPSHUFDZ256mi [HasVLX, HasAVX512]
vpshufd {src2, src1, dst|dst, src1, src2}
VPSHUFDZ256mik [HasVLX, HasAVX512]
vpshufd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSHUFDZ256mikz [HasVLX, HasAVX512]
vpshufd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSHUFDZ256ri [HasVLX, HasAVX512]
vpshufd {src2, src1, dst|dst, src1, src2}
VPSHUFDZ256rik [HasVLX, HasAVX512]
vpshufd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSHUFDZ256rikz [HasVLX, HasAVX512]
vpshufd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSLLDZ128mbi [HasVLX, HasAVX512]
vpslld {src2, src1{1to4}, dst|dst, src1{1to4}, src2}
VPSLLDZ128mbik [HasVLX, HasAVX512]
vpslld {src2, src1{1to4}, dst {mask}|dst {mask}, src1{1to4}, src2}
|
Note
|
Constraints: src0 = dst |
VPSLLDZ128mbikz [HasVLX, HasAVX512]
vpslld {src2, src1{1to4}, dst {mask} {z}|dst {mask} {z}, src1{1to4}, src2}
VPSLLDZ128mi [HasVLX, HasAVX512]
vpslld {src2, src1, dst|dst, src1, src2}
VPSLLDZ128mik [HasVLX, HasAVX512]
vpslld {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSLLDZ128mikz [HasVLX, HasAVX512]
vpslld {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSLLDZ128ri [HasVLX, HasAVX512]
vpslld {src2, src1, dst|dst, src1, src2}
VPSLLDZ128rik [HasVLX, HasAVX512]
vpslld {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSLLDZ128rikz [HasVLX, HasAVX512]
vpslld {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSLLDZ128rm [HasVLX, HasAVX512]
vpslld {src2, src1, dst|dst, src1, src2}
VPSLLDZ128rmk [HasVLX, HasAVX512]
vpslld {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSLLDZ128rmkz [HasVLX, HasAVX512]
vpslld {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSLLDZ128rr [HasVLX, HasAVX512]
vpslld {src2, src1, dst|dst, src1, src2}
VPSLLDZ128rrk [HasVLX, HasAVX512]
vpslld {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSLLDZ128rrkz [HasVLX, HasAVX512]
vpslld {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSLLDZ256mbi [HasVLX, HasAVX512]
vpslld {src2, src1{1to8}, dst|dst, src1{1to8}, src2}
VPSLLDZ256mbik [HasVLX, HasAVX512]
vpslld {src2, src1{1to8}, dst {mask}|dst {mask}, src1{1to8}, src2}
|
Note
|
Constraints: src0 = dst |
VPSLLDZ256mbikz [HasVLX, HasAVX512]
vpslld {src2, src1{1to8}, dst {mask} {z}|dst {mask} {z}, src1{1to8}, src2}
VPSLLDZ256mi [HasVLX, HasAVX512]
vpslld {src2, src1, dst|dst, src1, src2}
VPSLLDZ256mik [HasVLX, HasAVX512]
vpslld {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSLLDZ256mikz [HasVLX, HasAVX512]
vpslld {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSLLDZ256ri [HasVLX, HasAVX512]
vpslld {src2, src1, dst|dst, src1, src2}
VPSLLDZ256rik [HasVLX, HasAVX512]
vpslld {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSLLDZ256rikz [HasVLX, HasAVX512]
vpslld {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSLLDZ256rm [HasVLX, HasAVX512]
vpslld {src2, src1, dst|dst, src1, src2}
VPSLLDZ256rmk [HasVLX, HasAVX512]
vpslld {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSLLDZ256rmkz [HasVLX, HasAVX512]
vpslld {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSLLDZ256rr [HasVLX, HasAVX512]
vpslld {src2, src1, dst|dst, src1, src2}
VPSLLDZ256rrk [HasVLX, HasAVX512]
vpslld {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSLLDZ256rrkz [HasVLX, HasAVX512]
vpslld {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSLLQZ128mbi [HasVLX, HasAVX512]
vpsllq {src2, src1{1to2}, dst|dst, src1{1to2}, src2}
VPSLLQZ128mbik [HasVLX, HasAVX512]
vpsllq {src2, src1{1to2}, dst {mask}|dst {mask}, src1{1to2}, src2}
|
Note
|
Constraints: src0 = dst |
VPSLLQZ128mbikz [HasVLX, HasAVX512]
vpsllq {src2, src1{1to2}, dst {mask} {z}|dst {mask} {z}, src1{1to2}, src2}
VPSLLQZ128mi [HasVLX, HasAVX512]
vpsllq {src2, src1, dst|dst, src1, src2}
VPSLLQZ128mik [HasVLX, HasAVX512]
vpsllq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSLLQZ128mikz [HasVLX, HasAVX512]
vpsllq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSLLQZ128ri [HasVLX, HasAVX512]
vpsllq {src2, src1, dst|dst, src1, src2}
VPSLLQZ128rik [HasVLX, HasAVX512]
vpsllq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSLLQZ128rikz [HasVLX, HasAVX512]
vpsllq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSLLQZ128rm [HasVLX, HasAVX512]
vpsllq {src2, src1, dst|dst, src1, src2}
VPSLLQZ128rmk [HasVLX, HasAVX512]
vpsllq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSLLQZ128rmkz [HasVLX, HasAVX512]
vpsllq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSLLQZ128rr [HasVLX, HasAVX512]
vpsllq {src2, src1, dst|dst, src1, src2}
VPSLLQZ128rrk [HasVLX, HasAVX512]
vpsllq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSLLQZ128rrkz [HasVLX, HasAVX512]
vpsllq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSLLQZ256mbi [HasVLX, HasAVX512]
vpsllq {src2, src1{1to4}, dst|dst, src1{1to4}, src2}
VPSLLQZ256mbik [HasVLX, HasAVX512]
vpsllq {src2, src1{1to4}, dst {mask}|dst {mask}, src1{1to4}, src2}
|
Note
|
Constraints: src0 = dst |
VPSLLQZ256mbikz [HasVLX, HasAVX512]
vpsllq {src2, src1{1to4}, dst {mask} {z}|dst {mask} {z}, src1{1to4}, src2}
VPSLLQZ256mi [HasVLX, HasAVX512]
vpsllq {src2, src1, dst|dst, src1, src2}
VPSLLQZ256mik [HasVLX, HasAVX512]
vpsllq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSLLQZ256mikz [HasVLX, HasAVX512]
vpsllq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSLLQZ256ri [HasVLX, HasAVX512]
vpsllq {src2, src1, dst|dst, src1, src2}
VPSLLQZ256rik [HasVLX, HasAVX512]
vpsllq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSLLQZ256rikz [HasVLX, HasAVX512]
vpsllq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSLLQZ256rm [HasVLX, HasAVX512]
vpsllq {src2, src1, dst|dst, src1, src2}
VPSLLQZ256rmk [HasVLX, HasAVX512]
vpsllq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSLLQZ256rmkz [HasVLX, HasAVX512]
vpsllq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSLLQZ256rr [HasVLX, HasAVX512]
vpsllq {src2, src1, dst|dst, src1, src2}
VPSLLQZ256rrk [HasVLX, HasAVX512]
vpsllq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSLLQZ256rrkz [HasVLX, HasAVX512]
vpsllq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSLLVDZ128rm [HasVLX, HasAVX512]
vpsllvd {src2, src1, dst|dst, src1, src2}
VPSLLVDZ128rmb [HasVLX, HasAVX512]
vpsllvd {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
VPSLLVDZ128rmbk [HasVLX, HasAVX512]
vpsllvd {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Constraints: src0 = dst |
VPSLLVDZ128rmbkz [HasVLX, HasAVX512]
vpsllvd {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
VPSLLVDZ128rmk [HasVLX, HasAVX512]
vpsllvd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSLLVDZ128rmkz [HasVLX, HasAVX512]
vpsllvd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSLLVDZ128rr [HasVLX, HasAVX512]
vpsllvd {src2, src1, dst|dst, src1, src2}
VPSLLVDZ128rrk [HasVLX, HasAVX512]
vpsllvd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSLLVDZ128rrkz [HasVLX, HasAVX512]
vpsllvd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSLLVDZ256rm [HasVLX, HasAVX512]
vpsllvd {src2, src1, dst|dst, src1, src2}
VPSLLVDZ256rmb [HasVLX, HasAVX512]
vpsllvd {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
VPSLLVDZ256rmbk [HasVLX, HasAVX512]
vpsllvd {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Constraints: src0 = dst |
VPSLLVDZ256rmbkz [HasVLX, HasAVX512]
vpsllvd {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
VPSLLVDZ256rmk [HasVLX, HasAVX512]
vpsllvd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSLLVDZ256rmkz [HasVLX, HasAVX512]
vpsllvd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSLLVDZ256rr [HasVLX, HasAVX512]
vpsllvd {src2, src1, dst|dst, src1, src2}
VPSLLVDZ256rrk [HasVLX, HasAVX512]
vpsllvd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSLLVDZ256rrkz [HasVLX, HasAVX512]
vpsllvd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSLLVQZ128rm [HasVLX, HasAVX512]
vpsllvq {src2, src1, dst|dst, src1, src2}
VPSLLVQZ128rmb [HasVLX, HasAVX512]
vpsllvq {src2{1to2}, src1, dst|dst, src1, src2{1to2}}
VPSLLVQZ128rmbk [HasVLX, HasAVX512]
vpsllvq {src2{1to2}, src1, dst {mask}|dst {mask}, src1, src2{1to2}}
|
Note
|
Constraints: src0 = dst |
VPSLLVQZ128rmbkz [HasVLX, HasAVX512]
vpsllvq {src2{1to2}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to2}}
VPSLLVQZ128rmk [HasVLX, HasAVX512]
vpsllvq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSLLVQZ128rmkz [HasVLX, HasAVX512]
vpsllvq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSLLVQZ128rr [HasVLX, HasAVX512]
vpsllvq {src2, src1, dst|dst, src1, src2}
VPSLLVQZ128rrk [HasVLX, HasAVX512]
vpsllvq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSLLVQZ128rrkz [HasVLX, HasAVX512]
vpsllvq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSLLVQZ256rm [HasVLX, HasAVX512]
vpsllvq {src2, src1, dst|dst, src1, src2}
VPSLLVQZ256rmb [HasVLX, HasAVX512]
vpsllvq {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
VPSLLVQZ256rmbk [HasVLX, HasAVX512]
vpsllvq {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Constraints: src0 = dst |
VPSLLVQZ256rmbkz [HasVLX, HasAVX512]
vpsllvq {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
VPSLLVQZ256rmk [HasVLX, HasAVX512]
vpsllvq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSLLVQZ256rmkz [HasVLX, HasAVX512]
vpsllvq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSLLVQZ256rr [HasVLX, HasAVX512]
vpsllvq {src2, src1, dst|dst, src1, src2}
VPSLLVQZ256rrk [HasVLX, HasAVX512]
vpsllvq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSLLVQZ256rrkz [HasVLX, HasAVX512]
vpsllvq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRADZ128mbi [HasVLX, HasAVX512]
vpsrad {src2, src1{1to4}, dst|dst, src1{1to4}, src2}
VPSRADZ128mbik [HasVLX, HasAVX512]
vpsrad {src2, src1{1to4}, dst {mask}|dst {mask}, src1{1to4}, src2}
|
Note
|
Constraints: src0 = dst |
VPSRADZ128mbikz [HasVLX, HasAVX512]
vpsrad {src2, src1{1to4}, dst {mask} {z}|dst {mask} {z}, src1{1to4}, src2}
VPSRADZ128mi [HasVLX, HasAVX512]
vpsrad {src2, src1, dst|dst, src1, src2}
VPSRADZ128mik [HasVLX, HasAVX512]
vpsrad {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRADZ128mikz [HasVLX, HasAVX512]
vpsrad {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRADZ128ri [HasVLX, HasAVX512]
vpsrad {src2, src1, dst|dst, src1, src2}
VPSRADZ128rik [HasVLX, HasAVX512]
vpsrad {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRADZ128rikz [HasVLX, HasAVX512]
vpsrad {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRADZ128rm [HasVLX, HasAVX512]
vpsrad {src2, src1, dst|dst, src1, src2}
VPSRADZ128rmk [HasVLX, HasAVX512]
vpsrad {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRADZ128rmkz [HasVLX, HasAVX512]
vpsrad {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRADZ128rr [HasVLX, HasAVX512]
vpsrad {src2, src1, dst|dst, src1, src2}
VPSRADZ128rrk [HasVLX, HasAVX512]
vpsrad {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRADZ128rrkz [HasVLX, HasAVX512]
vpsrad {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRADZ256mbi [HasVLX, HasAVX512]
vpsrad {src2, src1{1to8}, dst|dst, src1{1to8}, src2}
VPSRADZ256mbik [HasVLX, HasAVX512]
vpsrad {src2, src1{1to8}, dst {mask}|dst {mask}, src1{1to8}, src2}
|
Note
|
Constraints: src0 = dst |
VPSRADZ256mbikz [HasVLX, HasAVX512]
vpsrad {src2, src1{1to8}, dst {mask} {z}|dst {mask} {z}, src1{1to8}, src2}
VPSRADZ256mi [HasVLX, HasAVX512]
vpsrad {src2, src1, dst|dst, src1, src2}
VPSRADZ256mik [HasVLX, HasAVX512]
vpsrad {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRADZ256mikz [HasVLX, HasAVX512]
vpsrad {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRADZ256ri [HasVLX, HasAVX512]
vpsrad {src2, src1, dst|dst, src1, src2}
VPSRADZ256rik [HasVLX, HasAVX512]
vpsrad {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRADZ256rikz [HasVLX, HasAVX512]
vpsrad {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRADZ256rm [HasVLX, HasAVX512]
vpsrad {src2, src1, dst|dst, src1, src2}
VPSRADZ256rmk [HasVLX, HasAVX512]
vpsrad {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRADZ256rmkz [HasVLX, HasAVX512]
vpsrad {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRADZ256rr [HasVLX, HasAVX512]
vpsrad {src2, src1, dst|dst, src1, src2}
VPSRADZ256rrk [HasVLX, HasAVX512]
vpsrad {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRADZ256rrkz [HasVLX, HasAVX512]
vpsrad {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRAQZ128mbi [HasVLX, HasAVX512]
vpsraq {src2, src1{1to2}, dst|dst, src1{1to2}, src2}
VPSRAQZ128mbik [HasVLX, HasAVX512]
vpsraq {src2, src1{1to2}, dst {mask}|dst {mask}, src1{1to2}, src2}
|
Note
|
Constraints: src0 = dst |
VPSRAQZ128mbikz [HasVLX, HasAVX512]
vpsraq {src2, src1{1to2}, dst {mask} {z}|dst {mask} {z}, src1{1to2}, src2}
VPSRAQZ128mi [HasVLX, HasAVX512]
vpsraq {src2, src1, dst|dst, src1, src2}
VPSRAQZ128mik [HasVLX, HasAVX512]
vpsraq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRAQZ128mikz [HasVLX, HasAVX512]
vpsraq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRAQZ128ri [HasVLX, HasAVX512]
vpsraq {src2, src1, dst|dst, src1, src2}
VPSRAQZ128rik [HasVLX, HasAVX512]
vpsraq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRAQZ128rikz [HasVLX, HasAVX512]
vpsraq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRAQZ128rm [HasVLX, HasAVX512]
vpsraq {src2, src1, dst|dst, src1, src2}
VPSRAQZ128rmk [HasVLX, HasAVX512]
vpsraq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRAQZ128rmkz [HasVLX, HasAVX512]
vpsraq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRAQZ128rr [HasVLX, HasAVX512]
vpsraq {src2, src1, dst|dst, src1, src2}
VPSRAQZ128rrk [HasVLX, HasAVX512]
vpsraq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRAQZ128rrkz [HasVLX, HasAVX512]
vpsraq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRAQZ256mbi [HasVLX, HasAVX512]
vpsraq {src2, src1{1to4}, dst|dst, src1{1to4}, src2}
VPSRAQZ256mbik [HasVLX, HasAVX512]
vpsraq {src2, src1{1to4}, dst {mask}|dst {mask}, src1{1to4}, src2}
|
Note
|
Constraints: src0 = dst |
VPSRAQZ256mbikz [HasVLX, HasAVX512]
vpsraq {src2, src1{1to4}, dst {mask} {z}|dst {mask} {z}, src1{1to4}, src2}
VPSRAQZ256mi [HasVLX, HasAVX512]
vpsraq {src2, src1, dst|dst, src1, src2}
VPSRAQZ256mik [HasVLX, HasAVX512]
vpsraq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRAQZ256mikz [HasVLX, HasAVX512]
vpsraq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRAQZ256ri [HasVLX, HasAVX512]
vpsraq {src2, src1, dst|dst, src1, src2}
VPSRAQZ256rik [HasVLX, HasAVX512]
vpsraq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRAQZ256rikz [HasVLX, HasAVX512]
vpsraq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRAQZ256rm [HasVLX, HasAVX512]
vpsraq {src2, src1, dst|dst, src1, src2}
VPSRAQZ256rmk [HasVLX, HasAVX512]
vpsraq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRAQZ256rmkz [HasVLX, HasAVX512]
vpsraq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRAQZ256rr [HasVLX, HasAVX512]
vpsraq {src2, src1, dst|dst, src1, src2}
VPSRAQZ256rrk [HasVLX, HasAVX512]
vpsraq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRAQZ256rrkz [HasVLX, HasAVX512]
vpsraq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRAVDZ128rm [HasVLX, HasAVX512]
vpsravd {src2, src1, dst|dst, src1, src2}
VPSRAVDZ128rmb [HasVLX, HasAVX512]
vpsravd {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
VPSRAVDZ128rmbk [HasVLX, HasAVX512]
vpsravd {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Constraints: src0 = dst |
VPSRAVDZ128rmbkz [HasVLX, HasAVX512]
vpsravd {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
VPSRAVDZ128rmk [HasVLX, HasAVX512]
vpsravd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRAVDZ128rmkz [HasVLX, HasAVX512]
vpsravd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRAVDZ128rr [HasVLX, HasAVX512]
vpsravd {src2, src1, dst|dst, src1, src2}
VPSRAVDZ128rrk [HasVLX, HasAVX512]
vpsravd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRAVDZ128rrkz [HasVLX, HasAVX512]
vpsravd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRAVDZ256rm [HasVLX, HasAVX512]
vpsravd {src2, src1, dst|dst, src1, src2}
VPSRAVDZ256rmb [HasVLX, HasAVX512]
vpsravd {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
VPSRAVDZ256rmbk [HasVLX, HasAVX512]
vpsravd {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Constraints: src0 = dst |
VPSRAVDZ256rmbkz [HasVLX, HasAVX512]
vpsravd {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
VPSRAVDZ256rmk [HasVLX, HasAVX512]
vpsravd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRAVDZ256rmkz [HasVLX, HasAVX512]
vpsravd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRAVDZ256rr [HasVLX, HasAVX512]
vpsravd {src2, src1, dst|dst, src1, src2}
VPSRAVDZ256rrk [HasVLX, HasAVX512]
vpsravd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRAVDZ256rrkz [HasVLX, HasAVX512]
vpsravd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRAVQZ128rm [HasVLX, HasAVX512]
vpsravq {src2, src1, dst|dst, src1, src2}
VPSRAVQZ128rmb [HasVLX, HasAVX512]
vpsravq {src2{1to2}, src1, dst|dst, src1, src2{1to2}}
VPSRAVQZ128rmbk [HasVLX, HasAVX512]
vpsravq {src2{1to2}, src1, dst {mask}|dst {mask}, src1, src2{1to2}}
|
Note
|
Constraints: src0 = dst |
VPSRAVQZ128rmbkz [HasVLX, HasAVX512]
vpsravq {src2{1to2}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to2}}
VPSRAVQZ128rmk [HasVLX, HasAVX512]
vpsravq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRAVQZ128rmkz [HasVLX, HasAVX512]
vpsravq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRAVQZ128rr [HasVLX, HasAVX512]
vpsravq {src2, src1, dst|dst, src1, src2}
VPSRAVQZ128rrk [HasVLX, HasAVX512]
vpsravq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRAVQZ128rrkz [HasVLX, HasAVX512]
vpsravq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRAVQZ256rm [HasVLX, HasAVX512]
vpsravq {src2, src1, dst|dst, src1, src2}
VPSRAVQZ256rmb [HasVLX, HasAVX512]
vpsravq {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
VPSRAVQZ256rmbk [HasVLX, HasAVX512]
vpsravq {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Constraints: src0 = dst |
VPSRAVQZ256rmbkz [HasVLX, HasAVX512]
vpsravq {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
VPSRAVQZ256rmk [HasVLX, HasAVX512]
vpsravq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRAVQZ256rmkz [HasVLX, HasAVX512]
vpsravq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRAVQZ256rr [HasVLX, HasAVX512]
vpsravq {src2, src1, dst|dst, src1, src2}
VPSRAVQZ256rrk [HasVLX, HasAVX512]
vpsravq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRAVQZ256rrkz [HasVLX, HasAVX512]
vpsravq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRLDZ128mbi [HasVLX, HasAVX512]
vpsrld {src2, src1{1to4}, dst|dst, src1{1to4}, src2}
VPSRLDZ128mbik [HasVLX, HasAVX512]
vpsrld {src2, src1{1to4}, dst {mask}|dst {mask}, src1{1to4}, src2}
|
Note
|
Constraints: src0 = dst |
VPSRLDZ128mbikz [HasVLX, HasAVX512]
vpsrld {src2, src1{1to4}, dst {mask} {z}|dst {mask} {z}, src1{1to4}, src2}
VPSRLDZ128mi [HasVLX, HasAVX512]
vpsrld {src2, src1, dst|dst, src1, src2}
VPSRLDZ128mik [HasVLX, HasAVX512]
vpsrld {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRLDZ128mikz [HasVLX, HasAVX512]
vpsrld {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRLDZ128ri [HasVLX, HasAVX512]
vpsrld {src2, src1, dst|dst, src1, src2}
VPSRLDZ128rik [HasVLX, HasAVX512]
vpsrld {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRLDZ128rikz [HasVLX, HasAVX512]
vpsrld {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRLDZ128rm [HasVLX, HasAVX512]
vpsrld {src2, src1, dst|dst, src1, src2}
VPSRLDZ128rmk [HasVLX, HasAVX512]
vpsrld {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRLDZ128rmkz [HasVLX, HasAVX512]
vpsrld {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRLDZ128rr [HasVLX, HasAVX512]
vpsrld {src2, src1, dst|dst, src1, src2}
VPSRLDZ128rrk [HasVLX, HasAVX512]
vpsrld {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRLDZ128rrkz [HasVLX, HasAVX512]
vpsrld {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRLDZ256mbi [HasVLX, HasAVX512]
vpsrld {src2, src1{1to8}, dst|dst, src1{1to8}, src2}
VPSRLDZ256mbik [HasVLX, HasAVX512]
vpsrld {src2, src1{1to8}, dst {mask}|dst {mask}, src1{1to8}, src2}
|
Note
|
Constraints: src0 = dst |
VPSRLDZ256mbikz [HasVLX, HasAVX512]
vpsrld {src2, src1{1to8}, dst {mask} {z}|dst {mask} {z}, src1{1to8}, src2}
VPSRLDZ256mi [HasVLX, HasAVX512]
vpsrld {src2, src1, dst|dst, src1, src2}
VPSRLDZ256mik [HasVLX, HasAVX512]
vpsrld {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRLDZ256mikz [HasVLX, HasAVX512]
vpsrld {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRLDZ256ri [HasVLX, HasAVX512]
vpsrld {src2, src1, dst|dst, src1, src2}
VPSRLDZ256rik [HasVLX, HasAVX512]
vpsrld {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRLDZ256rikz [HasVLX, HasAVX512]
vpsrld {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRLDZ256rm [HasVLX, HasAVX512]
vpsrld {src2, src1, dst|dst, src1, src2}
VPSRLDZ256rmk [HasVLX, HasAVX512]
vpsrld {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRLDZ256rmkz [HasVLX, HasAVX512]
vpsrld {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRLDZ256rr [HasVLX, HasAVX512]
vpsrld {src2, src1, dst|dst, src1, src2}
VPSRLDZ256rrk [HasVLX, HasAVX512]
vpsrld {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRLDZ256rrkz [HasVLX, HasAVX512]
vpsrld {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRLQZ128mbi [HasVLX, HasAVX512]
vpsrlq {src2, src1{1to2}, dst|dst, src1{1to2}, src2}
VPSRLQZ128mbik [HasVLX, HasAVX512]
vpsrlq {src2, src1{1to2}, dst {mask}|dst {mask}, src1{1to2}, src2}
|
Note
|
Constraints: src0 = dst |
VPSRLQZ128mbikz [HasVLX, HasAVX512]
vpsrlq {src2, src1{1to2}, dst {mask} {z}|dst {mask} {z}, src1{1to2}, src2}
VPSRLQZ128mi [HasVLX, HasAVX512]
vpsrlq {src2, src1, dst|dst, src1, src2}
VPSRLQZ128mik [HasVLX, HasAVX512]
vpsrlq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRLQZ128mikz [HasVLX, HasAVX512]
vpsrlq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRLQZ128ri [HasVLX, HasAVX512]
vpsrlq {src2, src1, dst|dst, src1, src2}
VPSRLQZ128rik [HasVLX, HasAVX512]
vpsrlq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRLQZ128rikz [HasVLX, HasAVX512]
vpsrlq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRLQZ128rm [HasVLX, HasAVX512]
vpsrlq {src2, src1, dst|dst, src1, src2}
VPSRLQZ128rmk [HasVLX, HasAVX512]
vpsrlq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRLQZ128rmkz [HasVLX, HasAVX512]
vpsrlq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRLQZ128rr [HasVLX, HasAVX512]
vpsrlq {src2, src1, dst|dst, src1, src2}
VPSRLQZ128rrk [HasVLX, HasAVX512]
vpsrlq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRLQZ128rrkz [HasVLX, HasAVX512]
vpsrlq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRLQZ256mbi [HasVLX, HasAVX512]
vpsrlq {src2, src1{1to4}, dst|dst, src1{1to4}, src2}
VPSRLQZ256mbik [HasVLX, HasAVX512]
vpsrlq {src2, src1{1to4}, dst {mask}|dst {mask}, src1{1to4}, src2}
|
Note
|
Constraints: src0 = dst |
VPSRLQZ256mbikz [HasVLX, HasAVX512]
vpsrlq {src2, src1{1to4}, dst {mask} {z}|dst {mask} {z}, src1{1to4}, src2}
VPSRLQZ256mi [HasVLX, HasAVX512]
vpsrlq {src2, src1, dst|dst, src1, src2}
VPSRLQZ256mik [HasVLX, HasAVX512]
vpsrlq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRLQZ256mikz [HasVLX, HasAVX512]
vpsrlq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRLQZ256ri [HasVLX, HasAVX512]
vpsrlq {src2, src1, dst|dst, src1, src2}
VPSRLQZ256rik [HasVLX, HasAVX512]
vpsrlq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRLQZ256rikz [HasVLX, HasAVX512]
vpsrlq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRLQZ256rm [HasVLX, HasAVX512]
vpsrlq {src2, src1, dst|dst, src1, src2}
VPSRLQZ256rmk [HasVLX, HasAVX512]
vpsrlq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRLQZ256rmkz [HasVLX, HasAVX512]
vpsrlq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRLQZ256rr [HasVLX, HasAVX512]
vpsrlq {src2, src1, dst|dst, src1, src2}
VPSRLQZ256rrk [HasVLX, HasAVX512]
vpsrlq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRLQZ256rrkz [HasVLX, HasAVX512]
vpsrlq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRLVDZ128rm [HasVLX, HasAVX512]
vpsrlvd {src2, src1, dst|dst, src1, src2}
VPSRLVDZ128rmb [HasVLX, HasAVX512]
vpsrlvd {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
VPSRLVDZ128rmbk [HasVLX, HasAVX512]
vpsrlvd {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Constraints: src0 = dst |
VPSRLVDZ128rmbkz [HasVLX, HasAVX512]
vpsrlvd {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
VPSRLVDZ128rmk [HasVLX, HasAVX512]
vpsrlvd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRLVDZ128rmkz [HasVLX, HasAVX512]
vpsrlvd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRLVDZ128rr [HasVLX, HasAVX512]
vpsrlvd {src2, src1, dst|dst, src1, src2}
VPSRLVDZ128rrk [HasVLX, HasAVX512]
vpsrlvd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRLVDZ128rrkz [HasVLX, HasAVX512]
vpsrlvd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRLVDZ256rm [HasVLX, HasAVX512]
vpsrlvd {src2, src1, dst|dst, src1, src2}
VPSRLVDZ256rmb [HasVLX, HasAVX512]
vpsrlvd {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
VPSRLVDZ256rmbk [HasVLX, HasAVX512]
vpsrlvd {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Constraints: src0 = dst |
VPSRLVDZ256rmbkz [HasVLX, HasAVX512]
vpsrlvd {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
VPSRLVDZ256rmk [HasVLX, HasAVX512]
vpsrlvd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRLVDZ256rmkz [HasVLX, HasAVX512]
vpsrlvd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRLVDZ256rr [HasVLX, HasAVX512]
vpsrlvd {src2, src1, dst|dst, src1, src2}
VPSRLVDZ256rrk [HasVLX, HasAVX512]
vpsrlvd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRLVDZ256rrkz [HasVLX, HasAVX512]
vpsrlvd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRLVQZ128rm [HasVLX, HasAVX512]
vpsrlvq {src2, src1, dst|dst, src1, src2}
VPSRLVQZ128rmb [HasVLX, HasAVX512]
vpsrlvq {src2{1to2}, src1, dst|dst, src1, src2{1to2}}
VPSRLVQZ128rmbk [HasVLX, HasAVX512]
vpsrlvq {src2{1to2}, src1, dst {mask}|dst {mask}, src1, src2{1to2}}
|
Note
|
Constraints: src0 = dst |
VPSRLVQZ128rmbkz [HasVLX, HasAVX512]
vpsrlvq {src2{1to2}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to2}}
VPSRLVQZ128rmk [HasVLX, HasAVX512]
vpsrlvq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRLVQZ128rmkz [HasVLX, HasAVX512]
vpsrlvq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRLVQZ128rr [HasVLX, HasAVX512]
vpsrlvq {src2, src1, dst|dst, src1, src2}
VPSRLVQZ128rrk [HasVLX, HasAVX512]
vpsrlvq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRLVQZ128rrkz [HasVLX, HasAVX512]
vpsrlvq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRLVQZ256rm [HasVLX, HasAVX512]
vpsrlvq {src2, src1, dst|dst, src1, src2}
VPSRLVQZ256rmb [HasVLX, HasAVX512]
vpsrlvq {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
VPSRLVQZ256rmbk [HasVLX, HasAVX512]
vpsrlvq {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Constraints: src0 = dst |
VPSRLVQZ256rmbkz [HasVLX, HasAVX512]
vpsrlvq {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
VPSRLVQZ256rmk [HasVLX, HasAVX512]
vpsrlvq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRLVQZ256rmkz [HasVLX, HasAVX512]
vpsrlvq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRLVQZ256rr [HasVLX, HasAVX512]
vpsrlvq {src2, src1, dst|dst, src1, src2}
VPSRLVQZ256rrk [HasVLX, HasAVX512]
vpsrlvq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRLVQZ256rrkz [HasVLX, HasAVX512]
vpsrlvq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSUBDZ128rm [HasVLX, HasAVX512]
vpsubd {src2, src1, dst|dst, src1, src2}
VPSUBDZ128rmb [HasVLX, HasAVX512]
vpsubd {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
VPSUBDZ128rmbk [HasVLX, HasAVX512]
vpsubd {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Constraints: src0 = dst |
VPSUBDZ128rmbkz [HasVLX, HasAVX512]
vpsubd {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
VPSUBDZ128rmk [HasVLX, HasAVX512]
vpsubd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSUBDZ128rmkz [HasVLX, HasAVX512]
vpsubd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSUBDZ128rr [HasVLX, HasAVX512]
vpsubd {src2, src1, dst|dst, src1, src2}
VPSUBDZ128rrk [HasVLX, HasAVX512]
vpsubd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSUBDZ128rrkz [HasVLX, HasAVX512]
vpsubd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSUBDZ256rm [HasVLX, HasAVX512]
vpsubd {src2, src1, dst|dst, src1, src2}
VPSUBDZ256rmb [HasVLX, HasAVX512]
vpsubd {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
VPSUBDZ256rmbk [HasVLX, HasAVX512]
vpsubd {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Constraints: src0 = dst |
VPSUBDZ256rmbkz [HasVLX, HasAVX512]
vpsubd {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
VPSUBDZ256rmk [HasVLX, HasAVX512]
vpsubd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSUBDZ256rmkz [HasVLX, HasAVX512]
vpsubd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSUBDZ256rr [HasVLX, HasAVX512]
vpsubd {src2, src1, dst|dst, src1, src2}
VPSUBDZ256rrk [HasVLX, HasAVX512]
vpsubd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSUBDZ256rrkz [HasVLX, HasAVX512]
vpsubd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSUBQZ128rm [HasVLX, HasAVX512]
vpsubq {src2, src1, dst|dst, src1, src2}
VPSUBQZ128rmb [HasVLX, HasAVX512]
vpsubq {src2{1to2}, src1, dst|dst, src1, src2{1to2}}
VPSUBQZ128rmbk [HasVLX, HasAVX512]
vpsubq {src2{1to2}, src1, dst {mask}|dst {mask}, src1, src2{1to2}}
|
Note
|
Constraints: src0 = dst |
VPSUBQZ128rmbkz [HasVLX, HasAVX512]
vpsubq {src2{1to2}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to2}}
VPSUBQZ128rmk [HasVLX, HasAVX512]
vpsubq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSUBQZ128rmkz [HasVLX, HasAVX512]
vpsubq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSUBQZ128rr [HasVLX, HasAVX512]
vpsubq {src2, src1, dst|dst, src1, src2}
VPSUBQZ128rrk [HasVLX, HasAVX512]
vpsubq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSUBQZ128rrkz [HasVLX, HasAVX512]
vpsubq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSUBQZ256rm [HasVLX, HasAVX512]
vpsubq {src2, src1, dst|dst, src1, src2}
VPSUBQZ256rmb [HasVLX, HasAVX512]
vpsubq {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
VPSUBQZ256rmbk [HasVLX, HasAVX512]
vpsubq {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Constraints: src0 = dst |
VPSUBQZ256rmbkz [HasVLX, HasAVX512]
vpsubq {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
VPSUBQZ256rmk [HasVLX, HasAVX512]
vpsubq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSUBQZ256rmkz [HasVLX, HasAVX512]
vpsubq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSUBQZ256rr [HasVLX, HasAVX512]
vpsubq {src2, src1, dst|dst, src1, src2}
VPSUBQZ256rrk [HasVLX, HasAVX512]
vpsubq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSUBQZ256rrkz [HasVLX, HasAVX512]
vpsubq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPTERNLOGDZ128rmbi [HasVLX, HasAVX512]
vpternlogd {src4, src3{1to4}, src2, dst|dst, src2, src3{1to4}, src4}
|
Note
|
Constraints: src1 = dst |
VPTERNLOGDZ128rmbik [HasVLX, HasAVX512]
vpternlogd {src4, src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}, src4}
|
Note
|
Constraints: src1 = dst |
VPTERNLOGDZ128rmbikz [HasVLX, HasAVX512]
vpternlogd {src4, src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}, src4}
|
Note
|
Constraints: src1 = dst |
VPTERNLOGDZ128rmi [HasVLX, HasAVX512]
vpternlogd {src4, src3, src2, dst|dst, src2, src3, src4}
|
Note
|
Constraints: src1 = dst |
VPTERNLOGDZ128rmik [HasVLX, HasAVX512]
vpternlogd {src4, src3, src2, dst {mask}|dst {mask}, src2, src3, src4}
|
Note
|
Constraints: src1 = dst |
VPTERNLOGDZ128rmikz [HasVLX, HasAVX512]
vpternlogd {src4, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, src4}
|
Note
|
Constraints: src1 = dst |
VPTERNLOGDZ128rri [HasVLX, HasAVX512]
vpternlogd {src4, src3, src2, dst|dst, src2, src3, src4}
|
Note
|
Constraints: src1 = dst |
VPTERNLOGDZ128rrik [HasVLX, HasAVX512]
vpternlogd {src4, src3, src2, dst {mask}|dst {mask}, src2, src3, src4}
|
Note
|
Constraints: src1 = dst |
VPTERNLOGDZ128rrikz [HasVLX, HasAVX512]
vpternlogd {src4, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, src4}
|
Note
|
Constraints: src1 = dst |
VPTERNLOGDZ256rmbi [HasVLX, HasAVX512]
vpternlogd {src4, src3{1to8}, src2, dst|dst, src2, src3{1to8}, src4}
|
Note
|
Constraints: src1 = dst |
VPTERNLOGDZ256rmbik [HasVLX, HasAVX512]
vpternlogd {src4, src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}, src4}
|
Note
|
Constraints: src1 = dst |
VPTERNLOGDZ256rmbikz [HasVLX, HasAVX512]
vpternlogd {src4, src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}, src4}
|
Note
|
Constraints: src1 = dst |
VPTERNLOGDZ256rmi [HasVLX, HasAVX512]
vpternlogd {src4, src3, src2, dst|dst, src2, src3, src4}
|
Note
|
Constraints: src1 = dst |
VPTERNLOGDZ256rmik [HasVLX, HasAVX512]
vpternlogd {src4, src3, src2, dst {mask}|dst {mask}, src2, src3, src4}
|
Note
|
Constraints: src1 = dst |
VPTERNLOGDZ256rmikz [HasVLX, HasAVX512]
vpternlogd {src4, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, src4}
|
Note
|
Constraints: src1 = dst |
VPTERNLOGDZ256rri [HasVLX, HasAVX512]
vpternlogd {src4, src3, src2, dst|dst, src2, src3, src4}
|
Note
|
Constraints: src1 = dst |
VPTERNLOGDZ256rrik [HasVLX, HasAVX512]
vpternlogd {src4, src3, src2, dst {mask}|dst {mask}, src2, src3, src4}
|
Note
|
Constraints: src1 = dst |
VPTERNLOGDZ256rrikz [HasVLX, HasAVX512]
vpternlogd {src4, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, src4}
|
Note
|
Constraints: src1 = dst |
VPTERNLOGQZ128rmbi [HasVLX, HasAVX512]
vpternlogq {src4, src3{1to2}, src2, dst|dst, src2, src3{1to2}, src4}
|
Note
|
Constraints: src1 = dst |
VPTERNLOGQZ128rmbik [HasVLX, HasAVX512]
vpternlogq {src4, src3{1to2}, src2, dst {mask}|dst {mask}, src2, src3{1to2}, src4}
|
Note
|
Constraints: src1 = dst |
VPTERNLOGQZ128rmbikz [HasVLX, HasAVX512]
vpternlogq {src4, src3{1to2}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to2}, src4}
|
Note
|
Constraints: src1 = dst |
VPTERNLOGQZ128rmi [HasVLX, HasAVX512]
vpternlogq {src4, src3, src2, dst|dst, src2, src3, src4}
|
Note
|
Constraints: src1 = dst |
VPTERNLOGQZ128rmik [HasVLX, HasAVX512]
vpternlogq {src4, src3, src2, dst {mask}|dst {mask}, src2, src3, src4}
|
Note
|
Constraints: src1 = dst |
VPTERNLOGQZ128rmikz [HasVLX, HasAVX512]
vpternlogq {src4, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, src4}
|
Note
|
Constraints: src1 = dst |
VPTERNLOGQZ128rri [HasVLX, HasAVX512]
vpternlogq {src4, src3, src2, dst|dst, src2, src3, src4}
|
Note
|
Constraints: src1 = dst |
VPTERNLOGQZ128rrik [HasVLX, HasAVX512]
vpternlogq {src4, src3, src2, dst {mask}|dst {mask}, src2, src3, src4}
|
Note
|
Constraints: src1 = dst |
VPTERNLOGQZ128rrikz [HasVLX, HasAVX512]
vpternlogq {src4, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, src4}
|
Note
|
Constraints: src1 = dst |
VPTERNLOGQZ256rmbi [HasVLX, HasAVX512]
vpternlogq {src4, src3{1to4}, src2, dst|dst, src2, src3{1to4}, src4}
|
Note
|
Constraints: src1 = dst |
VPTERNLOGQZ256rmbik [HasVLX, HasAVX512]
vpternlogq {src4, src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}, src4}
|
Note
|
Constraints: src1 = dst |
VPTERNLOGQZ256rmbikz [HasVLX, HasAVX512]
vpternlogq {src4, src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}, src4}
|
Note
|
Constraints: src1 = dst |
VPTERNLOGQZ256rmi [HasVLX, HasAVX512]
vpternlogq {src4, src3, src2, dst|dst, src2, src3, src4}
|
Note
|
Constraints: src1 = dst |
VPTERNLOGQZ256rmik [HasVLX, HasAVX512]
vpternlogq {src4, src3, src2, dst {mask}|dst {mask}, src2, src3, src4}
|
Note
|
Constraints: src1 = dst |
VPTERNLOGQZ256rmikz [HasVLX, HasAVX512]
vpternlogq {src4, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, src4}
|
Note
|
Constraints: src1 = dst |
VPTERNLOGQZ256rri [HasVLX, HasAVX512]
vpternlogq {src4, src3, src2, dst|dst, src2, src3, src4}
|
Note
|
Constraints: src1 = dst |
VPTERNLOGQZ256rrik [HasVLX, HasAVX512]
vpternlogq {src4, src3, src2, dst {mask}|dst {mask}, src2, src3, src4}
|
Note
|
Constraints: src1 = dst |
VPTERNLOGQZ256rrikz [HasVLX, HasAVX512]
vpternlogq {src4, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, src4}
|
Note
|
Constraints: src1 = dst |
VPTESTMDZ128rm [HasVLX, HasAVX512]
vptestmd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VPTESTMDZ128rmb [HasVLX, HasAVX512]
vptestmd {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
|
Note
|
Properties: mayLoad |
VPTESTMDZ128rmbk [HasVLX, HasAVX512]
vptestmd {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Properties: mayLoad |
VPTESTMDZ128rmk [HasVLX, HasAVX512]
vptestmd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
VPTESTMDZ128rr [HasVLX, HasAVX512]
vptestmd {src2, src1, dst|dst, src1, src2}
VPTESTMDZ128rrk [HasVLX, HasAVX512]
vptestmd {src2, src1, dst {mask}|dst {mask}, src1, src2}
VPTESTMDZ256rm [HasVLX, HasAVX512]
vptestmd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VPTESTMDZ256rmb [HasVLX, HasAVX512]
vptestmd {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
VPTESTMDZ256rmbk [HasVLX, HasAVX512]
vptestmd {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
VPTESTMDZ256rmk [HasVLX, HasAVX512]
vptestmd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
VPTESTMDZ256rr [HasVLX, HasAVX512]
vptestmd {src2, src1, dst|dst, src1, src2}
VPTESTMDZ256rrk [HasVLX, HasAVX512]
vptestmd {src2, src1, dst {mask}|dst {mask}, src1, src2}
VPTESTMQZ128rm [HasVLX, HasAVX512]
vptestmq {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VPTESTMQZ128rmb [HasVLX, HasAVX512]
vptestmq {src2{1to2}, src1, dst|dst, src1, src2{1to2}}
|
Note
|
Properties: mayLoad |
VPTESTMQZ128rmbk [HasVLX, HasAVX512]
vptestmq {src2{1to2}, src1, dst {mask}|dst {mask}, src1, src2{1to2}}
|
Note
|
Properties: mayLoad |
VPTESTMQZ128rmk [HasVLX, HasAVX512]
vptestmq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
VPTESTMQZ128rr [HasVLX, HasAVX512]
vptestmq {src2, src1, dst|dst, src1, src2}
VPTESTMQZ128rrk [HasVLX, HasAVX512]
vptestmq {src2, src1, dst {mask}|dst {mask}, src1, src2}
VPTESTMQZ256rm [HasVLX, HasAVX512]
vptestmq {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VPTESTMQZ256rmb [HasVLX, HasAVX512]
vptestmq {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
|
Note
|
Properties: mayLoad |
VPTESTMQZ256rmbk [HasVLX, HasAVX512]
vptestmq {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Properties: mayLoad |
VPTESTMQZ256rmk [HasVLX, HasAVX512]
vptestmq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
VPTESTMQZ256rr [HasVLX, HasAVX512]
vptestmq {src2, src1, dst|dst, src1, src2}
VPTESTMQZ256rrk [HasVLX, HasAVX512]
vptestmq {src2, src1, dst {mask}|dst {mask}, src1, src2}
VPTESTNMDZ128rm [HasVLX, HasAVX512]
vptestnmd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VPTESTNMDZ128rmb [HasVLX, HasAVX512]
vptestnmd {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
|
Note
|
Properties: mayLoad |
VPTESTNMDZ128rmbk [HasVLX, HasAVX512]
vptestnmd {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Properties: mayLoad |
VPTESTNMDZ128rmk [HasVLX, HasAVX512]
vptestnmd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
VPTESTNMDZ128rr [HasVLX, HasAVX512]
vptestnmd {src2, src1, dst|dst, src1, src2}
VPTESTNMDZ128rrk [HasVLX, HasAVX512]
vptestnmd {src2, src1, dst {mask}|dst {mask}, src1, src2}
VPTESTNMDZ256rm [HasVLX, HasAVX512]
vptestnmd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VPTESTNMDZ256rmb [HasVLX, HasAVX512]
vptestnmd {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
VPTESTNMDZ256rmbk [HasVLX, HasAVX512]
vptestnmd {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
VPTESTNMDZ256rmk [HasVLX, HasAVX512]
vptestnmd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
VPTESTNMDZ256rr [HasVLX, HasAVX512]
vptestnmd {src2, src1, dst|dst, src1, src2}
VPTESTNMDZ256rrk [HasVLX, HasAVX512]
vptestnmd {src2, src1, dst {mask}|dst {mask}, src1, src2}
VPTESTNMQZ128rm [HasVLX, HasAVX512]
vptestnmq {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VPTESTNMQZ128rmb [HasVLX, HasAVX512]
vptestnmq {src2{1to2}, src1, dst|dst, src1, src2{1to2}}
|
Note
|
Properties: mayLoad |
VPTESTNMQZ128rmbk [HasVLX, HasAVX512]
vptestnmq {src2{1to2}, src1, dst {mask}|dst {mask}, src1, src2{1to2}}
|
Note
|
Properties: mayLoad |
VPTESTNMQZ128rmk [HasVLX, HasAVX512]
vptestnmq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
VPTESTNMQZ128rr [HasVLX, HasAVX512]
vptestnmq {src2, src1, dst|dst, src1, src2}
VPTESTNMQZ128rrk [HasVLX, HasAVX512]
vptestnmq {src2, src1, dst {mask}|dst {mask}, src1, src2}
VPTESTNMQZ256rm [HasVLX, HasAVX512]
vptestnmq {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VPTESTNMQZ256rmb [HasVLX, HasAVX512]
vptestnmq {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
|
Note
|
Properties: mayLoad |
VPTESTNMQZ256rmbk [HasVLX, HasAVX512]
vptestnmq {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Properties: mayLoad |
VPTESTNMQZ256rmk [HasVLX, HasAVX512]
vptestnmq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
VPTESTNMQZ256rr [HasVLX, HasAVX512]
vptestnmq {src2, src1, dst|dst, src1, src2}
VPTESTNMQZ256rrk [HasVLX, HasAVX512]
vptestnmq {src2, src1, dst {mask}|dst {mask}, src1, src2}
VPUNPCKHDQZ128rm [HasVLX, HasAVX512]
vpunpckhdq {src2, src1, dst|dst, src1, src2}
VPUNPCKHDQZ128rmb [HasVLX, HasAVX512]
vpunpckhdq {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
VPUNPCKHDQZ128rmbk [HasVLX, HasAVX512]
vpunpckhdq {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Constraints: src0 = dst |
VPUNPCKHDQZ128rmbkz [HasVLX, HasAVX512]
vpunpckhdq {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
VPUNPCKHDQZ128rmk [HasVLX, HasAVX512]
vpunpckhdq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPUNPCKHDQZ128rmkz [HasVLX, HasAVX512]
vpunpckhdq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPUNPCKHDQZ128rr [HasVLX, HasAVX512]
vpunpckhdq {src2, src1, dst|dst, src1, src2}
VPUNPCKHDQZ128rrk [HasVLX, HasAVX512]
vpunpckhdq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPUNPCKHDQZ128rrkz [HasVLX, HasAVX512]
vpunpckhdq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPUNPCKHDQZ256rm [HasVLX, HasAVX512]
vpunpckhdq {src2, src1, dst|dst, src1, src2}
VPUNPCKHDQZ256rmb [HasVLX, HasAVX512]
vpunpckhdq {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
VPUNPCKHDQZ256rmbk [HasVLX, HasAVX512]
vpunpckhdq {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Constraints: src0 = dst |
VPUNPCKHDQZ256rmbkz [HasVLX, HasAVX512]
vpunpckhdq {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
VPUNPCKHDQZ256rmk [HasVLX, HasAVX512]
vpunpckhdq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPUNPCKHDQZ256rmkz [HasVLX, HasAVX512]
vpunpckhdq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPUNPCKHDQZ256rr [HasVLX, HasAVX512]
vpunpckhdq {src2, src1, dst|dst, src1, src2}
VPUNPCKHDQZ256rrk [HasVLX, HasAVX512]
vpunpckhdq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPUNPCKHDQZ256rrkz [HasVLX, HasAVX512]
vpunpckhdq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPUNPCKHQDQZ128rm [HasVLX, HasAVX512]
vpunpckhqdq {src2, src1, dst|dst, src1, src2}
VPUNPCKHQDQZ128rmb [HasVLX, HasAVX512]
vpunpckhqdq {src2{1to2}, src1, dst|dst, src1, src2{1to2}}
VPUNPCKHQDQZ128rmbk [HasVLX, HasAVX512]
vpunpckhqdq {src2{1to2}, src1, dst {mask}|dst {mask}, src1, src2{1to2}}
|
Note
|
Constraints: src0 = dst |
VPUNPCKHQDQZ128rmbkz [HasVLX, HasAVX512]
vpunpckhqdq {src2{1to2}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to2}}
VPUNPCKHQDQZ128rmk [HasVLX, HasAVX512]
vpunpckhqdq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPUNPCKHQDQZ128rmkz [HasVLX, HasAVX512]
vpunpckhqdq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPUNPCKHQDQZ128rr [HasVLX, HasAVX512]
vpunpckhqdq {src2, src1, dst|dst, src1, src2}
VPUNPCKHQDQZ128rrk [HasVLX, HasAVX512]
vpunpckhqdq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPUNPCKHQDQZ128rrkz [HasVLX, HasAVX512]
vpunpckhqdq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPUNPCKHQDQZ256rm [HasVLX, HasAVX512]
vpunpckhqdq {src2, src1, dst|dst, src1, src2}
VPUNPCKHQDQZ256rmb [HasVLX, HasAVX512]
vpunpckhqdq {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
VPUNPCKHQDQZ256rmbk [HasVLX, HasAVX512]
vpunpckhqdq {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Constraints: src0 = dst |
VPUNPCKHQDQZ256rmbkz [HasVLX, HasAVX512]
vpunpckhqdq {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
VPUNPCKHQDQZ256rmk [HasVLX, HasAVX512]
vpunpckhqdq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPUNPCKHQDQZ256rmkz [HasVLX, HasAVX512]
vpunpckhqdq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPUNPCKHQDQZ256rr [HasVLX, HasAVX512]
vpunpckhqdq {src2, src1, dst|dst, src1, src2}
VPUNPCKHQDQZ256rrk [HasVLX, HasAVX512]
vpunpckhqdq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPUNPCKHQDQZ256rrkz [HasVLX, HasAVX512]
vpunpckhqdq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPUNPCKLDQZ128rm [HasVLX, HasAVX512]
vpunpckldq {src2, src1, dst|dst, src1, src2}
VPUNPCKLDQZ128rmb [HasVLX, HasAVX512]
vpunpckldq {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
VPUNPCKLDQZ128rmbk [HasVLX, HasAVX512]
vpunpckldq {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Constraints: src0 = dst |
VPUNPCKLDQZ128rmbkz [HasVLX, HasAVX512]
vpunpckldq {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
VPUNPCKLDQZ128rmk [HasVLX, HasAVX512]
vpunpckldq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPUNPCKLDQZ128rmkz [HasVLX, HasAVX512]
vpunpckldq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPUNPCKLDQZ128rr [HasVLX, HasAVX512]
vpunpckldq {src2, src1, dst|dst, src1, src2}
VPUNPCKLDQZ128rrk [HasVLX, HasAVX512]
vpunpckldq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPUNPCKLDQZ128rrkz [HasVLX, HasAVX512]
vpunpckldq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPUNPCKLDQZ256rm [HasVLX, HasAVX512]
vpunpckldq {src2, src1, dst|dst, src1, src2}
VPUNPCKLDQZ256rmb [HasVLX, HasAVX512]
vpunpckldq {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
VPUNPCKLDQZ256rmbk [HasVLX, HasAVX512]
vpunpckldq {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Constraints: src0 = dst |
VPUNPCKLDQZ256rmbkz [HasVLX, HasAVX512]
vpunpckldq {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
VPUNPCKLDQZ256rmk [HasVLX, HasAVX512]
vpunpckldq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPUNPCKLDQZ256rmkz [HasVLX, HasAVX512]
vpunpckldq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPUNPCKLDQZ256rr [HasVLX, HasAVX512]
vpunpckldq {src2, src1, dst|dst, src1, src2}
VPUNPCKLDQZ256rrk [HasVLX, HasAVX512]
vpunpckldq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPUNPCKLDQZ256rrkz [HasVLX, HasAVX512]
vpunpckldq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPUNPCKLQDQZ128rm [HasVLX, HasAVX512]
vpunpcklqdq {src2, src1, dst|dst, src1, src2}
VPUNPCKLQDQZ128rmb [HasVLX, HasAVX512]
vpunpcklqdq {src2{1to2}, src1, dst|dst, src1, src2{1to2}}
VPUNPCKLQDQZ128rmbk [HasVLX, HasAVX512]
vpunpcklqdq {src2{1to2}, src1, dst {mask}|dst {mask}, src1, src2{1to2}}
|
Note
|
Constraints: src0 = dst |
VPUNPCKLQDQZ128rmbkz [HasVLX, HasAVX512]
vpunpcklqdq {src2{1to2}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to2}}
VPUNPCKLQDQZ128rmk [HasVLX, HasAVX512]
vpunpcklqdq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPUNPCKLQDQZ128rmkz [HasVLX, HasAVX512]
vpunpcklqdq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPUNPCKLQDQZ128rr [HasVLX, HasAVX512]
vpunpcklqdq {src2, src1, dst|dst, src1, src2}
VPUNPCKLQDQZ128rrk [HasVLX, HasAVX512]
vpunpcklqdq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPUNPCKLQDQZ128rrkz [HasVLX, HasAVX512]
vpunpcklqdq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPUNPCKLQDQZ256rm [HasVLX, HasAVX512]
vpunpcklqdq {src2, src1, dst|dst, src1, src2}
VPUNPCKLQDQZ256rmb [HasVLX, HasAVX512]
vpunpcklqdq {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
VPUNPCKLQDQZ256rmbk [HasVLX, HasAVX512]
vpunpcklqdq {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Constraints: src0 = dst |
VPUNPCKLQDQZ256rmbkz [HasVLX, HasAVX512]
vpunpcklqdq {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
VPUNPCKLQDQZ256rmk [HasVLX, HasAVX512]
vpunpcklqdq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPUNPCKLQDQZ256rmkz [HasVLX, HasAVX512]
vpunpcklqdq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPUNPCKLQDQZ256rr [HasVLX, HasAVX512]
vpunpcklqdq {src2, src1, dst|dst, src1, src2}
VPUNPCKLQDQZ256rrk [HasVLX, HasAVX512]
vpunpcklqdq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPUNPCKLQDQZ256rrkz [HasVLX, HasAVX512]
vpunpcklqdq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPXORDZ128rm [HasVLX, HasAVX512]
vpxord {src2, src1, dst|dst, src1, src2}
VPXORDZ128rmb [HasVLX, HasAVX512]
vpxord {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
VPXORDZ128rmbk [HasVLX, HasAVX512]
vpxord {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Constraints: src0 = dst |
VPXORDZ128rmbkz [HasVLX, HasAVX512]
vpxord {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
VPXORDZ128rmk [HasVLX, HasAVX512]
vpxord {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPXORDZ128rmkz [HasVLX, HasAVX512]
vpxord {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPXORDZ128rr [HasVLX, HasAVX512]
vpxord {src2, src1, dst|dst, src1, src2}
VPXORDZ128rrk [HasVLX, HasAVX512]
vpxord {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPXORDZ128rrkz [HasVLX, HasAVX512]
vpxord {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPXORDZ256rm [HasVLX, HasAVX512]
vpxord {src2, src1, dst|dst, src1, src2}
VPXORDZ256rmb [HasVLX, HasAVX512]
vpxord {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
VPXORDZ256rmbk [HasVLX, HasAVX512]
vpxord {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Constraints: src0 = dst |
VPXORDZ256rmbkz [HasVLX, HasAVX512]
vpxord {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
VPXORDZ256rmk [HasVLX, HasAVX512]
vpxord {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPXORDZ256rmkz [HasVLX, HasAVX512]
vpxord {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPXORDZ256rr [HasVLX, HasAVX512]
vpxord {src2, src1, dst|dst, src1, src2}
VPXORDZ256rrk [HasVLX, HasAVX512]
vpxord {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPXORDZ256rrkz [HasVLX, HasAVX512]
vpxord {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPXORQZ128rm [HasVLX, HasAVX512]
vpxorq {src2, src1, dst|dst, src1, src2}
VPXORQZ128rmb [HasVLX, HasAVX512]
vpxorq {src2{1to2}, src1, dst|dst, src1, src2{1to2}}
VPXORQZ128rmbk [HasVLX, HasAVX512]
vpxorq {src2{1to2}, src1, dst {mask}|dst {mask}, src1, src2{1to2}}
|
Note
|
Constraints: src0 = dst |
VPXORQZ128rmbkz [HasVLX, HasAVX512]
vpxorq {src2{1to2}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to2}}
VPXORQZ128rmk [HasVLX, HasAVX512]
vpxorq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPXORQZ128rmkz [HasVLX, HasAVX512]
vpxorq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPXORQZ128rr [HasVLX, HasAVX512]
vpxorq {src2, src1, dst|dst, src1, src2}
VPXORQZ128rrk [HasVLX, HasAVX512]
vpxorq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPXORQZ128rrkz [HasVLX, HasAVX512]
vpxorq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPXORQZ256rm [HasVLX, HasAVX512]
vpxorq {src2, src1, dst|dst, src1, src2}
VPXORQZ256rmb [HasVLX, HasAVX512]
vpxorq {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
VPXORQZ256rmbk [HasVLX, HasAVX512]
vpxorq {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Constraints: src0 = dst |
VPXORQZ256rmbkz [HasVLX, HasAVX512]
vpxorq {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
VPXORQZ256rmk [HasVLX, HasAVX512]
vpxorq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPXORQZ256rmkz [HasVLX, HasAVX512]
vpxorq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPXORQZ256rr [HasVLX, HasAVX512]
vpxorq {src2, src1, dst|dst, src1, src2}
VPXORQZ256rrk [HasVLX, HasAVX512]
vpxorq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPXORQZ256rrkz [HasVLX, HasAVX512]
vpxorq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VRNDSCALEPDZ128rmbi [HasVLX, HasAVX512]
vrndscalepd {src2, src1{1to2}, dst|dst, src1{1to2}, src2}
|
Note
|
Properties: mayRaiseFPException |
VRNDSCALEPDZ128rmbik [HasVLX, HasAVX512]
vrndscalepd {src2, src1{1to2}, dst {mask}|dst {mask}, src1{1to2}, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRNDSCALEPDZ128rmbikz [HasVLX, HasAVX512]
vrndscalepd {src2, src1{1to2}, dst {mask} {z}|dst {mask} {z}, src1{1to2}, src2}
|
Note
|
Properties: mayRaiseFPException |
VRNDSCALEPDZ128rmi [HasVLX, HasAVX512]
vrndscalepd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VRNDSCALEPDZ128rmik [HasVLX, HasAVX512]
vrndscalepd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRNDSCALEPDZ128rmikz [HasVLX, HasAVX512]
vrndscalepd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VRNDSCALEPDZ128rri [HasVLX, HasAVX512]
vrndscalepd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VRNDSCALEPDZ128rrik [HasVLX, HasAVX512]
vrndscalepd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRNDSCALEPDZ128rrikz [HasVLX, HasAVX512]
vrndscalepd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VRNDSCALEPDZ256rmbi [HasVLX, HasAVX512]
vrndscalepd {src2, src1{1to4}, dst|dst, src1{1to4}, src2}
|
Note
|
Properties: mayRaiseFPException |
VRNDSCALEPDZ256rmbik [HasVLX, HasAVX512]
vrndscalepd {src2, src1{1to4}, dst {mask}|dst {mask}, src1{1to4}, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRNDSCALEPDZ256rmbikz [HasVLX, HasAVX512]
vrndscalepd {src2, src1{1to4}, dst {mask} {z}|dst {mask} {z}, src1{1to4}, src2}
|
Note
|
Properties: mayRaiseFPException |
VRNDSCALEPDZ256rmi [HasVLX, HasAVX512]
vrndscalepd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VRNDSCALEPDZ256rmik [HasVLX, HasAVX512]
vrndscalepd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRNDSCALEPDZ256rmikz [HasVLX, HasAVX512]
vrndscalepd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VRNDSCALEPDZ256rri [HasVLX, HasAVX512]
vrndscalepd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VRNDSCALEPDZ256rrik [HasVLX, HasAVX512]
vrndscalepd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRNDSCALEPDZ256rrikz [HasVLX, HasAVX512]
vrndscalepd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VRNDSCALEPSZ128rmbi [HasVLX, HasAVX512]
vrndscaleps {src2, src1{1to4}, dst|dst, src1{1to4}, src2}
|
Note
|
Properties: mayRaiseFPException |
VRNDSCALEPSZ128rmbik [HasVLX, HasAVX512]
vrndscaleps {src2, src1{1to4}, dst {mask}|dst {mask}, src1{1to4}, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRNDSCALEPSZ128rmbikz [HasVLX, HasAVX512]
vrndscaleps {src2, src1{1to4}, dst {mask} {z}|dst {mask} {z}, src1{1to4}, src2}
|
Note
|
Properties: mayRaiseFPException |
VRNDSCALEPSZ128rmi [HasVLX, HasAVX512]
vrndscaleps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VRNDSCALEPSZ128rmik [HasVLX, HasAVX512]
vrndscaleps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRNDSCALEPSZ128rmikz [HasVLX, HasAVX512]
vrndscaleps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VRNDSCALEPSZ128rri [HasVLX, HasAVX512]
vrndscaleps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VRNDSCALEPSZ128rrik [HasVLX, HasAVX512]
vrndscaleps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRNDSCALEPSZ128rrikz [HasVLX, HasAVX512]
vrndscaleps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VRNDSCALEPSZ256rmbi [HasVLX, HasAVX512]
vrndscaleps {src2, src1{1to8}, dst|dst, src1{1to8}, src2}
|
Note
|
Properties: mayRaiseFPException |
VRNDSCALEPSZ256rmbik [HasVLX, HasAVX512]
vrndscaleps {src2, src1{1to8}, dst {mask}|dst {mask}, src1{1to8}, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRNDSCALEPSZ256rmbikz [HasVLX, HasAVX512]
vrndscaleps {src2, src1{1to8}, dst {mask} {z}|dst {mask} {z}, src1{1to8}, src2}
|
Note
|
Properties: mayRaiseFPException |
VRNDSCALEPSZ256rmi [HasVLX, HasAVX512]
vrndscaleps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VRNDSCALEPSZ256rmik [HasVLX, HasAVX512]
vrndscaleps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRNDSCALEPSZ256rmikz [HasVLX, HasAVX512]
vrndscaleps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VRNDSCALEPSZ256rri [HasVLX, HasAVX512]
vrndscaleps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VRNDSCALEPSZ256rrik [HasVLX, HasAVX512]
vrndscaleps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRNDSCALEPSZ256rrikz [HasVLX, HasAVX512]
vrndscaleps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSHUFF32X4Z256rmbi [HasVLX, HasAVX512]
vshuff32x4 {src3, src2{1to8}, src1, dst|dst, src1, src2{1to8}, src3}
VSHUFF32X4Z256rmbik [HasVLX, HasAVX512]
vshuff32x4 {src3, src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}, src3}
|
Note
|
Constraints: src0 = dst |
VSHUFF32X4Z256rmbikz [HasVLX, HasAVX512]
vshuff32x4 {src3, src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}, src3}
VSHUFF32X4Z256rmi [HasVLX, HasAVX512]
vshuff32x4 {src3, src2, src1, dst|dst, src1, src2, src3}
VSHUFF32X4Z256rmik [HasVLX, HasAVX512]
vshuff32x4 {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VSHUFF32X4Z256rmikz [HasVLX, HasAVX512]
vshuff32x4 {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VSHUFF32X4Z256rri [HasVLX, HasAVX512]
vshuff32x4 {src3, src2, src1, dst|dst, src1, src2, src3}
VSHUFF32X4Z256rrik [HasVLX, HasAVX512]
vshuff32x4 {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VSHUFF32X4Z256rrikz [HasVLX, HasAVX512]
vshuff32x4 {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VSHUFF64X2Z256rmbi [HasVLX, HasAVX512]
vshuff64x2 {src3, src2{1to4}, src1, dst|dst, src1, src2{1to4}, src3}
VSHUFF64X2Z256rmbik [HasVLX, HasAVX512]
vshuff64x2 {src3, src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}, src3}
|
Note
|
Constraints: src0 = dst |
VSHUFF64X2Z256rmbikz [HasVLX, HasAVX512]
vshuff64x2 {src3, src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}, src3}
VSHUFF64X2Z256rmi [HasVLX, HasAVX512]
vshuff64x2 {src3, src2, src1, dst|dst, src1, src2, src3}
VSHUFF64X2Z256rmik [HasVLX, HasAVX512]
vshuff64x2 {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VSHUFF64X2Z256rmikz [HasVLX, HasAVX512]
vshuff64x2 {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VSHUFF64X2Z256rri [HasVLX, HasAVX512]
vshuff64x2 {src3, src2, src1, dst|dst, src1, src2, src3}
VSHUFF64X2Z256rrik [HasVLX, HasAVX512]
vshuff64x2 {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VSHUFF64X2Z256rrikz [HasVLX, HasAVX512]
vshuff64x2 {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VSHUFI32X4Z256rmbi [HasVLX, HasAVX512]
vshufi32x4 {src3, src2{1to8}, src1, dst|dst, src1, src2{1to8}, src3}
VSHUFI32X4Z256rmbik [HasVLX, HasAVX512]
vshufi32x4 {src3, src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}, src3}
|
Note
|
Constraints: src0 = dst |
VSHUFI32X4Z256rmbikz [HasVLX, HasAVX512]
vshufi32x4 {src3, src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}, src3}
VSHUFI32X4Z256rmi [HasVLX, HasAVX512]
vshufi32x4 {src3, src2, src1, dst|dst, src1, src2, src3}
VSHUFI32X4Z256rmik [HasVLX, HasAVX512]
vshufi32x4 {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VSHUFI32X4Z256rmikz [HasVLX, HasAVX512]
vshufi32x4 {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VSHUFI32X4Z256rri [HasVLX, HasAVX512]
vshufi32x4 {src3, src2, src1, dst|dst, src1, src2, src3}
VSHUFI32X4Z256rrik [HasVLX, HasAVX512]
vshufi32x4 {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VSHUFI32X4Z256rrikz [HasVLX, HasAVX512]
vshufi32x4 {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VSHUFI64X2Z256rmbi [HasVLX, HasAVX512]
vshufi64x2 {src3, src2{1to4}, src1, dst|dst, src1, src2{1to4}, src3}
VSHUFI64X2Z256rmbik [HasVLX, HasAVX512]
vshufi64x2 {src3, src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}, src3}
|
Note
|
Constraints: src0 = dst |
VSHUFI64X2Z256rmbikz [HasVLX, HasAVX512]
vshufi64x2 {src3, src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}, src3}
VSHUFI64X2Z256rmi [HasVLX, HasAVX512]
vshufi64x2 {src3, src2, src1, dst|dst, src1, src2, src3}
VSHUFI64X2Z256rmik [HasVLX, HasAVX512]
vshufi64x2 {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VSHUFI64X2Z256rmikz [HasVLX, HasAVX512]
vshufi64x2 {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VSHUFI64X2Z256rri [HasVLX, HasAVX512]
vshufi64x2 {src3, src2, src1, dst|dst, src1, src2, src3}
VSHUFI64X2Z256rrik [HasVLX, HasAVX512]
vshufi64x2 {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VSHUFI64X2Z256rrikz [HasVLX, HasAVX512]
vshufi64x2 {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VSHUFPDZ128rmbi [HasVLX, HasAVX512]
vshufpd {src3, src2{1to2}, src1, dst|dst, src1, src2{1to2}, src3}
VSHUFPDZ128rmbik [HasVLX, HasAVX512]
vshufpd {src3, src2{1to2}, src1, dst {mask}|dst {mask}, src1, src2{1to2}, src3}
|
Note
|
Constraints: src0 = dst |
VSHUFPDZ128rmbikz [HasVLX, HasAVX512]
vshufpd {src3, src2{1to2}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to2}, src3}
VSHUFPDZ128rmi [HasVLX, HasAVX512]
vshufpd {src3, src2, src1, dst|dst, src1, src2, src3}
VSHUFPDZ128rmik [HasVLX, HasAVX512]
vshufpd {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VSHUFPDZ128rmikz [HasVLX, HasAVX512]
vshufpd {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VSHUFPDZ128rri [HasVLX, HasAVX512]
vshufpd {src3, src2, src1, dst|dst, src1, src2, src3}
VSHUFPDZ128rrik [HasVLX, HasAVX512]
vshufpd {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VSHUFPDZ128rrikz [HasVLX, HasAVX512]
vshufpd {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VSHUFPDZ256rmbi [HasVLX, HasAVX512]
vshufpd {src3, src2{1to4}, src1, dst|dst, src1, src2{1to4}, src3}
VSHUFPDZ256rmbik [HasVLX, HasAVX512]
vshufpd {src3, src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}, src3}
|
Note
|
Constraints: src0 = dst |
VSHUFPDZ256rmbikz [HasVLX, HasAVX512]
vshufpd {src3, src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}, src3}
VSHUFPDZ256rmi [HasVLX, HasAVX512]
vshufpd {src3, src2, src1, dst|dst, src1, src2, src3}
VSHUFPDZ256rmik [HasVLX, HasAVX512]
vshufpd {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VSHUFPDZ256rmikz [HasVLX, HasAVX512]
vshufpd {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VSHUFPDZ256rri [HasVLX, HasAVX512]
vshufpd {src3, src2, src1, dst|dst, src1, src2, src3}
VSHUFPDZ256rrik [HasVLX, HasAVX512]
vshufpd {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VSHUFPDZ256rrikz [HasVLX, HasAVX512]
vshufpd {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VSHUFPSZ128rmbi [HasVLX, HasAVX512]
vshufps {src3, src2{1to4}, src1, dst|dst, src1, src2{1to4}, src3}
VSHUFPSZ128rmbik [HasVLX, HasAVX512]
vshufps {src3, src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}, src3}
|
Note
|
Constraints: src0 = dst |
VSHUFPSZ128rmbikz [HasVLX, HasAVX512]
vshufps {src3, src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}, src3}
VSHUFPSZ128rmi [HasVLX, HasAVX512]
vshufps {src3, src2, src1, dst|dst, src1, src2, src3}
VSHUFPSZ128rmik [HasVLX, HasAVX512]
vshufps {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VSHUFPSZ128rmikz [HasVLX, HasAVX512]
vshufps {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VSHUFPSZ128rri [HasVLX, HasAVX512]
vshufps {src3, src2, src1, dst|dst, src1, src2, src3}
VSHUFPSZ128rrik [HasVLX, HasAVX512]
vshufps {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VSHUFPSZ128rrikz [HasVLX, HasAVX512]
vshufps {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VSHUFPSZ256rmbi [HasVLX, HasAVX512]
vshufps {src3, src2{1to8}, src1, dst|dst, src1, src2{1to8}, src3}
VSHUFPSZ256rmbik [HasVLX, HasAVX512]
vshufps {src3, src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}, src3}
|
Note
|
Constraints: src0 = dst |
VSHUFPSZ256rmbikz [HasVLX, HasAVX512]
vshufps {src3, src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}, src3}
VSHUFPSZ256rmi [HasVLX, HasAVX512]
vshufps {src3, src2, src1, dst|dst, src1, src2, src3}
VSHUFPSZ256rmik [HasVLX, HasAVX512]
vshufps {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VSHUFPSZ256rmikz [HasVLX, HasAVX512]
vshufps {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VSHUFPSZ256rri [HasVLX, HasAVX512]
vshufps {src3, src2, src1, dst|dst, src1, src2, src3}
VSHUFPSZ256rrik [HasVLX, HasAVX512]
vshufps {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VSHUFPSZ256rrikz [HasVLX, HasAVX512]
vshufps {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VSUBPDZ128rm [HasVLX, HasAVX512]
vsubpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VSUBPDZ128rmb [HasVLX, HasAVX512]
vsubpd {src2{1to2}, src1, dst|dst, src1, src2{1to2}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VSUBPDZ128rmbk [HasVLX, HasAVX512]
vsubpd {src2{1to2}, src1, dst {mask}|dst {mask}, src1, src2{1to2}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSUBPDZ128rmbkz [HasVLX, HasAVX512]
vsubpd {src2{1to2}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to2}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VSUBPDZ128rmk [HasVLX, HasAVX512]
vsubpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSUBPDZ128rmkz [HasVLX, HasAVX512]
vsubpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VSUBPDZ128rr [HasVLX, HasAVX512]
vsubpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSUBPDZ128rrk [HasVLX, HasAVX512]
vsubpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSUBPDZ128rrkz [HasVLX, HasAVX512]
vsubpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSUBPDZ256rm [HasVLX, HasAVX512]
vsubpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VSUBPDZ256rmb [HasVLX, HasAVX512]
vsubpd {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VSUBPDZ256rmbk [HasVLX, HasAVX512]
vsubpd {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSUBPDZ256rmbkz [HasVLX, HasAVX512]
vsubpd {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VSUBPDZ256rmk [HasVLX, HasAVX512]
vsubpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSUBPDZ256rmkz [HasVLX, HasAVX512]
vsubpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VSUBPDZ256rr [HasVLX, HasAVX512]
vsubpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSUBPDZ256rrk [HasVLX, HasAVX512]
vsubpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSUBPDZ256rrkz [HasVLX, HasAVX512]
vsubpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSUBPSZ128rm [HasVLX, HasAVX512]
vsubps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VSUBPSZ128rmb [HasVLX, HasAVX512]
vsubps {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VSUBPSZ128rmbk [HasVLX, HasAVX512]
vsubps {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSUBPSZ128rmbkz [HasVLX, HasAVX512]
vsubps {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VSUBPSZ128rmk [HasVLX, HasAVX512]
vsubps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSUBPSZ128rmkz [HasVLX, HasAVX512]
vsubps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VSUBPSZ128rr [HasVLX, HasAVX512]
vsubps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSUBPSZ128rrk [HasVLX, HasAVX512]
vsubps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSUBPSZ128rrkz [HasVLX, HasAVX512]
vsubps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSUBPSZ256rm [HasVLX, HasAVX512]
vsubps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VSUBPSZ256rmb [HasVLX, HasAVX512]
vsubps {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VSUBPSZ256rmbk [HasVLX, HasAVX512]
vsubps {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSUBPSZ256rmbkz [HasVLX, HasAVX512]
vsubps {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VSUBPSZ256rmk [HasVLX, HasAVX512]
vsubps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSUBPSZ256rmkz [HasVLX, HasAVX512]
vsubps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VSUBPSZ256rr [HasVLX, HasAVX512]
vsubps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSUBPSZ256rrk [HasVLX, HasAVX512]
vsubps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSUBPSZ256rrkz [HasVLX, HasAVX512]
vsubps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VUNPCKHPDZ128rm [HasVLX, HasAVX512]
vunpckhpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VUNPCKHPDZ128rmb [HasVLX, HasAVX512]
vunpckhpd {src2{1to2}, src1, dst|dst, src1, src2{1to2}}
|
Note
|
Properties: mayLoad |
VUNPCKHPDZ128rmbk [HasVLX, HasAVX512]
vunpckhpd {src2{1to2}, src1, dst {mask}|dst {mask}, src1, src2{1to2}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VUNPCKHPDZ128rmbkz [HasVLX, HasAVX512]
vunpckhpd {src2{1to2}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to2}}
|
Note
|
Properties: mayLoad |
VUNPCKHPDZ128rmk [HasVLX, HasAVX512]
vunpckhpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VUNPCKHPDZ128rmkz [HasVLX, HasAVX512]
vunpckhpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VUNPCKHPDZ128rr [HasVLX, HasAVX512]
vunpckhpd {src2, src1, dst|dst, src1, src2}
VUNPCKHPDZ128rrk [HasVLX, HasAVX512]
vunpckhpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VUNPCKHPDZ128rrkz [HasVLX, HasAVX512]
vunpckhpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VUNPCKHPDZ256rm [HasVLX, HasAVX512]
vunpckhpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VUNPCKHPDZ256rmb [HasVLX, HasAVX512]
vunpckhpd {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
|
Note
|
Properties: mayLoad |
VUNPCKHPDZ256rmbk [HasVLX, HasAVX512]
vunpckhpd {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VUNPCKHPDZ256rmbkz [HasVLX, HasAVX512]
vunpckhpd {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
|
Note
|
Properties: mayLoad |
VUNPCKHPDZ256rmk [HasVLX, HasAVX512]
vunpckhpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VUNPCKHPDZ256rmkz [HasVLX, HasAVX512]
vunpckhpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VUNPCKHPDZ256rr [HasVLX, HasAVX512]
vunpckhpd {src2, src1, dst|dst, src1, src2}
VUNPCKHPDZ256rrk [HasVLX, HasAVX512]
vunpckhpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VUNPCKHPDZ256rrkz [HasVLX, HasAVX512]
vunpckhpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VUNPCKHPSZ128rm [HasVLX, HasAVX512]
vunpckhps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VUNPCKHPSZ128rmb [HasVLX, HasAVX512]
vunpckhps {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
|
Note
|
Properties: mayLoad |
VUNPCKHPSZ128rmbk [HasVLX, HasAVX512]
vunpckhps {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VUNPCKHPSZ128rmbkz [HasVLX, HasAVX512]
vunpckhps {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
|
Note
|
Properties: mayLoad |
VUNPCKHPSZ128rmk [HasVLX, HasAVX512]
vunpckhps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VUNPCKHPSZ128rmkz [HasVLX, HasAVX512]
vunpckhps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VUNPCKHPSZ128rr [HasVLX, HasAVX512]
vunpckhps {src2, src1, dst|dst, src1, src2}
VUNPCKHPSZ128rrk [HasVLX, HasAVX512]
vunpckhps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VUNPCKHPSZ128rrkz [HasVLX, HasAVX512]
vunpckhps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VUNPCKHPSZ256rm [HasVLX, HasAVX512]
vunpckhps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VUNPCKHPSZ256rmb [HasVLX, HasAVX512]
vunpckhps {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
VUNPCKHPSZ256rmbk [HasVLX, HasAVX512]
vunpckhps {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VUNPCKHPSZ256rmbkz [HasVLX, HasAVX512]
vunpckhps {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
VUNPCKHPSZ256rmk [HasVLX, HasAVX512]
vunpckhps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VUNPCKHPSZ256rmkz [HasVLX, HasAVX512]
vunpckhps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VUNPCKHPSZ256rr [HasVLX, HasAVX512]
vunpckhps {src2, src1, dst|dst, src1, src2}
VUNPCKHPSZ256rrk [HasVLX, HasAVX512]
vunpckhps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VUNPCKHPSZ256rrkz [HasVLX, HasAVX512]
vunpckhps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VUNPCKLPDZ128rm [HasVLX, HasAVX512]
vunpcklpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VUNPCKLPDZ128rmb [HasVLX, HasAVX512]
vunpcklpd {src2{1to2}, src1, dst|dst, src1, src2{1to2}}
|
Note
|
Properties: mayLoad |
VUNPCKLPDZ128rmbk [HasVLX, HasAVX512]
vunpcklpd {src2{1to2}, src1, dst {mask}|dst {mask}, src1, src2{1to2}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VUNPCKLPDZ128rmbkz [HasVLX, HasAVX512]
vunpcklpd {src2{1to2}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to2}}
|
Note
|
Properties: mayLoad |
VUNPCKLPDZ128rmk [HasVLX, HasAVX512]
vunpcklpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VUNPCKLPDZ128rmkz [HasVLX, HasAVX512]
vunpcklpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VUNPCKLPDZ128rr [HasVLX, HasAVX512]
vunpcklpd {src2, src1, dst|dst, src1, src2}
VUNPCKLPDZ128rrk [HasVLX, HasAVX512]
vunpcklpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VUNPCKLPDZ128rrkz [HasVLX, HasAVX512]
vunpcklpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VUNPCKLPDZ256rm [HasVLX, HasAVX512]
vunpcklpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VUNPCKLPDZ256rmb [HasVLX, HasAVX512]
vunpcklpd {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
|
Note
|
Properties: mayLoad |
VUNPCKLPDZ256rmbk [HasVLX, HasAVX512]
vunpcklpd {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VUNPCKLPDZ256rmbkz [HasVLX, HasAVX512]
vunpcklpd {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
|
Note
|
Properties: mayLoad |
VUNPCKLPDZ256rmk [HasVLX, HasAVX512]
vunpcklpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VUNPCKLPDZ256rmkz [HasVLX, HasAVX512]
vunpcklpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VUNPCKLPDZ256rr [HasVLX, HasAVX512]
vunpcklpd {src2, src1, dst|dst, src1, src2}
VUNPCKLPDZ256rrk [HasVLX, HasAVX512]
vunpcklpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VUNPCKLPDZ256rrkz [HasVLX, HasAVX512]
vunpcklpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VUNPCKLPSZ128rm [HasVLX, HasAVX512]
vunpcklps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VUNPCKLPSZ128rmb [HasVLX, HasAVX512]
vunpcklps {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
|
Note
|
Properties: mayLoad |
VUNPCKLPSZ128rmbk [HasVLX, HasAVX512]
vunpcklps {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VUNPCKLPSZ128rmbkz [HasVLX, HasAVX512]
vunpcklps {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
|
Note
|
Properties: mayLoad |
VUNPCKLPSZ128rmk [HasVLX, HasAVX512]
vunpcklps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VUNPCKLPSZ128rmkz [HasVLX, HasAVX512]
vunpcklps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VUNPCKLPSZ128rr [HasVLX, HasAVX512]
vunpcklps {src2, src1, dst|dst, src1, src2}
VUNPCKLPSZ128rrk [HasVLX, HasAVX512]
vunpcklps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VUNPCKLPSZ128rrkz [HasVLX, HasAVX512]
vunpcklps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VUNPCKLPSZ256rm [HasVLX, HasAVX512]
vunpcklps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VUNPCKLPSZ256rmb [HasVLX, HasAVX512]
vunpcklps {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
VUNPCKLPSZ256rmbk [HasVLX, HasAVX512]
vunpcklps {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VUNPCKLPSZ256rmbkz [HasVLX, HasAVX512]
vunpcklps {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
VUNPCKLPSZ256rmk [HasVLX, HasAVX512]
vunpcklps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VUNPCKLPSZ256rmkz [HasVLX, HasAVX512]
vunpcklps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VUNPCKLPSZ256rr [HasVLX, HasAVX512]
vunpcklps {src2, src1, dst|dst, src1, src2}
VUNPCKLPSZ256rrk [HasVLX, HasAVX512]
vunpcklps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VUNPCKLPSZ256rrkz [HasVLX, HasAVX512]
vunpcklps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VP2INTERSECTDZ128rm [HasVLX, HasAVX512, HasVP2INTERSECT]
vp2intersectd {src2, src1, dst|dst, src1, src2}
VP2INTERSECTDZ128rmb [HasVLX, HasAVX512, HasVP2INTERSECT]
vp2intersectd {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
VP2INTERSECTDZ128rr [HasVLX, HasAVX512, HasVP2INTERSECT]
vp2intersectd {src2, src1, dst|dst, src1, src2}
VP2INTERSECTDZ256rm [HasVLX, HasAVX512, HasVP2INTERSECT]
vp2intersectd {src2, src1, dst|dst, src1, src2}
VP2INTERSECTDZ256rmb [HasVLX, HasAVX512, HasVP2INTERSECT]
vp2intersectd {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
VP2INTERSECTDZ256rr [HasVLX, HasAVX512, HasVP2INTERSECT]
vp2intersectd {src2, src1, dst|dst, src1, src2}
VP2INTERSECTQZ128rm [HasVLX, HasAVX512, HasVP2INTERSECT]
vp2intersectq {src2, src1, dst|dst, src1, src2}
VP2INTERSECTQZ128rmb [HasVLX, HasAVX512, HasVP2INTERSECT]
vp2intersectq {src2{1to2}, src1, dst|dst, src1, src2{1to2}}
VP2INTERSECTQZ128rr [HasVLX, HasAVX512, HasVP2INTERSECT]
vp2intersectq {src2, src1, dst|dst, src1, src2}
VP2INTERSECTQZ256rm [HasVLX, HasAVX512, HasVP2INTERSECT]
vp2intersectq {src2, src1, dst|dst, src1, src2}
VP2INTERSECTQZ256rmb [HasVLX, HasAVX512, HasVP2INTERSECT]
vp2intersectq {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
VP2INTERSECTQZ256rr [HasVLX, HasAVX512, HasVP2INTERSECT]
vp2intersectq {src2, src1, dst|dst, src1, src2}
VADDPHZ128rm [HasVLX, HasFP16]
vaddph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VADDPHZ128rmb [HasVLX, HasFP16]
vaddph {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VADDPHZ128rmbk [HasVLX, HasFP16]
vaddph {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VADDPHZ128rmbkz [HasVLX, HasFP16]
vaddph {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VADDPHZ128rmk [HasVLX, HasFP16]
vaddph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VADDPHZ128rmkz [HasVLX, HasFP16]
vaddph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VADDPHZ128rr [HasVLX, HasFP16]
vaddph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VADDPHZ128rrk [HasVLX, HasFP16]
vaddph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VADDPHZ128rrkz [HasVLX, HasFP16]
vaddph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VADDPHZ256rm [HasVLX, HasFP16]
vaddph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VADDPHZ256rmb [HasVLX, HasFP16]
vaddph {src2{1to16}, src1, dst|dst, src1, src2{1to16}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VADDPHZ256rmbk [HasVLX, HasFP16]
vaddph {src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VADDPHZ256rmbkz [HasVLX, HasFP16]
vaddph {src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VADDPHZ256rmk [HasVLX, HasFP16]
vaddph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VADDPHZ256rmkz [HasVLX, HasFP16]
vaddph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VADDPHZ256rr [HasVLX, HasFP16]
vaddph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VADDPHZ256rrk [HasVLX, HasFP16]
vaddph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VADDPHZ256rrkz [HasVLX, HasFP16]
vaddph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VCMPPHZ128rmbi [HasVLX, HasFP16]
vcmpph {cc, src2{1to8}, src1, dst|dst, src1, src2{1to8}, cc}
|
Note
|
Properties: mayRaiseFPException |
VCMPPHZ128rmbik [HasVLX, HasFP16]
vcmpph {cc, src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}, cc}
|
Note
|
Properties: mayRaiseFPException |
VCMPPHZ128rmi [HasVLX, HasFP16]
vcmpph {cc, src2, src1, dst|dst, src1, src2, cc}
|
Note
|
Properties: mayRaiseFPException |
VCMPPHZ128rmik [HasVLX, HasFP16]
vcmpph {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
|
Note
|
Properties: mayRaiseFPException |
VCMPPHZ128rri [HasVLX, HasFP16]
vcmpph {cc, src2, src1, dst|dst, src1, src2, cc}
|
Note
|
Properties: mayRaiseFPException |
VCMPPHZ128rrik [HasVLX, HasFP16]
vcmpph {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
|
Note
|
Properties: mayRaiseFPException |
VCMPPHZ256rmbi [HasVLX, HasFP16]
vcmpph {cc, src2{1to16}, src1, dst|dst, src1, src2{1to16}, cc}
|
Note
|
Properties: mayRaiseFPException |
VCMPPHZ256rmbik [HasVLX, HasFP16]
vcmpph {cc, src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}, cc}
|
Note
|
Properties: mayRaiseFPException |
VCMPPHZ256rmi [HasVLX, HasFP16]
vcmpph {cc, src2, src1, dst|dst, src1, src2, cc}
|
Note
|
Properties: mayRaiseFPException |
VCMPPHZ256rmik [HasVLX, HasFP16]
vcmpph {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
|
Note
|
Properties: mayRaiseFPException |
VCMPPHZ256rri [HasVLX, HasFP16]
vcmpph {cc, src2, src1, dst|dst, src1, src2, cc}
|
Note
|
Properties: mayRaiseFPException |
VCMPPHZ256rrik [HasVLX, HasFP16]
vcmpph {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
|
Note
|
Properties: mayRaiseFPException |
VCVTDQ2PHZ128rm [HasVLX, HasFP16]
vcvtdq2ph{x} {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTDQ2PHZ128rmb [HasVLX, HasFP16]
vcvtdq2ph {src{1to4}, dst|dst, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTDQ2PHZ128rmbk [HasVLX, HasFP16]
vcvtdq2ph {src{1to4}, dst {mask}|dst {mask}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTDQ2PHZ128rmbkz [HasVLX, HasFP16]
vcvtdq2ph {src{1to4}, dst {mask} {z}|dst {mask} {z}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTDQ2PHZ128rmk [HasVLX, HasFP16]
vcvtdq2ph{x} {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTDQ2PHZ128rmkz [HasVLX, HasFP16]
vcvtdq2ph{x} {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTDQ2PHZ128rr [HasVLX, HasFP16]
vcvtdq2ph {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTDQ2PHZ128rrk [HasVLX, HasFP16]
vcvtdq2ph {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTDQ2PHZ128rrkz [HasVLX, HasFP16]
vcvtdq2ph {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTDQ2PHZ256rm [HasVLX, HasFP16]
vcvtdq2ph{y} {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTDQ2PHZ256rmb [HasVLX, HasFP16]
vcvtdq2ph {src{1to8}, dst|dst, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTDQ2PHZ256rmbk [HasVLX, HasFP16]
vcvtdq2ph {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTDQ2PHZ256rmbkz [HasVLX, HasFP16]
vcvtdq2ph {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTDQ2PHZ256rmk [HasVLX, HasFP16]
vcvtdq2ph{y} {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTDQ2PHZ256rmkz [HasVLX, HasFP16]
vcvtdq2ph{y} {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTDQ2PHZ256rr [HasVLX, HasFP16]
vcvtdq2ph {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTDQ2PHZ256rrk [HasVLX, HasFP16]
vcvtdq2ph {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTDQ2PHZ256rrkz [HasVLX, HasFP16]
vcvtdq2ph {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2PHZ128rm [HasVLX, HasFP16]
vcvtpd2ph{x} {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2PHZ128rmb [HasVLX, HasFP16]
vcvtpd2ph {src{1to2}, dst|dst, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2PHZ128rmbk [HasVLX, HasFP16]
vcvtpd2ph {src{1to2}, dst {mask}|dst {mask}, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPD2PHZ128rmbkz [HasVLX, HasFP16]
vcvtpd2ph {src{1to2}, dst {mask} {z}|dst {mask} {z}, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2PHZ128rmk [HasVLX, HasFP16]
vcvtpd2ph{x} {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPD2PHZ128rmkz [HasVLX, HasFP16]
vcvtpd2ph{x} {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2PHZ128rr [HasVLX, HasFP16]
vcvtpd2ph {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2PHZ128rrk [HasVLX, HasFP16]
vcvtpd2ph {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPD2PHZ128rrkz [HasVLX, HasFP16]
vcvtpd2ph {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2PHZ256rm [HasVLX, HasFP16]
vcvtpd2ph{y} {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2PHZ256rmb [HasVLX, HasFP16]
vcvtpd2ph {src{1to4}, dst|dst, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2PHZ256rmbk [HasVLX, HasFP16]
vcvtpd2ph {src{1to4}, dst {mask}|dst {mask}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPD2PHZ256rmbkz [HasVLX, HasFP16]
vcvtpd2ph {src{1to4}, dst {mask} {z}|dst {mask} {z}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2PHZ256rmk [HasVLX, HasFP16]
vcvtpd2ph{y} {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPD2PHZ256rmkz [HasVLX, HasFP16]
vcvtpd2ph{y} {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2PHZ256rr [HasVLX, HasFP16]
vcvtpd2ph {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2PHZ256rrk [HasVLX, HasFP16]
vcvtpd2ph {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPD2PHZ256rrkz [HasVLX, HasFP16]
vcvtpd2ph {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2DQZ128rm [HasVLX, HasFP16]
vcvtph2dq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2DQZ128rmb [HasVLX, HasFP16]
vcvtph2dq {src{1to4}, dst|dst, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2DQZ128rmbk [HasVLX, HasFP16]
vcvtph2dq {src{1to4}, dst {mask}|dst {mask}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2DQZ128rmbkz [HasVLX, HasFP16]
vcvtph2dq {src{1to4}, dst {mask} {z}|dst {mask} {z}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2DQZ128rmk [HasVLX, HasFP16]
vcvtph2dq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2DQZ128rmkz [HasVLX, HasFP16]
vcvtph2dq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2DQZ128rr [HasVLX, HasFP16]
vcvtph2dq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2DQZ128rrk [HasVLX, HasFP16]
vcvtph2dq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2DQZ128rrkz [HasVLX, HasFP16]
vcvtph2dq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2DQZ256rm [HasVLX, HasFP16]
vcvtph2dq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2DQZ256rmb [HasVLX, HasFP16]
vcvtph2dq {src{1to8}, dst|dst, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2DQZ256rmbk [HasVLX, HasFP16]
vcvtph2dq {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2DQZ256rmbkz [HasVLX, HasFP16]
vcvtph2dq {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2DQZ256rmk [HasVLX, HasFP16]
vcvtph2dq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2DQZ256rmkz [HasVLX, HasFP16]
vcvtph2dq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2DQZ256rr [HasVLX, HasFP16]
vcvtph2dq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2DQZ256rrk [HasVLX, HasFP16]
vcvtph2dq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2DQZ256rrkz [HasVLX, HasFP16]
vcvtph2dq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2PDZ128rm [HasVLX, HasFP16]
vcvtph2pd {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2PDZ128rmb [HasVLX, HasFP16]
vcvtph2pd {src{1to2}, dst|dst, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2PDZ128rmbk [HasVLX, HasFP16]
vcvtph2pd {src{1to2}, dst {mask}|dst {mask}, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2PDZ128rmbkz [HasVLX, HasFP16]
vcvtph2pd {src{1to2}, dst {mask} {z}|dst {mask} {z}, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2PDZ128rmk [HasVLX, HasFP16]
vcvtph2pd {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2PDZ128rmkz [HasVLX, HasFP16]
vcvtph2pd {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2PDZ128rr [HasVLX, HasFP16]
vcvtph2pd {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2PDZ128rrk [HasVLX, HasFP16]
vcvtph2pd {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2PDZ128rrkz [HasVLX, HasFP16]
vcvtph2pd {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2PDZ256rm [HasVLX, HasFP16]
vcvtph2pd {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2PDZ256rmb [HasVLX, HasFP16]
vcvtph2pd {src{1to4}, dst|dst, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2PDZ256rmbk [HasVLX, HasFP16]
vcvtph2pd {src{1to4}, dst {mask}|dst {mask}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2PDZ256rmbkz [HasVLX, HasFP16]
vcvtph2pd {src{1to4}, dst {mask} {z}|dst {mask} {z}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2PDZ256rmk [HasVLX, HasFP16]
vcvtph2pd {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2PDZ256rmkz [HasVLX, HasFP16]
vcvtph2pd {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2PDZ256rr [HasVLX, HasFP16]
vcvtph2pd {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2PDZ256rrk [HasVLX, HasFP16]
vcvtph2pd {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2PDZ256rrkz [HasVLX, HasFP16]
vcvtph2pd {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2PSXZ128rm [HasVLX, HasFP16]
vcvtph2psx {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2PSXZ128rmb [HasVLX, HasFP16]
vcvtph2psx {src{1to4}, dst|dst, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2PSXZ128rmbk [HasVLX, HasFP16]
vcvtph2psx {src{1to4}, dst {mask}|dst {mask}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2PSXZ128rmbkz [HasVLX, HasFP16]
vcvtph2psx {src{1to4}, dst {mask} {z}|dst {mask} {z}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2PSXZ128rmk [HasVLX, HasFP16]
vcvtph2psx {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2PSXZ128rmkz [HasVLX, HasFP16]
vcvtph2psx {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2PSXZ128rr [HasVLX, HasFP16]
vcvtph2psx {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2PSXZ128rrk [HasVLX, HasFP16]
vcvtph2psx {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2PSXZ128rrkz [HasVLX, HasFP16]
vcvtph2psx {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2PSXZ256rm [HasVLX, HasFP16]
vcvtph2psx {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2PSXZ256rmb [HasVLX, HasFP16]
vcvtph2psx {src{1to8}, dst|dst, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2PSXZ256rmbk [HasVLX, HasFP16]
vcvtph2psx {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2PSXZ256rmbkz [HasVLX, HasFP16]
vcvtph2psx {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2PSXZ256rmk [HasVLX, HasFP16]
vcvtph2psx {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2PSXZ256rmkz [HasVLX, HasFP16]
vcvtph2psx {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2PSXZ256rr [HasVLX, HasFP16]
vcvtph2psx {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2PSXZ256rrk [HasVLX, HasFP16]
vcvtph2psx {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2PSXZ256rrkz [HasVLX, HasFP16]
vcvtph2psx {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2QQZ128rm [HasVLX, HasFP16]
vcvtph2qq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2QQZ128rmb [HasVLX, HasFP16]
vcvtph2qq {src{1to2}, dst|dst, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2QQZ128rmbk [HasVLX, HasFP16]
vcvtph2qq {src{1to2}, dst {mask}|dst {mask}, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2QQZ128rmbkz [HasVLX, HasFP16]
vcvtph2qq {src{1to2}, dst {mask} {z}|dst {mask} {z}, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2QQZ128rmk [HasVLX, HasFP16]
vcvtph2qq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2QQZ128rmkz [HasVLX, HasFP16]
vcvtph2qq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2QQZ128rr [HasVLX, HasFP16]
vcvtph2qq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2QQZ128rrk [HasVLX, HasFP16]
vcvtph2qq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2QQZ128rrkz [HasVLX, HasFP16]
vcvtph2qq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2QQZ256rm [HasVLX, HasFP16]
vcvtph2qq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2QQZ256rmb [HasVLX, HasFP16]
vcvtph2qq {src{1to4}, dst|dst, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2QQZ256rmbk [HasVLX, HasFP16]
vcvtph2qq {src{1to4}, dst {mask}|dst {mask}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2QQZ256rmbkz [HasVLX, HasFP16]
vcvtph2qq {src{1to4}, dst {mask} {z}|dst {mask} {z}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2QQZ256rmk [HasVLX, HasFP16]
vcvtph2qq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2QQZ256rmkz [HasVLX, HasFP16]
vcvtph2qq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2QQZ256rr [HasVLX, HasFP16]
vcvtph2qq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2QQZ256rrk [HasVLX, HasFP16]
vcvtph2qq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2QQZ256rrkz [HasVLX, HasFP16]
vcvtph2qq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2UDQZ128rm [HasVLX, HasFP16]
vcvtph2udq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2UDQZ128rmb [HasVLX, HasFP16]
vcvtph2udq {src{1to4}, dst|dst, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2UDQZ128rmbk [HasVLX, HasFP16]
vcvtph2udq {src{1to4}, dst {mask}|dst {mask}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2UDQZ128rmbkz [HasVLX, HasFP16]
vcvtph2udq {src{1to4}, dst {mask} {z}|dst {mask} {z}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2UDQZ128rmk [HasVLX, HasFP16]
vcvtph2udq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2UDQZ128rmkz [HasVLX, HasFP16]
vcvtph2udq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2UDQZ128rr [HasVLX, HasFP16]
vcvtph2udq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2UDQZ128rrk [HasVLX, HasFP16]
vcvtph2udq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2UDQZ128rrkz [HasVLX, HasFP16]
vcvtph2udq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2UDQZ256rm [HasVLX, HasFP16]
vcvtph2udq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2UDQZ256rmb [HasVLX, HasFP16]
vcvtph2udq {src{1to8}, dst|dst, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2UDQZ256rmbk [HasVLX, HasFP16]
vcvtph2udq {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2UDQZ256rmbkz [HasVLX, HasFP16]
vcvtph2udq {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2UDQZ256rmk [HasVLX, HasFP16]
vcvtph2udq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2UDQZ256rmkz [HasVLX, HasFP16]
vcvtph2udq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2UDQZ256rr [HasVLX, HasFP16]
vcvtph2udq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2UDQZ256rrk [HasVLX, HasFP16]
vcvtph2udq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2UDQZ256rrkz [HasVLX, HasFP16]
vcvtph2udq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2UQQZ128rm [HasVLX, HasFP16]
vcvtph2uqq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2UQQZ128rmb [HasVLX, HasFP16]
vcvtph2uqq {src{1to2}, dst|dst, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2UQQZ128rmbk [HasVLX, HasFP16]
vcvtph2uqq {src{1to2}, dst {mask}|dst {mask}, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2UQQZ128rmbkz [HasVLX, HasFP16]
vcvtph2uqq {src{1to2}, dst {mask} {z}|dst {mask} {z}, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2UQQZ128rmk [HasVLX, HasFP16]
vcvtph2uqq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2UQQZ128rmkz [HasVLX, HasFP16]
vcvtph2uqq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2UQQZ128rr [HasVLX, HasFP16]
vcvtph2uqq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2UQQZ128rrk [HasVLX, HasFP16]
vcvtph2uqq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2UQQZ128rrkz [HasVLX, HasFP16]
vcvtph2uqq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2UQQZ256rm [HasVLX, HasFP16]
vcvtph2uqq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2UQQZ256rmb [HasVLX, HasFP16]
vcvtph2uqq {src{1to4}, dst|dst, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2UQQZ256rmbk [HasVLX, HasFP16]
vcvtph2uqq {src{1to4}, dst {mask}|dst {mask}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2UQQZ256rmbkz [HasVLX, HasFP16]
vcvtph2uqq {src{1to4}, dst {mask} {z}|dst {mask} {z}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2UQQZ256rmk [HasVLX, HasFP16]
vcvtph2uqq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2UQQZ256rmkz [HasVLX, HasFP16]
vcvtph2uqq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2UQQZ256rr [HasVLX, HasFP16]
vcvtph2uqq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2UQQZ256rrk [HasVLX, HasFP16]
vcvtph2uqq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2UQQZ256rrkz [HasVLX, HasFP16]
vcvtph2uqq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2UWZ128rm [HasVLX, HasFP16]
vcvtph2uw {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2UWZ128rmb [HasVLX, HasFP16]
vcvtph2uw {src{1to8}, dst|dst, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2UWZ128rmbk [HasVLX, HasFP16]
vcvtph2uw {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2UWZ128rmbkz [HasVLX, HasFP16]
vcvtph2uw {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2UWZ128rmk [HasVLX, HasFP16]
vcvtph2uw {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2UWZ128rmkz [HasVLX, HasFP16]
vcvtph2uw {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2UWZ128rr [HasVLX, HasFP16]
vcvtph2uw {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2UWZ128rrk [HasVLX, HasFP16]
vcvtph2uw {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2UWZ128rrkz [HasVLX, HasFP16]
vcvtph2uw {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2UWZ256rm [HasVLX, HasFP16]
vcvtph2uw {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2UWZ256rmb [HasVLX, HasFP16]
vcvtph2uw {src{1to16}, dst|dst, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2UWZ256rmbk [HasVLX, HasFP16]
vcvtph2uw {src{1to16}, dst {mask}|dst {mask}, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2UWZ256rmbkz [HasVLX, HasFP16]
vcvtph2uw {src{1to16}, dst {mask} {z}|dst {mask} {z}, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2UWZ256rmk [HasVLX, HasFP16]
vcvtph2uw {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2UWZ256rmkz [HasVLX, HasFP16]
vcvtph2uw {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2UWZ256rr [HasVLX, HasFP16]
vcvtph2uw {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2UWZ256rrk [HasVLX, HasFP16]
vcvtph2uw {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2UWZ256rrkz [HasVLX, HasFP16]
vcvtph2uw {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2WZ128rm [HasVLX, HasFP16]
vcvtph2w {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2WZ128rmb [HasVLX, HasFP16]
vcvtph2w {src{1to8}, dst|dst, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2WZ128rmbk [HasVLX, HasFP16]
vcvtph2w {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2WZ128rmbkz [HasVLX, HasFP16]
vcvtph2w {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2WZ128rmk [HasVLX, HasFP16]
vcvtph2w {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2WZ128rmkz [HasVLX, HasFP16]
vcvtph2w {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2WZ128rr [HasVLX, HasFP16]
vcvtph2w {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2WZ128rrk [HasVLX, HasFP16]
vcvtph2w {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2WZ128rrkz [HasVLX, HasFP16]
vcvtph2w {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2WZ256rm [HasVLX, HasFP16]
vcvtph2w {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2WZ256rmb [HasVLX, HasFP16]
vcvtph2w {src{1to16}, dst|dst, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2WZ256rmbk [HasVLX, HasFP16]
vcvtph2w {src{1to16}, dst {mask}|dst {mask}, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2WZ256rmbkz [HasVLX, HasFP16]
vcvtph2w {src{1to16}, dst {mask} {z}|dst {mask} {z}, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2WZ256rmk [HasVLX, HasFP16]
vcvtph2w {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2WZ256rmkz [HasVLX, HasFP16]
vcvtph2w {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2WZ256rr [HasVLX, HasFP16]
vcvtph2w {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2WZ256rrk [HasVLX, HasFP16]
vcvtph2w {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2WZ256rrkz [HasVLX, HasFP16]
vcvtph2w {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2PHXZ128rm [HasVLX, HasFP16]
vcvtps2phx{x} {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2PHXZ128rmb [HasVLX, HasFP16]
vcvtps2phx {src{1to4}, dst|dst, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2PHXZ128rmbk [HasVLX, HasFP16]
vcvtps2phx {src{1to4}, dst {mask}|dst {mask}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPS2PHXZ128rmbkz [HasVLX, HasFP16]
vcvtps2phx {src{1to4}, dst {mask} {z}|dst {mask} {z}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2PHXZ128rmk [HasVLX, HasFP16]
vcvtps2phx{x} {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPS2PHXZ128rmkz [HasVLX, HasFP16]
vcvtps2phx{x} {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2PHXZ128rr [HasVLX, HasFP16]
vcvtps2phx {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2PHXZ128rrk [HasVLX, HasFP16]
vcvtps2phx {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPS2PHXZ128rrkz [HasVLX, HasFP16]
vcvtps2phx {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2PHXZ256rm [HasVLX, HasFP16]
vcvtps2phx{y} {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2PHXZ256rmb [HasVLX, HasFP16]
vcvtps2phx {src{1to8}, dst|dst, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2PHXZ256rmbk [HasVLX, HasFP16]
vcvtps2phx {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPS2PHXZ256rmbkz [HasVLX, HasFP16]
vcvtps2phx {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2PHXZ256rmk [HasVLX, HasFP16]
vcvtps2phx{y} {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPS2PHXZ256rmkz [HasVLX, HasFP16]
vcvtps2phx{y} {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2PHXZ256rr [HasVLX, HasFP16]
vcvtps2phx {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2PHXZ256rrk [HasVLX, HasFP16]
vcvtps2phx {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPS2PHXZ256rrkz [HasVLX, HasFP16]
vcvtps2phx {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTQQ2PHZ128rm [HasVLX, HasFP16]
vcvtqq2ph{x} {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTQQ2PHZ128rmb [HasVLX, HasFP16]
vcvtqq2ph {src{1to2}, dst|dst, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
VCVTQQ2PHZ128rmbk [HasVLX, HasFP16]
vcvtqq2ph {src{1to2}, dst {mask}|dst {mask}, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTQQ2PHZ128rmbkz [HasVLX, HasFP16]
vcvtqq2ph {src{1to2}, dst {mask} {z}|dst {mask} {z}, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
VCVTQQ2PHZ128rmk [HasVLX, HasFP16]
vcvtqq2ph{x} {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTQQ2PHZ128rmkz [HasVLX, HasFP16]
vcvtqq2ph{x} {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTQQ2PHZ128rr [HasVLX, HasFP16]
vcvtqq2ph {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTQQ2PHZ128rrk [HasVLX, HasFP16]
vcvtqq2ph {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTQQ2PHZ128rrkz [HasVLX, HasFP16]
vcvtqq2ph {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTQQ2PHZ256rm [HasVLX, HasFP16]
vcvtqq2ph{y} {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTQQ2PHZ256rmb [HasVLX, HasFP16]
vcvtqq2ph {src{1to4}, dst|dst, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTQQ2PHZ256rmbk [HasVLX, HasFP16]
vcvtqq2ph {src{1to4}, dst {mask}|dst {mask}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTQQ2PHZ256rmbkz [HasVLX, HasFP16]
vcvtqq2ph {src{1to4}, dst {mask} {z}|dst {mask} {z}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTQQ2PHZ256rmk [HasVLX, HasFP16]
vcvtqq2ph{y} {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTQQ2PHZ256rmkz [HasVLX, HasFP16]
vcvtqq2ph{y} {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTQQ2PHZ256rr [HasVLX, HasFP16]
vcvtqq2ph {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTQQ2PHZ256rrk [HasVLX, HasFP16]
vcvtqq2ph {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTQQ2PHZ256rrkz [HasVLX, HasFP16]
vcvtqq2ph {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2DQZ128rm [HasVLX, HasFP16]
vcvttph2dq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2DQZ128rmb [HasVLX, HasFP16]
vcvttph2dq {src{1to4}, dst|dst, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2DQZ128rmbk [HasVLX, HasFP16]
vcvttph2dq {src{1to4}, dst {mask}|dst {mask}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPH2DQZ128rmbkz [HasVLX, HasFP16]
vcvttph2dq {src{1to4}, dst {mask} {z}|dst {mask} {z}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2DQZ128rmk [HasVLX, HasFP16]
vcvttph2dq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPH2DQZ128rmkz [HasVLX, HasFP16]
vcvttph2dq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2DQZ128rr [HasVLX, HasFP16]
vcvttph2dq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2DQZ128rrk [HasVLX, HasFP16]
vcvttph2dq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPH2DQZ128rrkz [HasVLX, HasFP16]
vcvttph2dq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2DQZ256rm [HasVLX, HasFP16]
vcvttph2dq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2DQZ256rmb [HasVLX, HasFP16]
vcvttph2dq {src{1to8}, dst|dst, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2DQZ256rmbk [HasVLX, HasFP16]
vcvttph2dq {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPH2DQZ256rmbkz [HasVLX, HasFP16]
vcvttph2dq {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2DQZ256rmk [HasVLX, HasFP16]
vcvttph2dq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPH2DQZ256rmkz [HasVLX, HasFP16]
vcvttph2dq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2DQZ256rr [HasVLX, HasFP16]
vcvttph2dq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2DQZ256rrk [HasVLX, HasFP16]
vcvttph2dq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPH2DQZ256rrkz [HasVLX, HasFP16]
vcvttph2dq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2QQZ128rm [HasVLX, HasFP16]
vcvttph2qq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2QQZ128rmb [HasVLX, HasFP16]
vcvttph2qq {src{1to2}, dst|dst, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2QQZ128rmbk [HasVLX, HasFP16]
vcvttph2qq {src{1to2}, dst {mask}|dst {mask}, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPH2QQZ128rmbkz [HasVLX, HasFP16]
vcvttph2qq {src{1to2}, dst {mask} {z}|dst {mask} {z}, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2QQZ128rmk [HasVLX, HasFP16]
vcvttph2qq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPH2QQZ128rmkz [HasVLX, HasFP16]
vcvttph2qq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2QQZ128rr [HasVLX, HasFP16]
vcvttph2qq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2QQZ128rrk [HasVLX, HasFP16]
vcvttph2qq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPH2QQZ128rrkz [HasVLX, HasFP16]
vcvttph2qq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2QQZ256rm [HasVLX, HasFP16]
vcvttph2qq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2QQZ256rmb [HasVLX, HasFP16]
vcvttph2qq {src{1to4}, dst|dst, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2QQZ256rmbk [HasVLX, HasFP16]
vcvttph2qq {src{1to4}, dst {mask}|dst {mask}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPH2QQZ256rmbkz [HasVLX, HasFP16]
vcvttph2qq {src{1to4}, dst {mask} {z}|dst {mask} {z}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2QQZ256rmk [HasVLX, HasFP16]
vcvttph2qq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPH2QQZ256rmkz [HasVLX, HasFP16]
vcvttph2qq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2QQZ256rr [HasVLX, HasFP16]
vcvttph2qq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2QQZ256rrk [HasVLX, HasFP16]
vcvttph2qq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPH2QQZ256rrkz [HasVLX, HasFP16]
vcvttph2qq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2UDQZ128rm [HasVLX, HasFP16]
vcvttph2udq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2UDQZ128rmb [HasVLX, HasFP16]
vcvttph2udq {src{1to4}, dst|dst, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2UDQZ128rmbk [HasVLX, HasFP16]
vcvttph2udq {src{1to4}, dst {mask}|dst {mask}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPH2UDQZ128rmbkz [HasVLX, HasFP16]
vcvttph2udq {src{1to4}, dst {mask} {z}|dst {mask} {z}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2UDQZ128rmk [HasVLX, HasFP16]
vcvttph2udq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPH2UDQZ128rmkz [HasVLX, HasFP16]
vcvttph2udq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2UDQZ128rr [HasVLX, HasFP16]
vcvttph2udq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2UDQZ128rrk [HasVLX, HasFP16]
vcvttph2udq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPH2UDQZ128rrkz [HasVLX, HasFP16]
vcvttph2udq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2UDQZ256rm [HasVLX, HasFP16]
vcvttph2udq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2UDQZ256rmb [HasVLX, HasFP16]
vcvttph2udq {src{1to8}, dst|dst, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2UDQZ256rmbk [HasVLX, HasFP16]
vcvttph2udq {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPH2UDQZ256rmbkz [HasVLX, HasFP16]
vcvttph2udq {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2UDQZ256rmk [HasVLX, HasFP16]
vcvttph2udq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPH2UDQZ256rmkz [HasVLX, HasFP16]
vcvttph2udq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2UDQZ256rr [HasVLX, HasFP16]
vcvttph2udq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2UDQZ256rrk [HasVLX, HasFP16]
vcvttph2udq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPH2UDQZ256rrkz [HasVLX, HasFP16]
vcvttph2udq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2UQQZ128rm [HasVLX, HasFP16]
vcvttph2uqq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2UQQZ128rmb [HasVLX, HasFP16]
vcvttph2uqq {src{1to2}, dst|dst, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2UQQZ128rmbk [HasVLX, HasFP16]
vcvttph2uqq {src{1to2}, dst {mask}|dst {mask}, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPH2UQQZ128rmbkz [HasVLX, HasFP16]
vcvttph2uqq {src{1to2}, dst {mask} {z}|dst {mask} {z}, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2UQQZ128rmk [HasVLX, HasFP16]
vcvttph2uqq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPH2UQQZ128rmkz [HasVLX, HasFP16]
vcvttph2uqq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2UQQZ128rr [HasVLX, HasFP16]
vcvttph2uqq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2UQQZ128rrk [HasVLX, HasFP16]
vcvttph2uqq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPH2UQQZ128rrkz [HasVLX, HasFP16]
vcvttph2uqq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2UQQZ256rm [HasVLX, HasFP16]
vcvttph2uqq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2UQQZ256rmb [HasVLX, HasFP16]
vcvttph2uqq {src{1to4}, dst|dst, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2UQQZ256rmbk [HasVLX, HasFP16]
vcvttph2uqq {src{1to4}, dst {mask}|dst {mask}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPH2UQQZ256rmbkz [HasVLX, HasFP16]
vcvttph2uqq {src{1to4}, dst {mask} {z}|dst {mask} {z}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2UQQZ256rmk [HasVLX, HasFP16]
vcvttph2uqq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPH2UQQZ256rmkz [HasVLX, HasFP16]
vcvttph2uqq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2UQQZ256rr [HasVLX, HasFP16]
vcvttph2uqq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2UQQZ256rrk [HasVLX, HasFP16]
vcvttph2uqq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPH2UQQZ256rrkz [HasVLX, HasFP16]
vcvttph2uqq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2UWZ128rm [HasVLX, HasFP16]
vcvttph2uw {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2UWZ128rmb [HasVLX, HasFP16]
vcvttph2uw {src{1to8}, dst|dst, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2UWZ128rmbk [HasVLX, HasFP16]
vcvttph2uw {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPH2UWZ128rmbkz [HasVLX, HasFP16]
vcvttph2uw {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2UWZ128rmk [HasVLX, HasFP16]
vcvttph2uw {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPH2UWZ128rmkz [HasVLX, HasFP16]
vcvttph2uw {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2UWZ128rr [HasVLX, HasFP16]
vcvttph2uw {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2UWZ128rrk [HasVLX, HasFP16]
vcvttph2uw {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPH2UWZ128rrkz [HasVLX, HasFP16]
vcvttph2uw {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2UWZ256rm [HasVLX, HasFP16]
vcvttph2uw {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2UWZ256rmb [HasVLX, HasFP16]
vcvttph2uw {src{1to16}, dst|dst, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2UWZ256rmbk [HasVLX, HasFP16]
vcvttph2uw {src{1to16}, dst {mask}|dst {mask}, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPH2UWZ256rmbkz [HasVLX, HasFP16]
vcvttph2uw {src{1to16}, dst {mask} {z}|dst {mask} {z}, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2UWZ256rmk [HasVLX, HasFP16]
vcvttph2uw {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPH2UWZ256rmkz [HasVLX, HasFP16]
vcvttph2uw {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2UWZ256rr [HasVLX, HasFP16]
vcvttph2uw {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2UWZ256rrk [HasVLX, HasFP16]
vcvttph2uw {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPH2UWZ256rrkz [HasVLX, HasFP16]
vcvttph2uw {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2WZ128rm [HasVLX, HasFP16]
vcvttph2w {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2WZ128rmb [HasVLX, HasFP16]
vcvttph2w {src{1to8}, dst|dst, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2WZ128rmbk [HasVLX, HasFP16]
vcvttph2w {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPH2WZ128rmbkz [HasVLX, HasFP16]
vcvttph2w {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2WZ128rmk [HasVLX, HasFP16]
vcvttph2w {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPH2WZ128rmkz [HasVLX, HasFP16]
vcvttph2w {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2WZ128rr [HasVLX, HasFP16]
vcvttph2w {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2WZ128rrk [HasVLX, HasFP16]
vcvttph2w {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPH2WZ128rrkz [HasVLX, HasFP16]
vcvttph2w {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2WZ256rm [HasVLX, HasFP16]
vcvttph2w {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2WZ256rmb [HasVLX, HasFP16]
vcvttph2w {src{1to16}, dst|dst, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2WZ256rmbk [HasVLX, HasFP16]
vcvttph2w {src{1to16}, dst {mask}|dst {mask}, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPH2WZ256rmbkz [HasVLX, HasFP16]
vcvttph2w {src{1to16}, dst {mask} {z}|dst {mask} {z}, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2WZ256rmk [HasVLX, HasFP16]
vcvttph2w {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPH2WZ256rmkz [HasVLX, HasFP16]
vcvttph2w {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2WZ256rr [HasVLX, HasFP16]
vcvttph2w {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2WZ256rrk [HasVLX, HasFP16]
vcvttph2w {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPH2WZ256rrkz [HasVLX, HasFP16]
vcvttph2w {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTUDQ2PHZ128rm [HasVLX, HasFP16]
vcvtudq2ph{x} {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTUDQ2PHZ128rmb [HasVLX, HasFP16]
vcvtudq2ph {src{1to4}, dst|dst, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTUDQ2PHZ128rmbk [HasVLX, HasFP16]
vcvtudq2ph {src{1to4}, dst {mask}|dst {mask}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTUDQ2PHZ128rmbkz [HasVLX, HasFP16]
vcvtudq2ph {src{1to4}, dst {mask} {z}|dst {mask} {z}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTUDQ2PHZ128rmk [HasVLX, HasFP16]
vcvtudq2ph{x} {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTUDQ2PHZ128rmkz [HasVLX, HasFP16]
vcvtudq2ph{x} {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTUDQ2PHZ128rr [HasVLX, HasFP16]
vcvtudq2ph {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTUDQ2PHZ128rrk [HasVLX, HasFP16]
vcvtudq2ph {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTUDQ2PHZ128rrkz [HasVLX, HasFP16]
vcvtudq2ph {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTUDQ2PHZ256rm [HasVLX, HasFP16]
vcvtudq2ph{y} {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTUDQ2PHZ256rmb [HasVLX, HasFP16]
vcvtudq2ph {src{1to8}, dst|dst, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTUDQ2PHZ256rmbk [HasVLX, HasFP16]
vcvtudq2ph {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTUDQ2PHZ256rmbkz [HasVLX, HasFP16]
vcvtudq2ph {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTUDQ2PHZ256rmk [HasVLX, HasFP16]
vcvtudq2ph{y} {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTUDQ2PHZ256rmkz [HasVLX, HasFP16]
vcvtudq2ph{y} {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTUDQ2PHZ256rr [HasVLX, HasFP16]
vcvtudq2ph {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTUDQ2PHZ256rrk [HasVLX, HasFP16]
vcvtudq2ph {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTUDQ2PHZ256rrkz [HasVLX, HasFP16]
vcvtudq2ph {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTUQQ2PHZ128rm [HasVLX, HasFP16]
vcvtuqq2ph{x} {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTUQQ2PHZ128rmb [HasVLX, HasFP16]
vcvtuqq2ph {src{1to2}, dst|dst, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
VCVTUQQ2PHZ128rmbk [HasVLX, HasFP16]
vcvtuqq2ph {src{1to2}, dst {mask}|dst {mask}, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTUQQ2PHZ128rmbkz [HasVLX, HasFP16]
vcvtuqq2ph {src{1to2}, dst {mask} {z}|dst {mask} {z}, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
VCVTUQQ2PHZ128rmk [HasVLX, HasFP16]
vcvtuqq2ph{x} {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTUQQ2PHZ128rmkz [HasVLX, HasFP16]
vcvtuqq2ph{x} {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTUQQ2PHZ128rr [HasVLX, HasFP16]
vcvtuqq2ph {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTUQQ2PHZ128rrk [HasVLX, HasFP16]
vcvtuqq2ph {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTUQQ2PHZ128rrkz [HasVLX, HasFP16]
vcvtuqq2ph {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTUQQ2PHZ256rm [HasVLX, HasFP16]
vcvtuqq2ph{y} {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTUQQ2PHZ256rmb [HasVLX, HasFP16]
vcvtuqq2ph {src{1to4}, dst|dst, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTUQQ2PHZ256rmbk [HasVLX, HasFP16]
vcvtuqq2ph {src{1to4}, dst {mask}|dst {mask}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTUQQ2PHZ256rmbkz [HasVLX, HasFP16]
vcvtuqq2ph {src{1to4}, dst {mask} {z}|dst {mask} {z}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTUQQ2PHZ256rmk [HasVLX, HasFP16]
vcvtuqq2ph{y} {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTUQQ2PHZ256rmkz [HasVLX, HasFP16]
vcvtuqq2ph{y} {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTUQQ2PHZ256rr [HasVLX, HasFP16]
vcvtuqq2ph {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTUQQ2PHZ256rrk [HasVLX, HasFP16]
vcvtuqq2ph {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTUQQ2PHZ256rrkz [HasVLX, HasFP16]
vcvtuqq2ph {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTUW2PHZ128rm [HasVLX, HasFP16]
vcvtuw2ph {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTUW2PHZ128rmb [HasVLX, HasFP16]
vcvtuw2ph {src{1to8}, dst|dst, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTUW2PHZ128rmbk [HasVLX, HasFP16]
vcvtuw2ph {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTUW2PHZ128rmbkz [HasVLX, HasFP16]
vcvtuw2ph {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTUW2PHZ128rmk [HasVLX, HasFP16]
vcvtuw2ph {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTUW2PHZ128rmkz [HasVLX, HasFP16]
vcvtuw2ph {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTUW2PHZ128rr [HasVLX, HasFP16]
vcvtuw2ph {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTUW2PHZ128rrk [HasVLX, HasFP16]
vcvtuw2ph {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTUW2PHZ128rrkz [HasVLX, HasFP16]
vcvtuw2ph {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTUW2PHZ256rm [HasVLX, HasFP16]
vcvtuw2ph {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTUW2PHZ256rmb [HasVLX, HasFP16]
vcvtuw2ph {src{1to16}, dst|dst, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
VCVTUW2PHZ256rmbk [HasVLX, HasFP16]
vcvtuw2ph {src{1to16}, dst {mask}|dst {mask}, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTUW2PHZ256rmbkz [HasVLX, HasFP16]
vcvtuw2ph {src{1to16}, dst {mask} {z}|dst {mask} {z}, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
VCVTUW2PHZ256rmk [HasVLX, HasFP16]
vcvtuw2ph {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTUW2PHZ256rmkz [HasVLX, HasFP16]
vcvtuw2ph {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTUW2PHZ256rr [HasVLX, HasFP16]
vcvtuw2ph {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTUW2PHZ256rrk [HasVLX, HasFP16]
vcvtuw2ph {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTUW2PHZ256rrkz [HasVLX, HasFP16]
vcvtuw2ph {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTW2PHZ128rm [HasVLX, HasFP16]
vcvtw2ph {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTW2PHZ128rmb [HasVLX, HasFP16]
vcvtw2ph {src{1to8}, dst|dst, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTW2PHZ128rmbk [HasVLX, HasFP16]
vcvtw2ph {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTW2PHZ128rmbkz [HasVLX, HasFP16]
vcvtw2ph {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTW2PHZ128rmk [HasVLX, HasFP16]
vcvtw2ph {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTW2PHZ128rmkz [HasVLX, HasFP16]
vcvtw2ph {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTW2PHZ128rr [HasVLX, HasFP16]
vcvtw2ph {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTW2PHZ128rrk [HasVLX, HasFP16]
vcvtw2ph {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTW2PHZ128rrkz [HasVLX, HasFP16]
vcvtw2ph {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTW2PHZ256rm [HasVLX, HasFP16]
vcvtw2ph {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTW2PHZ256rmb [HasVLX, HasFP16]
vcvtw2ph {src{1to16}, dst|dst, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
VCVTW2PHZ256rmbk [HasVLX, HasFP16]
vcvtw2ph {src{1to16}, dst {mask}|dst {mask}, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTW2PHZ256rmbkz [HasVLX, HasFP16]
vcvtw2ph {src{1to16}, dst {mask} {z}|dst {mask} {z}, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
VCVTW2PHZ256rmk [HasVLX, HasFP16]
vcvtw2ph {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTW2PHZ256rmkz [HasVLX, HasFP16]
vcvtw2ph {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTW2PHZ256rr [HasVLX, HasFP16]
vcvtw2ph {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTW2PHZ256rrk [HasVLX, HasFP16]
vcvtw2ph {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTW2PHZ256rrkz [HasVLX, HasFP16]
vcvtw2ph {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VDIVPHZ128rm [HasVLX, HasFP16]
vdivph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VDIVPHZ128rmb [HasVLX, HasFP16]
vdivph {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VDIVPHZ128rmbk [HasVLX, HasFP16]
vdivph {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VDIVPHZ128rmbkz [HasVLX, HasFP16]
vdivph {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VDIVPHZ128rmk [HasVLX, HasFP16]
vdivph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VDIVPHZ128rmkz [HasVLX, HasFP16]
vdivph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VDIVPHZ128rr [HasVLX, HasFP16]
vdivph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VDIVPHZ128rrk [HasVLX, HasFP16]
vdivph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VDIVPHZ128rrkz [HasVLX, HasFP16]
vdivph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VDIVPHZ256rm [HasVLX, HasFP16]
vdivph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VDIVPHZ256rmb [HasVLX, HasFP16]
vdivph {src2{1to16}, src1, dst|dst, src1, src2{1to16}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VDIVPHZ256rmbk [HasVLX, HasFP16]
vdivph {src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VDIVPHZ256rmbkz [HasVLX, HasFP16]
vdivph {src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VDIVPHZ256rmk [HasVLX, HasFP16]
vdivph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VDIVPHZ256rmkz [HasVLX, HasFP16]
vdivph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VDIVPHZ256rr [HasVLX, HasFP16]
vdivph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VDIVPHZ256rrk [HasVLX, HasFP16]
vdivph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VDIVPHZ256rrkz [HasVLX, HasFP16]
vdivph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VFCMADDCPHZ128m [HasVLX, HasFP16]
vfcmaddcph {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFCMADDCPHZ128mb [HasVLX, HasFP16]
vfcmaddcph {src3{1to4}, src2, dst|dst, src2, src3{1to4}}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFCMADDCPHZ128mbk [HasVLX, HasFP16]
vfcmaddcph {src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFCMADDCPHZ128mbkz [HasVLX, HasFP16]
vfcmaddcph {src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFCMADDCPHZ128mk [HasVLX, HasFP16]
vfcmaddcph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFCMADDCPHZ128mkz [HasVLX, HasFP16]
vfcmaddcph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFCMADDCPHZ128r [HasVLX, HasFP16]
vfcmaddcph {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFCMADDCPHZ128rk [HasVLX, HasFP16]
vfcmaddcph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFCMADDCPHZ128rkz [HasVLX, HasFP16]
vfcmaddcph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFCMADDCPHZ256m [HasVLX, HasFP16]
vfcmaddcph {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFCMADDCPHZ256mb [HasVLX, HasFP16]
vfcmaddcph {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFCMADDCPHZ256mbk [HasVLX, HasFP16]
vfcmaddcph {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFCMADDCPHZ256mbkz [HasVLX, HasFP16]
vfcmaddcph {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFCMADDCPHZ256mk [HasVLX, HasFP16]
vfcmaddcph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFCMADDCPHZ256mkz [HasVLX, HasFP16]
vfcmaddcph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFCMADDCPHZ256r [HasVLX, HasFP16]
vfcmaddcph {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFCMADDCPHZ256rk [HasVLX, HasFP16]
vfcmaddcph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFCMADDCPHZ256rkz [HasVLX, HasFP16]
vfcmaddcph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFCMULCPHZ128rm [HasVLX, HasFP16]
vfcmulcph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst |
VFCMULCPHZ128rmb [HasVLX, HasFP16]
vfcmulcph {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst |
VFCMULCPHZ128rmbk [HasVLX, HasFP16]
vfcmulcph {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst, src0 = dst |
VFCMULCPHZ128rmbkz [HasVLX, HasFP16]
vfcmulcph {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst |
VFCMULCPHZ128rmk [HasVLX, HasFP16]
vfcmulcph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst, src0 = dst |
VFCMULCPHZ128rmkz [HasVLX, HasFP16]
vfcmulcph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst |
VFCMULCPHZ128rr [HasVLX, HasFP16]
vfcmulcph {src2, src1, dst|dst, src1, src2}
|
Note
|
Constraints: @earlyclobber dst |
VFCMULCPHZ128rrk [HasVLX, HasFP16]
vfcmulcph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: @earlyclobber dst, src0 = dst |
VFCMULCPHZ128rrkz [HasVLX, HasFP16]
vfcmulcph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Constraints: @earlyclobber dst |
VFCMULCPHZ256rm [HasVLX, HasFP16]
vfcmulcph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst |
VFCMULCPHZ256rmb [HasVLX, HasFP16]
vfcmulcph {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst |
VFCMULCPHZ256rmbk [HasVLX, HasFP16]
vfcmulcph {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst, src0 = dst |
VFCMULCPHZ256rmbkz [HasVLX, HasFP16]
vfcmulcph {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst |
VFCMULCPHZ256rmk [HasVLX, HasFP16]
vfcmulcph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst, src0 = dst |
VFCMULCPHZ256rmkz [HasVLX, HasFP16]
vfcmulcph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst |
VFCMULCPHZ256rr [HasVLX, HasFP16]
vfcmulcph {src2, src1, dst|dst, src1, src2}
|
Note
|
Constraints: @earlyclobber dst |
VFCMULCPHZ256rrk [HasVLX, HasFP16]
vfcmulcph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: @earlyclobber dst, src0 = dst |
VFCMULCPHZ256rrkz [HasVLX, HasFP16]
vfcmulcph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Constraints: @earlyclobber dst |
VFMADD132PHZ128m [HasVLX, HasFP16]
vfmadd132ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PHZ128mb [HasVLX, HasFP16]
vfmadd132ph {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PHZ128mbk [HasVLX, HasFP16]
vfmadd132ph {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PHZ128mbkz [HasVLX, HasFP16]
vfmadd132ph {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PHZ128mk [HasVLX, HasFP16]
vfmadd132ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PHZ128mkz [HasVLX, HasFP16]
vfmadd132ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PHZ128r [HasVLX, HasFP16]
vfmadd132ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PHZ128rk [HasVLX, HasFP16]
vfmadd132ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PHZ128rkz [HasVLX, HasFP16]
vfmadd132ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PHZ256m [HasVLX, HasFP16]
vfmadd132ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PHZ256mb [HasVLX, HasFP16]
vfmadd132ph {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PHZ256mbk [HasVLX, HasFP16]
vfmadd132ph {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PHZ256mbkz [HasVLX, HasFP16]
vfmadd132ph {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PHZ256mk [HasVLX, HasFP16]
vfmadd132ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PHZ256mkz [HasVLX, HasFP16]
vfmadd132ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PHZ256r [HasVLX, HasFP16]
vfmadd132ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PHZ256rk [HasVLX, HasFP16]
vfmadd132ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PHZ256rkz [HasVLX, HasFP16]
vfmadd132ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PHZ128m [HasVLX, HasFP16]
vfmadd213ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PHZ128mb [HasVLX, HasFP16]
vfmadd213ph {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PHZ128mbk [HasVLX, HasFP16]
vfmadd213ph {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PHZ128mbkz [HasVLX, HasFP16]
vfmadd213ph {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PHZ128mk [HasVLX, HasFP16]
vfmadd213ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PHZ128mkz [HasVLX, HasFP16]
vfmadd213ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PHZ128r [HasVLX, HasFP16]
vfmadd213ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PHZ128rk [HasVLX, HasFP16]
vfmadd213ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PHZ128rkz [HasVLX, HasFP16]
vfmadd213ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PHZ256m [HasVLX, HasFP16]
vfmadd213ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PHZ256mb [HasVLX, HasFP16]
vfmadd213ph {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PHZ256mbk [HasVLX, HasFP16]
vfmadd213ph {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PHZ256mbkz [HasVLX, HasFP16]
vfmadd213ph {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PHZ256mk [HasVLX, HasFP16]
vfmadd213ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PHZ256mkz [HasVLX, HasFP16]
vfmadd213ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PHZ256r [HasVLX, HasFP16]
vfmadd213ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PHZ256rk [HasVLX, HasFP16]
vfmadd213ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PHZ256rkz [HasVLX, HasFP16]
vfmadd213ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PHZ128m [HasVLX, HasFP16]
vfmadd231ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PHZ128mb [HasVLX, HasFP16]
vfmadd231ph {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PHZ128mbk [HasVLX, HasFP16]
vfmadd231ph {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PHZ128mbkz [HasVLX, HasFP16]
vfmadd231ph {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PHZ128mk [HasVLX, HasFP16]
vfmadd231ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PHZ128mkz [HasVLX, HasFP16]
vfmadd231ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PHZ128r [HasVLX, HasFP16]
vfmadd231ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PHZ128rk [HasVLX, HasFP16]
vfmadd231ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PHZ128rkz [HasVLX, HasFP16]
vfmadd231ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PHZ256m [HasVLX, HasFP16]
vfmadd231ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PHZ256mb [HasVLX, HasFP16]
vfmadd231ph {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PHZ256mbk [HasVLX, HasFP16]
vfmadd231ph {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PHZ256mbkz [HasVLX, HasFP16]
vfmadd231ph {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PHZ256mk [HasVLX, HasFP16]
vfmadd231ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PHZ256mkz [HasVLX, HasFP16]
vfmadd231ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PHZ256r [HasVLX, HasFP16]
vfmadd231ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PHZ256rk [HasVLX, HasFP16]
vfmadd231ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PHZ256rkz [HasVLX, HasFP16]
vfmadd231ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDCPHZ128m [HasVLX, HasFP16]
vfmaddcph {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFMADDCPHZ128mb [HasVLX, HasFP16]
vfmaddcph {src3{1to4}, src2, dst|dst, src2, src3{1to4}}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFMADDCPHZ128mbk [HasVLX, HasFP16]
vfmaddcph {src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFMADDCPHZ128mbkz [HasVLX, HasFP16]
vfmaddcph {src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFMADDCPHZ128mk [HasVLX, HasFP16]
vfmaddcph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFMADDCPHZ128mkz [HasVLX, HasFP16]
vfmaddcph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFMADDCPHZ128r [HasVLX, HasFP16]
vfmaddcph {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFMADDCPHZ128rk [HasVLX, HasFP16]
vfmaddcph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFMADDCPHZ128rkz [HasVLX, HasFP16]
vfmaddcph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFMADDCPHZ256m [HasVLX, HasFP16]
vfmaddcph {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFMADDCPHZ256mb [HasVLX, HasFP16]
vfmaddcph {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFMADDCPHZ256mbk [HasVLX, HasFP16]
vfmaddcph {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFMADDCPHZ256mbkz [HasVLX, HasFP16]
vfmaddcph {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFMADDCPHZ256mk [HasVLX, HasFP16]
vfmaddcph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFMADDCPHZ256mkz [HasVLX, HasFP16]
vfmaddcph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFMADDCPHZ256r [HasVLX, HasFP16]
vfmaddcph {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFMADDCPHZ256rk [HasVLX, HasFP16]
vfmaddcph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFMADDCPHZ256rkz [HasVLX, HasFP16]
vfmaddcph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFMADDSUB132PHZ128m [HasVLX, HasFP16]
vfmaddsub132ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PHZ128mb [HasVLX, HasFP16]
vfmaddsub132ph {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PHZ128mbk [HasVLX, HasFP16]
vfmaddsub132ph {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PHZ128mbkz [HasVLX, HasFP16]
vfmaddsub132ph {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PHZ128mk [HasVLX, HasFP16]
vfmaddsub132ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PHZ128mkz [HasVLX, HasFP16]
vfmaddsub132ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PHZ128r [HasVLX, HasFP16]
vfmaddsub132ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PHZ128rk [HasVLX, HasFP16]
vfmaddsub132ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PHZ128rkz [HasVLX, HasFP16]
vfmaddsub132ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PHZ256m [HasVLX, HasFP16]
vfmaddsub132ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PHZ256mb [HasVLX, HasFP16]
vfmaddsub132ph {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PHZ256mbk [HasVLX, HasFP16]
vfmaddsub132ph {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PHZ256mbkz [HasVLX, HasFP16]
vfmaddsub132ph {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PHZ256mk [HasVLX, HasFP16]
vfmaddsub132ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PHZ256mkz [HasVLX, HasFP16]
vfmaddsub132ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PHZ256r [HasVLX, HasFP16]
vfmaddsub132ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PHZ256rk [HasVLX, HasFP16]
vfmaddsub132ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PHZ256rkz [HasVLX, HasFP16]
vfmaddsub132ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PHZ128m [HasVLX, HasFP16]
vfmaddsub213ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PHZ128mb [HasVLX, HasFP16]
vfmaddsub213ph {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PHZ128mbk [HasVLX, HasFP16]
vfmaddsub213ph {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PHZ128mbkz [HasVLX, HasFP16]
vfmaddsub213ph {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PHZ128mk [HasVLX, HasFP16]
vfmaddsub213ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PHZ128mkz [HasVLX, HasFP16]
vfmaddsub213ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PHZ128r [HasVLX, HasFP16]
vfmaddsub213ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PHZ128rk [HasVLX, HasFP16]
vfmaddsub213ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PHZ128rkz [HasVLX, HasFP16]
vfmaddsub213ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PHZ256m [HasVLX, HasFP16]
vfmaddsub213ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PHZ256mb [HasVLX, HasFP16]
vfmaddsub213ph {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PHZ256mbk [HasVLX, HasFP16]
vfmaddsub213ph {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PHZ256mbkz [HasVLX, HasFP16]
vfmaddsub213ph {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PHZ256mk [HasVLX, HasFP16]
vfmaddsub213ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PHZ256mkz [HasVLX, HasFP16]
vfmaddsub213ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PHZ256r [HasVLX, HasFP16]
vfmaddsub213ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PHZ256rk [HasVLX, HasFP16]
vfmaddsub213ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PHZ256rkz [HasVLX, HasFP16]
vfmaddsub213ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PHZ128m [HasVLX, HasFP16]
vfmaddsub231ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PHZ128mb [HasVLX, HasFP16]
vfmaddsub231ph {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PHZ128mbk [HasVLX, HasFP16]
vfmaddsub231ph {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PHZ128mbkz [HasVLX, HasFP16]
vfmaddsub231ph {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PHZ128mk [HasVLX, HasFP16]
vfmaddsub231ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PHZ128mkz [HasVLX, HasFP16]
vfmaddsub231ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PHZ128r [HasVLX, HasFP16]
vfmaddsub231ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PHZ128rk [HasVLX, HasFP16]
vfmaddsub231ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PHZ128rkz [HasVLX, HasFP16]
vfmaddsub231ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PHZ256m [HasVLX, HasFP16]
vfmaddsub231ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PHZ256mb [HasVLX, HasFP16]
vfmaddsub231ph {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PHZ256mbk [HasVLX, HasFP16]
vfmaddsub231ph {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PHZ256mbkz [HasVLX, HasFP16]
vfmaddsub231ph {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PHZ256mk [HasVLX, HasFP16]
vfmaddsub231ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PHZ256mkz [HasVLX, HasFP16]
vfmaddsub231ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PHZ256r [HasVLX, HasFP16]
vfmaddsub231ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PHZ256rk [HasVLX, HasFP16]
vfmaddsub231ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PHZ256rkz [HasVLX, HasFP16]
vfmaddsub231ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PHZ128m [HasVLX, HasFP16]
vfmsub132ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PHZ128mb [HasVLX, HasFP16]
vfmsub132ph {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PHZ128mbk [HasVLX, HasFP16]
vfmsub132ph {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PHZ128mbkz [HasVLX, HasFP16]
vfmsub132ph {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PHZ128mk [HasVLX, HasFP16]
vfmsub132ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PHZ128mkz [HasVLX, HasFP16]
vfmsub132ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PHZ128r [HasVLX, HasFP16]
vfmsub132ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PHZ128rk [HasVLX, HasFP16]
vfmsub132ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PHZ128rkz [HasVLX, HasFP16]
vfmsub132ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PHZ256m [HasVLX, HasFP16]
vfmsub132ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PHZ256mb [HasVLX, HasFP16]
vfmsub132ph {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PHZ256mbk [HasVLX, HasFP16]
vfmsub132ph {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PHZ256mbkz [HasVLX, HasFP16]
vfmsub132ph {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PHZ256mk [HasVLX, HasFP16]
vfmsub132ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PHZ256mkz [HasVLX, HasFP16]
vfmsub132ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PHZ256r [HasVLX, HasFP16]
vfmsub132ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PHZ256rk [HasVLX, HasFP16]
vfmsub132ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PHZ256rkz [HasVLX, HasFP16]
vfmsub132ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PHZ128m [HasVLX, HasFP16]
vfmsub213ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PHZ128mb [HasVLX, HasFP16]
vfmsub213ph {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PHZ128mbk [HasVLX, HasFP16]
vfmsub213ph {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PHZ128mbkz [HasVLX, HasFP16]
vfmsub213ph {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PHZ128mk [HasVLX, HasFP16]
vfmsub213ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PHZ128mkz [HasVLX, HasFP16]
vfmsub213ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PHZ128r [HasVLX, HasFP16]
vfmsub213ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PHZ128rk [HasVLX, HasFP16]
vfmsub213ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PHZ128rkz [HasVLX, HasFP16]
vfmsub213ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PHZ256m [HasVLX, HasFP16]
vfmsub213ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PHZ256mb [HasVLX, HasFP16]
vfmsub213ph {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PHZ256mbk [HasVLX, HasFP16]
vfmsub213ph {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PHZ256mbkz [HasVLX, HasFP16]
vfmsub213ph {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PHZ256mk [HasVLX, HasFP16]
vfmsub213ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PHZ256mkz [HasVLX, HasFP16]
vfmsub213ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PHZ256r [HasVLX, HasFP16]
vfmsub213ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PHZ256rk [HasVLX, HasFP16]
vfmsub213ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PHZ256rkz [HasVLX, HasFP16]
vfmsub213ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PHZ128m [HasVLX, HasFP16]
vfmsub231ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PHZ128mb [HasVLX, HasFP16]
vfmsub231ph {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PHZ128mbk [HasVLX, HasFP16]
vfmsub231ph {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PHZ128mbkz [HasVLX, HasFP16]
vfmsub231ph {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PHZ128mk [HasVLX, HasFP16]
vfmsub231ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PHZ128mkz [HasVLX, HasFP16]
vfmsub231ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PHZ128r [HasVLX, HasFP16]
vfmsub231ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PHZ128rk [HasVLX, HasFP16]
vfmsub231ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PHZ128rkz [HasVLX, HasFP16]
vfmsub231ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PHZ256m [HasVLX, HasFP16]
vfmsub231ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PHZ256mb [HasVLX, HasFP16]
vfmsub231ph {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PHZ256mbk [HasVLX, HasFP16]
vfmsub231ph {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PHZ256mbkz [HasVLX, HasFP16]
vfmsub231ph {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PHZ256mk [HasVLX, HasFP16]
vfmsub231ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PHZ256mkz [HasVLX, HasFP16]
vfmsub231ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PHZ256r [HasVLX, HasFP16]
vfmsub231ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PHZ256rk [HasVLX, HasFP16]
vfmsub231ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PHZ256rkz [HasVLX, HasFP16]
vfmsub231ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PHZ128m [HasVLX, HasFP16]
vfmsubadd132ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PHZ128mb [HasVLX, HasFP16]
vfmsubadd132ph {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PHZ128mbk [HasVLX, HasFP16]
vfmsubadd132ph {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PHZ128mbkz [HasVLX, HasFP16]
vfmsubadd132ph {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PHZ128mk [HasVLX, HasFP16]
vfmsubadd132ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PHZ128mkz [HasVLX, HasFP16]
vfmsubadd132ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PHZ128r [HasVLX, HasFP16]
vfmsubadd132ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PHZ128rk [HasVLX, HasFP16]
vfmsubadd132ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PHZ128rkz [HasVLX, HasFP16]
vfmsubadd132ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PHZ256m [HasVLX, HasFP16]
vfmsubadd132ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PHZ256mb [HasVLX, HasFP16]
vfmsubadd132ph {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PHZ256mbk [HasVLX, HasFP16]
vfmsubadd132ph {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PHZ256mbkz [HasVLX, HasFP16]
vfmsubadd132ph {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PHZ256mk [HasVLX, HasFP16]
vfmsubadd132ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PHZ256mkz [HasVLX, HasFP16]
vfmsubadd132ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PHZ256r [HasVLX, HasFP16]
vfmsubadd132ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PHZ256rk [HasVLX, HasFP16]
vfmsubadd132ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PHZ256rkz [HasVLX, HasFP16]
vfmsubadd132ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PHZ128m [HasVLX, HasFP16]
vfmsubadd213ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PHZ128mb [HasVLX, HasFP16]
vfmsubadd213ph {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PHZ128mbk [HasVLX, HasFP16]
vfmsubadd213ph {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PHZ128mbkz [HasVLX, HasFP16]
vfmsubadd213ph {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PHZ128mk [HasVLX, HasFP16]
vfmsubadd213ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PHZ128mkz [HasVLX, HasFP16]
vfmsubadd213ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PHZ128r [HasVLX, HasFP16]
vfmsubadd213ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PHZ128rk [HasVLX, HasFP16]
vfmsubadd213ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PHZ128rkz [HasVLX, HasFP16]
vfmsubadd213ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PHZ256m [HasVLX, HasFP16]
vfmsubadd213ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PHZ256mb [HasVLX, HasFP16]
vfmsubadd213ph {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PHZ256mbk [HasVLX, HasFP16]
vfmsubadd213ph {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PHZ256mbkz [HasVLX, HasFP16]
vfmsubadd213ph {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PHZ256mk [HasVLX, HasFP16]
vfmsubadd213ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PHZ256mkz [HasVLX, HasFP16]
vfmsubadd213ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PHZ256r [HasVLX, HasFP16]
vfmsubadd213ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PHZ256rk [HasVLX, HasFP16]
vfmsubadd213ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PHZ256rkz [HasVLX, HasFP16]
vfmsubadd213ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PHZ128m [HasVLX, HasFP16]
vfmsubadd231ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PHZ128mb [HasVLX, HasFP16]
vfmsubadd231ph {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PHZ128mbk [HasVLX, HasFP16]
vfmsubadd231ph {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PHZ128mbkz [HasVLX, HasFP16]
vfmsubadd231ph {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PHZ128mk [HasVLX, HasFP16]
vfmsubadd231ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PHZ128mkz [HasVLX, HasFP16]
vfmsubadd231ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PHZ128r [HasVLX, HasFP16]
vfmsubadd231ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PHZ128rk [HasVLX, HasFP16]
vfmsubadd231ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PHZ128rkz [HasVLX, HasFP16]
vfmsubadd231ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PHZ256m [HasVLX, HasFP16]
vfmsubadd231ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PHZ256mb [HasVLX, HasFP16]
vfmsubadd231ph {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PHZ256mbk [HasVLX, HasFP16]
vfmsubadd231ph {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PHZ256mbkz [HasVLX, HasFP16]
vfmsubadd231ph {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PHZ256mk [HasVLX, HasFP16]
vfmsubadd231ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PHZ256mkz [HasVLX, HasFP16]
vfmsubadd231ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PHZ256r [HasVLX, HasFP16]
vfmsubadd231ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PHZ256rk [HasVLX, HasFP16]
vfmsubadd231ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PHZ256rkz [HasVLX, HasFP16]
vfmsubadd231ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMULCPHZ128rm [HasVLX, HasFP16]
vfmulcph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst |
VFMULCPHZ128rmb [HasVLX, HasFP16]
vfmulcph {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst |
VFMULCPHZ128rmbk [HasVLX, HasFP16]
vfmulcph {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst, src0 = dst |
VFMULCPHZ128rmbkz [HasVLX, HasFP16]
vfmulcph {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst |
VFMULCPHZ128rmk [HasVLX, HasFP16]
vfmulcph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst, src0 = dst |
VFMULCPHZ128rmkz [HasVLX, HasFP16]
vfmulcph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst |
VFMULCPHZ128rr [HasVLX, HasFP16]
vfmulcph {src2, src1, dst|dst, src1, src2}
|
Note
|
Constraints: @earlyclobber dst |
VFMULCPHZ128rrk [HasVLX, HasFP16]
vfmulcph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: @earlyclobber dst, src0 = dst |
VFMULCPHZ128rrkz [HasVLX, HasFP16]
vfmulcph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Constraints: @earlyclobber dst |
VFMULCPHZ256rm [HasVLX, HasFP16]
vfmulcph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst |
VFMULCPHZ256rmb [HasVLX, HasFP16]
vfmulcph {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst |
VFMULCPHZ256rmbk [HasVLX, HasFP16]
vfmulcph {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst, src0 = dst |
VFMULCPHZ256rmbkz [HasVLX, HasFP16]
vfmulcph {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst |
VFMULCPHZ256rmk [HasVLX, HasFP16]
vfmulcph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst, src0 = dst |
VFMULCPHZ256rmkz [HasVLX, HasFP16]
vfmulcph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst |
VFMULCPHZ256rr [HasVLX, HasFP16]
vfmulcph {src2, src1, dst|dst, src1, src2}
|
Note
|
Constraints: @earlyclobber dst |
VFMULCPHZ256rrk [HasVLX, HasFP16]
vfmulcph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: @earlyclobber dst, src0 = dst |
VFMULCPHZ256rrkz [HasVLX, HasFP16]
vfmulcph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Constraints: @earlyclobber dst |
VFNMADD132PHZ128m [HasVLX, HasFP16]
vfnmadd132ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PHZ128mb [HasVLX, HasFP16]
vfnmadd132ph {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PHZ128mbk [HasVLX, HasFP16]
vfnmadd132ph {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PHZ128mbkz [HasVLX, HasFP16]
vfnmadd132ph {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PHZ128mk [HasVLX, HasFP16]
vfnmadd132ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PHZ128mkz [HasVLX, HasFP16]
vfnmadd132ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PHZ128r [HasVLX, HasFP16]
vfnmadd132ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PHZ128rk [HasVLX, HasFP16]
vfnmadd132ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PHZ128rkz [HasVLX, HasFP16]
vfnmadd132ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PHZ256m [HasVLX, HasFP16]
vfnmadd132ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PHZ256mb [HasVLX, HasFP16]
vfnmadd132ph {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PHZ256mbk [HasVLX, HasFP16]
vfnmadd132ph {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PHZ256mbkz [HasVLX, HasFP16]
vfnmadd132ph {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PHZ256mk [HasVLX, HasFP16]
vfnmadd132ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PHZ256mkz [HasVLX, HasFP16]
vfnmadd132ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PHZ256r [HasVLX, HasFP16]
vfnmadd132ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PHZ256rk [HasVLX, HasFP16]
vfnmadd132ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PHZ256rkz [HasVLX, HasFP16]
vfnmadd132ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PHZ128m [HasVLX, HasFP16]
vfnmadd213ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PHZ128mb [HasVLX, HasFP16]
vfnmadd213ph {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PHZ128mbk [HasVLX, HasFP16]
vfnmadd213ph {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PHZ128mbkz [HasVLX, HasFP16]
vfnmadd213ph {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PHZ128mk [HasVLX, HasFP16]
vfnmadd213ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PHZ128mkz [HasVLX, HasFP16]
vfnmadd213ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PHZ128r [HasVLX, HasFP16]
vfnmadd213ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PHZ128rk [HasVLX, HasFP16]
vfnmadd213ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PHZ128rkz [HasVLX, HasFP16]
vfnmadd213ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PHZ256m [HasVLX, HasFP16]
vfnmadd213ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PHZ256mb [HasVLX, HasFP16]
vfnmadd213ph {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PHZ256mbk [HasVLX, HasFP16]
vfnmadd213ph {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PHZ256mbkz [HasVLX, HasFP16]
vfnmadd213ph {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PHZ256mk [HasVLX, HasFP16]
vfnmadd213ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PHZ256mkz [HasVLX, HasFP16]
vfnmadd213ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PHZ256r [HasVLX, HasFP16]
vfnmadd213ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PHZ256rk [HasVLX, HasFP16]
vfnmadd213ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PHZ256rkz [HasVLX, HasFP16]
vfnmadd213ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PHZ128m [HasVLX, HasFP16]
vfnmadd231ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PHZ128mb [HasVLX, HasFP16]
vfnmadd231ph {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PHZ128mbk [HasVLX, HasFP16]
vfnmadd231ph {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PHZ128mbkz [HasVLX, HasFP16]
vfnmadd231ph {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PHZ128mk [HasVLX, HasFP16]
vfnmadd231ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PHZ128mkz [HasVLX, HasFP16]
vfnmadd231ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PHZ128r [HasVLX, HasFP16]
vfnmadd231ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PHZ128rk [HasVLX, HasFP16]
vfnmadd231ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PHZ128rkz [HasVLX, HasFP16]
vfnmadd231ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PHZ256m [HasVLX, HasFP16]
vfnmadd231ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PHZ256mb [HasVLX, HasFP16]
vfnmadd231ph {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PHZ256mbk [HasVLX, HasFP16]
vfnmadd231ph {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PHZ256mbkz [HasVLX, HasFP16]
vfnmadd231ph {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PHZ256mk [HasVLX, HasFP16]
vfnmadd231ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PHZ256mkz [HasVLX, HasFP16]
vfnmadd231ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PHZ256r [HasVLX, HasFP16]
vfnmadd231ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PHZ256rk [HasVLX, HasFP16]
vfnmadd231ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PHZ256rkz [HasVLX, HasFP16]
vfnmadd231ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PHZ128m [HasVLX, HasFP16]
vfnmsub132ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PHZ128mb [HasVLX, HasFP16]
vfnmsub132ph {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PHZ128mbk [HasVLX, HasFP16]
vfnmsub132ph {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PHZ128mbkz [HasVLX, HasFP16]
vfnmsub132ph {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PHZ128mk [HasVLX, HasFP16]
vfnmsub132ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PHZ128mkz [HasVLX, HasFP16]
vfnmsub132ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PHZ128r [HasVLX, HasFP16]
vfnmsub132ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PHZ128rk [HasVLX, HasFP16]
vfnmsub132ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PHZ128rkz [HasVLX, HasFP16]
vfnmsub132ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PHZ256m [HasVLX, HasFP16]
vfnmsub132ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PHZ256mb [HasVLX, HasFP16]
vfnmsub132ph {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PHZ256mbk [HasVLX, HasFP16]
vfnmsub132ph {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PHZ256mbkz [HasVLX, HasFP16]
vfnmsub132ph {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PHZ256mk [HasVLX, HasFP16]
vfnmsub132ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PHZ256mkz [HasVLX, HasFP16]
vfnmsub132ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PHZ256r [HasVLX, HasFP16]
vfnmsub132ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PHZ256rk [HasVLX, HasFP16]
vfnmsub132ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PHZ256rkz [HasVLX, HasFP16]
vfnmsub132ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PHZ128m [HasVLX, HasFP16]
vfnmsub213ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PHZ128mb [HasVLX, HasFP16]
vfnmsub213ph {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PHZ128mbk [HasVLX, HasFP16]
vfnmsub213ph {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PHZ128mbkz [HasVLX, HasFP16]
vfnmsub213ph {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PHZ128mk [HasVLX, HasFP16]
vfnmsub213ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PHZ128mkz [HasVLX, HasFP16]
vfnmsub213ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PHZ128r [HasVLX, HasFP16]
vfnmsub213ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PHZ128rk [HasVLX, HasFP16]
vfnmsub213ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PHZ128rkz [HasVLX, HasFP16]
vfnmsub213ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PHZ256m [HasVLX, HasFP16]
vfnmsub213ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PHZ256mb [HasVLX, HasFP16]
vfnmsub213ph {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PHZ256mbk [HasVLX, HasFP16]
vfnmsub213ph {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PHZ256mbkz [HasVLX, HasFP16]
vfnmsub213ph {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PHZ256mk [HasVLX, HasFP16]
vfnmsub213ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PHZ256mkz [HasVLX, HasFP16]
vfnmsub213ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PHZ256r [HasVLX, HasFP16]
vfnmsub213ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PHZ256rk [HasVLX, HasFP16]
vfnmsub213ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PHZ256rkz [HasVLX, HasFP16]
vfnmsub213ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PHZ128m [HasVLX, HasFP16]
vfnmsub231ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PHZ128mb [HasVLX, HasFP16]
vfnmsub231ph {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PHZ128mbk [HasVLX, HasFP16]
vfnmsub231ph {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PHZ128mbkz [HasVLX, HasFP16]
vfnmsub231ph {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PHZ128mk [HasVLX, HasFP16]
vfnmsub231ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PHZ128mkz [HasVLX, HasFP16]
vfnmsub231ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PHZ128r [HasVLX, HasFP16]
vfnmsub231ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PHZ128rk [HasVLX, HasFP16]
vfnmsub231ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PHZ128rkz [HasVLX, HasFP16]
vfnmsub231ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PHZ256m [HasVLX, HasFP16]
vfnmsub231ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PHZ256mb [HasVLX, HasFP16]
vfnmsub231ph {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PHZ256mbk [HasVLX, HasFP16]
vfnmsub231ph {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PHZ256mbkz [HasVLX, HasFP16]
vfnmsub231ph {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PHZ256mk [HasVLX, HasFP16]
vfnmsub231ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PHZ256mkz [HasVLX, HasFP16]
vfnmsub231ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PHZ256r [HasVLX, HasFP16]
vfnmsub231ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PHZ256rk [HasVLX, HasFP16]
vfnmsub231ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PHZ256rkz [HasVLX, HasFP16]
vfnmsub231ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFPCLASSPHZ128mbi [HasVLX, HasFP16]
vfpclassph {src2, src1{1to8}, dst|dst, src1{1to8}, src2}
VFPCLASSPHZ128mbik [HasVLX, HasFP16]
vfpclassph {src2, src1{1to8}, dst {mask}|dst {mask}, src1{1to8}, src2}
VFPCLASSPHZ128mi [HasVLX, HasFP16]
vfpclassph{x} {src2, src1, dst|dst, src1, src2}
VFPCLASSPHZ128mik [HasVLX, HasFP16]
vfpclassph{x} {src2, src1, dst {mask}|dst {mask}, src1, src2}
VFPCLASSPHZ128ri [HasVLX, HasFP16]
vfpclassph {src2, src1, dst|dst, src1, src2}
VFPCLASSPHZ128rik [HasVLX, HasFP16]
vfpclassph {src2, src1, dst {mask}|dst {mask}, src1, src2}
VFPCLASSPHZ256mbi [HasVLX, HasFP16]
vfpclassph {src2, src1{1to16}, dst|dst, src1{1to16}, src2}
VFPCLASSPHZ256mbik [HasVLX, HasFP16]
vfpclassph {src2, src1{1to16}, dst {mask}|dst {mask}, src1{1to16}, src2}
VFPCLASSPHZ256mi [HasVLX, HasFP16]
vfpclassph{y} {src2, src1, dst|dst, src1, src2}
VFPCLASSPHZ256mik [HasVLX, HasFP16]
vfpclassph{y} {src2, src1, dst {mask}|dst {mask}, src1, src2}
VFPCLASSPHZ256ri [HasVLX, HasFP16]
vfpclassph {src2, src1, dst|dst, src1, src2}
VFPCLASSPHZ256rik [HasVLX, HasFP16]
vfpclassph {src2, src1, dst {mask}|dst {mask}, src1, src2}
VGETEXPPHZ128m [HasVLX, HasFP16]
vgetexpph {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VGETEXPPHZ128mb [HasVLX, HasFP16]
vgetexpph {src{1to8}, dst|dst, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VGETEXPPHZ128mbk [HasVLX, HasFP16]
vgetexpph {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VGETEXPPHZ128mbkz [HasVLX, HasFP16]
vgetexpph {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VGETEXPPHZ128mk [HasVLX, HasFP16]
vgetexpph {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VGETEXPPHZ128mkz [HasVLX, HasFP16]
vgetexpph {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VGETEXPPHZ128r [HasVLX, HasFP16]
vgetexpph {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VGETEXPPHZ128rk [HasVLX, HasFP16]
vgetexpph {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VGETEXPPHZ128rkz [HasVLX, HasFP16]
vgetexpph {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VGETEXPPHZ256m [HasVLX, HasFP16]
vgetexpph {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VGETEXPPHZ256mb [HasVLX, HasFP16]
vgetexpph {src{1to16}, dst|dst, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
VGETEXPPHZ256mbk [HasVLX, HasFP16]
vgetexpph {src{1to16}, dst {mask}|dst {mask}, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VGETEXPPHZ256mbkz [HasVLX, HasFP16]
vgetexpph {src{1to16}, dst {mask} {z}|dst {mask} {z}, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
VGETEXPPHZ256mk [HasVLX, HasFP16]
vgetexpph {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VGETEXPPHZ256mkz [HasVLX, HasFP16]
vgetexpph {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VGETEXPPHZ256r [HasVLX, HasFP16]
vgetexpph {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VGETEXPPHZ256rk [HasVLX, HasFP16]
vgetexpph {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VGETEXPPHZ256rkz [HasVLX, HasFP16]
vgetexpph {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VGETMANTPHZ128rmbi [HasVLX, HasFP16]
vgetmantph {src2, src1{1to8}, dst|dst, src1{1to8}, src2}
|
Note
|
Properties: mayRaiseFPException |
VGETMANTPHZ128rmbik [HasVLX, HasFP16]
vgetmantph {src2, src1{1to8}, dst {mask}|dst {mask}, src1{1to8}, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VGETMANTPHZ128rmbikz [HasVLX, HasFP16]
vgetmantph {src2, src1{1to8}, dst {mask} {z}|dst {mask} {z}, src1{1to8}, src2}
|
Note
|
Properties: mayRaiseFPException |
VGETMANTPHZ128rmi [HasVLX, HasFP16]
vgetmantph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VGETMANTPHZ128rmik [HasVLX, HasFP16]
vgetmantph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VGETMANTPHZ128rmikz [HasVLX, HasFP16]
vgetmantph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VGETMANTPHZ128rri [HasVLX, HasFP16]
vgetmantph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VGETMANTPHZ128rrik [HasVLX, HasFP16]
vgetmantph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VGETMANTPHZ128rrikz [HasVLX, HasFP16]
vgetmantph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VGETMANTPHZ256rmbi [HasVLX, HasFP16]
vgetmantph {src2, src1{1to16}, dst|dst, src1{1to16}, src2}
|
Note
|
Properties: mayRaiseFPException |
VGETMANTPHZ256rmbik [HasVLX, HasFP16]
vgetmantph {src2, src1{1to16}, dst {mask}|dst {mask}, src1{1to16}, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VGETMANTPHZ256rmbikz [HasVLX, HasFP16]
vgetmantph {src2, src1{1to16}, dst {mask} {z}|dst {mask} {z}, src1{1to16}, src2}
|
Note
|
Properties: mayRaiseFPException |
VGETMANTPHZ256rmi [HasVLX, HasFP16]
vgetmantph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VGETMANTPHZ256rmik [HasVLX, HasFP16]
vgetmantph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VGETMANTPHZ256rmikz [HasVLX, HasFP16]
vgetmantph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VGETMANTPHZ256rri [HasVLX, HasFP16]
vgetmantph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VGETMANTPHZ256rrik [HasVLX, HasFP16]
vgetmantph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VGETMANTPHZ256rrikz [HasVLX, HasFP16]
vgetmantph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMAXPHZ128rm [HasVLX, HasFP16]
vmaxph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMAXPHZ128rmb [HasVLX, HasFP16]
vmaxph {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMAXPHZ128rmbk [HasVLX, HasFP16]
vmaxph {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMAXPHZ128rmbkz [HasVLX, HasFP16]
vmaxph {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMAXPHZ128rmk [HasVLX, HasFP16]
vmaxph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMAXPHZ128rmkz [HasVLX, HasFP16]
vmaxph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMAXPHZ128rr [HasVLX, HasFP16]
vmaxph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMAXPHZ128rrk [HasVLX, HasFP16]
vmaxph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMAXPHZ128rrkz [HasVLX, HasFP16]
vmaxph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMAXPHZ256rm [HasVLX, HasFP16]
vmaxph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMAXPHZ256rmb [HasVLX, HasFP16]
vmaxph {src2{1to16}, src1, dst|dst, src1, src2{1to16}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMAXPHZ256rmbk [HasVLX, HasFP16]
vmaxph {src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMAXPHZ256rmbkz [HasVLX, HasFP16]
vmaxph {src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMAXPHZ256rmk [HasVLX, HasFP16]
vmaxph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMAXPHZ256rmkz [HasVLX, HasFP16]
vmaxph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMAXPHZ256rr [HasVLX, HasFP16]
vmaxph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMAXPHZ256rrk [HasVLX, HasFP16]
vmaxph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMAXPHZ256rrkz [HasVLX, HasFP16]
vmaxph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMINPHZ128rm [HasVLX, HasFP16]
vminph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMINPHZ128rmb [HasVLX, HasFP16]
vminph {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMINPHZ128rmbk [HasVLX, HasFP16]
vminph {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMINPHZ128rmbkz [HasVLX, HasFP16]
vminph {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMINPHZ128rmk [HasVLX, HasFP16]
vminph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMINPHZ128rmkz [HasVLX, HasFP16]
vminph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMINPHZ128rr [HasVLX, HasFP16]
vminph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMINPHZ128rrk [HasVLX, HasFP16]
vminph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMINPHZ128rrkz [HasVLX, HasFP16]
vminph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMINPHZ256rm [HasVLX, HasFP16]
vminph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMINPHZ256rmb [HasVLX, HasFP16]
vminph {src2{1to16}, src1, dst|dst, src1, src2{1to16}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMINPHZ256rmbk [HasVLX, HasFP16]
vminph {src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMINPHZ256rmbkz [HasVLX, HasFP16]
vminph {src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMINPHZ256rmk [HasVLX, HasFP16]
vminph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMINPHZ256rmkz [HasVLX, HasFP16]
vminph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMINPHZ256rr [HasVLX, HasFP16]
vminph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMINPHZ256rrk [HasVLX, HasFP16]
vminph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMINPHZ256rrkz [HasVLX, HasFP16]
vminph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMULPHZ128rm [HasVLX, HasFP16]
vmulph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMULPHZ128rmb [HasVLX, HasFP16]
vmulph {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMULPHZ128rmbk [HasVLX, HasFP16]
vmulph {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMULPHZ128rmbkz [HasVLX, HasFP16]
vmulph {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMULPHZ128rmk [HasVLX, HasFP16]
vmulph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMULPHZ128rmkz [HasVLX, HasFP16]
vmulph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMULPHZ128rr [HasVLX, HasFP16]
vmulph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMULPHZ128rrk [HasVLX, HasFP16]
vmulph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMULPHZ128rrkz [HasVLX, HasFP16]
vmulph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMULPHZ256rm [HasVLX, HasFP16]
vmulph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMULPHZ256rmb [HasVLX, HasFP16]
vmulph {src2{1to16}, src1, dst|dst, src1, src2{1to16}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMULPHZ256rmbk [HasVLX, HasFP16]
vmulph {src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMULPHZ256rmbkz [HasVLX, HasFP16]
vmulph {src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMULPHZ256rmk [HasVLX, HasFP16]
vmulph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMULPHZ256rmkz [HasVLX, HasFP16]
vmulph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMULPHZ256rr [HasVLX, HasFP16]
vmulph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMULPHZ256rrk [HasVLX, HasFP16]
vmulph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMULPHZ256rrkz [HasVLX, HasFP16]
vmulph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VRCPPHZ128m [HasVLX, HasFP16]
vrcpph {src, dst|dst, src}
VRCPPHZ128mb [HasVLX, HasFP16]
vrcpph {src{1to8}, dst|dst, src{1to8}}
VRCPPHZ128mbk [HasVLX, HasFP16]
vrcpph {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Constraints: src0 = dst |
VRCPPHZ128mbkz [HasVLX, HasFP16]
vrcpph {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
VRCPPHZ128mk [HasVLX, HasFP16]
vrcpph {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VRCPPHZ128mkz [HasVLX, HasFP16]
vrcpph {src, dst {mask} {z}|dst {mask} {z}, src}
VRCPPHZ128r [HasVLX, HasFP16]
vrcpph {src, dst|dst, src}
VRCPPHZ128rk [HasVLX, HasFP16]
vrcpph {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VRCPPHZ128rkz [HasVLX, HasFP16]
vrcpph {src, dst {mask} {z}|dst {mask} {z}, src}
VRCPPHZ256m [HasVLX, HasFP16]
vrcpph {src, dst|dst, src}
VRCPPHZ256mb [HasVLX, HasFP16]
vrcpph {src{1to16}, dst|dst, src{1to16}}
VRCPPHZ256mbk [HasVLX, HasFP16]
vrcpph {src{1to16}, dst {mask}|dst {mask}, src{1to16}}
|
Note
|
Constraints: src0 = dst |
VRCPPHZ256mbkz [HasVLX, HasFP16]
vrcpph {src{1to16}, dst {mask} {z}|dst {mask} {z}, src{1to16}}
VRCPPHZ256mk [HasVLX, HasFP16]
vrcpph {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VRCPPHZ256mkz [HasVLX, HasFP16]
vrcpph {src, dst {mask} {z}|dst {mask} {z}, src}
VRCPPHZ256r [HasVLX, HasFP16]
vrcpph {src, dst|dst, src}
VRCPPHZ256rk [HasVLX, HasFP16]
vrcpph {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VRCPPHZ256rkz [HasVLX, HasFP16]
vrcpph {src, dst {mask} {z}|dst {mask} {z}, src}
VREDUCEPHZ128rmbi [HasVLX, HasFP16]
vreduceph {src2, src1{1to8}, dst|dst, src1{1to8}, src2}
|
Note
|
Properties: mayRaiseFPException |
VREDUCEPHZ128rmbik [HasVLX, HasFP16]
vreduceph {src2, src1{1to8}, dst {mask}|dst {mask}, src1{1to8}, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VREDUCEPHZ128rmbikz [HasVLX, HasFP16]
vreduceph {src2, src1{1to8}, dst {mask} {z}|dst {mask} {z}, src1{1to8}, src2}
|
Note
|
Properties: mayRaiseFPException |
VREDUCEPHZ128rmi [HasVLX, HasFP16]
vreduceph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VREDUCEPHZ128rmik [HasVLX, HasFP16]
vreduceph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VREDUCEPHZ128rmikz [HasVLX, HasFP16]
vreduceph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VREDUCEPHZ128rri [HasVLX, HasFP16]
vreduceph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VREDUCEPHZ128rrik [HasVLX, HasFP16]
vreduceph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VREDUCEPHZ128rrikz [HasVLX, HasFP16]
vreduceph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VREDUCEPHZ256rmbi [HasVLX, HasFP16]
vreduceph {src2, src1{1to16}, dst|dst, src1{1to16}, src2}
|
Note
|
Properties: mayRaiseFPException |
VREDUCEPHZ256rmbik [HasVLX, HasFP16]
vreduceph {src2, src1{1to16}, dst {mask}|dst {mask}, src1{1to16}, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VREDUCEPHZ256rmbikz [HasVLX, HasFP16]
vreduceph {src2, src1{1to16}, dst {mask} {z}|dst {mask} {z}, src1{1to16}, src2}
|
Note
|
Properties: mayRaiseFPException |
VREDUCEPHZ256rmi [HasVLX, HasFP16]
vreduceph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VREDUCEPHZ256rmik [HasVLX, HasFP16]
vreduceph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VREDUCEPHZ256rmikz [HasVLX, HasFP16]
vreduceph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VREDUCEPHZ256rri [HasVLX, HasFP16]
vreduceph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VREDUCEPHZ256rrik [HasVLX, HasFP16]
vreduceph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VREDUCEPHZ256rrikz [HasVLX, HasFP16]
vreduceph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VRNDSCALEPHZ128rmbi [HasVLX, HasFP16]
vrndscaleph {src2, src1{1to8}, dst|dst, src1{1to8}, src2}
|
Note
|
Properties: mayRaiseFPException |
VRNDSCALEPHZ128rmbik [HasVLX, HasFP16]
vrndscaleph {src2, src1{1to8}, dst {mask}|dst {mask}, src1{1to8}, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRNDSCALEPHZ128rmbikz [HasVLX, HasFP16]
vrndscaleph {src2, src1{1to8}, dst {mask} {z}|dst {mask} {z}, src1{1to8}, src2}
|
Note
|
Properties: mayRaiseFPException |
VRNDSCALEPHZ128rmi [HasVLX, HasFP16]
vrndscaleph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VRNDSCALEPHZ128rmik [HasVLX, HasFP16]
vrndscaleph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRNDSCALEPHZ128rmikz [HasVLX, HasFP16]
vrndscaleph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VRNDSCALEPHZ128rri [HasVLX, HasFP16]
vrndscaleph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VRNDSCALEPHZ128rrik [HasVLX, HasFP16]
vrndscaleph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRNDSCALEPHZ128rrikz [HasVLX, HasFP16]
vrndscaleph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VRNDSCALEPHZ256rmbi [HasVLX, HasFP16]
vrndscaleph {src2, src1{1to16}, dst|dst, src1{1to16}, src2}
|
Note
|
Properties: mayRaiseFPException |
VRNDSCALEPHZ256rmbik [HasVLX, HasFP16]
vrndscaleph {src2, src1{1to16}, dst {mask}|dst {mask}, src1{1to16}, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRNDSCALEPHZ256rmbikz [HasVLX, HasFP16]
vrndscaleph {src2, src1{1to16}, dst {mask} {z}|dst {mask} {z}, src1{1to16}, src2}
|
Note
|
Properties: mayRaiseFPException |
VRNDSCALEPHZ256rmi [HasVLX, HasFP16]
vrndscaleph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VRNDSCALEPHZ256rmik [HasVLX, HasFP16]
vrndscaleph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRNDSCALEPHZ256rmikz [HasVLX, HasFP16]
vrndscaleph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VRNDSCALEPHZ256rri [HasVLX, HasFP16]
vrndscaleph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VRNDSCALEPHZ256rrik [HasVLX, HasFP16]
vrndscaleph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRNDSCALEPHZ256rrikz [HasVLX, HasFP16]
vrndscaleph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VRSQRTPHZ128m [HasVLX, HasFP16]
vrsqrtph {src, dst|dst, src}
VRSQRTPHZ128mb [HasVLX, HasFP16]
vrsqrtph {src{1to8}, dst|dst, src{1to8}}
VRSQRTPHZ128mbk [HasVLX, HasFP16]
vrsqrtph {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Constraints: src0 = dst |
VRSQRTPHZ128mbkz [HasVLX, HasFP16]
vrsqrtph {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
VRSQRTPHZ128mk [HasVLX, HasFP16]
vrsqrtph {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VRSQRTPHZ128mkz [HasVLX, HasFP16]
vrsqrtph {src, dst {mask} {z}|dst {mask} {z}, src}
VRSQRTPHZ128r [HasVLX, HasFP16]
vrsqrtph {src, dst|dst, src}
VRSQRTPHZ128rk [HasVLX, HasFP16]
vrsqrtph {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VRSQRTPHZ128rkz [HasVLX, HasFP16]
vrsqrtph {src, dst {mask} {z}|dst {mask} {z}, src}
VRSQRTPHZ256m [HasVLX, HasFP16]
vrsqrtph {src, dst|dst, src}
VRSQRTPHZ256mb [HasVLX, HasFP16]
vrsqrtph {src{1to16}, dst|dst, src{1to16}}
VRSQRTPHZ256mbk [HasVLX, HasFP16]
vrsqrtph {src{1to16}, dst {mask}|dst {mask}, src{1to16}}
|
Note
|
Constraints: src0 = dst |
VRSQRTPHZ256mbkz [HasVLX, HasFP16]
vrsqrtph {src{1to16}, dst {mask} {z}|dst {mask} {z}, src{1to16}}
VRSQRTPHZ256mk [HasVLX, HasFP16]
vrsqrtph {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VRSQRTPHZ256mkz [HasVLX, HasFP16]
vrsqrtph {src, dst {mask} {z}|dst {mask} {z}, src}
VRSQRTPHZ256r [HasVLX, HasFP16]
vrsqrtph {src, dst|dst, src}
VRSQRTPHZ256rk [HasVLX, HasFP16]
vrsqrtph {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VRSQRTPHZ256rkz [HasVLX, HasFP16]
vrsqrtph {src, dst {mask} {z}|dst {mask} {z}, src}
VSCALEFPHZ128rm [HasVLX, HasFP16]
vscalefph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSCALEFPHZ128rmb [HasVLX, HasFP16]
vscalefph {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VSCALEFPHZ128rmbk [HasVLX, HasFP16]
vscalefph {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSCALEFPHZ128rmbkz [HasVLX, HasFP16]
vscalefph {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VSCALEFPHZ128rmk [HasVLX, HasFP16]
vscalefph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSCALEFPHZ128rmkz [HasVLX, HasFP16]
vscalefph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSCALEFPHZ128rr [HasVLX, HasFP16]
vscalefph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSCALEFPHZ128rrk [HasVLX, HasFP16]
vscalefph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSCALEFPHZ128rrkz [HasVLX, HasFP16]
vscalefph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSCALEFPHZ256rm [HasVLX, HasFP16]
vscalefph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSCALEFPHZ256rmb [HasVLX, HasFP16]
vscalefph {src2{1to16}, src1, dst|dst, src1, src2{1to16}}
|
Note
|
Properties: mayRaiseFPException |
VSCALEFPHZ256rmbk [HasVLX, HasFP16]
vscalefph {src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSCALEFPHZ256rmbkz [HasVLX, HasFP16]
vscalefph {src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}}
|
Note
|
Properties: mayRaiseFPException |
VSCALEFPHZ256rmk [HasVLX, HasFP16]
vscalefph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSCALEFPHZ256rmkz [HasVLX, HasFP16]
vscalefph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSCALEFPHZ256rr [HasVLX, HasFP16]
vscalefph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSCALEFPHZ256rrk [HasVLX, HasFP16]
vscalefph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSCALEFPHZ256rrkz [HasVLX, HasFP16]
vscalefph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSQRTPHZ128m [HasVLX, HasFP16]
vsqrtph {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VSQRTPHZ128mb [HasVLX, HasFP16]
vsqrtph {src{1to8}, dst|dst, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VSQRTPHZ128mbk [HasVLX, HasFP16]
vsqrtph {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSQRTPHZ128mbkz [HasVLX, HasFP16]
vsqrtph {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VSQRTPHZ128mk [HasVLX, HasFP16]
vsqrtph {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSQRTPHZ128mkz [HasVLX, HasFP16]
vsqrtph {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VSQRTPHZ128r [HasVLX, HasFP16]
vsqrtph {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VSQRTPHZ128rk [HasVLX, HasFP16]
vsqrtph {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSQRTPHZ128rkz [HasVLX, HasFP16]
vsqrtph {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VSQRTPHZ256m [HasVLX, HasFP16]
vsqrtph {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VSQRTPHZ256mb [HasVLX, HasFP16]
vsqrtph {src{1to16}, dst|dst, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
VSQRTPHZ256mbk [HasVLX, HasFP16]
vsqrtph {src{1to16}, dst {mask}|dst {mask}, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSQRTPHZ256mbkz [HasVLX, HasFP16]
vsqrtph {src{1to16}, dst {mask} {z}|dst {mask} {z}, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
VSQRTPHZ256mk [HasVLX, HasFP16]
vsqrtph {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSQRTPHZ256mkz [HasVLX, HasFP16]
vsqrtph {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VSQRTPHZ256r [HasVLX, HasFP16]
vsqrtph {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VSQRTPHZ256rk [HasVLX, HasFP16]
vsqrtph {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSQRTPHZ256rkz [HasVLX, HasFP16]
vsqrtph {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VSUBPHZ128rm [HasVLX, HasFP16]
vsubph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VSUBPHZ128rmb [HasVLX, HasFP16]
vsubph {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VSUBPHZ128rmbk [HasVLX, HasFP16]
vsubph {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSUBPHZ128rmbkz [HasVLX, HasFP16]
vsubph {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VSUBPHZ128rmk [HasVLX, HasFP16]
vsubph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSUBPHZ128rmkz [HasVLX, HasFP16]
vsubph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VSUBPHZ128rr [HasVLX, HasFP16]
vsubph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSUBPHZ128rrk [HasVLX, HasFP16]
vsubph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSUBPHZ128rrkz [HasVLX, HasFP16]
vsubph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSUBPHZ256rm [HasVLX, HasFP16]
vsubph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VSUBPHZ256rmb [HasVLX, HasFP16]
vsubph {src2{1to16}, src1, dst|dst, src1, src2{1to16}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VSUBPHZ256rmbk [HasVLX, HasFP16]
vsubph {src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSUBPHZ256rmbkz [HasVLX, HasFP16]
vsubph {src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VSUBPHZ256rmk [HasVLX, HasFP16]
vsubph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSUBPHZ256rmkz [HasVLX, HasFP16]
vsubph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VSUBPHZ256rr [HasVLX, HasFP16]
vsubph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSUBPHZ256rrk [HasVLX, HasFP16]
vsubph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSUBPHZ256rrkz [HasVLX, HasFP16]
vsubph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMPSADBWZ128rmi [HasVLX, HasAVX10_2]
vmpsadbw {src3, src2, src1, dst|dst, src1, src2, src3}
VMPSADBWZ128rmik [HasVLX, HasAVX10_2]
vmpsadbw {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VMPSADBWZ128rmikz [HasVLX, HasAVX10_2]
vmpsadbw {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VMPSADBWZ128rri [HasVLX, HasAVX10_2]
vmpsadbw {src3, src2, src1, dst|dst, src1, src2, src3}
VMPSADBWZ128rrik [HasVLX, HasAVX10_2]
vmpsadbw {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VMPSADBWZ128rrikz [HasVLX, HasAVX10_2]
vmpsadbw {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VMPSADBWZ256rmi [HasVLX, HasAVX10_2]
vmpsadbw {src3, src2, src1, dst|dst, src1, src2, src3}
VMPSADBWZ256rmik [HasVLX, HasAVX10_2]
vmpsadbw {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VMPSADBWZ256rmikz [HasVLX, HasAVX10_2]
vmpsadbw {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VMPSADBWZ256rri [HasVLX, HasAVX10_2]
vmpsadbw {src3, src2, src1, dst|dst, src1, src2, src3}
VMPSADBWZ256rrik [HasVLX, HasAVX10_2]
vmpsadbw {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VMPSADBWZ256rrikz [HasVLX, HasAVX10_2]
vmpsadbw {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VDBPSADBWZ128rmi [HasVLX, HasBWI]
vdbpsadbw {src3, src2, src1, dst|dst, src1, src2, src3}
VDBPSADBWZ128rmik [HasVLX, HasBWI]
vdbpsadbw {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VDBPSADBWZ128rmikz [HasVLX, HasBWI]
vdbpsadbw {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VDBPSADBWZ128rri [HasVLX, HasBWI]
vdbpsadbw {src3, src2, src1, dst|dst, src1, src2, src3}
VDBPSADBWZ128rrik [HasVLX, HasBWI]
vdbpsadbw {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VDBPSADBWZ128rrikz [HasVLX, HasBWI]
vdbpsadbw {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VDBPSADBWZ256rmi [HasVLX, HasBWI]
vdbpsadbw {src3, src2, src1, dst|dst, src1, src2, src3}
VDBPSADBWZ256rmik [HasVLX, HasBWI]
vdbpsadbw {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VDBPSADBWZ256rmikz [HasVLX, HasBWI]
vdbpsadbw {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VDBPSADBWZ256rri [HasVLX, HasBWI]
vdbpsadbw {src3, src2, src1, dst|dst, src1, src2, src3}
VDBPSADBWZ256rrik [HasVLX, HasBWI]
vdbpsadbw {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VDBPSADBWZ256rrikz [HasVLX, HasBWI]
vdbpsadbw {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VMOVDQU16Z128mr [HasVLX, HasBWI]
vmovdqu16 {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VMOVDQU16Z128mrk [HasVLX, HasBWI]
vmovdqu16 {src, dst {mask}|dst {mask}, src}
VMOVDQU16Z128rm [HasVLX, HasBWI]
vmovdqu16 {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
VMOVDQU16Z128rmk [HasVLX, HasBWI]
vmovdqu16 {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVDQU16Z128rmkz [HasVLX, HasBWI]
vmovdqu16 {src, dst {mask} {z}|dst {mask} {z}, src}
VMOVDQU16Z128rr [HasVLX, HasBWI]
vmovdqu16 {src, dst|dst, src}
|
Note
|
Properties: isMoveReg |
VMOVDQU16Z128rrk [HasVLX, HasBWI]
vmovdqu16 {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVDQU16Z128rrkz [HasVLX, HasBWI]
vmovdqu16 {src, dst {mask} {z}|dst {mask} {z}, src}
VMOVDQU16Z256mr [HasVLX, HasBWI]
vmovdqu16 {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VMOVDQU16Z256mrk [HasVLX, HasBWI]
vmovdqu16 {src, dst {mask}|dst {mask}, src}
VMOVDQU16Z256rm [HasVLX, HasBWI]
vmovdqu16 {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
VMOVDQU16Z256rmk [HasVLX, HasBWI]
vmovdqu16 {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVDQU16Z256rmkz [HasVLX, HasBWI]
vmovdqu16 {src, dst {mask} {z}|dst {mask} {z}, src}
VMOVDQU16Z256rr [HasVLX, HasBWI]
vmovdqu16 {src, dst|dst, src}
|
Note
|
Properties: isMoveReg |
VMOVDQU16Z256rrk [HasVLX, HasBWI]
vmovdqu16 {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVDQU16Z256rrkz [HasVLX, HasBWI]
vmovdqu16 {src, dst {mask} {z}|dst {mask} {z}, src}
VMOVDQU8Z128mr [HasVLX, HasBWI]
vmovdqu8 {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VMOVDQU8Z128mrk [HasVLX, HasBWI]
vmovdqu8 {src, dst {mask}|dst {mask}, src}
VMOVDQU8Z128rm [HasVLX, HasBWI]
vmovdqu8 {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
VMOVDQU8Z128rmk [HasVLX, HasBWI]
vmovdqu8 {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVDQU8Z128rmkz [HasVLX, HasBWI]
vmovdqu8 {src, dst {mask} {z}|dst {mask} {z}, src}
VMOVDQU8Z128rr [HasVLX, HasBWI]
vmovdqu8 {src, dst|dst, src}
|
Note
|
Properties: isMoveReg |
VMOVDQU8Z128rrk [HasVLX, HasBWI]
vmovdqu8 {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVDQU8Z128rrkz [HasVLX, HasBWI]
vmovdqu8 {src, dst {mask} {z}|dst {mask} {z}, src}
VMOVDQU8Z256mr [HasVLX, HasBWI]
vmovdqu8 {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VMOVDQU8Z256mrk [HasVLX, HasBWI]
vmovdqu8 {src, dst {mask}|dst {mask}, src}
VMOVDQU8Z256rm [HasVLX, HasBWI]
vmovdqu8 {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
VMOVDQU8Z256rmk [HasVLX, HasBWI]
vmovdqu8 {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVDQU8Z256rmkz [HasVLX, HasBWI]
vmovdqu8 {src, dst {mask} {z}|dst {mask} {z}, src}
VMOVDQU8Z256rr [HasVLX, HasBWI]
vmovdqu8 {src, dst|dst, src}
|
Note
|
Properties: isMoveReg |
VMOVDQU8Z256rrk [HasVLX, HasBWI]
vmovdqu8 {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVDQU8Z256rrkz [HasVLX, HasBWI]
vmovdqu8 {src, dst {mask} {z}|dst {mask} {z}, src}
VPABSBZ128rm [HasVLX, HasBWI]
vpabsb {src1, dst|dst, src1}
VPABSBZ128rmk [HasVLX, HasBWI]
vpabsb {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPABSBZ128rmkz [HasVLX, HasBWI]
vpabsb {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPABSBZ128rr [HasVLX, HasBWI]
vpabsb {src1, dst|dst, src1}
VPABSBZ128rrk [HasVLX, HasBWI]
vpabsb {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPABSBZ128rrkz [HasVLX, HasBWI]
vpabsb {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPABSBZ256rm [HasVLX, HasBWI]
vpabsb {src1, dst|dst, src1}
VPABSBZ256rmk [HasVLX, HasBWI]
vpabsb {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPABSBZ256rmkz [HasVLX, HasBWI]
vpabsb {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPABSBZ256rr [HasVLX, HasBWI]
vpabsb {src1, dst|dst, src1}
VPABSBZ256rrk [HasVLX, HasBWI]
vpabsb {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPABSBZ256rrkz [HasVLX, HasBWI]
vpabsb {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPABSWZ128rm [HasVLX, HasBWI]
vpabsw {src1, dst|dst, src1}
VPABSWZ128rmk [HasVLX, HasBWI]
vpabsw {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPABSWZ128rmkz [HasVLX, HasBWI]
vpabsw {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPABSWZ128rr [HasVLX, HasBWI]
vpabsw {src1, dst|dst, src1}
VPABSWZ128rrk [HasVLX, HasBWI]
vpabsw {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPABSWZ128rrkz [HasVLX, HasBWI]
vpabsw {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPABSWZ256rm [HasVLX, HasBWI]
vpabsw {src1, dst|dst, src1}
VPABSWZ256rmk [HasVLX, HasBWI]
vpabsw {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPABSWZ256rmkz [HasVLX, HasBWI]
vpabsw {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPABSWZ256rr [HasVLX, HasBWI]
vpabsw {src1, dst|dst, src1}
VPABSWZ256rrk [HasVLX, HasBWI]
vpabsw {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPABSWZ256rrkz [HasVLX, HasBWI]
vpabsw {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPACKSSDWZ128rm [HasVLX, HasBWI]
vpackssdw {src2, src1, dst|dst, src1, src2}
VPACKSSDWZ128rmb [HasVLX, HasBWI]
vpackssdw {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
VPACKSSDWZ128rmbk [HasVLX, HasBWI]
vpackssdw {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Constraints: src0 = dst |
VPACKSSDWZ128rmbkz [HasVLX, HasBWI]
vpackssdw {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
VPACKSSDWZ128rmk [HasVLX, HasBWI]
vpackssdw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPACKSSDWZ128rmkz [HasVLX, HasBWI]
vpackssdw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPACKSSDWZ128rr [HasVLX, HasBWI]
vpackssdw {src2, src1, dst|dst, src1, src2}
VPACKSSDWZ128rrk [HasVLX, HasBWI]
vpackssdw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPACKSSDWZ128rrkz [HasVLX, HasBWI]
vpackssdw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPACKSSDWZ256rm [HasVLX, HasBWI]
vpackssdw {src2, src1, dst|dst, src1, src2}
VPACKSSDWZ256rmb [HasVLX, HasBWI]
vpackssdw {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
VPACKSSDWZ256rmbk [HasVLX, HasBWI]
vpackssdw {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Constraints: src0 = dst |
VPACKSSDWZ256rmbkz [HasVLX, HasBWI]
vpackssdw {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
VPACKSSDWZ256rmk [HasVLX, HasBWI]
vpackssdw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPACKSSDWZ256rmkz [HasVLX, HasBWI]
vpackssdw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPACKSSDWZ256rr [HasVLX, HasBWI]
vpackssdw {src2, src1, dst|dst, src1, src2}
VPACKSSDWZ256rrk [HasVLX, HasBWI]
vpackssdw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPACKSSDWZ256rrkz [HasVLX, HasBWI]
vpackssdw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPACKSSWBZ128rm [HasVLX, HasBWI]
vpacksswb {src2, src1, dst|dst, src1, src2}
VPACKSSWBZ128rmk [HasVLX, HasBWI]
vpacksswb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPACKSSWBZ128rmkz [HasVLX, HasBWI]
vpacksswb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPACKSSWBZ128rr [HasVLX, HasBWI]
vpacksswb {src2, src1, dst|dst, src1, src2}
VPACKSSWBZ128rrk [HasVLX, HasBWI]
vpacksswb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPACKSSWBZ128rrkz [HasVLX, HasBWI]
vpacksswb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPACKSSWBZ256rm [HasVLX, HasBWI]
vpacksswb {src2, src1, dst|dst, src1, src2}
VPACKSSWBZ256rmk [HasVLX, HasBWI]
vpacksswb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPACKSSWBZ256rmkz [HasVLX, HasBWI]
vpacksswb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPACKSSWBZ256rr [HasVLX, HasBWI]
vpacksswb {src2, src1, dst|dst, src1, src2}
VPACKSSWBZ256rrk [HasVLX, HasBWI]
vpacksswb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPACKSSWBZ256rrkz [HasVLX, HasBWI]
vpacksswb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPACKUSDWZ128rm [HasVLX, HasBWI]
vpackusdw {src2, src1, dst|dst, src1, src2}
VPACKUSDWZ128rmb [HasVLX, HasBWI]
vpackusdw {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
VPACKUSDWZ128rmbk [HasVLX, HasBWI]
vpackusdw {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Constraints: src0 = dst |
VPACKUSDWZ128rmbkz [HasVLX, HasBWI]
vpackusdw {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
VPACKUSDWZ128rmk [HasVLX, HasBWI]
vpackusdw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPACKUSDWZ128rmkz [HasVLX, HasBWI]
vpackusdw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPACKUSDWZ128rr [HasVLX, HasBWI]
vpackusdw {src2, src1, dst|dst, src1, src2}
VPACKUSDWZ128rrk [HasVLX, HasBWI]
vpackusdw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPACKUSDWZ128rrkz [HasVLX, HasBWI]
vpackusdw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPACKUSDWZ256rm [HasVLX, HasBWI]
vpackusdw {src2, src1, dst|dst, src1, src2}
VPACKUSDWZ256rmb [HasVLX, HasBWI]
vpackusdw {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
VPACKUSDWZ256rmbk [HasVLX, HasBWI]
vpackusdw {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Constraints: src0 = dst |
VPACKUSDWZ256rmbkz [HasVLX, HasBWI]
vpackusdw {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
VPACKUSDWZ256rmk [HasVLX, HasBWI]
vpackusdw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPACKUSDWZ256rmkz [HasVLX, HasBWI]
vpackusdw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPACKUSDWZ256rr [HasVLX, HasBWI]
vpackusdw {src2, src1, dst|dst, src1, src2}
VPACKUSDWZ256rrk [HasVLX, HasBWI]
vpackusdw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPACKUSDWZ256rrkz [HasVLX, HasBWI]
vpackusdw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPACKUSWBZ128rm [HasVLX, HasBWI]
vpackuswb {src2, src1, dst|dst, src1, src2}
VPACKUSWBZ128rmk [HasVLX, HasBWI]
vpackuswb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPACKUSWBZ128rmkz [HasVLX, HasBWI]
vpackuswb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPACKUSWBZ128rr [HasVLX, HasBWI]
vpackuswb {src2, src1, dst|dst, src1, src2}
VPACKUSWBZ128rrk [HasVLX, HasBWI]
vpackuswb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPACKUSWBZ128rrkz [HasVLX, HasBWI]
vpackuswb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPACKUSWBZ256rm [HasVLX, HasBWI]
vpackuswb {src2, src1, dst|dst, src1, src2}
VPACKUSWBZ256rmk [HasVLX, HasBWI]
vpackuswb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPACKUSWBZ256rmkz [HasVLX, HasBWI]
vpackuswb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPACKUSWBZ256rr [HasVLX, HasBWI]
vpackuswb {src2, src1, dst|dst, src1, src2}
VPACKUSWBZ256rrk [HasVLX, HasBWI]
vpackuswb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPACKUSWBZ256rrkz [HasVLX, HasBWI]
vpackuswb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPADDBZ128rm [HasVLX, HasBWI]
vpaddb {src2, src1, dst|dst, src1, src2}
VPADDBZ128rmk [HasVLX, HasBWI]
vpaddb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPADDBZ128rmkz [HasVLX, HasBWI]
vpaddb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPADDBZ128rr [HasVLX, HasBWI]
vpaddb {src2, src1, dst|dst, src1, src2}
VPADDBZ128rrk [HasVLX, HasBWI]
vpaddb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPADDBZ128rrkz [HasVLX, HasBWI]
vpaddb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPADDBZ256rm [HasVLX, HasBWI]
vpaddb {src2, src1, dst|dst, src1, src2}
VPADDBZ256rmk [HasVLX, HasBWI]
vpaddb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPADDBZ256rmkz [HasVLX, HasBWI]
vpaddb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPADDBZ256rr [HasVLX, HasBWI]
vpaddb {src2, src1, dst|dst, src1, src2}
VPADDBZ256rrk [HasVLX, HasBWI]
vpaddb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPADDBZ256rrkz [HasVLX, HasBWI]
vpaddb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPADDSBZ128rm [HasVLX, HasBWI]
vpaddsb {src2, src1, dst|dst, src1, src2}
VPADDSBZ128rmk [HasVLX, HasBWI]
vpaddsb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPADDSBZ128rmkz [HasVLX, HasBWI]
vpaddsb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPADDSBZ128rr [HasVLX, HasBWI]
vpaddsb {src2, src1, dst|dst, src1, src2}
VPADDSBZ128rrk [HasVLX, HasBWI]
vpaddsb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPADDSBZ128rrkz [HasVLX, HasBWI]
vpaddsb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPADDSBZ256rm [HasVLX, HasBWI]
vpaddsb {src2, src1, dst|dst, src1, src2}
VPADDSBZ256rmk [HasVLX, HasBWI]
vpaddsb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPADDSBZ256rmkz [HasVLX, HasBWI]
vpaddsb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPADDSBZ256rr [HasVLX, HasBWI]
vpaddsb {src2, src1, dst|dst, src1, src2}
VPADDSBZ256rrk [HasVLX, HasBWI]
vpaddsb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPADDSBZ256rrkz [HasVLX, HasBWI]
vpaddsb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPADDSWZ128rm [HasVLX, HasBWI]
vpaddsw {src2, src1, dst|dst, src1, src2}
VPADDSWZ128rmk [HasVLX, HasBWI]
vpaddsw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPADDSWZ128rmkz [HasVLX, HasBWI]
vpaddsw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPADDSWZ128rr [HasVLX, HasBWI]
vpaddsw {src2, src1, dst|dst, src1, src2}
VPADDSWZ128rrk [HasVLX, HasBWI]
vpaddsw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPADDSWZ128rrkz [HasVLX, HasBWI]
vpaddsw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPADDSWZ256rm [HasVLX, HasBWI]
vpaddsw {src2, src1, dst|dst, src1, src2}
VPADDSWZ256rmk [HasVLX, HasBWI]
vpaddsw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPADDSWZ256rmkz [HasVLX, HasBWI]
vpaddsw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPADDSWZ256rr [HasVLX, HasBWI]
vpaddsw {src2, src1, dst|dst, src1, src2}
VPADDSWZ256rrk [HasVLX, HasBWI]
vpaddsw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPADDSWZ256rrkz [HasVLX, HasBWI]
vpaddsw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPADDUSBZ128rm [HasVLX, HasBWI]
vpaddusb {src2, src1, dst|dst, src1, src2}
VPADDUSBZ128rmk [HasVLX, HasBWI]
vpaddusb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPADDUSBZ128rmkz [HasVLX, HasBWI]
vpaddusb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPADDUSBZ128rr [HasVLX, HasBWI]
vpaddusb {src2, src1, dst|dst, src1, src2}
VPADDUSBZ128rrk [HasVLX, HasBWI]
vpaddusb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPADDUSBZ128rrkz [HasVLX, HasBWI]
vpaddusb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPADDUSBZ256rm [HasVLX, HasBWI]
vpaddusb {src2, src1, dst|dst, src1, src2}
VPADDUSBZ256rmk [HasVLX, HasBWI]
vpaddusb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPADDUSBZ256rmkz [HasVLX, HasBWI]
vpaddusb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPADDUSBZ256rr [HasVLX, HasBWI]
vpaddusb {src2, src1, dst|dst, src1, src2}
VPADDUSBZ256rrk [HasVLX, HasBWI]
vpaddusb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPADDUSBZ256rrkz [HasVLX, HasBWI]
vpaddusb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPADDUSWZ128rm [HasVLX, HasBWI]
vpaddusw {src2, src1, dst|dst, src1, src2}
VPADDUSWZ128rmk [HasVLX, HasBWI]
vpaddusw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPADDUSWZ128rmkz [HasVLX, HasBWI]
vpaddusw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPADDUSWZ128rr [HasVLX, HasBWI]
vpaddusw {src2, src1, dst|dst, src1, src2}
VPADDUSWZ128rrk [HasVLX, HasBWI]
vpaddusw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPADDUSWZ128rrkz [HasVLX, HasBWI]
vpaddusw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPADDUSWZ256rm [HasVLX, HasBWI]
vpaddusw {src2, src1, dst|dst, src1, src2}
VPADDUSWZ256rmk [HasVLX, HasBWI]
vpaddusw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPADDUSWZ256rmkz [HasVLX, HasBWI]
vpaddusw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPADDUSWZ256rr [HasVLX, HasBWI]
vpaddusw {src2, src1, dst|dst, src1, src2}
VPADDUSWZ256rrk [HasVLX, HasBWI]
vpaddusw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPADDUSWZ256rrkz [HasVLX, HasBWI]
vpaddusw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPADDWZ128rm [HasVLX, HasBWI]
vpaddw {src2, src1, dst|dst, src1, src2}
VPADDWZ128rmk [HasVLX, HasBWI]
vpaddw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPADDWZ128rmkz [HasVLX, HasBWI]
vpaddw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPADDWZ128rr [HasVLX, HasBWI]
vpaddw {src2, src1, dst|dst, src1, src2}
VPADDWZ128rrk [HasVLX, HasBWI]
vpaddw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPADDWZ128rrkz [HasVLX, HasBWI]
vpaddw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPADDWZ256rm [HasVLX, HasBWI]
vpaddw {src2, src1, dst|dst, src1, src2}
VPADDWZ256rmk [HasVLX, HasBWI]
vpaddw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPADDWZ256rmkz [HasVLX, HasBWI]
vpaddw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPADDWZ256rr [HasVLX, HasBWI]
vpaddw {src2, src1, dst|dst, src1, src2}
VPADDWZ256rrk [HasVLX, HasBWI]
vpaddw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPADDWZ256rrkz [HasVLX, HasBWI]
vpaddw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPALIGNRZ128rmi [HasVLX, HasBWI]
vpalignr {src3, src2, src1, dst|dst, src1, src2, src3}
VPALIGNRZ128rmik [HasVLX, HasBWI]
vpalignr {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VPALIGNRZ128rmikz [HasVLX, HasBWI]
vpalignr {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VPALIGNRZ128rri [HasVLX, HasBWI]
vpalignr {src3, src2, src1, dst|dst, src1, src2, src3}
VPALIGNRZ128rrik [HasVLX, HasBWI]
vpalignr {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VPALIGNRZ128rrikz [HasVLX, HasBWI]
vpalignr {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VPALIGNRZ256rmi [HasVLX, HasBWI]
vpalignr {src3, src2, src1, dst|dst, src1, src2, src3}
VPALIGNRZ256rmik [HasVLX, HasBWI]
vpalignr {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VPALIGNRZ256rmikz [HasVLX, HasBWI]
vpalignr {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VPALIGNRZ256rri [HasVLX, HasBWI]
vpalignr {src3, src2, src1, dst|dst, src1, src2, src3}
VPALIGNRZ256rrik [HasVLX, HasBWI]
vpalignr {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VPALIGNRZ256rrikz [HasVLX, HasBWI]
vpalignr {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VPAVGBZ128rm [HasVLX, HasBWI]
vpavgb {src2, src1, dst|dst, src1, src2}
VPAVGBZ128rmk [HasVLX, HasBWI]
vpavgb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPAVGBZ128rmkz [HasVLX, HasBWI]
vpavgb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPAVGBZ128rr [HasVLX, HasBWI]
vpavgb {src2, src1, dst|dst, src1, src2}
VPAVGBZ128rrk [HasVLX, HasBWI]
vpavgb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPAVGBZ128rrkz [HasVLX, HasBWI]
vpavgb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPAVGBZ256rm [HasVLX, HasBWI]
vpavgb {src2, src1, dst|dst, src1, src2}
VPAVGBZ256rmk [HasVLX, HasBWI]
vpavgb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPAVGBZ256rmkz [HasVLX, HasBWI]
vpavgb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPAVGBZ256rr [HasVLX, HasBWI]
vpavgb {src2, src1, dst|dst, src1, src2}
VPAVGBZ256rrk [HasVLX, HasBWI]
vpavgb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPAVGBZ256rrkz [HasVLX, HasBWI]
vpavgb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPAVGWZ128rm [HasVLX, HasBWI]
vpavgw {src2, src1, dst|dst, src1, src2}
VPAVGWZ128rmk [HasVLX, HasBWI]
vpavgw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPAVGWZ128rmkz [HasVLX, HasBWI]
vpavgw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPAVGWZ128rr [HasVLX, HasBWI]
vpavgw {src2, src1, dst|dst, src1, src2}
VPAVGWZ128rrk [HasVLX, HasBWI]
vpavgw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPAVGWZ128rrkz [HasVLX, HasBWI]
vpavgw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPAVGWZ256rm [HasVLX, HasBWI]
vpavgw {src2, src1, dst|dst, src1, src2}
VPAVGWZ256rmk [HasVLX, HasBWI]
vpavgw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPAVGWZ256rmkz [HasVLX, HasBWI]
vpavgw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPAVGWZ256rr [HasVLX, HasBWI]
vpavgw {src2, src1, dst|dst, src1, src2}
VPAVGWZ256rrk [HasVLX, HasBWI]
vpavgw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPAVGWZ256rrkz [HasVLX, HasBWI]
vpavgw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPBLENDMBZ128rm [HasVLX, HasBWI]
vpblendmb {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VPBLENDMBZ128rmk [HasVLX, HasBWI]
vpblendmb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
VPBLENDMBZ128rmkz [HasVLX, HasBWI]
vpblendmb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VPBLENDMBZ128rr [HasVLX, HasBWI]
vpblendmb {src2, src1, dst|dst, src1, src2}
VPBLENDMBZ128rrk [HasVLX, HasBWI]
vpblendmb {src2, src1, dst {mask}|dst {mask}, src1, src2}
VPBLENDMBZ128rrkz [HasVLX, HasBWI]
vpblendmb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPBLENDMBZ256rm [HasVLX, HasBWI]
vpblendmb {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VPBLENDMBZ256rmk [HasVLX, HasBWI]
vpblendmb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
VPBLENDMBZ256rmkz [HasVLX, HasBWI]
vpblendmb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VPBLENDMBZ256rr [HasVLX, HasBWI]
vpblendmb {src2, src1, dst|dst, src1, src2}
VPBLENDMBZ256rrk [HasVLX, HasBWI]
vpblendmb {src2, src1, dst {mask}|dst {mask}, src1, src2}
VPBLENDMBZ256rrkz [HasVLX, HasBWI]
vpblendmb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPBLENDMWZ128rm [HasVLX, HasBWI]
vpblendmw {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VPBLENDMWZ128rmk [HasVLX, HasBWI]
vpblendmw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
VPBLENDMWZ128rmkz [HasVLX, HasBWI]
vpblendmw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VPBLENDMWZ128rr [HasVLX, HasBWI]
vpblendmw {src2, src1, dst|dst, src1, src2}
VPBLENDMWZ128rrk [HasVLX, HasBWI]
vpblendmw {src2, src1, dst {mask}|dst {mask}, src1, src2}
VPBLENDMWZ128rrkz [HasVLX, HasBWI]
vpblendmw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPBLENDMWZ256rm [HasVLX, HasBWI]
vpblendmw {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VPBLENDMWZ256rmk [HasVLX, HasBWI]
vpblendmw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
VPBLENDMWZ256rmkz [HasVLX, HasBWI]
vpblendmw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VPBLENDMWZ256rr [HasVLX, HasBWI]
vpblendmw {src2, src1, dst|dst, src1, src2}
VPBLENDMWZ256rrk [HasVLX, HasBWI]
vpblendmw {src2, src1, dst {mask}|dst {mask}, src1, src2}
VPBLENDMWZ256rrkz [HasVLX, HasBWI]
vpblendmw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPBROADCASTBZ128rm [HasVLX, HasBWI]
vpbroadcastb {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
VPBROADCASTBZ128rmk [HasVLX, HasBWI]
vpbroadcastb {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPBROADCASTBZ128rmkz [HasVLX, HasBWI]
vpbroadcastb {src, dst {mask} {z}|dst {mask} {z}, src}
VPBROADCASTBZ128rr [HasVLX, HasBWI]
vpbroadcastb {src, dst|dst, src}
VPBROADCASTBZ128rrk [HasVLX, HasBWI]
vpbroadcastb {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPBROADCASTBZ128rrkz [HasVLX, HasBWI]
vpbroadcastb {src, dst {mask} {z}|dst {mask} {z}, src}
VPBROADCASTBZ256rm [HasVLX, HasBWI]
vpbroadcastb {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
VPBROADCASTBZ256rmk [HasVLX, HasBWI]
vpbroadcastb {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPBROADCASTBZ256rmkz [HasVLX, HasBWI]
vpbroadcastb {src, dst {mask} {z}|dst {mask} {z}, src}
VPBROADCASTBZ256rr [HasVLX, HasBWI]
vpbroadcastb {src, dst|dst, src}
VPBROADCASTBZ256rrk [HasVLX, HasBWI]
vpbroadcastb {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPBROADCASTBZ256rrkz [HasVLX, HasBWI]
vpbroadcastb {src, dst {mask} {z}|dst {mask} {z}, src}
VPBROADCASTBrZ128rr [HasVLX, HasBWI]
vpbroadcastb {src, dst|dst, src}
VPBROADCASTBrZ128rrk [HasVLX, HasBWI]
vpbroadcastb {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPBROADCASTBrZ128rrkz [HasVLX, HasBWI]
vpbroadcastb {src, dst {mask} {z}|dst {mask} {z}, src}
VPBROADCASTBrZ256rr [HasVLX, HasBWI]
vpbroadcastb {src, dst|dst, src}
VPBROADCASTBrZ256rrk [HasVLX, HasBWI]
vpbroadcastb {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPBROADCASTBrZ256rrkz [HasVLX, HasBWI]
vpbroadcastb {src, dst {mask} {z}|dst {mask} {z}, src}
VPBROADCASTWZ128rm [HasVLX, HasBWI]
vpbroadcastw {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
VPBROADCASTWZ128rmk [HasVLX, HasBWI]
vpbroadcastw {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPBROADCASTWZ128rmkz [HasVLX, HasBWI]
vpbroadcastw {src, dst {mask} {z}|dst {mask} {z}, src}
VPBROADCASTWZ128rr [HasVLX, HasBWI]
vpbroadcastw {src, dst|dst, src}
VPBROADCASTWZ128rrk [HasVLX, HasBWI]
vpbroadcastw {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPBROADCASTWZ128rrkz [HasVLX, HasBWI]
vpbroadcastw {src, dst {mask} {z}|dst {mask} {z}, src}
VPBROADCASTWZ256rm [HasVLX, HasBWI]
vpbroadcastw {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
VPBROADCASTWZ256rmk [HasVLX, HasBWI]
vpbroadcastw {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPBROADCASTWZ256rmkz [HasVLX, HasBWI]
vpbroadcastw {src, dst {mask} {z}|dst {mask} {z}, src}
VPBROADCASTWZ256rr [HasVLX, HasBWI]
vpbroadcastw {src, dst|dst, src}
VPBROADCASTWZ256rrk [HasVLX, HasBWI]
vpbroadcastw {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPBROADCASTWZ256rrkz [HasVLX, HasBWI]
vpbroadcastw {src, dst {mask} {z}|dst {mask} {z}, src}
VPBROADCASTWrZ128rr [HasVLX, HasBWI]
vpbroadcastw {src, dst|dst, src}
VPBROADCASTWrZ128rrk [HasVLX, HasBWI]
vpbroadcastw {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPBROADCASTWrZ128rrkz [HasVLX, HasBWI]
vpbroadcastw {src, dst {mask} {z}|dst {mask} {z}, src}
VPBROADCASTWrZ256rr [HasVLX, HasBWI]
vpbroadcastw {src, dst|dst, src}
VPBROADCASTWrZ256rrk [HasVLX, HasBWI]
vpbroadcastw {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPBROADCASTWrZ256rrkz [HasVLX, HasBWI]
vpbroadcastw {src, dst {mask} {z}|dst {mask} {z}, src}
VPCMPBZ128rmi [HasVLX, HasBWI]
vpcmpb {cc, src2, src1, dst|dst, src1, src2, cc}
VPCMPBZ128rmik [HasVLX, HasBWI]
vpcmpb {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
VPCMPBZ128rri [HasVLX, HasBWI]
vpcmpb {cc, src2, src1, dst|dst, src1, src2, cc}
VPCMPBZ128rrik [HasVLX, HasBWI]
vpcmpb {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
VPCMPBZ256rmi [HasVLX, HasBWI]
vpcmpb {cc, src2, src1, dst|dst, src1, src2, cc}
VPCMPBZ256rmik [HasVLX, HasBWI]
vpcmpb {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
VPCMPBZ256rri [HasVLX, HasBWI]
vpcmpb {cc, src2, src1, dst|dst, src1, src2, cc}
VPCMPBZ256rrik [HasVLX, HasBWI]
vpcmpb {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
VPCMPEQBZ128rm [HasVLX, HasBWI]
vpcmpeqb {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VPCMPEQBZ128rmk [HasVLX, HasBWI]
vpcmpeqb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
VPCMPEQBZ128rr [HasVLX, HasBWI]
vpcmpeqb {src2, src1, dst|dst, src1, src2}
VPCMPEQBZ128rrk [HasVLX, HasBWI]
vpcmpeqb {src2, src1, dst {mask}|dst {mask}, src1, src2}
VPCMPEQBZ256rm [HasVLX, HasBWI]
vpcmpeqb {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VPCMPEQBZ256rmk [HasVLX, HasBWI]
vpcmpeqb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
VPCMPEQBZ256rr [HasVLX, HasBWI]
vpcmpeqb {src2, src1, dst|dst, src1, src2}
VPCMPEQBZ256rrk [HasVLX, HasBWI]
vpcmpeqb {src2, src1, dst {mask}|dst {mask}, src1, src2}
VPCMPEQWZ128rm [HasVLX, HasBWI]
vpcmpeqw {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VPCMPEQWZ128rmk [HasVLX, HasBWI]
vpcmpeqw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
VPCMPEQWZ128rr [HasVLX, HasBWI]
vpcmpeqw {src2, src1, dst|dst, src1, src2}
VPCMPEQWZ128rrk [HasVLX, HasBWI]
vpcmpeqw {src2, src1, dst {mask}|dst {mask}, src1, src2}
VPCMPEQWZ256rm [HasVLX, HasBWI]
vpcmpeqw {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VPCMPEQWZ256rmk [HasVLX, HasBWI]
vpcmpeqw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
VPCMPEQWZ256rr [HasVLX, HasBWI]
vpcmpeqw {src2, src1, dst|dst, src1, src2}
VPCMPEQWZ256rrk [HasVLX, HasBWI]
vpcmpeqw {src2, src1, dst {mask}|dst {mask}, src1, src2}
VPCMPGTBZ128rm [HasVLX, HasBWI]
vpcmpgtb {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VPCMPGTBZ128rmk [HasVLX, HasBWI]
vpcmpgtb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
VPCMPGTBZ128rr [HasVLX, HasBWI]
vpcmpgtb {src2, src1, dst|dst, src1, src2}
VPCMPGTBZ128rrk [HasVLX, HasBWI]
vpcmpgtb {src2, src1, dst {mask}|dst {mask}, src1, src2}
VPCMPGTBZ256rm [HasVLX, HasBWI]
vpcmpgtb {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VPCMPGTBZ256rmk [HasVLX, HasBWI]
vpcmpgtb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
VPCMPGTBZ256rr [HasVLX, HasBWI]
vpcmpgtb {src2, src1, dst|dst, src1, src2}
VPCMPGTBZ256rrk [HasVLX, HasBWI]
vpcmpgtb {src2, src1, dst {mask}|dst {mask}, src1, src2}
VPCMPGTWZ128rm [HasVLX, HasBWI]
vpcmpgtw {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VPCMPGTWZ128rmk [HasVLX, HasBWI]
vpcmpgtw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
VPCMPGTWZ128rr [HasVLX, HasBWI]
vpcmpgtw {src2, src1, dst|dst, src1, src2}
VPCMPGTWZ128rrk [HasVLX, HasBWI]
vpcmpgtw {src2, src1, dst {mask}|dst {mask}, src1, src2}
VPCMPGTWZ256rm [HasVLX, HasBWI]
vpcmpgtw {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VPCMPGTWZ256rmk [HasVLX, HasBWI]
vpcmpgtw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
VPCMPGTWZ256rr [HasVLX, HasBWI]
vpcmpgtw {src2, src1, dst|dst, src1, src2}
VPCMPGTWZ256rrk [HasVLX, HasBWI]
vpcmpgtw {src2, src1, dst {mask}|dst {mask}, src1, src2}
VPCMPUBZ128rmi [HasVLX, HasBWI]
vpcmpub {cc, src2, src1, dst|dst, src1, src2, cc}
VPCMPUBZ128rmik [HasVLX, HasBWI]
vpcmpub {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
VPCMPUBZ128rri [HasVLX, HasBWI]
vpcmpub {cc, src2, src1, dst|dst, src1, src2, cc}
VPCMPUBZ128rrik [HasVLX, HasBWI]
vpcmpub {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
VPCMPUBZ256rmi [HasVLX, HasBWI]
vpcmpub {cc, src2, src1, dst|dst, src1, src2, cc}
VPCMPUBZ256rmik [HasVLX, HasBWI]
vpcmpub {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
VPCMPUBZ256rri [HasVLX, HasBWI]
vpcmpub {cc, src2, src1, dst|dst, src1, src2, cc}
VPCMPUBZ256rrik [HasVLX, HasBWI]
vpcmpub {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
VPCMPUWZ128rmi [HasVLX, HasBWI]
vpcmpuw {cc, src2, src1, dst|dst, src1, src2, cc}
VPCMPUWZ128rmik [HasVLX, HasBWI]
vpcmpuw {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
VPCMPUWZ128rri [HasVLX, HasBWI]
vpcmpuw {cc, src2, src1, dst|dst, src1, src2, cc}
VPCMPUWZ128rrik [HasVLX, HasBWI]
vpcmpuw {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
VPCMPUWZ256rmi [HasVLX, HasBWI]
vpcmpuw {cc, src2, src1, dst|dst, src1, src2, cc}
VPCMPUWZ256rmik [HasVLX, HasBWI]
vpcmpuw {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
VPCMPUWZ256rri [HasVLX, HasBWI]
vpcmpuw {cc, src2, src1, dst|dst, src1, src2, cc}
VPCMPUWZ256rrik [HasVLX, HasBWI]
vpcmpuw {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
VPCMPWZ128rmi [HasVLX, HasBWI]
vpcmpw {cc, src2, src1, dst|dst, src1, src2, cc}
VPCMPWZ128rmik [HasVLX, HasBWI]
vpcmpw {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
VPCMPWZ128rri [HasVLX, HasBWI]
vpcmpw {cc, src2, src1, dst|dst, src1, src2, cc}
VPCMPWZ128rrik [HasVLX, HasBWI]
vpcmpw {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
VPCMPWZ256rmi [HasVLX, HasBWI]
vpcmpw {cc, src2, src1, dst|dst, src1, src2, cc}
VPCMPWZ256rmik [HasVLX, HasBWI]
vpcmpw {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
VPCMPWZ256rri [HasVLX, HasBWI]
vpcmpw {cc, src2, src1, dst|dst, src1, src2, cc}
VPCMPWZ256rrik [HasVLX, HasBWI]
vpcmpw {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
VPERMI2WZ128rm [HasVLX, HasBWI]
vpermi2w {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2WZ128rmk [HasVLX, HasBWI]
vpermi2w {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2WZ128rmkz [HasVLX, HasBWI]
vpermi2w {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2WZ128rr [HasVLX, HasBWI]
vpermi2w {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMI2WZ128rrk [HasVLX, HasBWI]
vpermi2w {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMI2WZ128rrkz [HasVLX, HasBWI]
vpermi2w {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMI2WZ256rm [HasVLX, HasBWI]
vpermi2w {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2WZ256rmk [HasVLX, HasBWI]
vpermi2w {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2WZ256rmkz [HasVLX, HasBWI]
vpermi2w {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2WZ256rr [HasVLX, HasBWI]
vpermi2w {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMI2WZ256rrk [HasVLX, HasBWI]
vpermi2w {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMI2WZ256rrkz [HasVLX, HasBWI]
vpermi2w {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2WZ128rm [HasVLX, HasBWI]
vpermt2w {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2WZ128rmk [HasVLX, HasBWI]
vpermt2w {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2WZ128rmkz [HasVLX, HasBWI]
vpermt2w {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2WZ128rr [HasVLX, HasBWI]
vpermt2w {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2WZ128rrk [HasVLX, HasBWI]
vpermt2w {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2WZ128rrkz [HasVLX, HasBWI]
vpermt2w {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2WZ256rm [HasVLX, HasBWI]
vpermt2w {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2WZ256rmk [HasVLX, HasBWI]
vpermt2w {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2WZ256rmkz [HasVLX, HasBWI]
vpermt2w {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2WZ256rr [HasVLX, HasBWI]
vpermt2w {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2WZ256rrk [HasVLX, HasBWI]
vpermt2w {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2WZ256rrkz [HasVLX, HasBWI]
vpermt2w {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMWZ128rm [HasVLX, HasBWI]
vpermw {src2, src1, dst|dst, src1, src2}
VPERMWZ128rmk [HasVLX, HasBWI]
vpermw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPERMWZ128rmkz [HasVLX, HasBWI]
vpermw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPERMWZ128rr [HasVLX, HasBWI]
vpermw {src2, src1, dst|dst, src1, src2}
VPERMWZ128rrk [HasVLX, HasBWI]
vpermw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPERMWZ128rrkz [HasVLX, HasBWI]
vpermw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPERMWZ256rm [HasVLX, HasBWI]
vpermw {src2, src1, dst|dst, src1, src2}
VPERMWZ256rmk [HasVLX, HasBWI]
vpermw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPERMWZ256rmkz [HasVLX, HasBWI]
vpermw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPERMWZ256rr [HasVLX, HasBWI]
vpermw {src2, src1, dst|dst, src1, src2}
VPERMWZ256rrk [HasVLX, HasBWI]
vpermw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPERMWZ256rrkz [HasVLX, HasBWI]
vpermw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMADDUBSWZ128rm [HasVLX, HasBWI]
vpmaddubsw {src2, src1, dst|dst, src1, src2}
VPMADDUBSWZ128rmk [HasVLX, HasBWI]
vpmaddubsw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMADDUBSWZ128rmkz [HasVLX, HasBWI]
vpmaddubsw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMADDUBSWZ128rr [HasVLX, HasBWI]
vpmaddubsw {src2, src1, dst|dst, src1, src2}
VPMADDUBSWZ128rrk [HasVLX, HasBWI]
vpmaddubsw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMADDUBSWZ128rrkz [HasVLX, HasBWI]
vpmaddubsw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMADDUBSWZ256rm [HasVLX, HasBWI]
vpmaddubsw {src2, src1, dst|dst, src1, src2}
VPMADDUBSWZ256rmk [HasVLX, HasBWI]
vpmaddubsw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMADDUBSWZ256rmkz [HasVLX, HasBWI]
vpmaddubsw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMADDUBSWZ256rr [HasVLX, HasBWI]
vpmaddubsw {src2, src1, dst|dst, src1, src2}
VPMADDUBSWZ256rrk [HasVLX, HasBWI]
vpmaddubsw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMADDUBSWZ256rrkz [HasVLX, HasBWI]
vpmaddubsw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMADDWDZ128rm [HasVLX, HasBWI]
vpmaddwd {src2, src1, dst|dst, src1, src2}
VPMADDWDZ128rmk [HasVLX, HasBWI]
vpmaddwd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMADDWDZ128rmkz [HasVLX, HasBWI]
vpmaddwd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMADDWDZ128rr [HasVLX, HasBWI]
vpmaddwd {src2, src1, dst|dst, src1, src2}
VPMADDWDZ128rrk [HasVLX, HasBWI]
vpmaddwd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMADDWDZ128rrkz [HasVLX, HasBWI]
vpmaddwd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMADDWDZ256rm [HasVLX, HasBWI]
vpmaddwd {src2, src1, dst|dst, src1, src2}
VPMADDWDZ256rmk [HasVLX, HasBWI]
vpmaddwd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMADDWDZ256rmkz [HasVLX, HasBWI]
vpmaddwd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMADDWDZ256rr [HasVLX, HasBWI]
vpmaddwd {src2, src1, dst|dst, src1, src2}
VPMADDWDZ256rrk [HasVLX, HasBWI]
vpmaddwd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMADDWDZ256rrkz [HasVLX, HasBWI]
vpmaddwd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMAXSBZ128rm [HasVLX, HasBWI]
vpmaxsb {src2, src1, dst|dst, src1, src2}
VPMAXSBZ128rmk [HasVLX, HasBWI]
vpmaxsb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMAXSBZ128rmkz [HasVLX, HasBWI]
vpmaxsb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMAXSBZ128rr [HasVLX, HasBWI]
vpmaxsb {src2, src1, dst|dst, src1, src2}
VPMAXSBZ128rrk [HasVLX, HasBWI]
vpmaxsb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMAXSBZ128rrkz [HasVLX, HasBWI]
vpmaxsb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMAXSBZ256rm [HasVLX, HasBWI]
vpmaxsb {src2, src1, dst|dst, src1, src2}
VPMAXSBZ256rmk [HasVLX, HasBWI]
vpmaxsb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMAXSBZ256rmkz [HasVLX, HasBWI]
vpmaxsb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMAXSBZ256rr [HasVLX, HasBWI]
vpmaxsb {src2, src1, dst|dst, src1, src2}
VPMAXSBZ256rrk [HasVLX, HasBWI]
vpmaxsb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMAXSBZ256rrkz [HasVLX, HasBWI]
vpmaxsb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMAXSWZ128rm [HasVLX, HasBWI]
vpmaxsw {src2, src1, dst|dst, src1, src2}
VPMAXSWZ128rmk [HasVLX, HasBWI]
vpmaxsw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMAXSWZ128rmkz [HasVLX, HasBWI]
vpmaxsw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMAXSWZ128rr [HasVLX, HasBWI]
vpmaxsw {src2, src1, dst|dst, src1, src2}
VPMAXSWZ128rrk [HasVLX, HasBWI]
vpmaxsw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMAXSWZ128rrkz [HasVLX, HasBWI]
vpmaxsw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMAXSWZ256rm [HasVLX, HasBWI]
vpmaxsw {src2, src1, dst|dst, src1, src2}
VPMAXSWZ256rmk [HasVLX, HasBWI]
vpmaxsw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMAXSWZ256rmkz [HasVLX, HasBWI]
vpmaxsw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMAXSWZ256rr [HasVLX, HasBWI]
vpmaxsw {src2, src1, dst|dst, src1, src2}
VPMAXSWZ256rrk [HasVLX, HasBWI]
vpmaxsw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMAXSWZ256rrkz [HasVLX, HasBWI]
vpmaxsw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMAXUBZ128rm [HasVLX, HasBWI]
vpmaxub {src2, src1, dst|dst, src1, src2}
VPMAXUBZ128rmk [HasVLX, HasBWI]
vpmaxub {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMAXUBZ128rmkz [HasVLX, HasBWI]
vpmaxub {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMAXUBZ128rr [HasVLX, HasBWI]
vpmaxub {src2, src1, dst|dst, src1, src2}
VPMAXUBZ128rrk [HasVLX, HasBWI]
vpmaxub {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMAXUBZ128rrkz [HasVLX, HasBWI]
vpmaxub {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMAXUBZ256rm [HasVLX, HasBWI]
vpmaxub {src2, src1, dst|dst, src1, src2}
VPMAXUBZ256rmk [HasVLX, HasBWI]
vpmaxub {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMAXUBZ256rmkz [HasVLX, HasBWI]
vpmaxub {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMAXUBZ256rr [HasVLX, HasBWI]
vpmaxub {src2, src1, dst|dst, src1, src2}
VPMAXUBZ256rrk [HasVLX, HasBWI]
vpmaxub {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMAXUBZ256rrkz [HasVLX, HasBWI]
vpmaxub {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMAXUWZ128rm [HasVLX, HasBWI]
vpmaxuw {src2, src1, dst|dst, src1, src2}
VPMAXUWZ128rmk [HasVLX, HasBWI]
vpmaxuw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMAXUWZ128rmkz [HasVLX, HasBWI]
vpmaxuw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMAXUWZ128rr [HasVLX, HasBWI]
vpmaxuw {src2, src1, dst|dst, src1, src2}
VPMAXUWZ128rrk [HasVLX, HasBWI]
vpmaxuw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMAXUWZ128rrkz [HasVLX, HasBWI]
vpmaxuw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMAXUWZ256rm [HasVLX, HasBWI]
vpmaxuw {src2, src1, dst|dst, src1, src2}
VPMAXUWZ256rmk [HasVLX, HasBWI]
vpmaxuw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMAXUWZ256rmkz [HasVLX, HasBWI]
vpmaxuw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMAXUWZ256rr [HasVLX, HasBWI]
vpmaxuw {src2, src1, dst|dst, src1, src2}
VPMAXUWZ256rrk [HasVLX, HasBWI]
vpmaxuw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMAXUWZ256rrkz [HasVLX, HasBWI]
vpmaxuw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMINSBZ128rm [HasVLX, HasBWI]
vpminsb {src2, src1, dst|dst, src1, src2}
VPMINSBZ128rmk [HasVLX, HasBWI]
vpminsb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMINSBZ128rmkz [HasVLX, HasBWI]
vpminsb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMINSBZ128rr [HasVLX, HasBWI]
vpminsb {src2, src1, dst|dst, src1, src2}
VPMINSBZ128rrk [HasVLX, HasBWI]
vpminsb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMINSBZ128rrkz [HasVLX, HasBWI]
vpminsb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMINSBZ256rm [HasVLX, HasBWI]
vpminsb {src2, src1, dst|dst, src1, src2}
VPMINSBZ256rmk [HasVLX, HasBWI]
vpminsb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMINSBZ256rmkz [HasVLX, HasBWI]
vpminsb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMINSBZ256rr [HasVLX, HasBWI]
vpminsb {src2, src1, dst|dst, src1, src2}
VPMINSBZ256rrk [HasVLX, HasBWI]
vpminsb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMINSBZ256rrkz [HasVLX, HasBWI]
vpminsb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMINSWZ128rm [HasVLX, HasBWI]
vpminsw {src2, src1, dst|dst, src1, src2}
VPMINSWZ128rmk [HasVLX, HasBWI]
vpminsw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMINSWZ128rmkz [HasVLX, HasBWI]
vpminsw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMINSWZ128rr [HasVLX, HasBWI]
vpminsw {src2, src1, dst|dst, src1, src2}
VPMINSWZ128rrk [HasVLX, HasBWI]
vpminsw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMINSWZ128rrkz [HasVLX, HasBWI]
vpminsw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMINSWZ256rm [HasVLX, HasBWI]
vpminsw {src2, src1, dst|dst, src1, src2}
VPMINSWZ256rmk [HasVLX, HasBWI]
vpminsw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMINSWZ256rmkz [HasVLX, HasBWI]
vpminsw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMINSWZ256rr [HasVLX, HasBWI]
vpminsw {src2, src1, dst|dst, src1, src2}
VPMINSWZ256rrk [HasVLX, HasBWI]
vpminsw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMINSWZ256rrkz [HasVLX, HasBWI]
vpminsw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMINUBZ128rm [HasVLX, HasBWI]
vpminub {src2, src1, dst|dst, src1, src2}
VPMINUBZ128rmk [HasVLX, HasBWI]
vpminub {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMINUBZ128rmkz [HasVLX, HasBWI]
vpminub {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMINUBZ128rr [HasVLX, HasBWI]
vpminub {src2, src1, dst|dst, src1, src2}
VPMINUBZ128rrk [HasVLX, HasBWI]
vpminub {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMINUBZ128rrkz [HasVLX, HasBWI]
vpminub {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMINUBZ256rm [HasVLX, HasBWI]
vpminub {src2, src1, dst|dst, src1, src2}
VPMINUBZ256rmk [HasVLX, HasBWI]
vpminub {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMINUBZ256rmkz [HasVLX, HasBWI]
vpminub {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMINUBZ256rr [HasVLX, HasBWI]
vpminub {src2, src1, dst|dst, src1, src2}
VPMINUBZ256rrk [HasVLX, HasBWI]
vpminub {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMINUBZ256rrkz [HasVLX, HasBWI]
vpminub {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMINUWZ128rm [HasVLX, HasBWI]
vpminuw {src2, src1, dst|dst, src1, src2}
VPMINUWZ128rmk [HasVLX, HasBWI]
vpminuw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMINUWZ128rmkz [HasVLX, HasBWI]
vpminuw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMINUWZ128rr [HasVLX, HasBWI]
vpminuw {src2, src1, dst|dst, src1, src2}
VPMINUWZ128rrk [HasVLX, HasBWI]
vpminuw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMINUWZ128rrkz [HasVLX, HasBWI]
vpminuw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMINUWZ256rm [HasVLX, HasBWI]
vpminuw {src2, src1, dst|dst, src1, src2}
VPMINUWZ256rmk [HasVLX, HasBWI]
vpminuw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMINUWZ256rmkz [HasVLX, HasBWI]
vpminuw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMINUWZ256rr [HasVLX, HasBWI]
vpminuw {src2, src1, dst|dst, src1, src2}
VPMINUWZ256rrk [HasVLX, HasBWI]
vpminuw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMINUWZ256rrkz [HasVLX, HasBWI]
vpminuw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMOVB2MZ128kr [HasVLX, HasBWI]
vpmovb2m {src, dst|dst, src}
VPMOVB2MZ256kr [HasVLX, HasBWI]
vpmovb2m {src, dst|dst, src}
VPMOVM2BZ128rk [HasVLX, HasBWI]
vpmovm2b {src, dst|dst, src}
VPMOVM2BZ256rk [HasVLX, HasBWI]
vpmovm2b {src, dst|dst, src}
VPMOVM2WZ128rk [HasVLX, HasBWI]
vpmovm2w {src, dst|dst, src}
VPMOVM2WZ256rk [HasVLX, HasBWI]
vpmovm2w {src, dst|dst, src}
VPMOVSWBZ128mr [HasVLX, HasBWI]
vpmovswb {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VPMOVSWBZ128mrk [HasVLX, HasBWI]
vpmovswb {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
VPMOVSWBZ128rr [HasVLX, HasBWI]
vpmovswb {src, dst|dst, src}
VPMOVSWBZ128rrk [HasVLX, HasBWI]
vpmovswb {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVSWBZ128rrkz [HasVLX, HasBWI]
vpmovswb {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVSWBZ256mr [HasVLX, HasBWI]
vpmovswb {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VPMOVSWBZ256mrk [HasVLX, HasBWI]
vpmovswb {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
VPMOVSWBZ256rr [HasVLX, HasBWI]
vpmovswb {src, dst|dst, src}
VPMOVSWBZ256rrk [HasVLX, HasBWI]
vpmovswb {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVSWBZ256rrkz [HasVLX, HasBWI]
vpmovswb {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVSXBWZ128rm [HasVLX, HasBWI]
vpmovsxbw {src, dst|dst, src}
VPMOVSXBWZ128rmk [HasVLX, HasBWI]
vpmovsxbw {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVSXBWZ128rmkz [HasVLX, HasBWI]
vpmovsxbw {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVSXBWZ128rr [HasVLX, HasBWI]
vpmovsxbw {src, dst|dst, src}
VPMOVSXBWZ128rrk [HasVLX, HasBWI]
vpmovsxbw {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVSXBWZ128rrkz [HasVLX, HasBWI]
vpmovsxbw {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVSXBWZ256rm [HasVLX, HasBWI]
vpmovsxbw {src, dst|dst, src}
VPMOVSXBWZ256rmk [HasVLX, HasBWI]
vpmovsxbw {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVSXBWZ256rmkz [HasVLX, HasBWI]
vpmovsxbw {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVSXBWZ256rr [HasVLX, HasBWI]
vpmovsxbw {src, dst|dst, src}
VPMOVSXBWZ256rrk [HasVLX, HasBWI]
vpmovsxbw {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVSXBWZ256rrkz [HasVLX, HasBWI]
vpmovsxbw {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVUSWBZ128mr [HasVLX, HasBWI]
vpmovuswb {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VPMOVUSWBZ128mrk [HasVLX, HasBWI]
vpmovuswb {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
VPMOVUSWBZ128rr [HasVLX, HasBWI]
vpmovuswb {src, dst|dst, src}
VPMOVUSWBZ128rrk [HasVLX, HasBWI]
vpmovuswb {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVUSWBZ128rrkz [HasVLX, HasBWI]
vpmovuswb {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVUSWBZ256mr [HasVLX, HasBWI]
vpmovuswb {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VPMOVUSWBZ256mrk [HasVLX, HasBWI]
vpmovuswb {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
VPMOVUSWBZ256rr [HasVLX, HasBWI]
vpmovuswb {src, dst|dst, src}
VPMOVUSWBZ256rrk [HasVLX, HasBWI]
vpmovuswb {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVUSWBZ256rrkz [HasVLX, HasBWI]
vpmovuswb {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVW2MZ128kr [HasVLX, HasBWI]
vpmovw2m {src, dst|dst, src}
VPMOVW2MZ256kr [HasVLX, HasBWI]
vpmovw2m {src, dst|dst, src}
VPMOVWBZ128mr [HasVLX, HasBWI]
vpmovwb {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VPMOVWBZ128mrk [HasVLX, HasBWI]
vpmovwb {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
VPMOVWBZ128rr [HasVLX, HasBWI]
vpmovwb {src, dst|dst, src}
VPMOVWBZ128rrk [HasVLX, HasBWI]
vpmovwb {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVWBZ128rrkz [HasVLX, HasBWI]
vpmovwb {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVWBZ256mr [HasVLX, HasBWI]
vpmovwb {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VPMOVWBZ256mrk [HasVLX, HasBWI]
vpmovwb {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
VPMOVWBZ256rr [HasVLX, HasBWI]
vpmovwb {src, dst|dst, src}
VPMOVWBZ256rrk [HasVLX, HasBWI]
vpmovwb {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVWBZ256rrkz [HasVLX, HasBWI]
vpmovwb {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVZXBWZ128rm [HasVLX, HasBWI]
vpmovzxbw {src, dst|dst, src}
VPMOVZXBWZ128rmk [HasVLX, HasBWI]
vpmovzxbw {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVZXBWZ128rmkz [HasVLX, HasBWI]
vpmovzxbw {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVZXBWZ128rr [HasVLX, HasBWI]
vpmovzxbw {src, dst|dst, src}
VPMOVZXBWZ128rrk [HasVLX, HasBWI]
vpmovzxbw {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVZXBWZ128rrkz [HasVLX, HasBWI]
vpmovzxbw {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVZXBWZ256rm [HasVLX, HasBWI]
vpmovzxbw {src, dst|dst, src}
VPMOVZXBWZ256rmk [HasVLX, HasBWI]
vpmovzxbw {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVZXBWZ256rmkz [HasVLX, HasBWI]
vpmovzxbw {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVZXBWZ256rr [HasVLX, HasBWI]
vpmovzxbw {src, dst|dst, src}
VPMOVZXBWZ256rrk [HasVLX, HasBWI]
vpmovzxbw {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVZXBWZ256rrkz [HasVLX, HasBWI]
vpmovzxbw {src, dst {mask} {z}|dst {mask} {z}, src}
VPMULHRSWZ128rm [HasVLX, HasBWI]
vpmulhrsw {src2, src1, dst|dst, src1, src2}
VPMULHRSWZ128rmk [HasVLX, HasBWI]
vpmulhrsw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMULHRSWZ128rmkz [HasVLX, HasBWI]
vpmulhrsw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMULHRSWZ128rr [HasVLX, HasBWI]
vpmulhrsw {src2, src1, dst|dst, src1, src2}
VPMULHRSWZ128rrk [HasVLX, HasBWI]
vpmulhrsw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMULHRSWZ128rrkz [HasVLX, HasBWI]
vpmulhrsw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMULHRSWZ256rm [HasVLX, HasBWI]
vpmulhrsw {src2, src1, dst|dst, src1, src2}
VPMULHRSWZ256rmk [HasVLX, HasBWI]
vpmulhrsw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMULHRSWZ256rmkz [HasVLX, HasBWI]
vpmulhrsw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMULHRSWZ256rr [HasVLX, HasBWI]
vpmulhrsw {src2, src1, dst|dst, src1, src2}
VPMULHRSWZ256rrk [HasVLX, HasBWI]
vpmulhrsw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMULHRSWZ256rrkz [HasVLX, HasBWI]
vpmulhrsw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMULHUWZ128rm [HasVLX, HasBWI]
vpmulhuw {src2, src1, dst|dst, src1, src2}
VPMULHUWZ128rmk [HasVLX, HasBWI]
vpmulhuw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMULHUWZ128rmkz [HasVLX, HasBWI]
vpmulhuw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMULHUWZ128rr [HasVLX, HasBWI]
vpmulhuw {src2, src1, dst|dst, src1, src2}
VPMULHUWZ128rrk [HasVLX, HasBWI]
vpmulhuw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMULHUWZ128rrkz [HasVLX, HasBWI]
vpmulhuw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMULHUWZ256rm [HasVLX, HasBWI]
vpmulhuw {src2, src1, dst|dst, src1, src2}
VPMULHUWZ256rmk [HasVLX, HasBWI]
vpmulhuw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMULHUWZ256rmkz [HasVLX, HasBWI]
vpmulhuw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMULHUWZ256rr [HasVLX, HasBWI]
vpmulhuw {src2, src1, dst|dst, src1, src2}
VPMULHUWZ256rrk [HasVLX, HasBWI]
vpmulhuw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMULHUWZ256rrkz [HasVLX, HasBWI]
vpmulhuw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMULHWZ128rm [HasVLX, HasBWI]
vpmulhw {src2, src1, dst|dst, src1, src2}
VPMULHWZ128rmk [HasVLX, HasBWI]
vpmulhw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMULHWZ128rmkz [HasVLX, HasBWI]
vpmulhw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMULHWZ128rr [HasVLX, HasBWI]
vpmulhw {src2, src1, dst|dst, src1, src2}
VPMULHWZ128rrk [HasVLX, HasBWI]
vpmulhw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMULHWZ128rrkz [HasVLX, HasBWI]
vpmulhw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMULHWZ256rm [HasVLX, HasBWI]
vpmulhw {src2, src1, dst|dst, src1, src2}
VPMULHWZ256rmk [HasVLX, HasBWI]
vpmulhw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMULHWZ256rmkz [HasVLX, HasBWI]
vpmulhw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMULHWZ256rr [HasVLX, HasBWI]
vpmulhw {src2, src1, dst|dst, src1, src2}
VPMULHWZ256rrk [HasVLX, HasBWI]
vpmulhw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMULHWZ256rrkz [HasVLX, HasBWI]
vpmulhw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMULLWZ128rm [HasVLX, HasBWI]
vpmullw {src2, src1, dst|dst, src1, src2}
VPMULLWZ128rmk [HasVLX, HasBWI]
vpmullw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMULLWZ128rmkz [HasVLX, HasBWI]
vpmullw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMULLWZ128rr [HasVLX, HasBWI]
vpmullw {src2, src1, dst|dst, src1, src2}
VPMULLWZ128rrk [HasVLX, HasBWI]
vpmullw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMULLWZ128rrkz [HasVLX, HasBWI]
vpmullw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMULLWZ256rm [HasVLX, HasBWI]
vpmullw {src2, src1, dst|dst, src1, src2}
VPMULLWZ256rmk [HasVLX, HasBWI]
vpmullw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMULLWZ256rmkz [HasVLX, HasBWI]
vpmullw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMULLWZ256rr [HasVLX, HasBWI]
vpmullw {src2, src1, dst|dst, src1, src2}
VPMULLWZ256rrk [HasVLX, HasBWI]
vpmullw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMULLWZ256rrkz [HasVLX, HasBWI]
vpmullw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSADBWZ128rm [HasVLX, HasBWI]
vpsadbw {src2, src1, dst|dst, src1, src2}
VPSADBWZ128rr [HasVLX, HasBWI]
vpsadbw {src2, src1, dst|dst, src1, src2}
VPSADBWZ256rm [HasVLX, HasBWI]
vpsadbw {src2, src1, dst|dst, src1, src2}
VPSADBWZ256rr [HasVLX, HasBWI]
vpsadbw {src2, src1, dst|dst, src1, src2}
VPSHUFBZ128rm [HasVLX, HasBWI]
vpshufb {src2, src1, dst|dst, src1, src2}
VPSHUFBZ128rmk [HasVLX, HasBWI]
vpshufb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSHUFBZ128rmkz [HasVLX, HasBWI]
vpshufb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSHUFBZ128rr [HasVLX, HasBWI]
vpshufb {src2, src1, dst|dst, src1, src2}
VPSHUFBZ128rrk [HasVLX, HasBWI]
vpshufb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSHUFBZ128rrkz [HasVLX, HasBWI]
vpshufb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSHUFBZ256rm [HasVLX, HasBWI]
vpshufb {src2, src1, dst|dst, src1, src2}
VPSHUFBZ256rmk [HasVLX, HasBWI]
vpshufb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSHUFBZ256rmkz [HasVLX, HasBWI]
vpshufb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSHUFBZ256rr [HasVLX, HasBWI]
vpshufb {src2, src1, dst|dst, src1, src2}
VPSHUFBZ256rrk [HasVLX, HasBWI]
vpshufb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSHUFBZ256rrkz [HasVLX, HasBWI]
vpshufb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSHUFHWZ128mi [HasVLX, HasBWI]
vpshufhw {src2, src1, dst|dst, src1, src2}
VPSHUFHWZ128mik [HasVLX, HasBWI]
vpshufhw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSHUFHWZ128mikz [HasVLX, HasBWI]
vpshufhw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSHUFHWZ128ri [HasVLX, HasBWI]
vpshufhw {src2, src1, dst|dst, src1, src2}
VPSHUFHWZ128rik [HasVLX, HasBWI]
vpshufhw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSHUFHWZ128rikz [HasVLX, HasBWI]
vpshufhw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSHUFHWZ256mi [HasVLX, HasBWI]
vpshufhw {src2, src1, dst|dst, src1, src2}
VPSHUFHWZ256mik [HasVLX, HasBWI]
vpshufhw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSHUFHWZ256mikz [HasVLX, HasBWI]
vpshufhw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSHUFHWZ256ri [HasVLX, HasBWI]
vpshufhw {src2, src1, dst|dst, src1, src2}
VPSHUFHWZ256rik [HasVLX, HasBWI]
vpshufhw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSHUFHWZ256rikz [HasVLX, HasBWI]
vpshufhw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSHUFLWZ128mi [HasVLX, HasBWI]
vpshuflw {src2, src1, dst|dst, src1, src2}
VPSHUFLWZ128mik [HasVLX, HasBWI]
vpshuflw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSHUFLWZ128mikz [HasVLX, HasBWI]
vpshuflw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSHUFLWZ128ri [HasVLX, HasBWI]
vpshuflw {src2, src1, dst|dst, src1, src2}
VPSHUFLWZ128rik [HasVLX, HasBWI]
vpshuflw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSHUFLWZ128rikz [HasVLX, HasBWI]
vpshuflw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSHUFLWZ256mi [HasVLX, HasBWI]
vpshuflw {src2, src1, dst|dst, src1, src2}
VPSHUFLWZ256mik [HasVLX, HasBWI]
vpshuflw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSHUFLWZ256mikz [HasVLX, HasBWI]
vpshuflw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSHUFLWZ256ri [HasVLX, HasBWI]
vpshuflw {src2, src1, dst|dst, src1, src2}
VPSHUFLWZ256rik [HasVLX, HasBWI]
vpshuflw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSHUFLWZ256rikz [HasVLX, HasBWI]
vpshuflw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSLLDQZ128mi [HasVLX, HasBWI]
vpslldq {src2, src1, dst|dst, src1, src2}
VPSLLDQZ128ri [HasVLX, HasBWI]
vpslldq {src2, src1, dst|dst, src1, src2}
VPSLLDQZ256mi [HasVLX, HasBWI]
vpslldq {src2, src1, dst|dst, src1, src2}
VPSLLDQZ256ri [HasVLX, HasBWI]
vpslldq {src2, src1, dst|dst, src1, src2}
VPSLLVWZ128rm [HasVLX, HasBWI]
vpsllvw {src2, src1, dst|dst, src1, src2}
VPSLLVWZ128rmk [HasVLX, HasBWI]
vpsllvw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSLLVWZ128rmkz [HasVLX, HasBWI]
vpsllvw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSLLVWZ128rr [HasVLX, HasBWI]
vpsllvw {src2, src1, dst|dst, src1, src2}
VPSLLVWZ128rrk [HasVLX, HasBWI]
vpsllvw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSLLVWZ128rrkz [HasVLX, HasBWI]
vpsllvw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSLLVWZ256rm [HasVLX, HasBWI]
vpsllvw {src2, src1, dst|dst, src1, src2}
VPSLLVWZ256rmk [HasVLX, HasBWI]
vpsllvw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSLLVWZ256rmkz [HasVLX, HasBWI]
vpsllvw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSLLVWZ256rr [HasVLX, HasBWI]
vpsllvw {src2, src1, dst|dst, src1, src2}
VPSLLVWZ256rrk [HasVLX, HasBWI]
vpsllvw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSLLVWZ256rrkz [HasVLX, HasBWI]
vpsllvw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSLLWZ128mi [HasVLX, HasBWI]
vpsllw {src2, src1, dst|dst, src1, src2}
VPSLLWZ128mik [HasVLX, HasBWI]
vpsllw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSLLWZ128mikz [HasVLX, HasBWI]
vpsllw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSLLWZ128ri [HasVLX, HasBWI]
vpsllw {src2, src1, dst|dst, src1, src2}
VPSLLWZ128rik [HasVLX, HasBWI]
vpsllw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSLLWZ128rikz [HasVLX, HasBWI]
vpsllw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSLLWZ128rm [HasVLX, HasBWI]
vpsllw {src2, src1, dst|dst, src1, src2}
VPSLLWZ128rmk [HasVLX, HasBWI]
vpsllw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSLLWZ128rmkz [HasVLX, HasBWI]
vpsllw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSLLWZ128rr [HasVLX, HasBWI]
vpsllw {src2, src1, dst|dst, src1, src2}
VPSLLWZ128rrk [HasVLX, HasBWI]
vpsllw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSLLWZ128rrkz [HasVLX, HasBWI]
vpsllw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSLLWZ256mi [HasVLX, HasBWI]
vpsllw {src2, src1, dst|dst, src1, src2}
VPSLLWZ256mik [HasVLX, HasBWI]
vpsllw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSLLWZ256mikz [HasVLX, HasBWI]
vpsllw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSLLWZ256ri [HasVLX, HasBWI]
vpsllw {src2, src1, dst|dst, src1, src2}
VPSLLWZ256rik [HasVLX, HasBWI]
vpsllw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSLLWZ256rikz [HasVLX, HasBWI]
vpsllw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSLLWZ256rm [HasVLX, HasBWI]
vpsllw {src2, src1, dst|dst, src1, src2}
VPSLLWZ256rmk [HasVLX, HasBWI]
vpsllw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSLLWZ256rmkz [HasVLX, HasBWI]
vpsllw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSLLWZ256rr [HasVLX, HasBWI]
vpsllw {src2, src1, dst|dst, src1, src2}
VPSLLWZ256rrk [HasVLX, HasBWI]
vpsllw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSLLWZ256rrkz [HasVLX, HasBWI]
vpsllw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRAVWZ128rm [HasVLX, HasBWI]
vpsravw {src2, src1, dst|dst, src1, src2}
VPSRAVWZ128rmk [HasVLX, HasBWI]
vpsravw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRAVWZ128rmkz [HasVLX, HasBWI]
vpsravw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRAVWZ128rr [HasVLX, HasBWI]
vpsravw {src2, src1, dst|dst, src1, src2}
VPSRAVWZ128rrk [HasVLX, HasBWI]
vpsravw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRAVWZ128rrkz [HasVLX, HasBWI]
vpsravw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRAVWZ256rm [HasVLX, HasBWI]
vpsravw {src2, src1, dst|dst, src1, src2}
VPSRAVWZ256rmk [HasVLX, HasBWI]
vpsravw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRAVWZ256rmkz [HasVLX, HasBWI]
vpsravw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRAVWZ256rr [HasVLX, HasBWI]
vpsravw {src2, src1, dst|dst, src1, src2}
VPSRAVWZ256rrk [HasVLX, HasBWI]
vpsravw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRAVWZ256rrkz [HasVLX, HasBWI]
vpsravw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRAWZ128mi [HasVLX, HasBWI]
vpsraw {src2, src1, dst|dst, src1, src2}
VPSRAWZ128mik [HasVLX, HasBWI]
vpsraw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRAWZ128mikz [HasVLX, HasBWI]
vpsraw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRAWZ128ri [HasVLX, HasBWI]
vpsraw {src2, src1, dst|dst, src1, src2}
VPSRAWZ128rik [HasVLX, HasBWI]
vpsraw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRAWZ128rikz [HasVLX, HasBWI]
vpsraw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRAWZ128rm [HasVLX, HasBWI]
vpsraw {src2, src1, dst|dst, src1, src2}
VPSRAWZ128rmk [HasVLX, HasBWI]
vpsraw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRAWZ128rmkz [HasVLX, HasBWI]
vpsraw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRAWZ128rr [HasVLX, HasBWI]
vpsraw {src2, src1, dst|dst, src1, src2}
VPSRAWZ128rrk [HasVLX, HasBWI]
vpsraw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRAWZ128rrkz [HasVLX, HasBWI]
vpsraw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRAWZ256mi [HasVLX, HasBWI]
vpsraw {src2, src1, dst|dst, src1, src2}
VPSRAWZ256mik [HasVLX, HasBWI]
vpsraw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRAWZ256mikz [HasVLX, HasBWI]
vpsraw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRAWZ256ri [HasVLX, HasBWI]
vpsraw {src2, src1, dst|dst, src1, src2}
VPSRAWZ256rik [HasVLX, HasBWI]
vpsraw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRAWZ256rikz [HasVLX, HasBWI]
vpsraw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRAWZ256rm [HasVLX, HasBWI]
vpsraw {src2, src1, dst|dst, src1, src2}
VPSRAWZ256rmk [HasVLX, HasBWI]
vpsraw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRAWZ256rmkz [HasVLX, HasBWI]
vpsraw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRAWZ256rr [HasVLX, HasBWI]
vpsraw {src2, src1, dst|dst, src1, src2}
VPSRAWZ256rrk [HasVLX, HasBWI]
vpsraw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRAWZ256rrkz [HasVLX, HasBWI]
vpsraw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRLDQZ128mi [HasVLX, HasBWI]
vpsrldq {src2, src1, dst|dst, src1, src2}
VPSRLDQZ128ri [HasVLX, HasBWI]
vpsrldq {src2, src1, dst|dst, src1, src2}
VPSRLDQZ256mi [HasVLX, HasBWI]
vpsrldq {src2, src1, dst|dst, src1, src2}
VPSRLDQZ256ri [HasVLX, HasBWI]
vpsrldq {src2, src1, dst|dst, src1, src2}
VPSRLVWZ128rm [HasVLX, HasBWI]
vpsrlvw {src2, src1, dst|dst, src1, src2}
VPSRLVWZ128rmk [HasVLX, HasBWI]
vpsrlvw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRLVWZ128rmkz [HasVLX, HasBWI]
vpsrlvw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRLVWZ128rr [HasVLX, HasBWI]
vpsrlvw {src2, src1, dst|dst, src1, src2}
VPSRLVWZ128rrk [HasVLX, HasBWI]
vpsrlvw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRLVWZ128rrkz [HasVLX, HasBWI]
vpsrlvw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRLVWZ256rm [HasVLX, HasBWI]
vpsrlvw {src2, src1, dst|dst, src1, src2}
VPSRLVWZ256rmk [HasVLX, HasBWI]
vpsrlvw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRLVWZ256rmkz [HasVLX, HasBWI]
vpsrlvw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRLVWZ256rr [HasVLX, HasBWI]
vpsrlvw {src2, src1, dst|dst, src1, src2}
VPSRLVWZ256rrk [HasVLX, HasBWI]
vpsrlvw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRLVWZ256rrkz [HasVLX, HasBWI]
vpsrlvw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRLWZ128mi [HasVLX, HasBWI]
vpsrlw {src2, src1, dst|dst, src1, src2}
VPSRLWZ128mik [HasVLX, HasBWI]
vpsrlw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRLWZ128mikz [HasVLX, HasBWI]
vpsrlw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRLWZ128ri [HasVLX, HasBWI]
vpsrlw {src2, src1, dst|dst, src1, src2}
VPSRLWZ128rik [HasVLX, HasBWI]
vpsrlw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRLWZ128rikz [HasVLX, HasBWI]
vpsrlw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRLWZ128rm [HasVLX, HasBWI]
vpsrlw {src2, src1, dst|dst, src1, src2}
VPSRLWZ128rmk [HasVLX, HasBWI]
vpsrlw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRLWZ128rmkz [HasVLX, HasBWI]
vpsrlw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRLWZ128rr [HasVLX, HasBWI]
vpsrlw {src2, src1, dst|dst, src1, src2}
VPSRLWZ128rrk [HasVLX, HasBWI]
vpsrlw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRLWZ128rrkz [HasVLX, HasBWI]
vpsrlw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRLWZ256mi [HasVLX, HasBWI]
vpsrlw {src2, src1, dst|dst, src1, src2}
VPSRLWZ256mik [HasVLX, HasBWI]
vpsrlw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRLWZ256mikz [HasVLX, HasBWI]
vpsrlw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRLWZ256ri [HasVLX, HasBWI]
vpsrlw {src2, src1, dst|dst, src1, src2}
VPSRLWZ256rik [HasVLX, HasBWI]
vpsrlw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRLWZ256rikz [HasVLX, HasBWI]
vpsrlw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRLWZ256rm [HasVLX, HasBWI]
vpsrlw {src2, src1, dst|dst, src1, src2}
VPSRLWZ256rmk [HasVLX, HasBWI]
vpsrlw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRLWZ256rmkz [HasVLX, HasBWI]
vpsrlw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRLWZ256rr [HasVLX, HasBWI]
vpsrlw {src2, src1, dst|dst, src1, src2}
VPSRLWZ256rrk [HasVLX, HasBWI]
vpsrlw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRLWZ256rrkz [HasVLX, HasBWI]
vpsrlw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSUBBZ128rm [HasVLX, HasBWI]
vpsubb {src2, src1, dst|dst, src1, src2}
VPSUBBZ128rmk [HasVLX, HasBWI]
vpsubb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSUBBZ128rmkz [HasVLX, HasBWI]
vpsubb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSUBBZ128rr [HasVLX, HasBWI]
vpsubb {src2, src1, dst|dst, src1, src2}
VPSUBBZ128rrk [HasVLX, HasBWI]
vpsubb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSUBBZ128rrkz [HasVLX, HasBWI]
vpsubb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSUBBZ256rm [HasVLX, HasBWI]
vpsubb {src2, src1, dst|dst, src1, src2}
VPSUBBZ256rmk [HasVLX, HasBWI]
vpsubb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSUBBZ256rmkz [HasVLX, HasBWI]
vpsubb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSUBBZ256rr [HasVLX, HasBWI]
vpsubb {src2, src1, dst|dst, src1, src2}
VPSUBBZ256rrk [HasVLX, HasBWI]
vpsubb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSUBBZ256rrkz [HasVLX, HasBWI]
vpsubb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSUBSBZ128rm [HasVLX, HasBWI]
vpsubsb {src2, src1, dst|dst, src1, src2}
VPSUBSBZ128rmk [HasVLX, HasBWI]
vpsubsb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSUBSBZ128rmkz [HasVLX, HasBWI]
vpsubsb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSUBSBZ128rr [HasVLX, HasBWI]
vpsubsb {src2, src1, dst|dst, src1, src2}
VPSUBSBZ128rrk [HasVLX, HasBWI]
vpsubsb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSUBSBZ128rrkz [HasVLX, HasBWI]
vpsubsb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSUBSBZ256rm [HasVLX, HasBWI]
vpsubsb {src2, src1, dst|dst, src1, src2}
VPSUBSBZ256rmk [HasVLX, HasBWI]
vpsubsb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSUBSBZ256rmkz [HasVLX, HasBWI]
vpsubsb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSUBSBZ256rr [HasVLX, HasBWI]
vpsubsb {src2, src1, dst|dst, src1, src2}
VPSUBSBZ256rrk [HasVLX, HasBWI]
vpsubsb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSUBSBZ256rrkz [HasVLX, HasBWI]
vpsubsb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSUBSWZ128rm [HasVLX, HasBWI]
vpsubsw {src2, src1, dst|dst, src1, src2}
VPSUBSWZ128rmk [HasVLX, HasBWI]
vpsubsw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSUBSWZ128rmkz [HasVLX, HasBWI]
vpsubsw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSUBSWZ128rr [HasVLX, HasBWI]
vpsubsw {src2, src1, dst|dst, src1, src2}
VPSUBSWZ128rrk [HasVLX, HasBWI]
vpsubsw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSUBSWZ128rrkz [HasVLX, HasBWI]
vpsubsw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSUBSWZ256rm [HasVLX, HasBWI]
vpsubsw {src2, src1, dst|dst, src1, src2}
VPSUBSWZ256rmk [HasVLX, HasBWI]
vpsubsw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSUBSWZ256rmkz [HasVLX, HasBWI]
vpsubsw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSUBSWZ256rr [HasVLX, HasBWI]
vpsubsw {src2, src1, dst|dst, src1, src2}
VPSUBSWZ256rrk [HasVLX, HasBWI]
vpsubsw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSUBSWZ256rrkz [HasVLX, HasBWI]
vpsubsw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSUBUSBZ128rm [HasVLX, HasBWI]
vpsubusb {src2, src1, dst|dst, src1, src2}
VPSUBUSBZ128rmk [HasVLX, HasBWI]
vpsubusb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSUBUSBZ128rmkz [HasVLX, HasBWI]
vpsubusb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSUBUSBZ128rr [HasVLX, HasBWI]
vpsubusb {src2, src1, dst|dst, src1, src2}
VPSUBUSBZ128rrk [HasVLX, HasBWI]
vpsubusb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSUBUSBZ128rrkz [HasVLX, HasBWI]
vpsubusb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSUBUSBZ256rm [HasVLX, HasBWI]
vpsubusb {src2, src1, dst|dst, src1, src2}
VPSUBUSBZ256rmk [HasVLX, HasBWI]
vpsubusb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSUBUSBZ256rmkz [HasVLX, HasBWI]
vpsubusb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSUBUSBZ256rr [HasVLX, HasBWI]
vpsubusb {src2, src1, dst|dst, src1, src2}
VPSUBUSBZ256rrk [HasVLX, HasBWI]
vpsubusb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSUBUSBZ256rrkz [HasVLX, HasBWI]
vpsubusb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSUBUSWZ128rm [HasVLX, HasBWI]
vpsubusw {src2, src1, dst|dst, src1, src2}
VPSUBUSWZ128rmk [HasVLX, HasBWI]
vpsubusw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSUBUSWZ128rmkz [HasVLX, HasBWI]
vpsubusw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSUBUSWZ128rr [HasVLX, HasBWI]
vpsubusw {src2, src1, dst|dst, src1, src2}
VPSUBUSWZ128rrk [HasVLX, HasBWI]
vpsubusw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSUBUSWZ128rrkz [HasVLX, HasBWI]
vpsubusw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSUBUSWZ256rm [HasVLX, HasBWI]
vpsubusw {src2, src1, dst|dst, src1, src2}
VPSUBUSWZ256rmk [HasVLX, HasBWI]
vpsubusw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSUBUSWZ256rmkz [HasVLX, HasBWI]
vpsubusw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSUBUSWZ256rr [HasVLX, HasBWI]
vpsubusw {src2, src1, dst|dst, src1, src2}
VPSUBUSWZ256rrk [HasVLX, HasBWI]
vpsubusw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSUBUSWZ256rrkz [HasVLX, HasBWI]
vpsubusw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSUBWZ128rm [HasVLX, HasBWI]
vpsubw {src2, src1, dst|dst, src1, src2}
VPSUBWZ128rmk [HasVLX, HasBWI]
vpsubw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSUBWZ128rmkz [HasVLX, HasBWI]
vpsubw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSUBWZ128rr [HasVLX, HasBWI]
vpsubw {src2, src1, dst|dst, src1, src2}
VPSUBWZ128rrk [HasVLX, HasBWI]
vpsubw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSUBWZ128rrkz [HasVLX, HasBWI]
vpsubw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSUBWZ256rm [HasVLX, HasBWI]
vpsubw {src2, src1, dst|dst, src1, src2}
VPSUBWZ256rmk [HasVLX, HasBWI]
vpsubw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSUBWZ256rmkz [HasVLX, HasBWI]
vpsubw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSUBWZ256rr [HasVLX, HasBWI]
vpsubw {src2, src1, dst|dst, src1, src2}
VPSUBWZ256rrk [HasVLX, HasBWI]
vpsubw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSUBWZ256rrkz [HasVLX, HasBWI]
vpsubw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPTESTMBZ128rm [HasVLX, HasBWI]
vptestmb {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VPTESTMBZ128rmk [HasVLX, HasBWI]
vptestmb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
VPTESTMBZ128rr [HasVLX, HasBWI]
vptestmb {src2, src1, dst|dst, src1, src2}
VPTESTMBZ128rrk [HasVLX, HasBWI]
vptestmb {src2, src1, dst {mask}|dst {mask}, src1, src2}
VPTESTMBZ256rm [HasVLX, HasBWI]
vptestmb {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VPTESTMBZ256rmk [HasVLX, HasBWI]
vptestmb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
VPTESTMBZ256rr [HasVLX, HasBWI]
vptestmb {src2, src1, dst|dst, src1, src2}
VPTESTMBZ256rrk [HasVLX, HasBWI]
vptestmb {src2, src1, dst {mask}|dst {mask}, src1, src2}
VPTESTMWZ128rm [HasVLX, HasBWI]
vptestmw {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VPTESTMWZ128rmk [HasVLX, HasBWI]
vptestmw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
VPTESTMWZ128rr [HasVLX, HasBWI]
vptestmw {src2, src1, dst|dst, src1, src2}
VPTESTMWZ128rrk [HasVLX, HasBWI]
vptestmw {src2, src1, dst {mask}|dst {mask}, src1, src2}
VPTESTMWZ256rm [HasVLX, HasBWI]
vptestmw {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VPTESTMWZ256rmk [HasVLX, HasBWI]
vptestmw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
VPTESTMWZ256rr [HasVLX, HasBWI]
vptestmw {src2, src1, dst|dst, src1, src2}
VPTESTMWZ256rrk [HasVLX, HasBWI]
vptestmw {src2, src1, dst {mask}|dst {mask}, src1, src2}
VPTESTNMBZ128rm [HasVLX, HasBWI]
vptestnmb {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VPTESTNMBZ128rmk [HasVLX, HasBWI]
vptestnmb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
VPTESTNMBZ128rr [HasVLX, HasBWI]
vptestnmb {src2, src1, dst|dst, src1, src2}
VPTESTNMBZ128rrk [HasVLX, HasBWI]
vptestnmb {src2, src1, dst {mask}|dst {mask}, src1, src2}
VPTESTNMBZ256rm [HasVLX, HasBWI]
vptestnmb {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VPTESTNMBZ256rmk [HasVLX, HasBWI]
vptestnmb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
VPTESTNMBZ256rr [HasVLX, HasBWI]
vptestnmb {src2, src1, dst|dst, src1, src2}
VPTESTNMBZ256rrk [HasVLX, HasBWI]
vptestnmb {src2, src1, dst {mask}|dst {mask}, src1, src2}
VPTESTNMWZ128rm [HasVLX, HasBWI]
vptestnmw {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VPTESTNMWZ128rmk [HasVLX, HasBWI]
vptestnmw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
VPTESTNMWZ128rr [HasVLX, HasBWI]
vptestnmw {src2, src1, dst|dst, src1, src2}
VPTESTNMWZ128rrk [HasVLX, HasBWI]
vptestnmw {src2, src1, dst {mask}|dst {mask}, src1, src2}
VPTESTNMWZ256rm [HasVLX, HasBWI]
vptestnmw {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VPTESTNMWZ256rmk [HasVLX, HasBWI]
vptestnmw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
VPTESTNMWZ256rr [HasVLX, HasBWI]
vptestnmw {src2, src1, dst|dst, src1, src2}
VPTESTNMWZ256rrk [HasVLX, HasBWI]
vptestnmw {src2, src1, dst {mask}|dst {mask}, src1, src2}
VPUNPCKHBWZ128rm [HasVLX, HasBWI]
vpunpckhbw {src2, src1, dst|dst, src1, src2}
VPUNPCKHBWZ128rmk [HasVLX, HasBWI]
vpunpckhbw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPUNPCKHBWZ128rmkz [HasVLX, HasBWI]
vpunpckhbw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPUNPCKHBWZ128rr [HasVLX, HasBWI]
vpunpckhbw {src2, src1, dst|dst, src1, src2}
VPUNPCKHBWZ128rrk [HasVLX, HasBWI]
vpunpckhbw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPUNPCKHBWZ128rrkz [HasVLX, HasBWI]
vpunpckhbw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPUNPCKHBWZ256rm [HasVLX, HasBWI]
vpunpckhbw {src2, src1, dst|dst, src1, src2}
VPUNPCKHBWZ256rmk [HasVLX, HasBWI]
vpunpckhbw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPUNPCKHBWZ256rmkz [HasVLX, HasBWI]
vpunpckhbw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPUNPCKHBWZ256rr [HasVLX, HasBWI]
vpunpckhbw {src2, src1, dst|dst, src1, src2}
VPUNPCKHBWZ256rrk [HasVLX, HasBWI]
vpunpckhbw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPUNPCKHBWZ256rrkz [HasVLX, HasBWI]
vpunpckhbw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPUNPCKHWDZ128rm [HasVLX, HasBWI]
vpunpckhwd {src2, src1, dst|dst, src1, src2}
VPUNPCKHWDZ128rmk [HasVLX, HasBWI]
vpunpckhwd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPUNPCKHWDZ128rmkz [HasVLX, HasBWI]
vpunpckhwd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPUNPCKHWDZ128rr [HasVLX, HasBWI]
vpunpckhwd {src2, src1, dst|dst, src1, src2}
VPUNPCKHWDZ128rrk [HasVLX, HasBWI]
vpunpckhwd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPUNPCKHWDZ128rrkz [HasVLX, HasBWI]
vpunpckhwd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPUNPCKHWDZ256rm [HasVLX, HasBWI]
vpunpckhwd {src2, src1, dst|dst, src1, src2}
VPUNPCKHWDZ256rmk [HasVLX, HasBWI]
vpunpckhwd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPUNPCKHWDZ256rmkz [HasVLX, HasBWI]
vpunpckhwd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPUNPCKHWDZ256rr [HasVLX, HasBWI]
vpunpckhwd {src2, src1, dst|dst, src1, src2}
VPUNPCKHWDZ256rrk [HasVLX, HasBWI]
vpunpckhwd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPUNPCKHWDZ256rrkz [HasVLX, HasBWI]
vpunpckhwd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPUNPCKLBWZ128rm [HasVLX, HasBWI]
vpunpcklbw {src2, src1, dst|dst, src1, src2}
VPUNPCKLBWZ128rmk [HasVLX, HasBWI]
vpunpcklbw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPUNPCKLBWZ128rmkz [HasVLX, HasBWI]
vpunpcklbw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPUNPCKLBWZ128rr [HasVLX, HasBWI]
vpunpcklbw {src2, src1, dst|dst, src1, src2}
VPUNPCKLBWZ128rrk [HasVLX, HasBWI]
vpunpcklbw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPUNPCKLBWZ128rrkz [HasVLX, HasBWI]
vpunpcklbw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPUNPCKLBWZ256rm [HasVLX, HasBWI]
vpunpcklbw {src2, src1, dst|dst, src1, src2}
VPUNPCKLBWZ256rmk [HasVLX, HasBWI]
vpunpcklbw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPUNPCKLBWZ256rmkz [HasVLX, HasBWI]
vpunpcklbw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPUNPCKLBWZ256rr [HasVLX, HasBWI]
vpunpcklbw {src2, src1, dst|dst, src1, src2}
VPUNPCKLBWZ256rrk [HasVLX, HasBWI]
vpunpcklbw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPUNPCKLBWZ256rrkz [HasVLX, HasBWI]
vpunpcklbw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPUNPCKLWDZ128rm [HasVLX, HasBWI]
vpunpcklwd {src2, src1, dst|dst, src1, src2}
VPUNPCKLWDZ128rmk [HasVLX, HasBWI]
vpunpcklwd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPUNPCKLWDZ128rmkz [HasVLX, HasBWI]
vpunpcklwd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPUNPCKLWDZ128rr [HasVLX, HasBWI]
vpunpcklwd {src2, src1, dst|dst, src1, src2}
VPUNPCKLWDZ128rrk [HasVLX, HasBWI]
vpunpcklwd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPUNPCKLWDZ128rrkz [HasVLX, HasBWI]
vpunpcklwd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPUNPCKLWDZ256rm [HasVLX, HasBWI]
vpunpcklwd {src2, src1, dst|dst, src1, src2}
VPUNPCKLWDZ256rmk [HasVLX, HasBWI]
vpunpcklwd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPUNPCKLWDZ256rmkz [HasVLX, HasBWI]
vpunpcklwd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPUNPCKLWDZ256rr [HasVLX, HasBWI]
vpunpcklwd {src2, src1, dst|dst, src1, src2}
VPUNPCKLWDZ256rrk [HasVLX, HasBWI]
vpunpcklwd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPUNPCKLWDZ256rrkz [HasVLX, HasBWI]
vpunpcklwd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VANDNPDZ128rm [HasVLX, HasDQI]
vandnpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VANDNPDZ128rmb [HasVLX, HasDQI]
vandnpd {src2{1to2}, src1, dst|dst, src1, src2{1to2}}
|
Note
|
Properties: mayLoad |
VANDNPDZ128rmbk [HasVLX, HasDQI]
vandnpd {src2{1to2}, src1, dst {mask}|dst {mask}, src1, src2{1to2}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VANDNPDZ128rmbkz [HasVLX, HasDQI]
vandnpd {src2{1to2}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to2}}
|
Note
|
Properties: mayLoad |
VANDNPDZ128rmk [HasVLX, HasDQI]
vandnpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VANDNPDZ128rmkz [HasVLX, HasDQI]
vandnpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VANDNPDZ128rr [HasVLX, HasDQI]
vandnpd {src2, src1, dst|dst, src1, src2}
VANDNPDZ128rrk [HasVLX, HasDQI]
vandnpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VANDNPDZ128rrkz [HasVLX, HasDQI]
vandnpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VANDNPDZ256rm [HasVLX, HasDQI]
vandnpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VANDNPDZ256rmb [HasVLX, HasDQI]
vandnpd {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
|
Note
|
Properties: mayLoad |
VANDNPDZ256rmbk [HasVLX, HasDQI]
vandnpd {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VANDNPDZ256rmbkz [HasVLX, HasDQI]
vandnpd {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
|
Note
|
Properties: mayLoad |
VANDNPDZ256rmk [HasVLX, HasDQI]
vandnpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VANDNPDZ256rmkz [HasVLX, HasDQI]
vandnpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VANDNPDZ256rr [HasVLX, HasDQI]
vandnpd {src2, src1, dst|dst, src1, src2}
VANDNPDZ256rrk [HasVLX, HasDQI]
vandnpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VANDNPDZ256rrkz [HasVLX, HasDQI]
vandnpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VANDNPSZ128rm [HasVLX, HasDQI]
vandnps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VANDNPSZ128rmb [HasVLX, HasDQI]
vandnps {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
|
Note
|
Properties: mayLoad |
VANDNPSZ128rmbk [HasVLX, HasDQI]
vandnps {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VANDNPSZ128rmbkz [HasVLX, HasDQI]
vandnps {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
|
Note
|
Properties: mayLoad |
VANDNPSZ128rmk [HasVLX, HasDQI]
vandnps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VANDNPSZ128rmkz [HasVLX, HasDQI]
vandnps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VANDNPSZ128rr [HasVLX, HasDQI]
vandnps {src2, src1, dst|dst, src1, src2}
VANDNPSZ128rrk [HasVLX, HasDQI]
vandnps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VANDNPSZ128rrkz [HasVLX, HasDQI]
vandnps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VANDNPSZ256rm [HasVLX, HasDQI]
vandnps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VANDNPSZ256rmb [HasVLX, HasDQI]
vandnps {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
VANDNPSZ256rmbk [HasVLX, HasDQI]
vandnps {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VANDNPSZ256rmbkz [HasVLX, HasDQI]
vandnps {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
VANDNPSZ256rmk [HasVLX, HasDQI]
vandnps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VANDNPSZ256rmkz [HasVLX, HasDQI]
vandnps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VANDNPSZ256rr [HasVLX, HasDQI]
vandnps {src2, src1, dst|dst, src1, src2}
VANDNPSZ256rrk [HasVLX, HasDQI]
vandnps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VANDNPSZ256rrkz [HasVLX, HasDQI]
vandnps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VANDPDZ128rm [HasVLX, HasDQI]
vandpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VANDPDZ128rmb [HasVLX, HasDQI]
vandpd {src2{1to2}, src1, dst|dst, src1, src2{1to2}}
|
Note
|
Properties: mayLoad |
VANDPDZ128rmbk [HasVLX, HasDQI]
vandpd {src2{1to2}, src1, dst {mask}|dst {mask}, src1, src2{1to2}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VANDPDZ128rmbkz [HasVLX, HasDQI]
vandpd {src2{1to2}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to2}}
|
Note
|
Properties: mayLoad |
VANDPDZ128rmk [HasVLX, HasDQI]
vandpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VANDPDZ128rmkz [HasVLX, HasDQI]
vandpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VANDPDZ128rr [HasVLX, HasDQI]
vandpd {src2, src1, dst|dst, src1, src2}
VANDPDZ128rrk [HasVLX, HasDQI]
vandpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VANDPDZ128rrkz [HasVLX, HasDQI]
vandpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VANDPDZ256rm [HasVLX, HasDQI]
vandpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VANDPDZ256rmb [HasVLX, HasDQI]
vandpd {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
|
Note
|
Properties: mayLoad |
VANDPDZ256rmbk [HasVLX, HasDQI]
vandpd {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VANDPDZ256rmbkz [HasVLX, HasDQI]
vandpd {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
|
Note
|
Properties: mayLoad |
VANDPDZ256rmk [HasVLX, HasDQI]
vandpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VANDPDZ256rmkz [HasVLX, HasDQI]
vandpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VANDPDZ256rr [HasVLX, HasDQI]
vandpd {src2, src1, dst|dst, src1, src2}
VANDPDZ256rrk [HasVLX, HasDQI]
vandpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VANDPDZ256rrkz [HasVLX, HasDQI]
vandpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VANDPSZ128rm [HasVLX, HasDQI]
vandps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VANDPSZ128rmb [HasVLX, HasDQI]
vandps {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
|
Note
|
Properties: mayLoad |
VANDPSZ128rmbk [HasVLX, HasDQI]
vandps {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VANDPSZ128rmbkz [HasVLX, HasDQI]
vandps {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
|
Note
|
Properties: mayLoad |
VANDPSZ128rmk [HasVLX, HasDQI]
vandps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VANDPSZ128rmkz [HasVLX, HasDQI]
vandps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VANDPSZ128rr [HasVLX, HasDQI]
vandps {src2, src1, dst|dst, src1, src2}
VANDPSZ128rrk [HasVLX, HasDQI]
vandps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VANDPSZ128rrkz [HasVLX, HasDQI]
vandps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VANDPSZ256rm [HasVLX, HasDQI]
vandps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VANDPSZ256rmb [HasVLX, HasDQI]
vandps {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
VANDPSZ256rmbk [HasVLX, HasDQI]
vandps {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VANDPSZ256rmbkz [HasVLX, HasDQI]
vandps {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
VANDPSZ256rmk [HasVLX, HasDQI]
vandps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VANDPSZ256rmkz [HasVLX, HasDQI]
vandps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VANDPSZ256rr [HasVLX, HasDQI]
vandps {src2, src1, dst|dst, src1, src2}
VANDPSZ256rrk [HasVLX, HasDQI]
vandps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VANDPSZ256rrkz [HasVLX, HasDQI]
vandps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VBROADCASTF32X2Z256rm [HasVLX, HasDQI]
vbroadcastf32x2 {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
VBROADCASTF32X2Z256rmk [HasVLX, HasDQI]
vbroadcastf32x2 {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VBROADCASTF32X2Z256rmkz [HasVLX, HasDQI]
vbroadcastf32x2 {src, dst {mask} {z}|dst {mask} {z}, src}
VBROADCASTF32X2Z256rr [HasVLX, HasDQI]
vbroadcastf32x2 {src, dst|dst, src}
VBROADCASTF32X2Z256rrk [HasVLX, HasDQI]
vbroadcastf32x2 {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VBROADCASTF32X2Z256rrkz [HasVLX, HasDQI]
vbroadcastf32x2 {src, dst {mask} {z}|dst {mask} {z}, src}
VBROADCASTF64X2Z256rm [HasVLX, HasDQI]
vbroadcastf64x2 {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
VBROADCASTF64X2Z256rmk [HasVLX, HasDQI]
vbroadcastf64x2 {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VBROADCASTF64X2Z256rmkz [HasVLX, HasDQI]
vbroadcastf64x2 {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayLoad |
VBROADCASTI32X2Z128rm [HasVLX, HasDQI]
vbroadcasti32x2 {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
VBROADCASTI32X2Z128rmk [HasVLX, HasDQI]
vbroadcasti32x2 {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VBROADCASTI32X2Z128rmkz [HasVLX, HasDQI]
vbroadcasti32x2 {src, dst {mask} {z}|dst {mask} {z}, src}
VBROADCASTI32X2Z128rr [HasVLX, HasDQI]
vbroadcasti32x2 {src, dst|dst, src}
VBROADCASTI32X2Z128rrk [HasVLX, HasDQI]
vbroadcasti32x2 {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VBROADCASTI32X2Z128rrkz [HasVLX, HasDQI]
vbroadcasti32x2 {src, dst {mask} {z}|dst {mask} {z}, src}
VBROADCASTI32X2Z256rm [HasVLX, HasDQI]
vbroadcasti32x2 {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
VBROADCASTI32X2Z256rmk [HasVLX, HasDQI]
vbroadcasti32x2 {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VBROADCASTI32X2Z256rmkz [HasVLX, HasDQI]
vbroadcasti32x2 {src, dst {mask} {z}|dst {mask} {z}, src}
VBROADCASTI32X2Z256rr [HasVLX, HasDQI]
vbroadcasti32x2 {src, dst|dst, src}
VBROADCASTI32X2Z256rrk [HasVLX, HasDQI]
vbroadcasti32x2 {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VBROADCASTI32X2Z256rrkz [HasVLX, HasDQI]
vbroadcasti32x2 {src, dst {mask} {z}|dst {mask} {z}, src}
VBROADCASTI64X2Z256rm [HasVLX, HasDQI]
vbroadcasti64x2 {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
VBROADCASTI64X2Z256rmk [HasVLX, HasDQI]
vbroadcasti64x2 {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VBROADCASTI64X2Z256rmkz [HasVLX, HasDQI]
vbroadcasti64x2 {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayLoad |
VCVTPD2QQZ128rm [HasVLX, HasDQI]
vcvtpd2qq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2QQZ128rmb [HasVLX, HasDQI]
vcvtpd2qq {src{1to2}, dst|dst, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2QQZ128rmbk [HasVLX, HasDQI]
vcvtpd2qq {src{1to2}, dst {mask}|dst {mask}, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPD2QQZ128rmbkz [HasVLX, HasDQI]
vcvtpd2qq {src{1to2}, dst {mask} {z}|dst {mask} {z}, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2QQZ128rmk [HasVLX, HasDQI]
vcvtpd2qq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPD2QQZ128rmkz [HasVLX, HasDQI]
vcvtpd2qq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2QQZ128rr [HasVLX, HasDQI]
vcvtpd2qq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2QQZ128rrk [HasVLX, HasDQI]
vcvtpd2qq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPD2QQZ128rrkz [HasVLX, HasDQI]
vcvtpd2qq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2QQZ256rm [HasVLX, HasDQI]
vcvtpd2qq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2QQZ256rmb [HasVLX, HasDQI]
vcvtpd2qq {src{1to4}, dst|dst, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2QQZ256rmbk [HasVLX, HasDQI]
vcvtpd2qq {src{1to4}, dst {mask}|dst {mask}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPD2QQZ256rmbkz [HasVLX, HasDQI]
vcvtpd2qq {src{1to4}, dst {mask} {z}|dst {mask} {z}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2QQZ256rmk [HasVLX, HasDQI]
vcvtpd2qq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPD2QQZ256rmkz [HasVLX, HasDQI]
vcvtpd2qq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2QQZ256rr [HasVLX, HasDQI]
vcvtpd2qq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2QQZ256rrk [HasVLX, HasDQI]
vcvtpd2qq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPD2QQZ256rrkz [HasVLX, HasDQI]
vcvtpd2qq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2UQQZ128rm [HasVLX, HasDQI]
vcvtpd2uqq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2UQQZ128rmb [HasVLX, HasDQI]
vcvtpd2uqq {src{1to2}, dst|dst, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2UQQZ128rmbk [HasVLX, HasDQI]
vcvtpd2uqq {src{1to2}, dst {mask}|dst {mask}, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPD2UQQZ128rmbkz [HasVLX, HasDQI]
vcvtpd2uqq {src{1to2}, dst {mask} {z}|dst {mask} {z}, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2UQQZ128rmk [HasVLX, HasDQI]
vcvtpd2uqq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPD2UQQZ128rmkz [HasVLX, HasDQI]
vcvtpd2uqq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2UQQZ128rr [HasVLX, HasDQI]
vcvtpd2uqq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2UQQZ128rrk [HasVLX, HasDQI]
vcvtpd2uqq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPD2UQQZ128rrkz [HasVLX, HasDQI]
vcvtpd2uqq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2UQQZ256rm [HasVLX, HasDQI]
vcvtpd2uqq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2UQQZ256rmb [HasVLX, HasDQI]
vcvtpd2uqq {src{1to4}, dst|dst, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2UQQZ256rmbk [HasVLX, HasDQI]
vcvtpd2uqq {src{1to4}, dst {mask}|dst {mask}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPD2UQQZ256rmbkz [HasVLX, HasDQI]
vcvtpd2uqq {src{1to4}, dst {mask} {z}|dst {mask} {z}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2UQQZ256rmk [HasVLX, HasDQI]
vcvtpd2uqq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPD2UQQZ256rmkz [HasVLX, HasDQI]
vcvtpd2uqq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2UQQZ256rr [HasVLX, HasDQI]
vcvtpd2uqq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2UQQZ256rrk [HasVLX, HasDQI]
vcvtpd2uqq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPD2UQQZ256rrkz [HasVLX, HasDQI]
vcvtpd2uqq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2QQZ128rm [HasVLX, HasDQI]
vcvtps2qq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2QQZ128rmb [HasVLX, HasDQI]
vcvtps2qq {src{1to2}, dst|dst, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2QQZ128rmbk [HasVLX, HasDQI]
vcvtps2qq {src{1to2}, dst {mask}|dst {mask}, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPS2QQZ128rmbkz [HasVLX, HasDQI]
vcvtps2qq {src{1to2}, dst {mask} {z}|dst {mask} {z}, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2QQZ128rmk [HasVLX, HasDQI]
vcvtps2qq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPS2QQZ128rmkz [HasVLX, HasDQI]
vcvtps2qq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2QQZ128rr [HasVLX, HasDQI]
vcvtps2qq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2QQZ128rrk [HasVLX, HasDQI]
vcvtps2qq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPS2QQZ128rrkz [HasVLX, HasDQI]
vcvtps2qq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2QQZ256rm [HasVLX, HasDQI]
vcvtps2qq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2QQZ256rmb [HasVLX, HasDQI]
vcvtps2qq {src{1to4}, dst|dst, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2QQZ256rmbk [HasVLX, HasDQI]
vcvtps2qq {src{1to4}, dst {mask}|dst {mask}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPS2QQZ256rmbkz [HasVLX, HasDQI]
vcvtps2qq {src{1to4}, dst {mask} {z}|dst {mask} {z}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2QQZ256rmk [HasVLX, HasDQI]
vcvtps2qq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPS2QQZ256rmkz [HasVLX, HasDQI]
vcvtps2qq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2QQZ256rr [HasVLX, HasDQI]
vcvtps2qq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2QQZ256rrk [HasVLX, HasDQI]
vcvtps2qq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPS2QQZ256rrkz [HasVLX, HasDQI]
vcvtps2qq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2UQQZ128rm [HasVLX, HasDQI]
vcvtps2uqq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2UQQZ128rmb [HasVLX, HasDQI]
vcvtps2uqq {src{1to2}, dst|dst, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2UQQZ128rmbk [HasVLX, HasDQI]
vcvtps2uqq {src{1to2}, dst {mask}|dst {mask}, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPS2UQQZ128rmbkz [HasVLX, HasDQI]
vcvtps2uqq {src{1to2}, dst {mask} {z}|dst {mask} {z}, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2UQQZ128rmk [HasVLX, HasDQI]
vcvtps2uqq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPS2UQQZ128rmkz [HasVLX, HasDQI]
vcvtps2uqq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2UQQZ128rr [HasVLX, HasDQI]
vcvtps2uqq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2UQQZ128rrk [HasVLX, HasDQI]
vcvtps2uqq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPS2UQQZ128rrkz [HasVLX, HasDQI]
vcvtps2uqq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2UQQZ256rm [HasVLX, HasDQI]
vcvtps2uqq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2UQQZ256rmb [HasVLX, HasDQI]
vcvtps2uqq {src{1to4}, dst|dst, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2UQQZ256rmbk [HasVLX, HasDQI]
vcvtps2uqq {src{1to4}, dst {mask}|dst {mask}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPS2UQQZ256rmbkz [HasVLX, HasDQI]
vcvtps2uqq {src{1to4}, dst {mask} {z}|dst {mask} {z}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2UQQZ256rmk [HasVLX, HasDQI]
vcvtps2uqq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPS2UQQZ256rmkz [HasVLX, HasDQI]
vcvtps2uqq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2UQQZ256rr [HasVLX, HasDQI]
vcvtps2uqq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2UQQZ256rrk [HasVLX, HasDQI]
vcvtps2uqq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPS2UQQZ256rrkz [HasVLX, HasDQI]
vcvtps2uqq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTQQ2PDZ128rm [HasVLX, HasDQI]
vcvtqq2pd {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTQQ2PDZ128rmb [HasVLX, HasDQI]
vcvtqq2pd {src{1to2}, dst|dst, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
VCVTQQ2PDZ128rmbk [HasVLX, HasDQI]
vcvtqq2pd {src{1to2}, dst {mask}|dst {mask}, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTQQ2PDZ128rmbkz [HasVLX, HasDQI]
vcvtqq2pd {src{1to2}, dst {mask} {z}|dst {mask} {z}, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
VCVTQQ2PDZ128rmk [HasVLX, HasDQI]
vcvtqq2pd {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTQQ2PDZ128rmkz [HasVLX, HasDQI]
vcvtqq2pd {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTQQ2PDZ128rr [HasVLX, HasDQI]
vcvtqq2pd {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTQQ2PDZ128rrk [HasVLX, HasDQI]
vcvtqq2pd {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTQQ2PDZ128rrkz [HasVLX, HasDQI]
vcvtqq2pd {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTQQ2PDZ256rm [HasVLX, HasDQI]
vcvtqq2pd {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTQQ2PDZ256rmb [HasVLX, HasDQI]
vcvtqq2pd {src{1to4}, dst|dst, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTQQ2PDZ256rmbk [HasVLX, HasDQI]
vcvtqq2pd {src{1to4}, dst {mask}|dst {mask}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTQQ2PDZ256rmbkz [HasVLX, HasDQI]
vcvtqq2pd {src{1to4}, dst {mask} {z}|dst {mask} {z}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTQQ2PDZ256rmk [HasVLX, HasDQI]
vcvtqq2pd {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTQQ2PDZ256rmkz [HasVLX, HasDQI]
vcvtqq2pd {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTQQ2PDZ256rr [HasVLX, HasDQI]
vcvtqq2pd {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTQQ2PDZ256rrk [HasVLX, HasDQI]
vcvtqq2pd {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTQQ2PDZ256rrkz [HasVLX, HasDQI]
vcvtqq2pd {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTQQ2PSZ128rm [HasVLX, HasDQI]
vcvtqq2ps{x} {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTQQ2PSZ128rmb [HasVLX, HasDQI]
vcvtqq2ps {src{1to2}, dst|dst, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
VCVTQQ2PSZ128rmbk [HasVLX, HasDQI]
vcvtqq2ps {src{1to2}, dst {mask}|dst {mask}, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTQQ2PSZ128rmbkz [HasVLX, HasDQI]
vcvtqq2ps {src{1to2}, dst {mask} {z}|dst {mask} {z}, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
VCVTQQ2PSZ128rmk [HasVLX, HasDQI]
vcvtqq2ps{x} {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTQQ2PSZ128rmkz [HasVLX, HasDQI]
vcvtqq2ps{x} {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTQQ2PSZ128rr [HasVLX, HasDQI]
vcvtqq2ps {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTQQ2PSZ128rrk [HasVLX, HasDQI]
vcvtqq2ps {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTQQ2PSZ128rrkz [HasVLX, HasDQI]
vcvtqq2ps {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTQQ2PSZ256rm [HasVLX, HasDQI]
vcvtqq2ps{y} {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTQQ2PSZ256rmb [HasVLX, HasDQI]
vcvtqq2ps {src{1to4}, dst|dst, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTQQ2PSZ256rmbk [HasVLX, HasDQI]
vcvtqq2ps {src{1to4}, dst {mask}|dst {mask}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTQQ2PSZ256rmbkz [HasVLX, HasDQI]
vcvtqq2ps {src{1to4}, dst {mask} {z}|dst {mask} {z}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTQQ2PSZ256rmk [HasVLX, HasDQI]
vcvtqq2ps{y} {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTQQ2PSZ256rmkz [HasVLX, HasDQI]
vcvtqq2ps{y} {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTQQ2PSZ256rr [HasVLX, HasDQI]
vcvtqq2ps {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTQQ2PSZ256rrk [HasVLX, HasDQI]
vcvtqq2ps {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTQQ2PSZ256rrkz [HasVLX, HasDQI]
vcvtqq2ps {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2QQZ128rm [HasVLX, HasDQI]
vcvttpd2qq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2QQZ128rmb [HasVLX, HasDQI]
vcvttpd2qq {src{1to2}, dst|dst, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2QQZ128rmbk [HasVLX, HasDQI]
vcvttpd2qq {src{1to2}, dst {mask}|dst {mask}, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPD2QQZ128rmbkz [HasVLX, HasDQI]
vcvttpd2qq {src{1to2}, dst {mask} {z}|dst {mask} {z}, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2QQZ128rmk [HasVLX, HasDQI]
vcvttpd2qq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPD2QQZ128rmkz [HasVLX, HasDQI]
vcvttpd2qq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2QQZ128rr [HasVLX, HasDQI]
vcvttpd2qq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2QQZ128rrk [HasVLX, HasDQI]
vcvttpd2qq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPD2QQZ128rrkz [HasVLX, HasDQI]
vcvttpd2qq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2QQZ256rm [HasVLX, HasDQI]
vcvttpd2qq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2QQZ256rmb [HasVLX, HasDQI]
vcvttpd2qq {src{1to4}, dst|dst, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2QQZ256rmbk [HasVLX, HasDQI]
vcvttpd2qq {src{1to4}, dst {mask}|dst {mask}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPD2QQZ256rmbkz [HasVLX, HasDQI]
vcvttpd2qq {src{1to4}, dst {mask} {z}|dst {mask} {z}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2QQZ256rmk [HasVLX, HasDQI]
vcvttpd2qq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPD2QQZ256rmkz [HasVLX, HasDQI]
vcvttpd2qq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2QQZ256rr [HasVLX, HasDQI]
vcvttpd2qq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2QQZ256rrk [HasVLX, HasDQI]
vcvttpd2qq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPD2QQZ256rrkz [HasVLX, HasDQI]
vcvttpd2qq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2UQQZ128rm [HasVLX, HasDQI]
vcvttpd2uqq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2UQQZ128rmb [HasVLX, HasDQI]
vcvttpd2uqq {src{1to2}, dst|dst, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2UQQZ128rmbk [HasVLX, HasDQI]
vcvttpd2uqq {src{1to2}, dst {mask}|dst {mask}, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPD2UQQZ128rmbkz [HasVLX, HasDQI]
vcvttpd2uqq {src{1to2}, dst {mask} {z}|dst {mask} {z}, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2UQQZ128rmk [HasVLX, HasDQI]
vcvttpd2uqq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPD2UQQZ128rmkz [HasVLX, HasDQI]
vcvttpd2uqq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2UQQZ128rr [HasVLX, HasDQI]
vcvttpd2uqq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2UQQZ128rrk [HasVLX, HasDQI]
vcvttpd2uqq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPD2UQQZ128rrkz [HasVLX, HasDQI]
vcvttpd2uqq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2UQQZ256rm [HasVLX, HasDQI]
vcvttpd2uqq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2UQQZ256rmb [HasVLX, HasDQI]
vcvttpd2uqq {src{1to4}, dst|dst, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2UQQZ256rmbk [HasVLX, HasDQI]
vcvttpd2uqq {src{1to4}, dst {mask}|dst {mask}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPD2UQQZ256rmbkz [HasVLX, HasDQI]
vcvttpd2uqq {src{1to4}, dst {mask} {z}|dst {mask} {z}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2UQQZ256rmk [HasVLX, HasDQI]
vcvttpd2uqq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPD2UQQZ256rmkz [HasVLX, HasDQI]
vcvttpd2uqq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2UQQZ256rr [HasVLX, HasDQI]
vcvttpd2uqq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2UQQZ256rrk [HasVLX, HasDQI]
vcvttpd2uqq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPD2UQQZ256rrkz [HasVLX, HasDQI]
vcvttpd2uqq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2QQZ128rm [HasVLX, HasDQI]
vcvttps2qq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2QQZ128rmb [HasVLX, HasDQI]
vcvttps2qq {src{1to2}, dst|dst, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2QQZ128rmbk [HasVLX, HasDQI]
vcvttps2qq {src{1to2}, dst {mask}|dst {mask}, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPS2QQZ128rmbkz [HasVLX, HasDQI]
vcvttps2qq {src{1to2}, dst {mask} {z}|dst {mask} {z}, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2QQZ128rmk [HasVLX, HasDQI]
vcvttps2qq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPS2QQZ128rmkz [HasVLX, HasDQI]
vcvttps2qq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2QQZ128rr [HasVLX, HasDQI]
vcvttps2qq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2QQZ128rrk [HasVLX, HasDQI]
vcvttps2qq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPS2QQZ128rrkz [HasVLX, HasDQI]
vcvttps2qq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2QQZ256rm [HasVLX, HasDQI]
vcvttps2qq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2QQZ256rmb [HasVLX, HasDQI]
vcvttps2qq {src{1to4}, dst|dst, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2QQZ256rmbk [HasVLX, HasDQI]
vcvttps2qq {src{1to4}, dst {mask}|dst {mask}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPS2QQZ256rmbkz [HasVLX, HasDQI]
vcvttps2qq {src{1to4}, dst {mask} {z}|dst {mask} {z}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2QQZ256rmk [HasVLX, HasDQI]
vcvttps2qq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPS2QQZ256rmkz [HasVLX, HasDQI]
vcvttps2qq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2QQZ256rr [HasVLX, HasDQI]
vcvttps2qq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2QQZ256rrk [HasVLX, HasDQI]
vcvttps2qq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPS2QQZ256rrkz [HasVLX, HasDQI]
vcvttps2qq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2UQQZ128rm [HasVLX, HasDQI]
vcvttps2uqq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2UQQZ128rmb [HasVLX, HasDQI]
vcvttps2uqq {src{1to2}, dst|dst, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2UQQZ128rmbk [HasVLX, HasDQI]
vcvttps2uqq {src{1to2}, dst {mask}|dst {mask}, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPS2UQQZ128rmbkz [HasVLX, HasDQI]
vcvttps2uqq {src{1to2}, dst {mask} {z}|dst {mask} {z}, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2UQQZ128rmk [HasVLX, HasDQI]
vcvttps2uqq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPS2UQQZ128rmkz [HasVLX, HasDQI]
vcvttps2uqq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2UQQZ128rr [HasVLX, HasDQI]
vcvttps2uqq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2UQQZ128rrk [HasVLX, HasDQI]
vcvttps2uqq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPS2UQQZ128rrkz [HasVLX, HasDQI]
vcvttps2uqq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2UQQZ256rm [HasVLX, HasDQI]
vcvttps2uqq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2UQQZ256rmb [HasVLX, HasDQI]
vcvttps2uqq {src{1to4}, dst|dst, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2UQQZ256rmbk [HasVLX, HasDQI]
vcvttps2uqq {src{1to4}, dst {mask}|dst {mask}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPS2UQQZ256rmbkz [HasVLX, HasDQI]
vcvttps2uqq {src{1to4}, dst {mask} {z}|dst {mask} {z}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2UQQZ256rmk [HasVLX, HasDQI]
vcvttps2uqq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPS2UQQZ256rmkz [HasVLX, HasDQI]
vcvttps2uqq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2UQQZ256rr [HasVLX, HasDQI]
vcvttps2uqq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2UQQZ256rrk [HasVLX, HasDQI]
vcvttps2uqq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPS2UQQZ256rrkz [HasVLX, HasDQI]
vcvttps2uqq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTUQQ2PDZ128rm [HasVLX, HasDQI]
vcvtuqq2pd {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTUQQ2PDZ128rmb [HasVLX, HasDQI]
vcvtuqq2pd {src{1to2}, dst|dst, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
VCVTUQQ2PDZ128rmbk [HasVLX, HasDQI]
vcvtuqq2pd {src{1to2}, dst {mask}|dst {mask}, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTUQQ2PDZ128rmbkz [HasVLX, HasDQI]
vcvtuqq2pd {src{1to2}, dst {mask} {z}|dst {mask} {z}, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
VCVTUQQ2PDZ128rmk [HasVLX, HasDQI]
vcvtuqq2pd {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTUQQ2PDZ128rmkz [HasVLX, HasDQI]
vcvtuqq2pd {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTUQQ2PDZ128rr [HasVLX, HasDQI]
vcvtuqq2pd {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTUQQ2PDZ128rrk [HasVLX, HasDQI]
vcvtuqq2pd {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTUQQ2PDZ128rrkz [HasVLX, HasDQI]
vcvtuqq2pd {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTUQQ2PDZ256rm [HasVLX, HasDQI]
vcvtuqq2pd {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTUQQ2PDZ256rmb [HasVLX, HasDQI]
vcvtuqq2pd {src{1to4}, dst|dst, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTUQQ2PDZ256rmbk [HasVLX, HasDQI]
vcvtuqq2pd {src{1to4}, dst {mask}|dst {mask}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTUQQ2PDZ256rmbkz [HasVLX, HasDQI]
vcvtuqq2pd {src{1to4}, dst {mask} {z}|dst {mask} {z}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTUQQ2PDZ256rmk [HasVLX, HasDQI]
vcvtuqq2pd {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTUQQ2PDZ256rmkz [HasVLX, HasDQI]
vcvtuqq2pd {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTUQQ2PDZ256rr [HasVLX, HasDQI]
vcvtuqq2pd {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTUQQ2PDZ256rrk [HasVLX, HasDQI]
vcvtuqq2pd {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTUQQ2PDZ256rrkz [HasVLX, HasDQI]
vcvtuqq2pd {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTUQQ2PSZ128rm [HasVLX, HasDQI]
vcvtuqq2ps{x} {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTUQQ2PSZ128rmb [HasVLX, HasDQI]
vcvtuqq2ps {src{1to2}, dst|dst, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
VCVTUQQ2PSZ128rmbk [HasVLX, HasDQI]
vcvtuqq2ps {src{1to2}, dst {mask}|dst {mask}, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTUQQ2PSZ128rmbkz [HasVLX, HasDQI]
vcvtuqq2ps {src{1to2}, dst {mask} {z}|dst {mask} {z}, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
VCVTUQQ2PSZ128rmk [HasVLX, HasDQI]
vcvtuqq2ps{x} {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTUQQ2PSZ128rmkz [HasVLX, HasDQI]
vcvtuqq2ps{x} {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTUQQ2PSZ128rr [HasVLX, HasDQI]
vcvtuqq2ps {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTUQQ2PSZ128rrk [HasVLX, HasDQI]
vcvtuqq2ps {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTUQQ2PSZ128rrkz [HasVLX, HasDQI]
vcvtuqq2ps {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTUQQ2PSZ256rm [HasVLX, HasDQI]
vcvtuqq2ps{y} {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTUQQ2PSZ256rmb [HasVLX, HasDQI]
vcvtuqq2ps {src{1to4}, dst|dst, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTUQQ2PSZ256rmbk [HasVLX, HasDQI]
vcvtuqq2ps {src{1to4}, dst {mask}|dst {mask}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTUQQ2PSZ256rmbkz [HasVLX, HasDQI]
vcvtuqq2ps {src{1to4}, dst {mask} {z}|dst {mask} {z}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTUQQ2PSZ256rmk [HasVLX, HasDQI]
vcvtuqq2ps{y} {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTUQQ2PSZ256rmkz [HasVLX, HasDQI]
vcvtuqq2ps{y} {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTUQQ2PSZ256rr [HasVLX, HasDQI]
vcvtuqq2ps {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTUQQ2PSZ256rrk [HasVLX, HasDQI]
vcvtuqq2ps {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTUQQ2PSZ256rrkz [HasVLX, HasDQI]
vcvtuqq2ps {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VEXTRACTF64X2Z256mri [HasVLX, HasDQI]
vextractf64x2 {idx, src1, dst|dst, src1, idx}
VEXTRACTF64X2Z256mrik [HasVLX, HasDQI]
vextractf64x2 {idx, src1, dst {mask}|dst {mask}, src1, idx}
|
Note
|
Properties: mayStore |
VEXTRACTF64X2Z256rri [HasVLX, HasDQI]
vextractf64x2 {idx, src1, dst|dst, src1, idx}
VEXTRACTF64X2Z256rrik [HasVLX, HasDQI]
vextractf64x2 {idx, src1, dst {mask}|dst {mask}, src1, idx}
|
Note
|
Constraints: src0 = dst |
VEXTRACTF64X2Z256rrikz [HasVLX, HasDQI]
vextractf64x2 {idx, src1, dst {mask} {z}|dst {mask} {z}, src1, idx}
VEXTRACTI64X2Z256mri [HasVLX, HasDQI]
vextracti64x2 {idx, src1, dst|dst, src1, idx}
VEXTRACTI64X2Z256mrik [HasVLX, HasDQI]
vextracti64x2 {idx, src1, dst {mask}|dst {mask}, src1, idx}
|
Note
|
Properties: mayStore |
VEXTRACTI64X2Z256rri [HasVLX, HasDQI]
vextracti64x2 {idx, src1, dst|dst, src1, idx}
VEXTRACTI64X2Z256rrik [HasVLX, HasDQI]
vextracti64x2 {idx, src1, dst {mask}|dst {mask}, src1, idx}
|
Note
|
Constraints: src0 = dst |
VEXTRACTI64X2Z256rrikz [HasVLX, HasDQI]
vextracti64x2 {idx, src1, dst {mask} {z}|dst {mask} {z}, src1, idx}
VFPCLASSPDZ128mbi [HasVLX, HasDQI]
vfpclasspd {src2, src1{1to2}, dst|dst, src1{1to2}, src2}
VFPCLASSPDZ128mbik [HasVLX, HasDQI]
vfpclasspd {src2, src1{1to2}, dst {mask}|dst {mask}, src1{1to2}, src2}
VFPCLASSPDZ128mi [HasVLX, HasDQI]
vfpclasspd{x} {src2, src1, dst|dst, src1, src2}
VFPCLASSPDZ128mik [HasVLX, HasDQI]
vfpclasspd{x} {src2, src1, dst {mask}|dst {mask}, src1, src2}
VFPCLASSPDZ128ri [HasVLX, HasDQI]
vfpclasspd {src2, src1, dst|dst, src1, src2}
VFPCLASSPDZ128rik [HasVLX, HasDQI]
vfpclasspd {src2, src1, dst {mask}|dst {mask}, src1, src2}
VFPCLASSPDZ256mbi [HasVLX, HasDQI]
vfpclasspd {src2, src1{1to4}, dst|dst, src1{1to4}, src2}
VFPCLASSPDZ256mbik [HasVLX, HasDQI]
vfpclasspd {src2, src1{1to4}, dst {mask}|dst {mask}, src1{1to4}, src2}
VFPCLASSPDZ256mi [HasVLX, HasDQI]
vfpclasspd{y} {src2, src1, dst|dst, src1, src2}
VFPCLASSPDZ256mik [HasVLX, HasDQI]
vfpclasspd{y} {src2, src1, dst {mask}|dst {mask}, src1, src2}
VFPCLASSPDZ256ri [HasVLX, HasDQI]
vfpclasspd {src2, src1, dst|dst, src1, src2}
VFPCLASSPDZ256rik [HasVLX, HasDQI]
vfpclasspd {src2, src1, dst {mask}|dst {mask}, src1, src2}
VFPCLASSPSZ128mbi [HasVLX, HasDQI]
vfpclassps {src2, src1{1to4}, dst|dst, src1{1to4}, src2}
VFPCLASSPSZ128mbik [HasVLX, HasDQI]
vfpclassps {src2, src1{1to4}, dst {mask}|dst {mask}, src1{1to4}, src2}
VFPCLASSPSZ128mi [HasVLX, HasDQI]
vfpclassps{x} {src2, src1, dst|dst, src1, src2}
VFPCLASSPSZ128mik [HasVLX, HasDQI]
vfpclassps{x} {src2, src1, dst {mask}|dst {mask}, src1, src2}
VFPCLASSPSZ128ri [HasVLX, HasDQI]
vfpclassps {src2, src1, dst|dst, src1, src2}
VFPCLASSPSZ128rik [HasVLX, HasDQI]
vfpclassps {src2, src1, dst {mask}|dst {mask}, src1, src2}
VFPCLASSPSZ256mbi [HasVLX, HasDQI]
vfpclassps {src2, src1{1to8}, dst|dst, src1{1to8}, src2}
VFPCLASSPSZ256mbik [HasVLX, HasDQI]
vfpclassps {src2, src1{1to8}, dst {mask}|dst {mask}, src1{1to8}, src2}
VFPCLASSPSZ256mi [HasVLX, HasDQI]
vfpclassps{y} {src2, src1, dst|dst, src1, src2}
VFPCLASSPSZ256mik [HasVLX, HasDQI]
vfpclassps{y} {src2, src1, dst {mask}|dst {mask}, src1, src2}
VFPCLASSPSZ256ri [HasVLX, HasDQI]
vfpclassps {src2, src1, dst|dst, src1, src2}
VFPCLASSPSZ256rik [HasVLX, HasDQI]
vfpclassps {src2, src1, dst {mask}|dst {mask}, src1, src2}
VINSERTF64X2Z256rmi [HasVLX, HasDQI]
vinsertf64x2 {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayLoad |
VINSERTF64X2Z256rmik [HasVLX, HasDQI]
vinsertf64x2 {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VINSERTF64X2Z256rmikz [HasVLX, HasDQI]
vinsertf64x2 {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
|
Note
|
Properties: mayLoad |
VINSERTF64X2Z256rri [HasVLX, HasDQI]
vinsertf64x2 {src3, src2, src1, dst|dst, src1, src2, src3}
VINSERTF64X2Z256rrik [HasVLX, HasDQI]
vinsertf64x2 {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VINSERTF64X2Z256rrikz [HasVLX, HasDQI]
vinsertf64x2 {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VINSERTI64X2Z256rmi [HasVLX, HasDQI]
vinserti64x2 {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayLoad |
VINSERTI64X2Z256rmik [HasVLX, HasDQI]
vinserti64x2 {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VINSERTI64X2Z256rmikz [HasVLX, HasDQI]
vinserti64x2 {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
|
Note
|
Properties: mayLoad |
VINSERTI64X2Z256rri [HasVLX, HasDQI]
vinserti64x2 {src3, src2, src1, dst|dst, src1, src2, src3}
VINSERTI64X2Z256rrik [HasVLX, HasDQI]
vinserti64x2 {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VINSERTI64X2Z256rrikz [HasVLX, HasDQI]
vinserti64x2 {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VORPDZ128rm [HasVLX, HasDQI]
vorpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VORPDZ128rmb [HasVLX, HasDQI]
vorpd {src2{1to2}, src1, dst|dst, src1, src2{1to2}}
|
Note
|
Properties: mayLoad |
VORPDZ128rmbk [HasVLX, HasDQI]
vorpd {src2{1to2}, src1, dst {mask}|dst {mask}, src1, src2{1to2}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VORPDZ128rmbkz [HasVLX, HasDQI]
vorpd {src2{1to2}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to2}}
|
Note
|
Properties: mayLoad |
VORPDZ128rmk [HasVLX, HasDQI]
vorpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VORPDZ128rmkz [HasVLX, HasDQI]
vorpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VORPDZ128rr [HasVLX, HasDQI]
vorpd {src2, src1, dst|dst, src1, src2}
VORPDZ128rrk [HasVLX, HasDQI]
vorpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VORPDZ128rrkz [HasVLX, HasDQI]
vorpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VORPDZ256rm [HasVLX, HasDQI]
vorpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VORPDZ256rmb [HasVLX, HasDQI]
vorpd {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
|
Note
|
Properties: mayLoad |
VORPDZ256rmbk [HasVLX, HasDQI]
vorpd {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VORPDZ256rmbkz [HasVLX, HasDQI]
vorpd {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
|
Note
|
Properties: mayLoad |
VORPDZ256rmk [HasVLX, HasDQI]
vorpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VORPDZ256rmkz [HasVLX, HasDQI]
vorpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VORPDZ256rr [HasVLX, HasDQI]
vorpd {src2, src1, dst|dst, src1, src2}
VORPDZ256rrk [HasVLX, HasDQI]
vorpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VORPDZ256rrkz [HasVLX, HasDQI]
vorpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VORPSZ128rm [HasVLX, HasDQI]
vorps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VORPSZ128rmb [HasVLX, HasDQI]
vorps {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
|
Note
|
Properties: mayLoad |
VORPSZ128rmbk [HasVLX, HasDQI]
vorps {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VORPSZ128rmbkz [HasVLX, HasDQI]
vorps {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
|
Note
|
Properties: mayLoad |
VORPSZ128rmk [HasVLX, HasDQI]
vorps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VORPSZ128rmkz [HasVLX, HasDQI]
vorps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VORPSZ128rr [HasVLX, HasDQI]
vorps {src2, src1, dst|dst, src1, src2}
VORPSZ128rrk [HasVLX, HasDQI]
vorps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VORPSZ128rrkz [HasVLX, HasDQI]
vorps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VORPSZ256rm [HasVLX, HasDQI]
vorps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VORPSZ256rmb [HasVLX, HasDQI]
vorps {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
VORPSZ256rmbk [HasVLX, HasDQI]
vorps {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VORPSZ256rmbkz [HasVLX, HasDQI]
vorps {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
VORPSZ256rmk [HasVLX, HasDQI]
vorps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VORPSZ256rmkz [HasVLX, HasDQI]
vorps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VORPSZ256rr [HasVLX, HasDQI]
vorps {src2, src1, dst|dst, src1, src2}
VORPSZ256rrk [HasVLX, HasDQI]
vorps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VORPSZ256rrkz [HasVLX, HasDQI]
vorps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMOVD2MZ128kr [HasVLX, HasDQI]
vpmovd2m {src, dst|dst, src}
VPMOVD2MZ256kr [HasVLX, HasDQI]
vpmovd2m {src, dst|dst, src}
VPMOVM2DZ128rk [HasVLX, HasDQI]
vpmovm2d {src, dst|dst, src}
VPMOVM2DZ256rk [HasVLX, HasDQI]
vpmovm2d {src, dst|dst, src}
VPMOVM2QZ128rk [HasVLX, HasDQI]
vpmovm2q {src, dst|dst, src}
VPMOVM2QZ256rk [HasVLX, HasDQI]
vpmovm2q {src, dst|dst, src}
VPMOVQ2MZ128kr [HasVLX, HasDQI]
vpmovq2m {src, dst|dst, src}
VPMOVQ2MZ256kr [HasVLX, HasDQI]
vpmovq2m {src, dst|dst, src}
VPMULLQZ128rm [HasVLX, HasDQI]
vpmullq {src2, src1, dst|dst, src1, src2}
VPMULLQZ128rmb [HasVLX, HasDQI]
vpmullq {src2{1to2}, src1, dst|dst, src1, src2{1to2}}
VPMULLQZ128rmbk [HasVLX, HasDQI]
vpmullq {src2{1to2}, src1, dst {mask}|dst {mask}, src1, src2{1to2}}
|
Note
|
Constraints: src0 = dst |
VPMULLQZ128rmbkz [HasVLX, HasDQI]
vpmullq {src2{1to2}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to2}}
VPMULLQZ128rmk [HasVLX, HasDQI]
vpmullq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMULLQZ128rmkz [HasVLX, HasDQI]
vpmullq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMULLQZ128rr [HasVLX, HasDQI]
vpmullq {src2, src1, dst|dst, src1, src2}
VPMULLQZ128rrk [HasVLX, HasDQI]
vpmullq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMULLQZ128rrkz [HasVLX, HasDQI]
vpmullq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMULLQZ256rm [HasVLX, HasDQI]
vpmullq {src2, src1, dst|dst, src1, src2}
VPMULLQZ256rmb [HasVLX, HasDQI]
vpmullq {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
VPMULLQZ256rmbk [HasVLX, HasDQI]
vpmullq {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Constraints: src0 = dst |
VPMULLQZ256rmbkz [HasVLX, HasDQI]
vpmullq {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
VPMULLQZ256rmk [HasVLX, HasDQI]
vpmullq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMULLQZ256rmkz [HasVLX, HasDQI]
vpmullq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMULLQZ256rr [HasVLX, HasDQI]
vpmullq {src2, src1, dst|dst, src1, src2}
VPMULLQZ256rrk [HasVLX, HasDQI]
vpmullq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMULLQZ256rrkz [HasVLX, HasDQI]
vpmullq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VRANGEPDZ128rmbi [HasVLX, HasDQI]
vrangepd {src3, src2{1to2}, src1, dst|dst, src1, src2{1to2}, src3}
|
Note
|
Properties: mayRaiseFPException |
VRANGEPDZ128rmbik [HasVLX, HasDQI]
vrangepd {src3, src2{1to2}, src1, dst {mask}|dst {mask}, src1, src2{1to2}, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRANGEPDZ128rmbikz [HasVLX, HasDQI]
vrangepd {src3, src2{1to2}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to2}, src3}
|
Note
|
Properties: mayRaiseFPException |
VRANGEPDZ128rmi [HasVLX, HasDQI]
vrangepd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VRANGEPDZ128rmik [HasVLX, HasDQI]
vrangepd {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRANGEPDZ128rmikz [HasVLX, HasDQI]
vrangepd {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VRANGEPDZ128rri [HasVLX, HasDQI]
vrangepd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VRANGEPDZ128rrik [HasVLX, HasDQI]
vrangepd {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRANGEPDZ128rrikz [HasVLX, HasDQI]
vrangepd {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VRANGEPDZ256rmbi [HasVLX, HasDQI]
vrangepd {src3, src2{1to4}, src1, dst|dst, src1, src2{1to4}, src3}
|
Note
|
Properties: mayRaiseFPException |
VRANGEPDZ256rmbik [HasVLX, HasDQI]
vrangepd {src3, src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRANGEPDZ256rmbikz [HasVLX, HasDQI]
vrangepd {src3, src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}, src3}
|
Note
|
Properties: mayRaiseFPException |
VRANGEPDZ256rmi [HasVLX, HasDQI]
vrangepd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VRANGEPDZ256rmik [HasVLX, HasDQI]
vrangepd {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRANGEPDZ256rmikz [HasVLX, HasDQI]
vrangepd {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VRANGEPDZ256rri [HasVLX, HasDQI]
vrangepd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VRANGEPDZ256rrik [HasVLX, HasDQI]
vrangepd {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRANGEPDZ256rrikz [HasVLX, HasDQI]
vrangepd {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VRANGEPSZ128rmbi [HasVLX, HasDQI]
vrangeps {src3, src2{1to4}, src1, dst|dst, src1, src2{1to4}, src3}
|
Note
|
Properties: mayRaiseFPException |
VRANGEPSZ128rmbik [HasVLX, HasDQI]
vrangeps {src3, src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRANGEPSZ128rmbikz [HasVLX, HasDQI]
vrangeps {src3, src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}, src3}
|
Note
|
Properties: mayRaiseFPException |
VRANGEPSZ128rmi [HasVLX, HasDQI]
vrangeps {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VRANGEPSZ128rmik [HasVLX, HasDQI]
vrangeps {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRANGEPSZ128rmikz [HasVLX, HasDQI]
vrangeps {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VRANGEPSZ128rri [HasVLX, HasDQI]
vrangeps {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VRANGEPSZ128rrik [HasVLX, HasDQI]
vrangeps {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRANGEPSZ128rrikz [HasVLX, HasDQI]
vrangeps {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VRANGEPSZ256rmbi [HasVLX, HasDQI]
vrangeps {src3, src2{1to8}, src1, dst|dst, src1, src2{1to8}, src3}
|
Note
|
Properties: mayRaiseFPException |
VRANGEPSZ256rmbik [HasVLX, HasDQI]
vrangeps {src3, src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRANGEPSZ256rmbikz [HasVLX, HasDQI]
vrangeps {src3, src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}, src3}
|
Note
|
Properties: mayRaiseFPException |
VRANGEPSZ256rmi [HasVLX, HasDQI]
vrangeps {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VRANGEPSZ256rmik [HasVLX, HasDQI]
vrangeps {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRANGEPSZ256rmikz [HasVLX, HasDQI]
vrangeps {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VRANGEPSZ256rri [HasVLX, HasDQI]
vrangeps {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VRANGEPSZ256rrik [HasVLX, HasDQI]
vrangeps {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRANGEPSZ256rrikz [HasVLX, HasDQI]
vrangeps {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VREDUCEPDZ128rmbi [HasVLX, HasDQI]
vreducepd {src2, src1{1to2}, dst|dst, src1{1to2}, src2}
|
Note
|
Properties: mayRaiseFPException |
VREDUCEPDZ128rmbik [HasVLX, HasDQI]
vreducepd {src2, src1{1to2}, dst {mask}|dst {mask}, src1{1to2}, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VREDUCEPDZ128rmbikz [HasVLX, HasDQI]
vreducepd {src2, src1{1to2}, dst {mask} {z}|dst {mask} {z}, src1{1to2}, src2}
|
Note
|
Properties: mayRaiseFPException |
VREDUCEPDZ128rmi [HasVLX, HasDQI]
vreducepd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VREDUCEPDZ128rmik [HasVLX, HasDQI]
vreducepd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VREDUCEPDZ128rmikz [HasVLX, HasDQI]
vreducepd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VREDUCEPDZ128rri [HasVLX, HasDQI]
vreducepd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VREDUCEPDZ128rrik [HasVLX, HasDQI]
vreducepd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VREDUCEPDZ128rrikz [HasVLX, HasDQI]
vreducepd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VREDUCEPDZ256rmbi [HasVLX, HasDQI]
vreducepd {src2, src1{1to4}, dst|dst, src1{1to4}, src2}
|
Note
|
Properties: mayRaiseFPException |
VREDUCEPDZ256rmbik [HasVLX, HasDQI]
vreducepd {src2, src1{1to4}, dst {mask}|dst {mask}, src1{1to4}, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VREDUCEPDZ256rmbikz [HasVLX, HasDQI]
vreducepd {src2, src1{1to4}, dst {mask} {z}|dst {mask} {z}, src1{1to4}, src2}
|
Note
|
Properties: mayRaiseFPException |
VREDUCEPDZ256rmi [HasVLX, HasDQI]
vreducepd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VREDUCEPDZ256rmik [HasVLX, HasDQI]
vreducepd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VREDUCEPDZ256rmikz [HasVLX, HasDQI]
vreducepd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VREDUCEPDZ256rri [HasVLX, HasDQI]
vreducepd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VREDUCEPDZ256rrik [HasVLX, HasDQI]
vreducepd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VREDUCEPDZ256rrikz [HasVLX, HasDQI]
vreducepd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VREDUCEPSZ128rmbi [HasVLX, HasDQI]
vreduceps {src2, src1{1to4}, dst|dst, src1{1to4}, src2}
|
Note
|
Properties: mayRaiseFPException |
VREDUCEPSZ128rmbik [HasVLX, HasDQI]
vreduceps {src2, src1{1to4}, dst {mask}|dst {mask}, src1{1to4}, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VREDUCEPSZ128rmbikz [HasVLX, HasDQI]
vreduceps {src2, src1{1to4}, dst {mask} {z}|dst {mask} {z}, src1{1to4}, src2}
|
Note
|
Properties: mayRaiseFPException |
VREDUCEPSZ128rmi [HasVLX, HasDQI]
vreduceps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VREDUCEPSZ128rmik [HasVLX, HasDQI]
vreduceps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VREDUCEPSZ128rmikz [HasVLX, HasDQI]
vreduceps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VREDUCEPSZ128rri [HasVLX, HasDQI]
vreduceps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VREDUCEPSZ128rrik [HasVLX, HasDQI]
vreduceps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VREDUCEPSZ128rrikz [HasVLX, HasDQI]
vreduceps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VREDUCEPSZ256rmbi [HasVLX, HasDQI]
vreduceps {src2, src1{1to8}, dst|dst, src1{1to8}, src2}
|
Note
|
Properties: mayRaiseFPException |
VREDUCEPSZ256rmbik [HasVLX, HasDQI]
vreduceps {src2, src1{1to8}, dst {mask}|dst {mask}, src1{1to8}, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VREDUCEPSZ256rmbikz [HasVLX, HasDQI]
vreduceps {src2, src1{1to8}, dst {mask} {z}|dst {mask} {z}, src1{1to8}, src2}
|
Note
|
Properties: mayRaiseFPException |
VREDUCEPSZ256rmi [HasVLX, HasDQI]
vreduceps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VREDUCEPSZ256rmik [HasVLX, HasDQI]
vreduceps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VREDUCEPSZ256rmikz [HasVLX, HasDQI]
vreduceps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VREDUCEPSZ256rri [HasVLX, HasDQI]
vreduceps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VREDUCEPSZ256rrik [HasVLX, HasDQI]
vreduceps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VREDUCEPSZ256rrikz [HasVLX, HasDQI]
vreduceps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VXORPDZ128rm [HasVLX, HasDQI]
vxorpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VXORPDZ128rmb [HasVLX, HasDQI]
vxorpd {src2{1to2}, src1, dst|dst, src1, src2{1to2}}
|
Note
|
Properties: mayLoad |
VXORPDZ128rmbk [HasVLX, HasDQI]
vxorpd {src2{1to2}, src1, dst {mask}|dst {mask}, src1, src2{1to2}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VXORPDZ128rmbkz [HasVLX, HasDQI]
vxorpd {src2{1to2}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to2}}
|
Note
|
Properties: mayLoad |
VXORPDZ128rmk [HasVLX, HasDQI]
vxorpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VXORPDZ128rmkz [HasVLX, HasDQI]
vxorpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VXORPDZ128rr [HasVLX, HasDQI]
vxorpd {src2, src1, dst|dst, src1, src2}
VXORPDZ128rrk [HasVLX, HasDQI]
vxorpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VXORPDZ128rrkz [HasVLX, HasDQI]
vxorpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VXORPDZ256rm [HasVLX, HasDQI]
vxorpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VXORPDZ256rmb [HasVLX, HasDQI]
vxorpd {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
|
Note
|
Properties: mayLoad |
VXORPDZ256rmbk [HasVLX, HasDQI]
vxorpd {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VXORPDZ256rmbkz [HasVLX, HasDQI]
vxorpd {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
|
Note
|
Properties: mayLoad |
VXORPDZ256rmk [HasVLX, HasDQI]
vxorpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VXORPDZ256rmkz [HasVLX, HasDQI]
vxorpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VXORPDZ256rr [HasVLX, HasDQI]
vxorpd {src2, src1, dst|dst, src1, src2}
VXORPDZ256rrk [HasVLX, HasDQI]
vxorpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VXORPDZ256rrkz [HasVLX, HasDQI]
vxorpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VXORPSZ128rm [HasVLX, HasDQI]
vxorps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VXORPSZ128rmb [HasVLX, HasDQI]
vxorps {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
|
Note
|
Properties: mayLoad |
VXORPSZ128rmbk [HasVLX, HasDQI]
vxorps {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VXORPSZ128rmbkz [HasVLX, HasDQI]
vxorps {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
|
Note
|
Properties: mayLoad |
VXORPSZ128rmk [HasVLX, HasDQI]
vxorps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VXORPSZ128rmkz [HasVLX, HasDQI]
vxorps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VXORPSZ128rr [HasVLX, HasDQI]
vxorps {src2, src1, dst|dst, src1, src2}
VXORPSZ128rrk [HasVLX, HasDQI]
vxorps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VXORPSZ128rrkz [HasVLX, HasDQI]
vxorps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VXORPSZ256rm [HasVLX, HasDQI]
vxorps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VXORPSZ256rmb [HasVLX, HasDQI]
vxorps {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
VXORPSZ256rmbk [HasVLX, HasDQI]
vxorps {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VXORPSZ256rmbkz [HasVLX, HasDQI]
vxorps {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
VXORPSZ256rmk [HasVLX, HasDQI]
vxorps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VXORPSZ256rmkz [HasVLX, HasDQI]
vxorps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VXORPSZ256rr [HasVLX, HasDQI]
vxorps {src2, src1, dst|dst, src1, src2}
VXORPSZ256rrk [HasVLX, HasDQI]
vxorps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VXORPSZ256rrkz [HasVLX, HasDQI]
vxorps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPCOMPRESSBZ128mr [HasVLX, HasVBMI2]
vpcompressb {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VPCOMPRESSBZ128mrk [HasVLX, HasVBMI2]
vpcompressb {src, dst {mask}|dst {mask}, src}
VPCOMPRESSBZ128rr [HasVLX, HasVBMI2]
vpcompressb {src1, dst|dst, src1}
VPCOMPRESSBZ128rrk [HasVLX, HasVBMI2]
vpcompressb {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPCOMPRESSBZ128rrkz [HasVLX, HasVBMI2]
vpcompressb {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPCOMPRESSBZ256mr [HasVLX, HasVBMI2]
vpcompressb {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VPCOMPRESSBZ256mrk [HasVLX, HasVBMI2]
vpcompressb {src, dst {mask}|dst {mask}, src}
VPCOMPRESSBZ256rr [HasVLX, HasVBMI2]
vpcompressb {src1, dst|dst, src1}
VPCOMPRESSBZ256rrk [HasVLX, HasVBMI2]
vpcompressb {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPCOMPRESSBZ256rrkz [HasVLX, HasVBMI2]
vpcompressb {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPCOMPRESSWZ128mr [HasVLX, HasVBMI2]
vpcompressw {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VPCOMPRESSWZ128mrk [HasVLX, HasVBMI2]
vpcompressw {src, dst {mask}|dst {mask}, src}
VPCOMPRESSWZ128rr [HasVLX, HasVBMI2]
vpcompressw {src1, dst|dst, src1}
VPCOMPRESSWZ128rrk [HasVLX, HasVBMI2]
vpcompressw {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPCOMPRESSWZ128rrkz [HasVLX, HasVBMI2]
vpcompressw {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPCOMPRESSWZ256mr [HasVLX, HasVBMI2]
vpcompressw {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VPCOMPRESSWZ256mrk [HasVLX, HasVBMI2]
vpcompressw {src, dst {mask}|dst {mask}, src}
VPCOMPRESSWZ256rr [HasVLX, HasVBMI2]
vpcompressw {src1, dst|dst, src1}
VPCOMPRESSWZ256rrk [HasVLX, HasVBMI2]
vpcompressw {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPCOMPRESSWZ256rrkz [HasVLX, HasVBMI2]
vpcompressw {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPEXPANDBZ128rm [HasVLX, HasVBMI2]
vpexpandb {src1, dst|dst, src1}
VPEXPANDBZ128rmk [HasVLX, HasVBMI2]
vpexpandb {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPEXPANDBZ128rmkz [HasVLX, HasVBMI2]
vpexpandb {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPEXPANDBZ128rr [HasVLX, HasVBMI2]
vpexpandb {src1, dst|dst, src1}
VPEXPANDBZ128rrk [HasVLX, HasVBMI2]
vpexpandb {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPEXPANDBZ128rrkz [HasVLX, HasVBMI2]
vpexpandb {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPEXPANDBZ256rm [HasVLX, HasVBMI2]
vpexpandb {src1, dst|dst, src1}
VPEXPANDBZ256rmk [HasVLX, HasVBMI2]
vpexpandb {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPEXPANDBZ256rmkz [HasVLX, HasVBMI2]
vpexpandb {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPEXPANDBZ256rr [HasVLX, HasVBMI2]
vpexpandb {src1, dst|dst, src1}
VPEXPANDBZ256rrk [HasVLX, HasVBMI2]
vpexpandb {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPEXPANDBZ256rrkz [HasVLX, HasVBMI2]
vpexpandb {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPEXPANDWZ128rm [HasVLX, HasVBMI2]
vpexpandw {src1, dst|dst, src1}
VPEXPANDWZ128rmk [HasVLX, HasVBMI2]
vpexpandw {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPEXPANDWZ128rmkz [HasVLX, HasVBMI2]
vpexpandw {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPEXPANDWZ128rr [HasVLX, HasVBMI2]
vpexpandw {src1, dst|dst, src1}
VPEXPANDWZ128rrk [HasVLX, HasVBMI2]
vpexpandw {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPEXPANDWZ128rrkz [HasVLX, HasVBMI2]
vpexpandw {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPEXPANDWZ256rm [HasVLX, HasVBMI2]
vpexpandw {src1, dst|dst, src1}
VPEXPANDWZ256rmk [HasVLX, HasVBMI2]
vpexpandw {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPEXPANDWZ256rmkz [HasVLX, HasVBMI2]
vpexpandw {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPEXPANDWZ256rr [HasVLX, HasVBMI2]
vpexpandw {src1, dst|dst, src1}
VPEXPANDWZ256rrk [HasVLX, HasVBMI2]
vpexpandw {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPEXPANDWZ256rrkz [HasVLX, HasVBMI2]
vpexpandw {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPSHLDDZ128rmbi [HasVLX, HasVBMI2]
vpshldd {src3, src2{1to4}, src1, dst|dst, src1, src2{1to4}, src3}
VPSHLDDZ128rmbik [HasVLX, HasVBMI2]
vpshldd {src3, src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}, src3}
|
Note
|
Constraints: src0 = dst |
VPSHLDDZ128rmbikz [HasVLX, HasVBMI2]
vpshldd {src3, src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}, src3}
VPSHLDDZ128rmi [HasVLX, HasVBMI2]
vpshldd {src3, src2, src1, dst|dst, src1, src2, src3}
VPSHLDDZ128rmik [HasVLX, HasVBMI2]
vpshldd {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VPSHLDDZ128rmikz [HasVLX, HasVBMI2]
vpshldd {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VPSHLDDZ128rri [HasVLX, HasVBMI2]
vpshldd {src3, src2, src1, dst|dst, src1, src2, src3}
VPSHLDDZ128rrik [HasVLX, HasVBMI2]
vpshldd {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VPSHLDDZ128rrikz [HasVLX, HasVBMI2]
vpshldd {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VPSHLDDZ256rmbi [HasVLX, HasVBMI2]
vpshldd {src3, src2{1to8}, src1, dst|dst, src1, src2{1to8}, src3}
VPSHLDDZ256rmbik [HasVLX, HasVBMI2]
vpshldd {src3, src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}, src3}
|
Note
|
Constraints: src0 = dst |
VPSHLDDZ256rmbikz [HasVLX, HasVBMI2]
vpshldd {src3, src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}, src3}
VPSHLDDZ256rmi [HasVLX, HasVBMI2]
vpshldd {src3, src2, src1, dst|dst, src1, src2, src3}
VPSHLDDZ256rmik [HasVLX, HasVBMI2]
vpshldd {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VPSHLDDZ256rmikz [HasVLX, HasVBMI2]
vpshldd {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VPSHLDDZ256rri [HasVLX, HasVBMI2]
vpshldd {src3, src2, src1, dst|dst, src1, src2, src3}
VPSHLDDZ256rrik [HasVLX, HasVBMI2]
vpshldd {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VPSHLDDZ256rrikz [HasVLX, HasVBMI2]
vpshldd {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VPSHLDQZ128rmbi [HasVLX, HasVBMI2]
vpshldq {src3, src2{1to2}, src1, dst|dst, src1, src2{1to2}, src3}
VPSHLDQZ128rmbik [HasVLX, HasVBMI2]
vpshldq {src3, src2{1to2}, src1, dst {mask}|dst {mask}, src1, src2{1to2}, src3}
|
Note
|
Constraints: src0 = dst |
VPSHLDQZ128rmbikz [HasVLX, HasVBMI2]
vpshldq {src3, src2{1to2}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to2}, src3}
VPSHLDQZ128rmi [HasVLX, HasVBMI2]
vpshldq {src3, src2, src1, dst|dst, src1, src2, src3}
VPSHLDQZ128rmik [HasVLX, HasVBMI2]
vpshldq {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VPSHLDQZ128rmikz [HasVLX, HasVBMI2]
vpshldq {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VPSHLDQZ128rri [HasVLX, HasVBMI2]
vpshldq {src3, src2, src1, dst|dst, src1, src2, src3}
VPSHLDQZ128rrik [HasVLX, HasVBMI2]
vpshldq {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VPSHLDQZ128rrikz [HasVLX, HasVBMI2]
vpshldq {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VPSHLDQZ256rmbi [HasVLX, HasVBMI2]
vpshldq {src3, src2{1to4}, src1, dst|dst, src1, src2{1to4}, src3}
VPSHLDQZ256rmbik [HasVLX, HasVBMI2]
vpshldq {src3, src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}, src3}
|
Note
|
Constraints: src0 = dst |
VPSHLDQZ256rmbikz [HasVLX, HasVBMI2]
vpshldq {src3, src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}, src3}
VPSHLDQZ256rmi [HasVLX, HasVBMI2]
vpshldq {src3, src2, src1, dst|dst, src1, src2, src3}
VPSHLDQZ256rmik [HasVLX, HasVBMI2]
vpshldq {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VPSHLDQZ256rmikz [HasVLX, HasVBMI2]
vpshldq {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VPSHLDQZ256rri [HasVLX, HasVBMI2]
vpshldq {src3, src2, src1, dst|dst, src1, src2, src3}
VPSHLDQZ256rrik [HasVLX, HasVBMI2]
vpshldq {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VPSHLDQZ256rrikz [HasVLX, HasVBMI2]
vpshldq {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VPSHLDVDZ128m [HasVLX, HasVBMI2]
vpshldvd {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHLDVDZ128mb [HasVLX, HasVBMI2]
vpshldvd {src3{1to4}, src2, dst|dst, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPSHLDVDZ128mbk [HasVLX, HasVBMI2]
vpshldvd {src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPSHLDVDZ128mbkz [HasVLX, HasVBMI2]
vpshldvd {src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPSHLDVDZ128mk [HasVLX, HasVBMI2]
vpshldvd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHLDVDZ128mkz [HasVLX, HasVBMI2]
vpshldvd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHLDVDZ128r [HasVLX, HasVBMI2]
vpshldvd {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHLDVDZ128rk [HasVLX, HasVBMI2]
vpshldvd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHLDVDZ128rkz [HasVLX, HasVBMI2]
vpshldvd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHLDVDZ256m [HasVLX, HasVBMI2]
vpshldvd {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHLDVDZ256mb [HasVLX, HasVBMI2]
vpshldvd {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPSHLDVDZ256mbk [HasVLX, HasVBMI2]
vpshldvd {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPSHLDVDZ256mbkz [HasVLX, HasVBMI2]
vpshldvd {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPSHLDVDZ256mk [HasVLX, HasVBMI2]
vpshldvd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHLDVDZ256mkz [HasVLX, HasVBMI2]
vpshldvd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHLDVDZ256r [HasVLX, HasVBMI2]
vpshldvd {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHLDVDZ256rk [HasVLX, HasVBMI2]
vpshldvd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHLDVDZ256rkz [HasVLX, HasVBMI2]
vpshldvd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHLDVQZ128m [HasVLX, HasVBMI2]
vpshldvq {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHLDVQZ128mb [HasVLX, HasVBMI2]
vpshldvq {src3{1to2}, src2, dst|dst, src2, src3{1to2}}
|
Note
|
Constraints: src1 = dst |
VPSHLDVQZ128mbk [HasVLX, HasVBMI2]
vpshldvq {src3{1to2}, src2, dst {mask}|dst {mask}, src2, src3{1to2}}
|
Note
|
Constraints: src1 = dst |
VPSHLDVQZ128mbkz [HasVLX, HasVBMI2]
vpshldvq {src3{1to2}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to2}}
|
Note
|
Constraints: src1 = dst |
VPSHLDVQZ128mk [HasVLX, HasVBMI2]
vpshldvq {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHLDVQZ128mkz [HasVLX, HasVBMI2]
vpshldvq {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHLDVQZ128r [HasVLX, HasVBMI2]
vpshldvq {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHLDVQZ128rk [HasVLX, HasVBMI2]
vpshldvq {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHLDVQZ128rkz [HasVLX, HasVBMI2]
vpshldvq {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHLDVQZ256m [HasVLX, HasVBMI2]
vpshldvq {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHLDVQZ256mb [HasVLX, HasVBMI2]
vpshldvq {src3{1to4}, src2, dst|dst, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPSHLDVQZ256mbk [HasVLX, HasVBMI2]
vpshldvq {src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPSHLDVQZ256mbkz [HasVLX, HasVBMI2]
vpshldvq {src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPSHLDVQZ256mk [HasVLX, HasVBMI2]
vpshldvq {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHLDVQZ256mkz [HasVLX, HasVBMI2]
vpshldvq {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHLDVQZ256r [HasVLX, HasVBMI2]
vpshldvq {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHLDVQZ256rk [HasVLX, HasVBMI2]
vpshldvq {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHLDVQZ256rkz [HasVLX, HasVBMI2]
vpshldvq {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHLDVWZ128m [HasVLX, HasVBMI2]
vpshldvw {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHLDVWZ128mk [HasVLX, HasVBMI2]
vpshldvw {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHLDVWZ128mkz [HasVLX, HasVBMI2]
vpshldvw {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHLDVWZ128r [HasVLX, HasVBMI2]
vpshldvw {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHLDVWZ128rk [HasVLX, HasVBMI2]
vpshldvw {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHLDVWZ128rkz [HasVLX, HasVBMI2]
vpshldvw {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHLDVWZ256m [HasVLX, HasVBMI2]
vpshldvw {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHLDVWZ256mk [HasVLX, HasVBMI2]
vpshldvw {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHLDVWZ256mkz [HasVLX, HasVBMI2]
vpshldvw {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHLDVWZ256r [HasVLX, HasVBMI2]
vpshldvw {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHLDVWZ256rk [HasVLX, HasVBMI2]
vpshldvw {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHLDVWZ256rkz [HasVLX, HasVBMI2]
vpshldvw {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHLDWZ128rmi [HasVLX, HasVBMI2]
vpshldw {src3, src2, src1, dst|dst, src1, src2, src3}
VPSHLDWZ128rmik [HasVLX, HasVBMI2]
vpshldw {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VPSHLDWZ128rmikz [HasVLX, HasVBMI2]
vpshldw {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VPSHLDWZ128rri [HasVLX, HasVBMI2]
vpshldw {src3, src2, src1, dst|dst, src1, src2, src3}
VPSHLDWZ128rrik [HasVLX, HasVBMI2]
vpshldw {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VPSHLDWZ128rrikz [HasVLX, HasVBMI2]
vpshldw {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VPSHLDWZ256rmi [HasVLX, HasVBMI2]
vpshldw {src3, src2, src1, dst|dst, src1, src2, src3}
VPSHLDWZ256rmik [HasVLX, HasVBMI2]
vpshldw {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VPSHLDWZ256rmikz [HasVLX, HasVBMI2]
vpshldw {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VPSHLDWZ256rri [HasVLX, HasVBMI2]
vpshldw {src3, src2, src1, dst|dst, src1, src2, src3}
VPSHLDWZ256rrik [HasVLX, HasVBMI2]
vpshldw {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VPSHLDWZ256rrikz [HasVLX, HasVBMI2]
vpshldw {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VPSHRDDZ128rmbi [HasVLX, HasVBMI2]
vpshrdd {src3, src2{1to4}, src1, dst|dst, src1, src2{1to4}, src3}
VPSHRDDZ128rmbik [HasVLX, HasVBMI2]
vpshrdd {src3, src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}, src3}
|
Note
|
Constraints: src0 = dst |
VPSHRDDZ128rmbikz [HasVLX, HasVBMI2]
vpshrdd {src3, src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}, src3}
VPSHRDDZ128rmi [HasVLX, HasVBMI2]
vpshrdd {src3, src2, src1, dst|dst, src1, src2, src3}
VPSHRDDZ128rmik [HasVLX, HasVBMI2]
vpshrdd {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VPSHRDDZ128rmikz [HasVLX, HasVBMI2]
vpshrdd {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VPSHRDDZ128rri [HasVLX, HasVBMI2]
vpshrdd {src3, src2, src1, dst|dst, src1, src2, src3}
VPSHRDDZ128rrik [HasVLX, HasVBMI2]
vpshrdd {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VPSHRDDZ128rrikz [HasVLX, HasVBMI2]
vpshrdd {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VPSHRDDZ256rmbi [HasVLX, HasVBMI2]
vpshrdd {src3, src2{1to8}, src1, dst|dst, src1, src2{1to8}, src3}
VPSHRDDZ256rmbik [HasVLX, HasVBMI2]
vpshrdd {src3, src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}, src3}
|
Note
|
Constraints: src0 = dst |
VPSHRDDZ256rmbikz [HasVLX, HasVBMI2]
vpshrdd {src3, src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}, src3}
VPSHRDDZ256rmi [HasVLX, HasVBMI2]
vpshrdd {src3, src2, src1, dst|dst, src1, src2, src3}
VPSHRDDZ256rmik [HasVLX, HasVBMI2]
vpshrdd {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VPSHRDDZ256rmikz [HasVLX, HasVBMI2]
vpshrdd {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VPSHRDDZ256rri [HasVLX, HasVBMI2]
vpshrdd {src3, src2, src1, dst|dst, src1, src2, src3}
VPSHRDDZ256rrik [HasVLX, HasVBMI2]
vpshrdd {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VPSHRDDZ256rrikz [HasVLX, HasVBMI2]
vpshrdd {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VPSHRDQZ128rmbi [HasVLX, HasVBMI2]
vpshrdq {src3, src2{1to2}, src1, dst|dst, src1, src2{1to2}, src3}
VPSHRDQZ128rmbik [HasVLX, HasVBMI2]
vpshrdq {src3, src2{1to2}, src1, dst {mask}|dst {mask}, src1, src2{1to2}, src3}
|
Note
|
Constraints: src0 = dst |
VPSHRDQZ128rmbikz [HasVLX, HasVBMI2]
vpshrdq {src3, src2{1to2}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to2}, src3}
VPSHRDQZ128rmi [HasVLX, HasVBMI2]
vpshrdq {src3, src2, src1, dst|dst, src1, src2, src3}
VPSHRDQZ128rmik [HasVLX, HasVBMI2]
vpshrdq {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VPSHRDQZ128rmikz [HasVLX, HasVBMI2]
vpshrdq {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VPSHRDQZ128rri [HasVLX, HasVBMI2]
vpshrdq {src3, src2, src1, dst|dst, src1, src2, src3}
VPSHRDQZ128rrik [HasVLX, HasVBMI2]
vpshrdq {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VPSHRDQZ128rrikz [HasVLX, HasVBMI2]
vpshrdq {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VPSHRDQZ256rmbi [HasVLX, HasVBMI2]
vpshrdq {src3, src2{1to4}, src1, dst|dst, src1, src2{1to4}, src3}
VPSHRDQZ256rmbik [HasVLX, HasVBMI2]
vpshrdq {src3, src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}, src3}
|
Note
|
Constraints: src0 = dst |
VPSHRDQZ256rmbikz [HasVLX, HasVBMI2]
vpshrdq {src3, src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}, src3}
VPSHRDQZ256rmi [HasVLX, HasVBMI2]
vpshrdq {src3, src2, src1, dst|dst, src1, src2, src3}
VPSHRDQZ256rmik [HasVLX, HasVBMI2]
vpshrdq {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VPSHRDQZ256rmikz [HasVLX, HasVBMI2]
vpshrdq {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VPSHRDQZ256rri [HasVLX, HasVBMI2]
vpshrdq {src3, src2, src1, dst|dst, src1, src2, src3}
VPSHRDQZ256rrik [HasVLX, HasVBMI2]
vpshrdq {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VPSHRDQZ256rrikz [HasVLX, HasVBMI2]
vpshrdq {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VPSHRDVDZ128m [HasVLX, HasVBMI2]
vpshrdvd {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHRDVDZ128mb [HasVLX, HasVBMI2]
vpshrdvd {src3{1to4}, src2, dst|dst, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPSHRDVDZ128mbk [HasVLX, HasVBMI2]
vpshrdvd {src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPSHRDVDZ128mbkz [HasVLX, HasVBMI2]
vpshrdvd {src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPSHRDVDZ128mk [HasVLX, HasVBMI2]
vpshrdvd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHRDVDZ128mkz [HasVLX, HasVBMI2]
vpshrdvd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHRDVDZ128r [HasVLX, HasVBMI2]
vpshrdvd {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHRDVDZ128rk [HasVLX, HasVBMI2]
vpshrdvd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHRDVDZ128rkz [HasVLX, HasVBMI2]
vpshrdvd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHRDVDZ256m [HasVLX, HasVBMI2]
vpshrdvd {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHRDVDZ256mb [HasVLX, HasVBMI2]
vpshrdvd {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPSHRDVDZ256mbk [HasVLX, HasVBMI2]
vpshrdvd {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPSHRDVDZ256mbkz [HasVLX, HasVBMI2]
vpshrdvd {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPSHRDVDZ256mk [HasVLX, HasVBMI2]
vpshrdvd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHRDVDZ256mkz [HasVLX, HasVBMI2]
vpshrdvd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHRDVDZ256r [HasVLX, HasVBMI2]
vpshrdvd {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHRDVDZ256rk [HasVLX, HasVBMI2]
vpshrdvd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHRDVDZ256rkz [HasVLX, HasVBMI2]
vpshrdvd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHRDVQZ128m [HasVLX, HasVBMI2]
vpshrdvq {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHRDVQZ128mb [HasVLX, HasVBMI2]
vpshrdvq {src3{1to2}, src2, dst|dst, src2, src3{1to2}}
|
Note
|
Constraints: src1 = dst |
VPSHRDVQZ128mbk [HasVLX, HasVBMI2]
vpshrdvq {src3{1to2}, src2, dst {mask}|dst {mask}, src2, src3{1to2}}
|
Note
|
Constraints: src1 = dst |
VPSHRDVQZ128mbkz [HasVLX, HasVBMI2]
vpshrdvq {src3{1to2}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to2}}
|
Note
|
Constraints: src1 = dst |
VPSHRDVQZ128mk [HasVLX, HasVBMI2]
vpshrdvq {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHRDVQZ128mkz [HasVLX, HasVBMI2]
vpshrdvq {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHRDVQZ128r [HasVLX, HasVBMI2]
vpshrdvq {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHRDVQZ128rk [HasVLX, HasVBMI2]
vpshrdvq {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHRDVQZ128rkz [HasVLX, HasVBMI2]
vpshrdvq {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHRDVQZ256m [HasVLX, HasVBMI2]
vpshrdvq {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHRDVQZ256mb [HasVLX, HasVBMI2]
vpshrdvq {src3{1to4}, src2, dst|dst, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPSHRDVQZ256mbk [HasVLX, HasVBMI2]
vpshrdvq {src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPSHRDVQZ256mbkz [HasVLX, HasVBMI2]
vpshrdvq {src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPSHRDVQZ256mk [HasVLX, HasVBMI2]
vpshrdvq {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHRDVQZ256mkz [HasVLX, HasVBMI2]
vpshrdvq {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHRDVQZ256r [HasVLX, HasVBMI2]
vpshrdvq {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHRDVQZ256rk [HasVLX, HasVBMI2]
vpshrdvq {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHRDVQZ256rkz [HasVLX, HasVBMI2]
vpshrdvq {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHRDVWZ128m [HasVLX, HasVBMI2]
vpshrdvw {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHRDVWZ128mk [HasVLX, HasVBMI2]
vpshrdvw {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHRDVWZ128mkz [HasVLX, HasVBMI2]
vpshrdvw {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHRDVWZ128r [HasVLX, HasVBMI2]
vpshrdvw {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHRDVWZ128rk [HasVLX, HasVBMI2]
vpshrdvw {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHRDVWZ128rkz [HasVLX, HasVBMI2]
vpshrdvw {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHRDVWZ256m [HasVLX, HasVBMI2]
vpshrdvw {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHRDVWZ256mk [HasVLX, HasVBMI2]
vpshrdvw {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHRDVWZ256mkz [HasVLX, HasVBMI2]
vpshrdvw {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHRDVWZ256r [HasVLX, HasVBMI2]
vpshrdvw {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHRDVWZ256rk [HasVLX, HasVBMI2]
vpshrdvw {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHRDVWZ256rkz [HasVLX, HasVBMI2]
vpshrdvw {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHRDWZ128rmi [HasVLX, HasVBMI2]
vpshrdw {src3, src2, src1, dst|dst, src1, src2, src3}
VPSHRDWZ128rmik [HasVLX, HasVBMI2]
vpshrdw {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VPSHRDWZ128rmikz [HasVLX, HasVBMI2]
vpshrdw {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VPSHRDWZ128rri [HasVLX, HasVBMI2]
vpshrdw {src3, src2, src1, dst|dst, src1, src2, src3}
VPSHRDWZ128rrik [HasVLX, HasVBMI2]
vpshrdw {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VPSHRDWZ128rrikz [HasVLX, HasVBMI2]
vpshrdw {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VPSHRDWZ256rmi [HasVLX, HasVBMI2]
vpshrdw {src3, src2, src1, dst|dst, src1, src2, src3}
VPSHRDWZ256rmik [HasVLX, HasVBMI2]
vpshrdw {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VPSHRDWZ256rmikz [HasVLX, HasVBMI2]
vpshrdw {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VPSHRDWZ256rri [HasVLX, HasVBMI2]
vpshrdw {src3, src2, src1, dst|dst, src1, src2, src3}
VPSHRDWZ256rrik [HasVLX, HasVBMI2]
vpshrdw {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VPSHRDWZ256rrikz [HasVLX, HasVBMI2]
vpshrdw {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VPBROADCASTMB2QZ128rr [HasVLX, HasCDI]
vpbroadcastmb2q {src, dst|dst, src}
VPBROADCASTMB2QZ256rr [HasVLX, HasCDI]
vpbroadcastmb2q {src, dst|dst, src}
VPBROADCASTMW2DZ128rr [HasVLX, HasCDI]
vpbroadcastmw2d {src, dst|dst, src}
VPBROADCASTMW2DZ256rr [HasVLX, HasCDI]
vpbroadcastmw2d {src, dst|dst, src}
VPCONFLICTDZ128rm [HasVLX, HasCDI]
vpconflictd {src1, dst|dst, src1}
VPCONFLICTDZ128rmb [HasVLX, HasCDI]
vpconflictd {src1{1to4}, dst|dst, src1{1to4}}
VPCONFLICTDZ128rmbk [HasVLX, HasCDI]
vpconflictd {src1{1to4}, dst {mask}|dst {mask}, src1{1to4}}
|
Note
|
Constraints: src0 = dst |
VPCONFLICTDZ128rmbkz [HasVLX, HasCDI]
vpconflictd {src1{1to4}, dst {mask} {z}|dst {mask} {z}, src1{1to4}}
VPCONFLICTDZ128rmk [HasVLX, HasCDI]
vpconflictd {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPCONFLICTDZ128rmkz [HasVLX, HasCDI]
vpconflictd {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPCONFLICTDZ128rr [HasVLX, HasCDI]
vpconflictd {src1, dst|dst, src1}
VPCONFLICTDZ128rrk [HasVLX, HasCDI]
vpconflictd {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPCONFLICTDZ128rrkz [HasVLX, HasCDI]
vpconflictd {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPCONFLICTDZ256rm [HasVLX, HasCDI]
vpconflictd {src1, dst|dst, src1}
VPCONFLICTDZ256rmb [HasVLX, HasCDI]
vpconflictd {src1{1to8}, dst|dst, src1{1to8}}
VPCONFLICTDZ256rmbk [HasVLX, HasCDI]
vpconflictd {src1{1to8}, dst {mask}|dst {mask}, src1{1to8}}
|
Note
|
Constraints: src0 = dst |
VPCONFLICTDZ256rmbkz [HasVLX, HasCDI]
vpconflictd {src1{1to8}, dst {mask} {z}|dst {mask} {z}, src1{1to8}}
VPCONFLICTDZ256rmk [HasVLX, HasCDI]
vpconflictd {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPCONFLICTDZ256rmkz [HasVLX, HasCDI]
vpconflictd {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPCONFLICTDZ256rr [HasVLX, HasCDI]
vpconflictd {src1, dst|dst, src1}
VPCONFLICTDZ256rrk [HasVLX, HasCDI]
vpconflictd {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPCONFLICTDZ256rrkz [HasVLX, HasCDI]
vpconflictd {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPCONFLICTQZ128rm [HasVLX, HasCDI]
vpconflictq {src1, dst|dst, src1}
VPCONFLICTQZ128rmb [HasVLX, HasCDI]
vpconflictq {src1{1to2}, dst|dst, src1{1to2}}
VPCONFLICTQZ128rmbk [HasVLX, HasCDI]
vpconflictq {src1{1to2}, dst {mask}|dst {mask}, src1{1to2}}
|
Note
|
Constraints: src0 = dst |
VPCONFLICTQZ128rmbkz [HasVLX, HasCDI]
vpconflictq {src1{1to2}, dst {mask} {z}|dst {mask} {z}, src1{1to2}}
VPCONFLICTQZ128rmk [HasVLX, HasCDI]
vpconflictq {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPCONFLICTQZ128rmkz [HasVLX, HasCDI]
vpconflictq {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPCONFLICTQZ128rr [HasVLX, HasCDI]
vpconflictq {src1, dst|dst, src1}
VPCONFLICTQZ128rrk [HasVLX, HasCDI]
vpconflictq {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPCONFLICTQZ128rrkz [HasVLX, HasCDI]
vpconflictq {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPCONFLICTQZ256rm [HasVLX, HasCDI]
vpconflictq {src1, dst|dst, src1}
VPCONFLICTQZ256rmb [HasVLX, HasCDI]
vpconflictq {src1{1to4}, dst|dst, src1{1to4}}
VPCONFLICTQZ256rmbk [HasVLX, HasCDI]
vpconflictq {src1{1to4}, dst {mask}|dst {mask}, src1{1to4}}
|
Note
|
Constraints: src0 = dst |
VPCONFLICTQZ256rmbkz [HasVLX, HasCDI]
vpconflictq {src1{1to4}, dst {mask} {z}|dst {mask} {z}, src1{1to4}}
VPCONFLICTQZ256rmk [HasVLX, HasCDI]
vpconflictq {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPCONFLICTQZ256rmkz [HasVLX, HasCDI]
vpconflictq {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPCONFLICTQZ256rr [HasVLX, HasCDI]
vpconflictq {src1, dst|dst, src1}
VPCONFLICTQZ256rrk [HasVLX, HasCDI]
vpconflictq {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPCONFLICTQZ256rrkz [HasVLX, HasCDI]
vpconflictq {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPLZCNTDZ128rm [HasVLX, HasCDI]
vplzcntd {src1, dst|dst, src1}
VPLZCNTDZ128rmb [HasVLX, HasCDI]
vplzcntd {src1{1to4}, dst|dst, src1{1to4}}
VPLZCNTDZ128rmbk [HasVLX, HasCDI]
vplzcntd {src1{1to4}, dst {mask}|dst {mask}, src1{1to4}}
|
Note
|
Constraints: src0 = dst |
VPLZCNTDZ128rmbkz [HasVLX, HasCDI]
vplzcntd {src1{1to4}, dst {mask} {z}|dst {mask} {z}, src1{1to4}}
VPLZCNTDZ128rmk [HasVLX, HasCDI]
vplzcntd {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPLZCNTDZ128rmkz [HasVLX, HasCDI]
vplzcntd {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPLZCNTDZ128rr [HasVLX, HasCDI]
vplzcntd {src1, dst|dst, src1}
VPLZCNTDZ128rrk [HasVLX, HasCDI]
vplzcntd {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPLZCNTDZ128rrkz [HasVLX, HasCDI]
vplzcntd {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPLZCNTDZ256rm [HasVLX, HasCDI]
vplzcntd {src1, dst|dst, src1}
VPLZCNTDZ256rmb [HasVLX, HasCDI]
vplzcntd {src1{1to8}, dst|dst, src1{1to8}}
VPLZCNTDZ256rmbk [HasVLX, HasCDI]
vplzcntd {src1{1to8}, dst {mask}|dst {mask}, src1{1to8}}
|
Note
|
Constraints: src0 = dst |
VPLZCNTDZ256rmbkz [HasVLX, HasCDI]
vplzcntd {src1{1to8}, dst {mask} {z}|dst {mask} {z}, src1{1to8}}
VPLZCNTDZ256rmk [HasVLX, HasCDI]
vplzcntd {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPLZCNTDZ256rmkz [HasVLX, HasCDI]
vplzcntd {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPLZCNTDZ256rr [HasVLX, HasCDI]
vplzcntd {src1, dst|dst, src1}
VPLZCNTDZ256rrk [HasVLX, HasCDI]
vplzcntd {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPLZCNTDZ256rrkz [HasVLX, HasCDI]
vplzcntd {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPLZCNTQZ128rm [HasVLX, HasCDI]
vplzcntq {src1, dst|dst, src1}
VPLZCNTQZ128rmb [HasVLX, HasCDI]
vplzcntq {src1{1to2}, dst|dst, src1{1to2}}
VPLZCNTQZ128rmbk [HasVLX, HasCDI]
vplzcntq {src1{1to2}, dst {mask}|dst {mask}, src1{1to2}}
|
Note
|
Constraints: src0 = dst |
VPLZCNTQZ128rmbkz [HasVLX, HasCDI]
vplzcntq {src1{1to2}, dst {mask} {z}|dst {mask} {z}, src1{1to2}}
VPLZCNTQZ128rmk [HasVLX, HasCDI]
vplzcntq {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPLZCNTQZ128rmkz [HasVLX, HasCDI]
vplzcntq {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPLZCNTQZ128rr [HasVLX, HasCDI]
vplzcntq {src1, dst|dst, src1}
VPLZCNTQZ128rrk [HasVLX, HasCDI]
vplzcntq {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPLZCNTQZ128rrkz [HasVLX, HasCDI]
vplzcntq {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPLZCNTQZ256rm [HasVLX, HasCDI]
vplzcntq {src1, dst|dst, src1}
VPLZCNTQZ256rmb [HasVLX, HasCDI]
vplzcntq {src1{1to4}, dst|dst, src1{1to4}}
VPLZCNTQZ256rmbk [HasVLX, HasCDI]
vplzcntq {src1{1to4}, dst {mask}|dst {mask}, src1{1to4}}
|
Note
|
Constraints: src0 = dst |
VPLZCNTQZ256rmbkz [HasVLX, HasCDI]
vplzcntq {src1{1to4}, dst {mask} {z}|dst {mask} {z}, src1{1to4}}
VPLZCNTQZ256rmk [HasVLX, HasCDI]
vplzcntq {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPLZCNTQZ256rmkz [HasVLX, HasCDI]
vplzcntq {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPLZCNTQZ256rr [HasVLX, HasCDI]
vplzcntq {src1, dst|dst, src1}
VPLZCNTQZ256rrk [HasVLX, HasCDI]
vplzcntq {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPLZCNTQZ256rrkz [HasVLX, HasCDI]
vplzcntq {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPDPBUSDSZ128m [HasVLX, HasVNNI]
vpdpbusds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUSDSZ128mb [HasVLX, HasVNNI]
vpdpbusds {src3{1to4}, src2, dst|dst, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPDPBUSDSZ128mbk [HasVLX, HasVNNI]
vpdpbusds {src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPDPBUSDSZ128mbkz [HasVLX, HasVNNI]
vpdpbusds {src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPDPBUSDSZ128mk [HasVLX, HasVNNI]
vpdpbusds {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUSDSZ128mkz [HasVLX, HasVNNI]
vpdpbusds {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUSDSZ128r [HasVLX, HasVNNI]
vpdpbusds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUSDSZ128rk [HasVLX, HasVNNI]
vpdpbusds {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUSDSZ128rkz [HasVLX, HasVNNI]
vpdpbusds {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUSDSZ256m [HasVLX, HasVNNI]
vpdpbusds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUSDSZ256mb [HasVLX, HasVNNI]
vpdpbusds {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPDPBUSDSZ256mbk [HasVLX, HasVNNI]
vpdpbusds {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPDPBUSDSZ256mbkz [HasVLX, HasVNNI]
vpdpbusds {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPDPBUSDSZ256mk [HasVLX, HasVNNI]
vpdpbusds {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUSDSZ256mkz [HasVLX, HasVNNI]
vpdpbusds {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUSDSZ256r [HasVLX, HasVNNI]
vpdpbusds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUSDSZ256rk [HasVLX, HasVNNI]
vpdpbusds {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUSDSZ256rkz [HasVLX, HasVNNI]
vpdpbusds {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUSDZ128m [HasVLX, HasVNNI]
vpdpbusd {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUSDZ128mb [HasVLX, HasVNNI]
vpdpbusd {src3{1to4}, src2, dst|dst, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPDPBUSDZ128mbk [HasVLX, HasVNNI]
vpdpbusd {src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPDPBUSDZ128mbkz [HasVLX, HasVNNI]
vpdpbusd {src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPDPBUSDZ128mk [HasVLX, HasVNNI]
vpdpbusd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUSDZ128mkz [HasVLX, HasVNNI]
vpdpbusd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUSDZ128r [HasVLX, HasVNNI]
vpdpbusd {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUSDZ128rk [HasVLX, HasVNNI]
vpdpbusd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUSDZ128rkz [HasVLX, HasVNNI]
vpdpbusd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUSDZ256m [HasVLX, HasVNNI]
vpdpbusd {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUSDZ256mb [HasVLX, HasVNNI]
vpdpbusd {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPDPBUSDZ256mbk [HasVLX, HasVNNI]
vpdpbusd {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPDPBUSDZ256mbkz [HasVLX, HasVNNI]
vpdpbusd {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPDPBUSDZ256mk [HasVLX, HasVNNI]
vpdpbusd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUSDZ256mkz [HasVLX, HasVNNI]
vpdpbusd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUSDZ256r [HasVLX, HasVNNI]
vpdpbusd {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUSDZ256rk [HasVLX, HasVNNI]
vpdpbusd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUSDZ256rkz [HasVLX, HasVNNI]
vpdpbusd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSSDSZ128m [HasVLX, HasVNNI]
vpdpwssds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSSDSZ128mb [HasVLX, HasVNNI]
vpdpwssds {src3{1to4}, src2, dst|dst, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPDPWSSDSZ128mbk [HasVLX, HasVNNI]
vpdpwssds {src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPDPWSSDSZ128mbkz [HasVLX, HasVNNI]
vpdpwssds {src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPDPWSSDSZ128mk [HasVLX, HasVNNI]
vpdpwssds {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSSDSZ128mkz [HasVLX, HasVNNI]
vpdpwssds {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSSDSZ128r [HasVLX, HasVNNI]
vpdpwssds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSSDSZ128rk [HasVLX, HasVNNI]
vpdpwssds {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSSDSZ128rkz [HasVLX, HasVNNI]
vpdpwssds {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSSDSZ256m [HasVLX, HasVNNI]
vpdpwssds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSSDSZ256mb [HasVLX, HasVNNI]
vpdpwssds {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPDPWSSDSZ256mbk [HasVLX, HasVNNI]
vpdpwssds {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPDPWSSDSZ256mbkz [HasVLX, HasVNNI]
vpdpwssds {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPDPWSSDSZ256mk [HasVLX, HasVNNI]
vpdpwssds {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSSDSZ256mkz [HasVLX, HasVNNI]
vpdpwssds {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSSDSZ256r [HasVLX, HasVNNI]
vpdpwssds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSSDSZ256rk [HasVLX, HasVNNI]
vpdpwssds {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSSDSZ256rkz [HasVLX, HasVNNI]
vpdpwssds {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSSDZ128m [HasVLX, HasVNNI]
vpdpwssd {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSSDZ128mb [HasVLX, HasVNNI]
vpdpwssd {src3{1to4}, src2, dst|dst, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPDPWSSDZ128mbk [HasVLX, HasVNNI]
vpdpwssd {src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPDPWSSDZ128mbkz [HasVLX, HasVNNI]
vpdpwssd {src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPDPWSSDZ128mk [HasVLX, HasVNNI]
vpdpwssd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSSDZ128mkz [HasVLX, HasVNNI]
vpdpwssd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSSDZ128r [HasVLX, HasVNNI]
vpdpwssd {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSSDZ128rk [HasVLX, HasVNNI]
vpdpwssd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSSDZ128rkz [HasVLX, HasVNNI]
vpdpwssd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSSDZ256m [HasVLX, HasVNNI]
vpdpwssd {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSSDZ256mb [HasVLX, HasVNNI]
vpdpwssd {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPDPWSSDZ256mbk [HasVLX, HasVNNI]
vpdpwssd {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPDPWSSDZ256mbkz [HasVLX, HasVNNI]
vpdpwssd {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPDPWSSDZ256mk [HasVLX, HasVNNI]
vpdpwssd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSSDZ256mkz [HasVLX, HasVNNI]
vpdpwssd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSSDZ256r [HasVLX, HasVNNI]
vpdpwssd {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSSDZ256rk [HasVLX, HasVNNI]
vpdpwssd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSSDZ256rkz [HasVLX, HasVNNI]
vpdpwssd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VGF2P8AFFINEINVQBZ128rmbi [HasVLX, HasGFNI]
vgf2p8affineinvqb {src3, src2{1to2}, src1, dst|dst, src1, src2{1to2}, src3}
VGF2P8AFFINEINVQBZ128rmbik [HasVLX, HasGFNI]
vgf2p8affineinvqb {src3, src2{1to2}, src1, dst {mask}|dst {mask}, src1, src2{1to2}, src3}
|
Note
|
Constraints: src0 = dst |
VGF2P8AFFINEINVQBZ128rmbikz [HasVLX, HasGFNI]
vgf2p8affineinvqb {src3, src2{1to2}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to2}, src3}
VGF2P8AFFINEINVQBZ128rmi [HasVLX, HasGFNI]
vgf2p8affineinvqb {src3, src2, src1, dst|dst, src1, src2, src3}
VGF2P8AFFINEINVQBZ128rmik [HasVLX, HasGFNI]
vgf2p8affineinvqb {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VGF2P8AFFINEINVQBZ128rmikz [HasVLX, HasGFNI]
vgf2p8affineinvqb {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VGF2P8AFFINEINVQBZ128rri [HasVLX, HasGFNI]
vgf2p8affineinvqb {src3, src2, src1, dst|dst, src1, src2, src3}
VGF2P8AFFINEINVQBZ128rrik [HasVLX, HasGFNI]
vgf2p8affineinvqb {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VGF2P8AFFINEINVQBZ128rrikz [HasVLX, HasGFNI]
vgf2p8affineinvqb {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VGF2P8AFFINEINVQBZ256rmbi [HasVLX, HasGFNI]
vgf2p8affineinvqb {src3, src2{1to4}, src1, dst|dst, src1, src2{1to4}, src3}
VGF2P8AFFINEINVQBZ256rmbik [HasVLX, HasGFNI]
vgf2p8affineinvqb {src3, src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}, src3}
|
Note
|
Constraints: src0 = dst |
VGF2P8AFFINEINVQBZ256rmbikz [HasVLX, HasGFNI]
vgf2p8affineinvqb {src3, src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}, src3}
VGF2P8AFFINEINVQBZ256rmi [HasVLX, HasGFNI]
vgf2p8affineinvqb {src3, src2, src1, dst|dst, src1, src2, src3}
VGF2P8AFFINEINVQBZ256rmik [HasVLX, HasGFNI]
vgf2p8affineinvqb {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VGF2P8AFFINEINVQBZ256rmikz [HasVLX, HasGFNI]
vgf2p8affineinvqb {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VGF2P8AFFINEINVQBZ256rri [HasVLX, HasGFNI]
vgf2p8affineinvqb {src3, src2, src1, dst|dst, src1, src2, src3}
VGF2P8AFFINEINVQBZ256rrik [HasVLX, HasGFNI]
vgf2p8affineinvqb {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VGF2P8AFFINEINVQBZ256rrikz [HasVLX, HasGFNI]
vgf2p8affineinvqb {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VGF2P8AFFINEQBZ128rmbi [HasVLX, HasGFNI]
vgf2p8affineqb {src3, src2{1to2}, src1, dst|dst, src1, src2{1to2}, src3}
VGF2P8AFFINEQBZ128rmbik [HasVLX, HasGFNI]
vgf2p8affineqb {src3, src2{1to2}, src1, dst {mask}|dst {mask}, src1, src2{1to2}, src3}
|
Note
|
Constraints: src0 = dst |
VGF2P8AFFINEQBZ128rmbikz [HasVLX, HasGFNI]
vgf2p8affineqb {src3, src2{1to2}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to2}, src3}
VGF2P8AFFINEQBZ128rmi [HasVLX, HasGFNI]
vgf2p8affineqb {src3, src2, src1, dst|dst, src1, src2, src3}
VGF2P8AFFINEQBZ128rmik [HasVLX, HasGFNI]
vgf2p8affineqb {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VGF2P8AFFINEQBZ128rmikz [HasVLX, HasGFNI]
vgf2p8affineqb {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VGF2P8AFFINEQBZ128rri [HasVLX, HasGFNI]
vgf2p8affineqb {src3, src2, src1, dst|dst, src1, src2, src3}
VGF2P8AFFINEQBZ128rrik [HasVLX, HasGFNI]
vgf2p8affineqb {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VGF2P8AFFINEQBZ128rrikz [HasVLX, HasGFNI]
vgf2p8affineqb {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VGF2P8AFFINEQBZ256rmbi [HasVLX, HasGFNI]
vgf2p8affineqb {src3, src2{1to4}, src1, dst|dst, src1, src2{1to4}, src3}
VGF2P8AFFINEQBZ256rmbik [HasVLX, HasGFNI]
vgf2p8affineqb {src3, src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}, src3}
|
Note
|
Constraints: src0 = dst |
VGF2P8AFFINEQBZ256rmbikz [HasVLX, HasGFNI]
vgf2p8affineqb {src3, src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}, src3}
VGF2P8AFFINEQBZ256rmi [HasVLX, HasGFNI]
vgf2p8affineqb {src3, src2, src1, dst|dst, src1, src2, src3}
VGF2P8AFFINEQBZ256rmik [HasVLX, HasGFNI]
vgf2p8affineqb {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VGF2P8AFFINEQBZ256rmikz [HasVLX, HasGFNI]
vgf2p8affineqb {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VGF2P8AFFINEQBZ256rri [HasVLX, HasGFNI]
vgf2p8affineqb {src3, src2, src1, dst|dst, src1, src2, src3}
VGF2P8AFFINEQBZ256rrik [HasVLX, HasGFNI]
vgf2p8affineqb {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VGF2P8AFFINEQBZ256rrikz [HasVLX, HasGFNI]
vgf2p8affineqb {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VGF2P8MULBZ128rm [HasVLX, HasGFNI]
vgf2p8mulb {src2, src1, dst|dst, src1, src2}
VGF2P8MULBZ128rmk [HasVLX, HasGFNI]
vgf2p8mulb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VGF2P8MULBZ128rmkz [HasVLX, HasGFNI]
vgf2p8mulb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VGF2P8MULBZ128rr [HasVLX, HasGFNI]
vgf2p8mulb {src2, src1, dst|dst, src1, src2}
VGF2P8MULBZ128rrk [HasVLX, HasGFNI]
vgf2p8mulb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VGF2P8MULBZ128rrkz [HasVLX, HasGFNI]
vgf2p8mulb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VGF2P8MULBZ256rm [HasVLX, HasGFNI]
vgf2p8mulb {src2, src1, dst|dst, src1, src2}
VGF2P8MULBZ256rmk [HasVLX, HasGFNI]
vgf2p8mulb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VGF2P8MULBZ256rmkz [HasVLX, HasGFNI]
vgf2p8mulb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VGF2P8MULBZ256rr [HasVLX, HasGFNI]
vgf2p8mulb {src2, src1, dst|dst, src1, src2}
VGF2P8MULBZ256rrk [HasVLX, HasGFNI]
vgf2p8mulb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VGF2P8MULBZ256rrkz [HasVLX, HasGFNI]
vgf2p8mulb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VCVTNE2PS2BF16Z128rm [HasVLX, HasBF16]
vcvtne2ps2bf16 {src2, src1, dst|dst, src1, src2}
VCVTNE2PS2BF16Z128rmb [HasVLX, HasBF16]
vcvtne2ps2bf16 {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
VCVTNE2PS2BF16Z128rmbk [HasVLX, HasBF16]
vcvtne2ps2bf16 {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Constraints: src0 = dst |
VCVTNE2PS2BF16Z128rmbkz [HasVLX, HasBF16]
vcvtne2ps2bf16 {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
VCVTNE2PS2BF16Z128rmk [HasVLX, HasBF16]
vcvtne2ps2bf16 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VCVTNE2PS2BF16Z128rmkz [HasVLX, HasBF16]
vcvtne2ps2bf16 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VCVTNE2PS2BF16Z128rr [HasVLX, HasBF16]
vcvtne2ps2bf16 {src2, src1, dst|dst, src1, src2}
VCVTNE2PS2BF16Z128rrk [HasVLX, HasBF16]
vcvtne2ps2bf16 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VCVTNE2PS2BF16Z128rrkz [HasVLX, HasBF16]
vcvtne2ps2bf16 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VCVTNE2PS2BF16Z256rm [HasVLX, HasBF16]
vcvtne2ps2bf16 {src2, src1, dst|dst, src1, src2}
VCVTNE2PS2BF16Z256rmb [HasVLX, HasBF16]
vcvtne2ps2bf16 {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
VCVTNE2PS2BF16Z256rmbk [HasVLX, HasBF16]
vcvtne2ps2bf16 {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Constraints: src0 = dst |
VCVTNE2PS2BF16Z256rmbkz [HasVLX, HasBF16]
vcvtne2ps2bf16 {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
VCVTNE2PS2BF16Z256rmk [HasVLX, HasBF16]
vcvtne2ps2bf16 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VCVTNE2PS2BF16Z256rmkz [HasVLX, HasBF16]
vcvtne2ps2bf16 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VCVTNE2PS2BF16Z256rr [HasVLX, HasBF16]
vcvtne2ps2bf16 {src2, src1, dst|dst, src1, src2}
VCVTNE2PS2BF16Z256rrk [HasVLX, HasBF16]
vcvtne2ps2bf16 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VCVTNE2PS2BF16Z256rrkz [HasVLX, HasBF16]
vcvtne2ps2bf16 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VCVTNEPS2BF16Z128rm [HasVLX, HasBF16]
vcvtneps2bf16{x} {src, dst|dst, src}
VCVTNEPS2BF16Z128rmb [HasVLX, HasBF16]
vcvtneps2bf16 {src{1to4}, dst|dst, src{1to4}}
VCVTNEPS2BF16Z128rmbk [HasVLX, HasBF16]
vcvtneps2bf16 {src{1to4}, dst {mask}|dst {mask}, src{1to4}}
|
Note
|
Constraints: src0 = dst |
VCVTNEPS2BF16Z128rmbkz [HasVLX, HasBF16]
vcvtneps2bf16 {src{1to4}, dst {mask} {z}|dst {mask} {z}, src{1to4}}
VCVTNEPS2BF16Z128rmk [HasVLX, HasBF16]
vcvtneps2bf16{x} {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTNEPS2BF16Z128rmkz [HasVLX, HasBF16]
vcvtneps2bf16{x} {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTNEPS2BF16Z128rr [HasVLX, HasBF16]
vcvtneps2bf16 {src, dst|dst, src}
VCVTNEPS2BF16Z128rrk [HasVLX, HasBF16]
vcvtneps2bf16 {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTNEPS2BF16Z128rrkz [HasVLX, HasBF16]
vcvtneps2bf16 {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTNEPS2BF16Z256rm [HasVLX, HasBF16]
vcvtneps2bf16{y} {src, dst|dst, src}
VCVTNEPS2BF16Z256rmb [HasVLX, HasBF16]
vcvtneps2bf16 {src{1to8}, dst|dst, src{1to8}}
VCVTNEPS2BF16Z256rmbk [HasVLX, HasBF16]
vcvtneps2bf16 {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Constraints: src0 = dst |
VCVTNEPS2BF16Z256rmbkz [HasVLX, HasBF16]
vcvtneps2bf16 {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
VCVTNEPS2BF16Z256rmk [HasVLX, HasBF16]
vcvtneps2bf16{y} {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTNEPS2BF16Z256rmkz [HasVLX, HasBF16]
vcvtneps2bf16{y} {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTNEPS2BF16Z256rr [HasVLX, HasBF16]
vcvtneps2bf16 {src, dst|dst, src}
VCVTNEPS2BF16Z256rrk [HasVLX, HasBF16]
vcvtneps2bf16 {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTNEPS2BF16Z256rrkz [HasVLX, HasBF16]
vcvtneps2bf16 {src, dst {mask} {z}|dst {mask} {z}, src}
VDPBF16PSZ128m [HasVLX, HasBF16]
vdpbf16ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VDPBF16PSZ128mb [HasVLX, HasBF16]
vdpbf16ps {src3{1to4}, src2, dst|dst, src2, src3{1to4}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VDPBF16PSZ128mbk [HasVLX, HasBF16]
vdpbf16ps {src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VDPBF16PSZ128mbkz [HasVLX, HasBF16]
vdpbf16ps {src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VDPBF16PSZ128mk [HasVLX, HasBF16]
vdpbf16ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VDPBF16PSZ128mkz [HasVLX, HasBF16]
vdpbf16ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VDPBF16PSZ128r [HasVLX, HasBF16]
vdpbf16ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VDPBF16PSZ128rk [HasVLX, HasBF16]
vdpbf16ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VDPBF16PSZ128rkz [HasVLX, HasBF16]
vdpbf16ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VDPBF16PSZ256m [HasVLX, HasBF16]
vdpbf16ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VDPBF16PSZ256mb [HasVLX, HasBF16]
vdpbf16ps {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VDPBF16PSZ256mbk [HasVLX, HasBF16]
vdpbf16ps {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VDPBF16PSZ256mbkz [HasVLX, HasBF16]
vdpbf16ps {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VDPBF16PSZ256mk [HasVLX, HasBF16]
vdpbf16ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VDPBF16PSZ256mkz [HasVLX, HasBF16]
vdpbf16ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VDPBF16PSZ256r [HasVLX, HasBF16]
vdpbf16ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VDPBF16PSZ256rk [HasVLX, HasBF16]
vdpbf16ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VDPBF16PSZ256rkz [HasVLX, HasBF16]
vdpbf16ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMBZ128rm [HasVLX, HasVBMI]
vpermb {src2, src1, dst|dst, src1, src2}
VPERMBZ128rmk [HasVLX, HasVBMI]
vpermb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPERMBZ128rmkz [HasVLX, HasVBMI]
vpermb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPERMBZ128rr [HasVLX, HasVBMI]
vpermb {src2, src1, dst|dst, src1, src2}
VPERMBZ128rrk [HasVLX, HasVBMI]
vpermb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPERMBZ128rrkz [HasVLX, HasVBMI]
vpermb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPERMBZ256rm [HasVLX, HasVBMI]
vpermb {src2, src1, dst|dst, src1, src2}
VPERMBZ256rmk [HasVLX, HasVBMI]
vpermb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPERMBZ256rmkz [HasVLX, HasVBMI]
vpermb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPERMBZ256rr [HasVLX, HasVBMI]
vpermb {src2, src1, dst|dst, src1, src2}
VPERMBZ256rrk [HasVLX, HasVBMI]
vpermb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPERMBZ256rrkz [HasVLX, HasVBMI]
vpermb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPERMI2BZ128rm [HasVLX, HasVBMI]
vpermi2b {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2BZ128rmk [HasVLX, HasVBMI]
vpermi2b {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2BZ128rmkz [HasVLX, HasVBMI]
vpermi2b {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2BZ128rr [HasVLX, HasVBMI]
vpermi2b {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMI2BZ128rrk [HasVLX, HasVBMI]
vpermi2b {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMI2BZ128rrkz [HasVLX, HasVBMI]
vpermi2b {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMI2BZ256rm [HasVLX, HasVBMI]
vpermi2b {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2BZ256rmk [HasVLX, HasVBMI]
vpermi2b {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2BZ256rmkz [HasVLX, HasVBMI]
vpermi2b {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2BZ256rr [HasVLX, HasVBMI]
vpermi2b {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMI2BZ256rrk [HasVLX, HasVBMI]
vpermi2b {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMI2BZ256rrkz [HasVLX, HasVBMI]
vpermi2b {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2BZ128rm [HasVLX, HasVBMI]
vpermt2b {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2BZ128rmk [HasVLX, HasVBMI]
vpermt2b {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2BZ128rmkz [HasVLX, HasVBMI]
vpermt2b {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2BZ128rr [HasVLX, HasVBMI]
vpermt2b {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2BZ128rrk [HasVLX, HasVBMI]
vpermt2b {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2BZ128rrkz [HasVLX, HasVBMI]
vpermt2b {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2BZ256rm [HasVLX, HasVBMI]
vpermt2b {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2BZ256rmk [HasVLX, HasVBMI]
vpermt2b {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2BZ256rmkz [HasVLX, HasVBMI]
vpermt2b {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2BZ256rr [HasVLX, HasVBMI]
vpermt2b {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2BZ256rrk [HasVLX, HasVBMI]
vpermt2b {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2BZ256rrkz [HasVLX, HasVBMI]
vpermt2b {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPMULTISHIFTQBZ128rm [HasVLX, HasVBMI]
vpmultishiftqb {src2, src1, dst|dst, src1, src2}
VPMULTISHIFTQBZ128rmb [HasVLX, HasVBMI]
vpmultishiftqb {src2{1to2}, src1, dst|dst, src1, src2{1to2}}
VPMULTISHIFTQBZ128rmbk [HasVLX, HasVBMI]
vpmultishiftqb {src2{1to2}, src1, dst {mask}|dst {mask}, src1, src2{1to2}}
|
Note
|
Constraints: src0 = dst |
VPMULTISHIFTQBZ128rmbkz [HasVLX, HasVBMI]
vpmultishiftqb {src2{1to2}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to2}}
VPMULTISHIFTQBZ128rmk [HasVLX, HasVBMI]
vpmultishiftqb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMULTISHIFTQBZ128rmkz [HasVLX, HasVBMI]
vpmultishiftqb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMULTISHIFTQBZ128rr [HasVLX, HasVBMI]
vpmultishiftqb {src2, src1, dst|dst, src1, src2}
VPMULTISHIFTQBZ128rrk [HasVLX, HasVBMI]
vpmultishiftqb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMULTISHIFTQBZ128rrkz [HasVLX, HasVBMI]
vpmultishiftqb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMULTISHIFTQBZ256rm [HasVLX, HasVBMI]
vpmultishiftqb {src2, src1, dst|dst, src1, src2}
VPMULTISHIFTQBZ256rmb [HasVLX, HasVBMI]
vpmultishiftqb {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
VPMULTISHIFTQBZ256rmbk [HasVLX, HasVBMI]
vpmultishiftqb {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Constraints: src0 = dst |
VPMULTISHIFTQBZ256rmbkz [HasVLX, HasVBMI]
vpmultishiftqb {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
VPMULTISHIFTQBZ256rmk [HasVLX, HasVBMI]
vpmultishiftqb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMULTISHIFTQBZ256rmkz [HasVLX, HasVBMI]
vpmultishiftqb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMULTISHIFTQBZ256rr [HasVLX, HasVBMI]
vpmultishiftqb {src2, src1, dst|dst, src1, src2}
VPMULTISHIFTQBZ256rrk [HasVLX, HasVBMI]
vpmultishiftqb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMULTISHIFTQBZ256rrkz [HasVLX, HasVBMI]
vpmultishiftqb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMADD52HUQZ128m [HasVLX, HasIFMA]
vpmadd52huq {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPMADD52HUQZ128mb [HasVLX, HasIFMA]
vpmadd52huq {src3{1to2}, src2, dst|dst, src2, src3{1to2}}
|
Note
|
Constraints: src1 = dst |
VPMADD52HUQZ128mbk [HasVLX, HasIFMA]
vpmadd52huq {src3{1to2}, src2, dst {mask}|dst {mask}, src2, src3{1to2}}
|
Note
|
Constraints: src1 = dst |
VPMADD52HUQZ128mbkz [HasVLX, HasIFMA]
vpmadd52huq {src3{1to2}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to2}}
|
Note
|
Constraints: src1 = dst |
VPMADD52HUQZ128mk [HasVLX, HasIFMA]
vpmadd52huq {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPMADD52HUQZ128mkz [HasVLX, HasIFMA]
vpmadd52huq {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPMADD52HUQZ128r [HasVLX, HasIFMA]
vpmadd52huq {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPMADD52HUQZ128rk [HasVLX, HasIFMA]
vpmadd52huq {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPMADD52HUQZ128rkz [HasVLX, HasIFMA]
vpmadd52huq {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPMADD52HUQZ256m [HasVLX, HasIFMA]
vpmadd52huq {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPMADD52HUQZ256mb [HasVLX, HasIFMA]
vpmadd52huq {src3{1to4}, src2, dst|dst, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPMADD52HUQZ256mbk [HasVLX, HasIFMA]
vpmadd52huq {src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPMADD52HUQZ256mbkz [HasVLX, HasIFMA]
vpmadd52huq {src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPMADD52HUQZ256mk [HasVLX, HasIFMA]
vpmadd52huq {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPMADD52HUQZ256mkz [HasVLX, HasIFMA]
vpmadd52huq {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPMADD52HUQZ256r [HasVLX, HasIFMA]
vpmadd52huq {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPMADD52HUQZ256rk [HasVLX, HasIFMA]
vpmadd52huq {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPMADD52HUQZ256rkz [HasVLX, HasIFMA]
vpmadd52huq {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPMADD52LUQZ128m [HasVLX, HasIFMA]
vpmadd52luq {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPMADD52LUQZ128mb [HasVLX, HasIFMA]
vpmadd52luq {src3{1to2}, src2, dst|dst, src2, src3{1to2}}
|
Note
|
Constraints: src1 = dst |
VPMADD52LUQZ128mbk [HasVLX, HasIFMA]
vpmadd52luq {src3{1to2}, src2, dst {mask}|dst {mask}, src2, src3{1to2}}
|
Note
|
Constraints: src1 = dst |
VPMADD52LUQZ128mbkz [HasVLX, HasIFMA]
vpmadd52luq {src3{1to2}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to2}}
|
Note
|
Constraints: src1 = dst |
VPMADD52LUQZ128mk [HasVLX, HasIFMA]
vpmadd52luq {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPMADD52LUQZ128mkz [HasVLX, HasIFMA]
vpmadd52luq {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPMADD52LUQZ128r [HasVLX, HasIFMA]
vpmadd52luq {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPMADD52LUQZ128rk [HasVLX, HasIFMA]
vpmadd52luq {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPMADD52LUQZ128rkz [HasVLX, HasIFMA]
vpmadd52luq {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPMADD52LUQZ256m [HasVLX, HasIFMA]
vpmadd52luq {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPMADD52LUQZ256mb [HasVLX, HasIFMA]
vpmadd52luq {src3{1to4}, src2, dst|dst, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPMADD52LUQZ256mbk [HasVLX, HasIFMA]
vpmadd52luq {src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPMADD52LUQZ256mbkz [HasVLX, HasIFMA]
vpmadd52luq {src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPMADD52LUQZ256mk [HasVLX, HasIFMA]
vpmadd52luq {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPMADD52LUQZ256mkz [HasVLX, HasIFMA]
vpmadd52luq {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPMADD52LUQZ256r [HasVLX, HasIFMA]
vpmadd52luq {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPMADD52LUQZ256rk [HasVLX, HasIFMA]
vpmadd52luq {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPMADD52LUQZ256rkz [HasVLX, HasIFMA]
vpmadd52luq {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPOPCNTDZ128rm [HasVLX, HasVPOPCNTDQ]
vpopcntd {src1, dst|dst, src1}
VPOPCNTDZ128rmb [HasVLX, HasVPOPCNTDQ]
vpopcntd {src1{1to4}, dst|dst, src1{1to4}}
VPOPCNTDZ128rmbk [HasVLX, HasVPOPCNTDQ]
vpopcntd {src1{1to4}, dst {mask}|dst {mask}, src1{1to4}}
|
Note
|
Constraints: src0 = dst |
VPOPCNTDZ128rmbkz [HasVLX, HasVPOPCNTDQ]
vpopcntd {src1{1to4}, dst {mask} {z}|dst {mask} {z}, src1{1to4}}
VPOPCNTDZ128rmk [HasVLX, HasVPOPCNTDQ]
vpopcntd {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPOPCNTDZ128rmkz [HasVLX, HasVPOPCNTDQ]
vpopcntd {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPOPCNTDZ128rr [HasVLX, HasVPOPCNTDQ]
vpopcntd {src1, dst|dst, src1}
VPOPCNTDZ128rrk [HasVLX, HasVPOPCNTDQ]
vpopcntd {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPOPCNTDZ128rrkz [HasVLX, HasVPOPCNTDQ]
vpopcntd {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPOPCNTDZ256rm [HasVLX, HasVPOPCNTDQ]
vpopcntd {src1, dst|dst, src1}
VPOPCNTDZ256rmb [HasVLX, HasVPOPCNTDQ]
vpopcntd {src1{1to8}, dst|dst, src1{1to8}}
VPOPCNTDZ256rmbk [HasVLX, HasVPOPCNTDQ]
vpopcntd {src1{1to8}, dst {mask}|dst {mask}, src1{1to8}}
|
Note
|
Constraints: src0 = dst |
VPOPCNTDZ256rmbkz [HasVLX, HasVPOPCNTDQ]
vpopcntd {src1{1to8}, dst {mask} {z}|dst {mask} {z}, src1{1to8}}
VPOPCNTDZ256rmk [HasVLX, HasVPOPCNTDQ]
vpopcntd {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPOPCNTDZ256rmkz [HasVLX, HasVPOPCNTDQ]
vpopcntd {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPOPCNTDZ256rr [HasVLX, HasVPOPCNTDQ]
vpopcntd {src1, dst|dst, src1}
VPOPCNTDZ256rrk [HasVLX, HasVPOPCNTDQ]
vpopcntd {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPOPCNTDZ256rrkz [HasVLX, HasVPOPCNTDQ]
vpopcntd {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPOPCNTQZ128rm [HasVLX, HasVPOPCNTDQ]
vpopcntq {src1, dst|dst, src1}
VPOPCNTQZ128rmb [HasVLX, HasVPOPCNTDQ]
vpopcntq {src1{1to2}, dst|dst, src1{1to2}}
VPOPCNTQZ128rmbk [HasVLX, HasVPOPCNTDQ]
vpopcntq {src1{1to2}, dst {mask}|dst {mask}, src1{1to2}}
|
Note
|
Constraints: src0 = dst |
VPOPCNTQZ128rmbkz [HasVLX, HasVPOPCNTDQ]
vpopcntq {src1{1to2}, dst {mask} {z}|dst {mask} {z}, src1{1to2}}
VPOPCNTQZ128rmk [HasVLX, HasVPOPCNTDQ]
vpopcntq {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPOPCNTQZ128rmkz [HasVLX, HasVPOPCNTDQ]
vpopcntq {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPOPCNTQZ128rr [HasVLX, HasVPOPCNTDQ]
vpopcntq {src1, dst|dst, src1}
VPOPCNTQZ128rrk [HasVLX, HasVPOPCNTDQ]
vpopcntq {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPOPCNTQZ128rrkz [HasVLX, HasVPOPCNTDQ]
vpopcntq {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPOPCNTQZ256rm [HasVLX, HasVPOPCNTDQ]
vpopcntq {src1, dst|dst, src1}
VPOPCNTQZ256rmb [HasVLX, HasVPOPCNTDQ]
vpopcntq {src1{1to4}, dst|dst, src1{1to4}}
VPOPCNTQZ256rmbk [HasVLX, HasVPOPCNTDQ]
vpopcntq {src1{1to4}, dst {mask}|dst {mask}, src1{1to4}}
|
Note
|
Constraints: src0 = dst |
VPOPCNTQZ256rmbkz [HasVLX, HasVPOPCNTDQ]
vpopcntq {src1{1to4}, dst {mask} {z}|dst {mask} {z}, src1{1to4}}
VPOPCNTQZ256rmk [HasVLX, HasVPOPCNTDQ]
vpopcntq {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPOPCNTQZ256rmkz [HasVLX, HasVPOPCNTDQ]
vpopcntq {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPOPCNTQZ256rr [HasVLX, HasVPOPCNTDQ]
vpopcntq {src1, dst|dst, src1}
VPOPCNTQZ256rrk [HasVLX, HasVPOPCNTDQ]
vpopcntq {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPOPCNTQZ256rrkz [HasVLX, HasVPOPCNTDQ]
vpopcntq {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPOPCNTBZ128rm [HasVLX, HasBITALG]
vpopcntb {src1, dst|dst, src1}
VPOPCNTBZ128rmk [HasVLX, HasBITALG]
vpopcntb {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPOPCNTBZ128rmkz [HasVLX, HasBITALG]
vpopcntb {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPOPCNTBZ128rr [HasVLX, HasBITALG]
vpopcntb {src1, dst|dst, src1}
VPOPCNTBZ128rrk [HasVLX, HasBITALG]
vpopcntb {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPOPCNTBZ128rrkz [HasVLX, HasBITALG]
vpopcntb {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPOPCNTBZ256rm [HasVLX, HasBITALG]
vpopcntb {src1, dst|dst, src1}
VPOPCNTBZ256rmk [HasVLX, HasBITALG]
vpopcntb {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPOPCNTBZ256rmkz [HasVLX, HasBITALG]
vpopcntb {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPOPCNTBZ256rr [HasVLX, HasBITALG]
vpopcntb {src1, dst|dst, src1}
VPOPCNTBZ256rrk [HasVLX, HasBITALG]
vpopcntb {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPOPCNTBZ256rrkz [HasVLX, HasBITALG]
vpopcntb {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPOPCNTWZ128rm [HasVLX, HasBITALG]
vpopcntw {src1, dst|dst, src1}
VPOPCNTWZ128rmk [HasVLX, HasBITALG]
vpopcntw {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPOPCNTWZ128rmkz [HasVLX, HasBITALG]
vpopcntw {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPOPCNTWZ128rr [HasVLX, HasBITALG]
vpopcntw {src1, dst|dst, src1}
VPOPCNTWZ128rrk [HasVLX, HasBITALG]
vpopcntw {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPOPCNTWZ128rrkz [HasVLX, HasBITALG]
vpopcntw {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPOPCNTWZ256rm [HasVLX, HasBITALG]
vpopcntw {src1, dst|dst, src1}
VPOPCNTWZ256rmk [HasVLX, HasBITALG]
vpopcntw {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPOPCNTWZ256rmkz [HasVLX, HasBITALG]
vpopcntw {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPOPCNTWZ256rr [HasVLX, HasBITALG]
vpopcntw {src1, dst|dst, src1}
VPOPCNTWZ256rrk [HasVLX, HasBITALG]
vpopcntw {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPOPCNTWZ256rrkz [HasVLX, HasBITALG]
vpopcntw {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPSHUFBITQMBZ128rm [HasVLX, HasBITALG]
vpshufbitqmb {src2, src1, dst|dst, src1, src2}
VPSHUFBITQMBZ128rmk [HasVLX, HasBITALG]
vpshufbitqmb {src2, src1, dst {mask}|dst {mask}, src1, src2}
VPSHUFBITQMBZ128rr [HasVLX, HasBITALG]
vpshufbitqmb {src2, src1, dst|dst, src1, src2}
VPSHUFBITQMBZ128rrk [HasVLX, HasBITALG]
vpshufbitqmb {src2, src1, dst {mask}|dst {mask}, src1, src2}
VPSHUFBITQMBZ256rm [HasVLX, HasBITALG]
vpshufbitqmb {src2, src1, dst|dst, src1, src2}
VPSHUFBITQMBZ256rmk [HasVLX, HasBITALG]
vpshufbitqmb {src2, src1, dst {mask}|dst {mask}, src1, src2}
VPSHUFBITQMBZ256rr [HasVLX, HasBITALG]
vpshufbitqmb {src2, src1, dst|dst, src1, src2}
VPSHUFBITQMBZ256rrk [HasVLX, HasBITALG]
vpshufbitqmb {src2, src1, dst {mask}|dst {mask}, src1, src2}
VAESDECLASTZ128rm [HasVLX, HasVAES]
vaesdeclast {src2, src1, dst|dst, src1, src2}
VAESDECLASTZ128rr [HasVLX, HasVAES]
vaesdeclast {src2, src1, dst|dst, src1, src2}
VAESDECLASTZ256rm [HasVLX, HasVAES]
vaesdeclast {src2, src1, dst|dst, src1, src2}
VAESDECLASTZ256rr [HasVLX, HasVAES]
vaesdeclast {src2, src1, dst|dst, src1, src2}
VAESDECZ128rm [HasVLX, HasVAES]
vaesdec {src2, src1, dst|dst, src1, src2}
VAESDECZ128rr [HasVLX, HasVAES]
vaesdec {src2, src1, dst|dst, src1, src2}
VAESDECZ256rm [HasVLX, HasVAES]
vaesdec {src2, src1, dst|dst, src1, src2}
VAESDECZ256rr [HasVLX, HasVAES]
vaesdec {src2, src1, dst|dst, src1, src2}
VAESENCLASTZ128rm [HasVLX, HasVAES]
vaesenclast {src2, src1, dst|dst, src1, src2}
VAESENCLASTZ128rr [HasVLX, HasVAES]
vaesenclast {src2, src1, dst|dst, src1, src2}
VAESENCLASTZ256rm [HasVLX, HasVAES]
vaesenclast {src2, src1, dst|dst, src1, src2}
VAESENCLASTZ256rr [HasVLX, HasVAES]
vaesenclast {src2, src1, dst|dst, src1, src2}
VAESENCZ128rm [HasVLX, HasVAES]
vaesenc {src2, src1, dst|dst, src1, src2}
VAESENCZ128rr [HasVLX, HasVAES]
vaesenc {src2, src1, dst|dst, src1, src2}
VAESENCZ256rm [HasVLX, HasVAES]
vaesenc {src2, src1, dst|dst, src1, src2}
VAESENCZ256rr [HasVLX, HasVAES]
vaesenc {src2, src1, dst|dst, src1, src2}
VPCLMULQDQZ128rmi [HasVLX, HasVPCLMULQDQ]
vpclmulqdq {src3, src2, src1, dst|dst, src1, src2, src3}
VPCLMULQDQZ128rri [HasVLX, HasVPCLMULQDQ]
vpclmulqdq {src3, src2, src1, dst|dst, src1, src2, src3}
VPCLMULQDQZ256rmi [HasVLX, HasVPCLMULQDQ]
vpclmulqdq {src3, src2, src1, dst|dst, src1, src2, src3}
VPCLMULQDQZ256rri [HasVLX, HasVPCLMULQDQ]
vpclmulqdq {src3, src2, src1, dst|dst, src1, src2, src3}
KANDNWkk [HasAVX512]
kandnw {src2, src1, dst|dst, src1, src2}
KANDWkk [HasAVX512]
kandw {src2, src1, dst|dst, src1, src2}
KNOTWkk [HasAVX512]
knotw {src, dst|dst, src}
KORTESTWkk [HasAVX512]
kortestw {src2, src1|src1, src2}
KORWkk [HasAVX512]
korw {src2, src1, dst|dst, src1, src2}
KSHIFTLWki [HasAVX512]
kshiftlw {imm, src, dst|dst, src, imm}
KSHIFTRWki [HasAVX512]
kshiftrw {imm, src, dst|dst, src, imm}
KUNPCKBWkk [HasAVX512]
kunpckbw {src2, src1, dst|dst, src1, src2}
KXNORWkk [HasAVX512]
kxnorw {src2, src1, dst|dst, src1, src2}
KXORWkk [HasAVX512]
kxorw {src2, src1, dst|dst, src1, src2}
V4FMADDPSrm [HasAVX512]
v4fmaddps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
V4FMADDPSrmk [HasAVX512]
v4fmaddps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
V4FMADDPSrmkz [HasAVX512]
v4fmaddps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
V4FMADDSSrm [HasAVX512]
v4fmaddss {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
V4FMADDSSrmk [HasAVX512]
v4fmaddss {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
V4FMADDSSrmkz [HasAVX512]
v4fmaddss {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
V4FNMADDPSrm [HasAVX512]
v4fnmaddps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
V4FNMADDPSrmk [HasAVX512]
v4fnmaddps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
V4FNMADDPSrmkz [HasAVX512]
v4fnmaddps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
V4FNMADDSSrm [HasAVX512]
v4fnmaddss {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
V4FNMADDSSrmk [HasAVX512]
v4fnmaddss {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
V4FNMADDSSrmkz [HasAVX512]
v4fnmaddss {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VADDPDZrm [HasAVX512]
vaddpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VADDPDZrmb [HasAVX512]
vaddpd {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VADDPDZrmbk [HasAVX512]
vaddpd {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VADDPDZrmbkz [HasAVX512]
vaddpd {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VADDPDZrmk [HasAVX512]
vaddpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VADDPDZrmkz [HasAVX512]
vaddpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VADDPDZrr [HasAVX512]
vaddpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VADDPDZrrb [HasAVX512]
vaddpd {rc, src2, src1, dst|dst, src1, src2, rc}
VADDPDZrrbk [HasAVX512]
vaddpd {rc, src2, src1, dst {mask}|dst {mask}, src1, src2, rc}
|
Note
|
Constraints: src0 = dst |
VADDPDZrrbkz [HasAVX512]
vaddpd {rc, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, rc}
VADDPDZrrk [HasAVX512]
vaddpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VADDPDZrrkz [HasAVX512]
vaddpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VADDPSZrm [HasAVX512]
vaddps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VADDPSZrmb [HasAVX512]
vaddps {src2{1to16}, src1, dst|dst, src1, src2{1to16}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VADDPSZrmbk [HasAVX512]
vaddps {src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VADDPSZrmbkz [HasAVX512]
vaddps {src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VADDPSZrmk [HasAVX512]
vaddps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VADDPSZrmkz [HasAVX512]
vaddps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VADDPSZrr [HasAVX512]
vaddps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VADDPSZrrb [HasAVX512]
vaddps {rc, src2, src1, dst|dst, src1, src2, rc}
VADDPSZrrbk [HasAVX512]
vaddps {rc, src2, src1, dst {mask}|dst {mask}, src1, src2, rc}
|
Note
|
Constraints: src0 = dst |
VADDPSZrrbkz [HasAVX512]
vaddps {rc, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, rc}
VADDPSZrrk [HasAVX512]
vaddps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VADDPSZrrkz [HasAVX512]
vaddps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VADDSDZrm_Int [HasAVX512]
vaddsd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VADDSDZrmk_Int [HasAVX512]
vaddsd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VADDSDZrmkz_Int [HasAVX512]
vaddsd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VADDSDZrr_Int [HasAVX512]
vaddsd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VADDSDZrrb_Int [HasAVX512]
vaddsd {rc, src2, src1, dst|dst, src1, src2, rc}
VADDSDZrrbk_Int [HasAVX512]
vaddsd {rc, src2, src1, dst {mask}|dst {mask}, src1, src2, rc}
|
Note
|
Constraints: src0 = dst |
VADDSDZrrbkz_Int [HasAVX512]
vaddsd {rc, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, rc}
VADDSDZrrk_Int [HasAVX512]
vaddsd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VADDSDZrrkz_Int [HasAVX512]
vaddsd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VADDSSZrm_Int [HasAVX512]
vaddss {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VADDSSZrmk_Int [HasAVX512]
vaddss {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VADDSSZrmkz_Int [HasAVX512]
vaddss {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VADDSSZrr_Int [HasAVX512]
vaddss {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VADDSSZrrb_Int [HasAVX512]
vaddss {rc, src2, src1, dst|dst, src1, src2, rc}
VADDSSZrrbk_Int [HasAVX512]
vaddss {rc, src2, src1, dst {mask}|dst {mask}, src1, src2, rc}
|
Note
|
Constraints: src0 = dst |
VADDSSZrrbkz_Int [HasAVX512]
vaddss {rc, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, rc}
VADDSSZrrk_Int [HasAVX512]
vaddss {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VADDSSZrrkz_Int [HasAVX512]
vaddss {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VALIGNDZrmbi [HasAVX512]
valignd {src3, src2{1to16}, src1, dst|dst, src1, src2{1to16}, src3}
VALIGNDZrmbik [HasAVX512]
valignd {src3, src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}, src3}
|
Note
|
Constraints: src0 = dst |
VALIGNDZrmbikz [HasAVX512]
valignd {src3, src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}, src3}
VALIGNDZrmi [HasAVX512]
valignd {src3, src2, src1, dst|dst, src1, src2, src3}
VALIGNDZrmik [HasAVX512]
valignd {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VALIGNDZrmikz [HasAVX512]
valignd {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VALIGNDZrri [HasAVX512]
valignd {src3, src2, src1, dst|dst, src1, src2, src3}
VALIGNDZrrik [HasAVX512]
valignd {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VALIGNDZrrikz [HasAVX512]
valignd {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VALIGNQZrmbi [HasAVX512]
valignq {src3, src2{1to8}, src1, dst|dst, src1, src2{1to8}, src3}
VALIGNQZrmbik [HasAVX512]
valignq {src3, src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}, src3}
|
Note
|
Constraints: src0 = dst |
VALIGNQZrmbikz [HasAVX512]
valignq {src3, src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}, src3}
VALIGNQZrmi [HasAVX512]
valignq {src3, src2, src1, dst|dst, src1, src2, src3}
VALIGNQZrmik [HasAVX512]
valignq {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VALIGNQZrmikz [HasAVX512]
valignq {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VALIGNQZrri [HasAVX512]
valignq {src3, src2, src1, dst|dst, src1, src2, src3}
VALIGNQZrrik [HasAVX512]
valignq {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VALIGNQZrrikz [HasAVX512]
valignq {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VBLENDMPDZrm [HasAVX512]
vblendmpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VBLENDMPDZrmb [HasAVX512]
vblendmpd {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
VBLENDMPDZrmbk [HasAVX512]
vblendmpd {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
VBLENDMPDZrmbkz [HasAVX512]
vblendmpd {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
VBLENDMPDZrmk [HasAVX512]
vblendmpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
VBLENDMPDZrmkz [HasAVX512]
vblendmpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VBLENDMPDZrr [HasAVX512]
vblendmpd {src2, src1, dst|dst, src1, src2}
VBLENDMPDZrrk [HasAVX512]
vblendmpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
VBLENDMPDZrrkz [HasAVX512]
vblendmpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VBLENDMPSZrm [HasAVX512]
vblendmps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VBLENDMPSZrmb [HasAVX512]
vblendmps {src2{1to16}, src1, dst|dst, src1, src2{1to16}}
|
Note
|
Properties: mayLoad |
VBLENDMPSZrmbk [HasAVX512]
vblendmps {src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}}
|
Note
|
Properties: mayLoad |
VBLENDMPSZrmbkz [HasAVX512]
vblendmps {src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}}
|
Note
|
Properties: mayLoad |
VBLENDMPSZrmk [HasAVX512]
vblendmps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
VBLENDMPSZrmkz [HasAVX512]
vblendmps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VBLENDMPSZrr [HasAVX512]
vblendmps {src2, src1, dst|dst, src1, src2}
VBLENDMPSZrrk [HasAVX512]
vblendmps {src2, src1, dst {mask}|dst {mask}, src1, src2}
VBLENDMPSZrrkz [HasAVX512]
vblendmps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VBROADCASTF32X4Zrm [HasAVX512]
vbroadcastf32x4 {src, dst|dst, src}
VBROADCASTF32X4Zrmk [HasAVX512]
vbroadcastf32x4 {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VBROADCASTF32X4Zrmkz [HasAVX512]
vbroadcastf32x4 {src, dst {mask} {z}|dst {mask} {z}, src}
VBROADCASTF64X4Zrm [HasAVX512]
vbroadcastf64x4 {src, dst|dst, src}
VBROADCASTF64X4Zrmk [HasAVX512]
vbroadcastf64x4 {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VBROADCASTF64X4Zrmkz [HasAVX512]
vbroadcastf64x4 {src, dst {mask} {z}|dst {mask} {z}, src}
VBROADCASTI32X4Zrm [HasAVX512]
vbroadcasti32x4 {src, dst|dst, src}
VBROADCASTI32X4Zrmk [HasAVX512]
vbroadcasti32x4 {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VBROADCASTI32X4Zrmkz [HasAVX512]
vbroadcasti32x4 {src, dst {mask} {z}|dst {mask} {z}, src}
VBROADCASTI64X4Zrm [HasAVX512]
vbroadcasti64x4 {src, dst|dst, src}
VBROADCASTI64X4Zrmk [HasAVX512]
vbroadcasti64x4 {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VBROADCASTI64X4Zrmkz [HasAVX512]
vbroadcasti64x4 {src, dst {mask} {z}|dst {mask} {z}, src}
VBROADCASTSDZrm [HasAVX512]
vbroadcastsd {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
VBROADCASTSDZrmk [HasAVX512]
vbroadcastsd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VBROADCASTSDZrmkz [HasAVX512]
vbroadcastsd {src, dst {mask} {z}|dst {mask} {z}, src}
VBROADCASTSDZrr [HasAVX512]
vbroadcastsd {src, dst|dst, src}
VBROADCASTSDZrrk [HasAVX512]
vbroadcastsd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VBROADCASTSDZrrkz [HasAVX512]
vbroadcastsd {src, dst {mask} {z}|dst {mask} {z}, src}
VBROADCASTSSZrm [HasAVX512]
vbroadcastss {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
VBROADCASTSSZrmk [HasAVX512]
vbroadcastss {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VBROADCASTSSZrmkz [HasAVX512]
vbroadcastss {src, dst {mask} {z}|dst {mask} {z}, src}
VBROADCASTSSZrr [HasAVX512]
vbroadcastss {src, dst|dst, src}
VBROADCASTSSZrrk [HasAVX512]
vbroadcastss {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VBROADCASTSSZrrkz [HasAVX512]
vbroadcastss {src, dst {mask} {z}|dst {mask} {z}, src}
VCMPPDZrmbi [HasAVX512]
vcmppd {cc, src2{1to8}, src1, dst|dst, src1, src2{1to8}, cc}
|
Note
|
Properties: mayRaiseFPException |
VCMPPDZrmbik [HasAVX512]
vcmppd {cc, src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}, cc}
|
Note
|
Properties: mayRaiseFPException |
VCMPPDZrmi [HasAVX512]
vcmppd {cc, src2, src1, dst|dst, src1, src2, cc}
|
Note
|
Properties: mayRaiseFPException |
VCMPPDZrmik [HasAVX512]
vcmppd {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
|
Note
|
Properties: mayRaiseFPException |
VCMPPDZrri [HasAVX512]
vcmppd {cc, src2, src1, dst|dst, src1, src2, cc}
|
Note
|
Properties: mayRaiseFPException |
VCMPPDZrrib [HasAVX512]
vcmppd {cc, {sae}, src2, src1, dst|dst, src1, src2, {sae}, cc}
VCMPPDZrribk [HasAVX512]
vcmppd {cc, {sae}, src2, src1, dst {mask}|dst {mask}, src1, src2, {sae}, cc}
VCMPPDZrrik [HasAVX512]
vcmppd {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
|
Note
|
Properties: mayRaiseFPException |
VCMPPSZrmbi [HasAVX512]
vcmpps {cc, src2{1to16}, src1, dst|dst, src1, src2{1to16}, cc}
|
Note
|
Properties: mayRaiseFPException |
VCMPPSZrmbik [HasAVX512]
vcmpps {cc, src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}, cc}
|
Note
|
Properties: mayRaiseFPException |
VCMPPSZrmi [HasAVX512]
vcmpps {cc, src2, src1, dst|dst, src1, src2, cc}
|
Note
|
Properties: mayRaiseFPException |
VCMPPSZrmik [HasAVX512]
vcmpps {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
|
Note
|
Properties: mayRaiseFPException |
VCMPPSZrri [HasAVX512]
vcmpps {cc, src2, src1, dst|dst, src1, src2, cc}
|
Note
|
Properties: mayRaiseFPException |
VCMPPSZrrib [HasAVX512]
vcmpps {cc, {sae}, src2, src1, dst|dst, src1, src2, {sae}, cc}
VCMPPSZrribk [HasAVX512]
vcmpps {cc, {sae}, src2, src1, dst {mask}|dst {mask}, src1, src2, {sae}, cc}
VCMPPSZrrik [HasAVX512]
vcmpps {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
|
Note
|
Properties: mayRaiseFPException |
VCMPSDZrmi_Int [HasAVX512]
vcmpsd {cc, src2, src1, dst|dst, src1, src2, cc}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VCMPSDZrmik_Int [HasAVX512]
vcmpsd {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VCMPSDZrri_Int [HasAVX512]
vcmpsd {cc, src2, src1, dst|dst, src1, src2, cc}
|
Note
|
Properties: mayRaiseFPException |
VCMPSDZrrib_Int [HasAVX512]
vcmpsd {cc, {sae}, src2, src1, dst|dst, src1, src2, {sae}, cc}
VCMPSDZrribk_Int [HasAVX512]
vcmpsd {cc, {sae}, src2, src1, dst {mask}|dst {mask}, src1, src2, {sae}, cc}
VCMPSDZrrik_Int [HasAVX512]
vcmpsd {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
|
Note
|
Properties: mayRaiseFPException |
VCMPSSZrmi_Int [HasAVX512]
vcmpss {cc, src2, src1, dst|dst, src1, src2, cc}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VCMPSSZrmik_Int [HasAVX512]
vcmpss {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VCMPSSZrri_Int [HasAVX512]
vcmpss {cc, src2, src1, dst|dst, src1, src2, cc}
|
Note
|
Properties: mayRaiseFPException |
VCMPSSZrrib_Int [HasAVX512]
vcmpss {cc, {sae}, src2, src1, dst|dst, src1, src2, {sae}, cc}
VCMPSSZrribk_Int [HasAVX512]
vcmpss {cc, {sae}, src2, src1, dst {mask}|dst {mask}, src1, src2, {sae}, cc}
VCMPSSZrrik_Int [HasAVX512]
vcmpss {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
|
Note
|
Properties: mayRaiseFPException |
VCOMISDZrm [HasAVX512]
vcomisd {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VCOMISDZrr [HasAVX512]
vcomisd {src2, src1|src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VCOMISDZrrb [HasAVX512]
vcomisd {{sae}, src2, src1|src1, src2, {sae}}
VCOMISSZrm [HasAVX512]
vcomiss {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VCOMISSZrr [HasAVX512]
vcomiss {src2, src1|src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VCOMISSZrrb [HasAVX512]
vcomiss {{sae}, src2, src1|src1, src2, {sae}}
VCOMPRESSPDZmr [HasAVX512]
vcompresspd {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VCOMPRESSPDZmrk [HasAVX512]
vcompresspd {src, dst {mask}|dst {mask}, src}
VCOMPRESSPDZrr [HasAVX512]
vcompresspd {src1, dst|dst, src1}
VCOMPRESSPDZrrk [HasAVX512]
vcompresspd {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VCOMPRESSPDZrrkz [HasAVX512]
vcompresspd {src1, dst {mask} {z}|dst {mask} {z}, src1}
VCOMPRESSPSZmr [HasAVX512]
vcompressps {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VCOMPRESSPSZmrk [HasAVX512]
vcompressps {src, dst {mask}|dst {mask}, src}
VCOMPRESSPSZrr [HasAVX512]
vcompressps {src1, dst|dst, src1}
VCOMPRESSPSZrrk [HasAVX512]
vcompressps {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VCOMPRESSPSZrrkz [HasAVX512]
vcompressps {src1, dst {mask} {z}|dst {mask} {z}, src1}
VCVTDQ2PDZrm [HasAVX512]
vcvtdq2pd {src, dst|dst, src}
VCVTDQ2PDZrmb [HasAVX512]
vcvtdq2pd {src{1to8}, dst|dst, src{1to8}}
VCVTDQ2PDZrmbk [HasAVX512]
vcvtdq2pd {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Constraints: src0 = dst |
VCVTDQ2PDZrmbkz [HasAVX512]
vcvtdq2pd {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
VCVTDQ2PDZrmk [HasAVX512]
vcvtdq2pd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTDQ2PDZrmkz [HasAVX512]
vcvtdq2pd {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTDQ2PDZrr [HasAVX512]
vcvtdq2pd {src, dst|dst, src}
VCVTDQ2PDZrrk [HasAVX512]
vcvtdq2pd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTDQ2PDZrrkz [HasAVX512]
vcvtdq2pd {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTDQ2PSZrm [HasAVX512]
vcvtdq2ps {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTDQ2PSZrmb [HasAVX512]
vcvtdq2ps {src{1to16}, dst|dst, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
VCVTDQ2PSZrmbk [HasAVX512]
vcvtdq2ps {src{1to16}, dst {mask}|dst {mask}, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTDQ2PSZrmbkz [HasAVX512]
vcvtdq2ps {src{1to16}, dst {mask} {z}|dst {mask} {z}, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
VCVTDQ2PSZrmk [HasAVX512]
vcvtdq2ps {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTDQ2PSZrmkz [HasAVX512]
vcvtdq2ps {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTDQ2PSZrr [HasAVX512]
vcvtdq2ps {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTDQ2PSZrrb [HasAVX512]
vcvtdq2ps {rc, src, dst|dst, src, rc}
VCVTDQ2PSZrrbk [HasAVX512]
vcvtdq2ps {rc, src, dst {mask}|dst {mask}, src, rc}
|
Note
|
Constraints: src0 = dst |
VCVTDQ2PSZrrbkz [HasAVX512]
vcvtdq2ps {rc, src, dst {mask} {z}|dst {mask} {z}, src, rc}
VCVTDQ2PSZrrk [HasAVX512]
vcvtdq2ps {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTDQ2PSZrrkz [HasAVX512]
vcvtdq2ps {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2DQZrm [HasAVX512]
vcvtpd2dq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2DQZrmb [HasAVX512]
vcvtpd2dq {src{1to8}, dst|dst, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2DQZrmbk [HasAVX512]
vcvtpd2dq {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPD2DQZrmbkz [HasAVX512]
vcvtpd2dq {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2DQZrmk [HasAVX512]
vcvtpd2dq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPD2DQZrmkz [HasAVX512]
vcvtpd2dq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2DQZrr [HasAVX512]
vcvtpd2dq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2DQZrrb [HasAVX512]
vcvtpd2dq {rc, src, dst|dst, src, rc}
VCVTPD2DQZrrbk [HasAVX512]
vcvtpd2dq {rc, src, dst {mask}|dst {mask}, src, rc}
|
Note
|
Constraints: src0 = dst |
VCVTPD2DQZrrbkz [HasAVX512]
vcvtpd2dq {rc, src, dst {mask} {z}|dst {mask} {z}, src, rc}
VCVTPD2DQZrrk [HasAVX512]
vcvtpd2dq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPD2DQZrrkz [HasAVX512]
vcvtpd2dq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2PSZrm [HasAVX512]
vcvtpd2ps {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2PSZrmb [HasAVX512]
vcvtpd2ps {src{1to8}, dst|dst, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2PSZrmbk [HasAVX512]
vcvtpd2ps {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPD2PSZrmbkz [HasAVX512]
vcvtpd2ps {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2PSZrmk [HasAVX512]
vcvtpd2ps {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPD2PSZrmkz [HasAVX512]
vcvtpd2ps {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2PSZrr [HasAVX512]
vcvtpd2ps {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2PSZrrb [HasAVX512]
vcvtpd2ps {rc, src, dst|dst, src, rc}
VCVTPD2PSZrrbk [HasAVX512]
vcvtpd2ps {rc, src, dst {mask}|dst {mask}, src, rc}
|
Note
|
Constraints: src0 = dst |
VCVTPD2PSZrrbkz [HasAVX512]
vcvtpd2ps {rc, src, dst {mask} {z}|dst {mask} {z}, src, rc}
VCVTPD2PSZrrk [HasAVX512]
vcvtpd2ps {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPD2PSZrrkz [HasAVX512]
vcvtpd2ps {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2UDQZrm [HasAVX512]
vcvtpd2udq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2UDQZrmb [HasAVX512]
vcvtpd2udq {src{1to8}, dst|dst, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2UDQZrmbk [HasAVX512]
vcvtpd2udq {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPD2UDQZrmbkz [HasAVX512]
vcvtpd2udq {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2UDQZrmk [HasAVX512]
vcvtpd2udq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPD2UDQZrmkz [HasAVX512]
vcvtpd2udq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2UDQZrr [HasAVX512]
vcvtpd2udq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2UDQZrrb [HasAVX512]
vcvtpd2udq {rc, src, dst|dst, src, rc}
VCVTPD2UDQZrrbk [HasAVX512]
vcvtpd2udq {rc, src, dst {mask}|dst {mask}, src, rc}
|
Note
|
Constraints: src0 = dst |
VCVTPD2UDQZrrbkz [HasAVX512]
vcvtpd2udq {rc, src, dst {mask} {z}|dst {mask} {z}, src, rc}
VCVTPD2UDQZrrk [HasAVX512]
vcvtpd2udq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPD2UDQZrrkz [HasAVX512]
vcvtpd2udq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2PSZrm [HasAVX512]
vcvtph2ps {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2PSZrmk [HasAVX512]
vcvtph2ps {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2PSZrmkz [HasAVX512]
vcvtph2ps {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2PSZrr [HasAVX512]
vcvtph2ps {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2PSZrrb [HasAVX512]
vcvtph2ps {{sae}, src, dst|dst, src, {sae}}
VCVTPH2PSZrrbk [HasAVX512]
vcvtph2ps {{sae}, src, dst {mask}|dst {mask}, src, {sae}}
|
Note
|
Constraints: src0 = dst |
VCVTPH2PSZrrbkz [HasAVX512]
vcvtph2ps {{sae}, src, dst {mask} {z}|dst {mask} {z}, src, {sae}}
VCVTPH2PSZrrk [HasAVX512]
vcvtph2ps {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2PSZrrkz [HasAVX512]
vcvtph2ps {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2DQZrm [HasAVX512]
vcvtps2dq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2DQZrmb [HasAVX512]
vcvtps2dq {src{1to16}, dst|dst, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2DQZrmbk [HasAVX512]
vcvtps2dq {src{1to16}, dst {mask}|dst {mask}, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPS2DQZrmbkz [HasAVX512]
vcvtps2dq {src{1to16}, dst {mask} {z}|dst {mask} {z}, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2DQZrmk [HasAVX512]
vcvtps2dq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPS2DQZrmkz [HasAVX512]
vcvtps2dq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2DQZrr [HasAVX512]
vcvtps2dq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2DQZrrb [HasAVX512]
vcvtps2dq {rc, src, dst|dst, src, rc}
VCVTPS2DQZrrbk [HasAVX512]
vcvtps2dq {rc, src, dst {mask}|dst {mask}, src, rc}
|
Note
|
Constraints: src0 = dst |
VCVTPS2DQZrrbkz [HasAVX512]
vcvtps2dq {rc, src, dst {mask} {z}|dst {mask} {z}, src, rc}
VCVTPS2DQZrrk [HasAVX512]
vcvtps2dq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPS2DQZrrkz [HasAVX512]
vcvtps2dq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2PDZrm [HasAVX512]
vcvtps2pd {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2PDZrmb [HasAVX512]
vcvtps2pd {src{1to8}, dst|dst, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2PDZrmbk [HasAVX512]
vcvtps2pd {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPS2PDZrmbkz [HasAVX512]
vcvtps2pd {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2PDZrmk [HasAVX512]
vcvtps2pd {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPS2PDZrmkz [HasAVX512]
vcvtps2pd {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2PDZrr [HasAVX512]
vcvtps2pd {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2PDZrrb [HasAVX512]
vcvtps2pd {{sae}, src, dst|dst, src, {sae}}
VCVTPS2PDZrrbk [HasAVX512]
vcvtps2pd {{sae}, src, dst {mask}|dst {mask}, src, {sae}}
|
Note
|
Constraints: src0 = dst |
VCVTPS2PDZrrbkz [HasAVX512]
vcvtps2pd {{sae}, src, dst {mask} {z}|dst {mask} {z}, src, {sae}}
VCVTPS2PDZrrk [HasAVX512]
vcvtps2pd {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPS2PDZrrkz [HasAVX512]
vcvtps2pd {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2PHZmr [HasAVX512]
vcvtps2ph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException, mayStore |
VCVTPS2PHZmrk [HasAVX512]
vcvtps2ph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException, mayStore |
VCVTPS2PHZrr [HasAVX512]
vcvtps2ph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2PHZrrb [HasAVX512]
vcvtps2ph {src2, {sae}, src1, dst|dst, src1, {sae}, src2}
VCVTPS2PHZrrbk [HasAVX512]
vcvtps2ph {src2, {sae}, src1, dst {mask}|dst {mask}, src1, {sae}, src2}
|
Note
|
Constraints: src0 = dst |
VCVTPS2PHZrrbkz [HasAVX512]
vcvtps2ph {src2, {sae}, src1, dst {mask} {z}|dst {mask} {z}, src1, {sae}, src2}
VCVTPS2PHZrrk [HasAVX512]
vcvtps2ph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPS2PHZrrkz [HasAVX512]
vcvtps2ph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2UDQZrm [HasAVX512]
vcvtps2udq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2UDQZrmb [HasAVX512]
vcvtps2udq {src{1to16}, dst|dst, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2UDQZrmbk [HasAVX512]
vcvtps2udq {src{1to16}, dst {mask}|dst {mask}, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPS2UDQZrmbkz [HasAVX512]
vcvtps2udq {src{1to16}, dst {mask} {z}|dst {mask} {z}, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2UDQZrmk [HasAVX512]
vcvtps2udq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPS2UDQZrmkz [HasAVX512]
vcvtps2udq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2UDQZrr [HasAVX512]
vcvtps2udq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2UDQZrrb [HasAVX512]
vcvtps2udq {rc, src, dst|dst, src, rc}
VCVTPS2UDQZrrbk [HasAVX512]
vcvtps2udq {rc, src, dst {mask}|dst {mask}, src, rc}
|
Note
|
Constraints: src0 = dst |
VCVTPS2UDQZrrbkz [HasAVX512]
vcvtps2udq {rc, src, dst {mask} {z}|dst {mask} {z}, src, rc}
VCVTPS2UDQZrrk [HasAVX512]
vcvtps2udq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPS2UDQZrrkz [HasAVX512]
vcvtps2udq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTSD2SI64Zrm_Int [HasAVX512]
vcvtsd2si {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTSD2SI64Zrr_Int [HasAVX512]
vcvtsd2si {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTSD2SI64Zrrb_Int [HasAVX512]
vcvtsd2si {rc, src, dst|dst, src, rc}
VCVTSD2SIZrm_Int [HasAVX512]
vcvtsd2si {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTSD2SIZrr_Int [HasAVX512]
vcvtsd2si {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTSD2SIZrrb_Int [HasAVX512]
vcvtsd2si {rc, src, dst|dst, src, rc}
VCVTSD2SSZrm_Int [HasAVX512]
vcvtsd2ss {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VCVTSD2SSZrmk_Int [HasAVX512]
vcvtsd2ss {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTSD2SSZrmkz_Int [HasAVX512]
vcvtsd2ss {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VCVTSD2SSZrr_Int [HasAVX512]
vcvtsd2ss {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VCVTSD2SSZrrb_Int [HasAVX512]
vcvtsd2ss {rc, src2, src1, dst|dst, src1, src2, rc}
VCVTSD2SSZrrbk_Int [HasAVX512]
vcvtsd2ss {rc, src2, src1, dst {mask}|dst {mask}, src1, src2, rc}
|
Note
|
Constraints: src0 = dst |
VCVTSD2SSZrrbkz_Int [HasAVX512]
vcvtsd2ss {rc, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, rc}
VCVTSD2SSZrrk_Int [HasAVX512]
vcvtsd2ss {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTSD2SSZrrkz_Int [HasAVX512]
vcvtsd2ss {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VCVTSD2USI64Zrm_Int [HasAVX512]
vcvtsd2usi {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTSD2USI64Zrr_Int [HasAVX512]
vcvtsd2usi {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTSD2USI64Zrrb_Int [HasAVX512]
vcvtsd2usi {rc, src, dst|dst, src, rc}
VCVTSD2USIZrm_Int [HasAVX512]
vcvtsd2usi {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTSD2USIZrr_Int [HasAVX512]
vcvtsd2usi {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTSD2USIZrrb_Int [HasAVX512]
vcvtsd2usi {rc, src, dst|dst, src, rc}
VCVTSI2SDZrm_Int [HasAVX512]
vcvtsi2sd{l} {src2, src1, dst|dst, src1, src2}
VCVTSI2SDZrr_Int [HasAVX512]
vcvtsi2sd {src2, src1, dst|dst, src1, src2}
VCVTSI2SSZrm_Int [HasAVX512]
vcvtsi2ss{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VCVTSI2SSZrr_Int [HasAVX512]
vcvtsi2ss {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VCVTSI2SSZrrb_Int [HasAVX512]
vcvtsi2ss {src2, rc, src1, dst|dst, src1, rc, src2}
VCVTSI642SDZrm_Int [HasAVX512]
vcvtsi2sd{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VCVTSI642SDZrr_Int [HasAVX512]
vcvtsi2sd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VCVTSI642SDZrrb_Int [HasAVX512]
vcvtsi2sd {src2, rc, src1, dst|dst, src1, rc, src2}
VCVTSI642SSZrm_Int [HasAVX512]
vcvtsi2ss{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VCVTSI642SSZrr_Int [HasAVX512]
vcvtsi2ss {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VCVTSI642SSZrrb_Int [HasAVX512]
vcvtsi2ss {src2, rc, src1, dst|dst, src1, rc, src2}
VCVTSS2SDZrm_Int [HasAVX512]
vcvtss2sd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VCVTSS2SDZrmk_Int [HasAVX512]
vcvtss2sd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTSS2SDZrmkz_Int [HasAVX512]
vcvtss2sd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VCVTSS2SDZrr_Int [HasAVX512]
vcvtss2sd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VCVTSS2SDZrrb_Int [HasAVX512]
vcvtss2sd {{sae}, src2, src1, dst|dst, src1, src2, {sae}}
VCVTSS2SDZrrbk_Int [HasAVX512]
vcvtss2sd {{sae}, src2, src1, dst {mask}|dst {mask}, src1, src2, {sae}}
|
Note
|
Constraints: src0 = dst |
VCVTSS2SDZrrbkz_Int [HasAVX512]
vcvtss2sd {{sae}, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, {sae}}
VCVTSS2SDZrrk_Int [HasAVX512]
vcvtss2sd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTSS2SDZrrkz_Int [HasAVX512]
vcvtss2sd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VCVTSS2SI64Zrm_Int [HasAVX512]
vcvtss2si {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTSS2SI64Zrr_Int [HasAVX512]
vcvtss2si {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTSS2SI64Zrrb_Int [HasAVX512]
vcvtss2si {rc, src, dst|dst, src, rc}
VCVTSS2SIZrm_Int [HasAVX512]
vcvtss2si {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTSS2SIZrr_Int [HasAVX512]
vcvtss2si {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTSS2SIZrrb_Int [HasAVX512]
vcvtss2si {rc, src, dst|dst, src, rc}
VCVTSS2USI64Zrm_Int [HasAVX512]
vcvtss2usi {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTSS2USI64Zrr_Int [HasAVX512]
vcvtss2usi {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTSS2USI64Zrrb_Int [HasAVX512]
vcvtss2usi {rc, src, dst|dst, src, rc}
VCVTSS2USIZrm_Int [HasAVX512]
vcvtss2usi {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTSS2USIZrr_Int [HasAVX512]
vcvtss2usi {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTSS2USIZrrb_Int [HasAVX512]
vcvtss2usi {rc, src, dst|dst, src, rc}
VCVTTPD2DQZrm [HasAVX512]
vcvttpd2dq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2DQZrmb [HasAVX512]
vcvttpd2dq {src{1to8}, dst|dst, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2DQZrmbk [HasAVX512]
vcvttpd2dq {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPD2DQZrmbkz [HasAVX512]
vcvttpd2dq {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2DQZrmk [HasAVX512]
vcvttpd2dq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPD2DQZrmkz [HasAVX512]
vcvttpd2dq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2DQZrr [HasAVX512]
vcvttpd2dq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2DQZrrb [HasAVX512]
vcvttpd2dq {{sae}, src, dst|dst, src, {sae}}
VCVTTPD2DQZrrbk [HasAVX512]
vcvttpd2dq {{sae}, src, dst {mask}|dst {mask}, src, {sae}}
|
Note
|
Constraints: src0 = dst |
VCVTTPD2DQZrrbkz [HasAVX512]
vcvttpd2dq {{sae}, src, dst {mask} {z}|dst {mask} {z}, src, {sae}}
VCVTTPD2DQZrrk [HasAVX512]
vcvttpd2dq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPD2DQZrrkz [HasAVX512]
vcvttpd2dq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2UDQZrm [HasAVX512]
vcvttpd2udq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2UDQZrmb [HasAVX512]
vcvttpd2udq {src{1to8}, dst|dst, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2UDQZrmbk [HasAVX512]
vcvttpd2udq {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPD2UDQZrmbkz [HasAVX512]
vcvttpd2udq {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2UDQZrmk [HasAVX512]
vcvttpd2udq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPD2UDQZrmkz [HasAVX512]
vcvttpd2udq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2UDQZrr [HasAVX512]
vcvttpd2udq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2UDQZrrb [HasAVX512]
vcvttpd2udq {{sae}, src, dst|dst, src, {sae}}
VCVTTPD2UDQZrrbk [HasAVX512]
vcvttpd2udq {{sae}, src, dst {mask}|dst {mask}, src, {sae}}
|
Note
|
Constraints: src0 = dst |
VCVTTPD2UDQZrrbkz [HasAVX512]
vcvttpd2udq {{sae}, src, dst {mask} {z}|dst {mask} {z}, src, {sae}}
VCVTTPD2UDQZrrk [HasAVX512]
vcvttpd2udq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPD2UDQZrrkz [HasAVX512]
vcvttpd2udq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2DQZrm [HasAVX512]
vcvttps2dq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2DQZrmb [HasAVX512]
vcvttps2dq {src{1to16}, dst|dst, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2DQZrmbk [HasAVX512]
vcvttps2dq {src{1to16}, dst {mask}|dst {mask}, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPS2DQZrmbkz [HasAVX512]
vcvttps2dq {src{1to16}, dst {mask} {z}|dst {mask} {z}, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2DQZrmk [HasAVX512]
vcvttps2dq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPS2DQZrmkz [HasAVX512]
vcvttps2dq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2DQZrr [HasAVX512]
vcvttps2dq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2DQZrrb [HasAVX512]
vcvttps2dq {{sae}, src, dst|dst, src, {sae}}
VCVTTPS2DQZrrbk [HasAVX512]
vcvttps2dq {{sae}, src, dst {mask}|dst {mask}, src, {sae}}
|
Note
|
Constraints: src0 = dst |
VCVTTPS2DQZrrbkz [HasAVX512]
vcvttps2dq {{sae}, src, dst {mask} {z}|dst {mask} {z}, src, {sae}}
VCVTTPS2DQZrrk [HasAVX512]
vcvttps2dq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPS2DQZrrkz [HasAVX512]
vcvttps2dq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2UDQZrm [HasAVX512]
vcvttps2udq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2UDQZrmb [HasAVX512]
vcvttps2udq {src{1to16}, dst|dst, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2UDQZrmbk [HasAVX512]
vcvttps2udq {src{1to16}, dst {mask}|dst {mask}, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPS2UDQZrmbkz [HasAVX512]
vcvttps2udq {src{1to16}, dst {mask} {z}|dst {mask} {z}, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2UDQZrmk [HasAVX512]
vcvttps2udq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPS2UDQZrmkz [HasAVX512]
vcvttps2udq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2UDQZrr [HasAVX512]
vcvttps2udq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2UDQZrrb [HasAVX512]
vcvttps2udq {{sae}, src, dst|dst, src, {sae}}
VCVTTPS2UDQZrrbk [HasAVX512]
vcvttps2udq {{sae}, src, dst {mask}|dst {mask}, src, {sae}}
|
Note
|
Constraints: src0 = dst |
VCVTTPS2UDQZrrbkz [HasAVX512]
vcvttps2udq {{sae}, src, dst {mask} {z}|dst {mask} {z}, src, {sae}}
VCVTTPS2UDQZrrk [HasAVX512]
vcvttps2udq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPS2UDQZrrkz [HasAVX512]
vcvttps2udq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTSD2SI64Zrm_Int [HasAVX512]
vcvttsd2si {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTSD2SI64Zrr_Int [HasAVX512]
vcvttsd2si {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTSD2SI64Zrrb_Int [HasAVX512]
vcvttsd2si {{sae}, src, dst|dst, src, {sae}}
VCVTTSD2SIZrm_Int [HasAVX512]
vcvttsd2si {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTSD2SIZrr_Int [HasAVX512]
vcvttsd2si {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTSD2SIZrrb_Int [HasAVX512]
vcvttsd2si {{sae}, src, dst|dst, src, {sae}}
VCVTTSD2USI64Zrm_Int [HasAVX512]
vcvttsd2usi {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTSD2USI64Zrr_Int [HasAVX512]
vcvttsd2usi {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTSD2USI64Zrrb_Int [HasAVX512]
vcvttsd2usi {{sae}, src, dst|dst, src, {sae}}
VCVTTSD2USIZrm_Int [HasAVX512]
vcvttsd2usi {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTSD2USIZrr_Int [HasAVX512]
vcvttsd2usi {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTSD2USIZrrb_Int [HasAVX512]
vcvttsd2usi {{sae}, src, dst|dst, src, {sae}}
VCVTTSS2SI64Zrm_Int [HasAVX512]
vcvttss2si {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTSS2SI64Zrr_Int [HasAVX512]
vcvttss2si {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTSS2SI64Zrrb_Int [HasAVX512]
vcvttss2si {{sae}, src, dst|dst, src, {sae}}
VCVTTSS2SIZrm_Int [HasAVX512]
vcvttss2si {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTSS2SIZrr_Int [HasAVX512]
vcvttss2si {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTSS2SIZrrb_Int [HasAVX512]
vcvttss2si {{sae}, src, dst|dst, src, {sae}}
VCVTTSS2USI64Zrm_Int [HasAVX512]
vcvttss2usi {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTSS2USI64Zrr_Int [HasAVX512]
vcvttss2usi {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTSS2USI64Zrrb_Int [HasAVX512]
vcvttss2usi {{sae}, src, dst|dst, src, {sae}}
VCVTTSS2USIZrm_Int [HasAVX512]
vcvttss2usi {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTSS2USIZrr_Int [HasAVX512]
vcvttss2usi {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTSS2USIZrrb_Int [HasAVX512]
vcvttss2usi {{sae}, src, dst|dst, src, {sae}}
VCVTUDQ2PDZrm [HasAVX512]
vcvtudq2pd {src, dst|dst, src}
VCVTUDQ2PDZrmb [HasAVX512]
vcvtudq2pd {src{1to8}, dst|dst, src{1to8}}
VCVTUDQ2PDZrmbk [HasAVX512]
vcvtudq2pd {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Constraints: src0 = dst |
VCVTUDQ2PDZrmbkz [HasAVX512]
vcvtudq2pd {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
VCVTUDQ2PDZrmk [HasAVX512]
vcvtudq2pd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTUDQ2PDZrmkz [HasAVX512]
vcvtudq2pd {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTUDQ2PDZrr [HasAVX512]
vcvtudq2pd {src, dst|dst, src}
VCVTUDQ2PDZrrk [HasAVX512]
vcvtudq2pd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTUDQ2PDZrrkz [HasAVX512]
vcvtudq2pd {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTUDQ2PSZrm [HasAVX512]
vcvtudq2ps {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTUDQ2PSZrmb [HasAVX512]
vcvtudq2ps {src{1to16}, dst|dst, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
VCVTUDQ2PSZrmbk [HasAVX512]
vcvtudq2ps {src{1to16}, dst {mask}|dst {mask}, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTUDQ2PSZrmbkz [HasAVX512]
vcvtudq2ps {src{1to16}, dst {mask} {z}|dst {mask} {z}, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
VCVTUDQ2PSZrmk [HasAVX512]
vcvtudq2ps {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTUDQ2PSZrmkz [HasAVX512]
vcvtudq2ps {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTUDQ2PSZrr [HasAVX512]
vcvtudq2ps {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTUDQ2PSZrrb [HasAVX512]
vcvtudq2ps {rc, src, dst|dst, src, rc}
VCVTUDQ2PSZrrbk [HasAVX512]
vcvtudq2ps {rc, src, dst {mask}|dst {mask}, src, rc}
|
Note
|
Constraints: src0 = dst |
VCVTUDQ2PSZrrbkz [HasAVX512]
vcvtudq2ps {rc, src, dst {mask} {z}|dst {mask} {z}, src, rc}
VCVTUDQ2PSZrrk [HasAVX512]
vcvtudq2ps {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTUDQ2PSZrrkz [HasAVX512]
vcvtudq2ps {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTUSI2SDZrm_Int [HasAVX512]
vcvtusi2sd{l} {src2, src1, dst|dst, src1, src2}
VCVTUSI2SDZrr_Int [HasAVX512]
vcvtusi2sd {src2, src1, dst|dst, src1, src2}
VCVTUSI2SSZrm_Int [HasAVX512]
vcvtusi2ss{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VCVTUSI2SSZrr_Int [HasAVX512]
vcvtusi2ss {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VCVTUSI2SSZrrb_Int [HasAVX512]
vcvtusi2ss {src2, rc, src1, dst|dst, src1, rc, src2}
VCVTUSI642SDZrm_Int [HasAVX512]
vcvtusi2sd{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VCVTUSI642SDZrr_Int [HasAVX512]
vcvtusi2sd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VCVTUSI642SDZrrb_Int [HasAVX512]
vcvtusi2sd {src2, rc, src1, dst|dst, src1, rc, src2}
VCVTUSI642SSZrm_Int [HasAVX512]
vcvtusi2ss{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VCVTUSI642SSZrr_Int [HasAVX512]
vcvtusi2ss {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VCVTUSI642SSZrrb_Int [HasAVX512]
vcvtusi2ss {src2, rc, src1, dst|dst, src1, rc, src2}
VDIVPDZrm [HasAVX512]
vdivpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VDIVPDZrmb [HasAVX512]
vdivpd {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VDIVPDZrmbk [HasAVX512]
vdivpd {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VDIVPDZrmbkz [HasAVX512]
vdivpd {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VDIVPDZrmk [HasAVX512]
vdivpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VDIVPDZrmkz [HasAVX512]
vdivpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VDIVPDZrr [HasAVX512]
vdivpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VDIVPDZrrb [HasAVX512]
vdivpd {rc, src2, src1, dst|dst, src1, src2, rc}
VDIVPDZrrbk [HasAVX512]
vdivpd {rc, src2, src1, dst {mask}|dst {mask}, src1, src2, rc}
|
Note
|
Constraints: src0 = dst |
VDIVPDZrrbkz [HasAVX512]
vdivpd {rc, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, rc}
VDIVPDZrrk [HasAVX512]
vdivpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VDIVPDZrrkz [HasAVX512]
vdivpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VDIVPSZrm [HasAVX512]
vdivps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VDIVPSZrmb [HasAVX512]
vdivps {src2{1to16}, src1, dst|dst, src1, src2{1to16}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VDIVPSZrmbk [HasAVX512]
vdivps {src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VDIVPSZrmbkz [HasAVX512]
vdivps {src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VDIVPSZrmk [HasAVX512]
vdivps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VDIVPSZrmkz [HasAVX512]
vdivps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VDIVPSZrr [HasAVX512]
vdivps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VDIVPSZrrb [HasAVX512]
vdivps {rc, src2, src1, dst|dst, src1, src2, rc}
VDIVPSZrrbk [HasAVX512]
vdivps {rc, src2, src1, dst {mask}|dst {mask}, src1, src2, rc}
|
Note
|
Constraints: src0 = dst |
VDIVPSZrrbkz [HasAVX512]
vdivps {rc, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, rc}
VDIVPSZrrk [HasAVX512]
vdivps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VDIVPSZrrkz [HasAVX512]
vdivps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VDIVSDZrm_Int [HasAVX512]
vdivsd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VDIVSDZrmk_Int [HasAVX512]
vdivsd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VDIVSDZrmkz_Int [HasAVX512]
vdivsd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VDIVSDZrr_Int [HasAVX512]
vdivsd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VDIVSDZrrb_Int [HasAVX512]
vdivsd {rc, src2, src1, dst|dst, src1, src2, rc}
VDIVSDZrrbk_Int [HasAVX512]
vdivsd {rc, src2, src1, dst {mask}|dst {mask}, src1, src2, rc}
|
Note
|
Constraints: src0 = dst |
VDIVSDZrrbkz_Int [HasAVX512]
vdivsd {rc, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, rc}
VDIVSDZrrk_Int [HasAVX512]
vdivsd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VDIVSDZrrkz_Int [HasAVX512]
vdivsd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VDIVSSZrm_Int [HasAVX512]
vdivss {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VDIVSSZrmk_Int [HasAVX512]
vdivss {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VDIVSSZrmkz_Int [HasAVX512]
vdivss {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VDIVSSZrr_Int [HasAVX512]
vdivss {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VDIVSSZrrb_Int [HasAVX512]
vdivss {rc, src2, src1, dst|dst, src1, src2, rc}
VDIVSSZrrbk_Int [HasAVX512]
vdivss {rc, src2, src1, dst {mask}|dst {mask}, src1, src2, rc}
|
Note
|
Constraints: src0 = dst |
VDIVSSZrrbkz_Int [HasAVX512]
vdivss {rc, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, rc}
VDIVSSZrrk_Int [HasAVX512]
vdivss {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VDIVSSZrrkz_Int [HasAVX512]
vdivss {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VEXP2PDZm [HasAVX512]
vexp2pd {src, dst|dst, src}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VEXP2PDZmb [HasAVX512]
vexp2pd {src{1to8}, dst|dst, src{1to8}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VEXP2PDZmbk [HasAVX512]
vexp2pd {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VEXP2PDZmbkz [HasAVX512]
vexp2pd {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VEXP2PDZmk [HasAVX512]
vexp2pd {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VEXP2PDZmkz [HasAVX512]
vexp2pd {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VEXP2PDZr [HasAVX512]
vexp2pd {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VEXP2PDZrb [HasAVX512]
vexp2pd {{sae}, src, dst|dst, src, {sae}}
VEXP2PDZrbk [HasAVX512]
vexp2pd {{sae}, src, dst {mask}|dst {mask}, src, {sae}}
|
Note
|
Constraints: src0 = dst |
VEXP2PDZrbkz [HasAVX512]
vexp2pd {{sae}, src, dst {mask} {z}|dst {mask} {z}, src, {sae}}
VEXP2PDZrk [HasAVX512]
vexp2pd {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VEXP2PDZrkz [HasAVX512]
vexp2pd {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VEXP2PSZm [HasAVX512]
vexp2ps {src, dst|dst, src}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VEXP2PSZmb [HasAVX512]
vexp2ps {src{1to16}, dst|dst, src{1to16}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VEXP2PSZmbk [HasAVX512]
vexp2ps {src{1to16}, dst {mask}|dst {mask}, src{1to16}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VEXP2PSZmbkz [HasAVX512]
vexp2ps {src{1to16}, dst {mask} {z}|dst {mask} {z}, src{1to16}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VEXP2PSZmk [HasAVX512]
vexp2ps {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VEXP2PSZmkz [HasAVX512]
vexp2ps {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VEXP2PSZr [HasAVX512]
vexp2ps {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VEXP2PSZrb [HasAVX512]
vexp2ps {{sae}, src, dst|dst, src, {sae}}
VEXP2PSZrbk [HasAVX512]
vexp2ps {{sae}, src, dst {mask}|dst {mask}, src, {sae}}
|
Note
|
Constraints: src0 = dst |
VEXP2PSZrbkz [HasAVX512]
vexp2ps {{sae}, src, dst {mask} {z}|dst {mask} {z}, src, {sae}}
VEXP2PSZrk [HasAVX512]
vexp2ps {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VEXP2PSZrkz [HasAVX512]
vexp2ps {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VEXPANDPDZrm [HasAVX512]
vexpandpd {src1, dst|dst, src1}
VEXPANDPDZrmk [HasAVX512]
vexpandpd {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VEXPANDPDZrmkz [HasAVX512]
vexpandpd {src1, dst {mask} {z}|dst {mask} {z}, src1}
VEXPANDPDZrr [HasAVX512]
vexpandpd {src1, dst|dst, src1}
VEXPANDPDZrrk [HasAVX512]
vexpandpd {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VEXPANDPDZrrkz [HasAVX512]
vexpandpd {src1, dst {mask} {z}|dst {mask} {z}, src1}
VEXPANDPSZrm [HasAVX512]
vexpandps {src1, dst|dst, src1}
VEXPANDPSZrmk [HasAVX512]
vexpandps {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VEXPANDPSZrmkz [HasAVX512]
vexpandps {src1, dst {mask} {z}|dst {mask} {z}, src1}
VEXPANDPSZrr [HasAVX512]
vexpandps {src1, dst|dst, src1}
VEXPANDPSZrrk [HasAVX512]
vexpandps {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VEXPANDPSZrrkz [HasAVX512]
vexpandps {src1, dst {mask} {z}|dst {mask} {z}, src1}
VEXTRACTF32X4Zmri [HasAVX512]
vextractf32x4 {idx, src1, dst|dst, src1, idx}
VEXTRACTF32X4Zmrik [HasAVX512]
vextractf32x4 {idx, src1, dst {mask}|dst {mask}, src1, idx}
|
Note
|
Properties: mayStore |
VEXTRACTF32X4Zrri [HasAVX512]
vextractf32x4 {idx, src1, dst|dst, src1, idx}
VEXTRACTF32X4Zrrik [HasAVX512]
vextractf32x4 {idx, src1, dst {mask}|dst {mask}, src1, idx}
|
Note
|
Constraints: src0 = dst |
VEXTRACTF32X4Zrrikz [HasAVX512]
vextractf32x4 {idx, src1, dst {mask} {z}|dst {mask} {z}, src1, idx}
VEXTRACTF64X4Zmri [HasAVX512]
vextractf64x4 {idx, src1, dst|dst, src1, idx}
VEXTRACTF64X4Zmrik [HasAVX512]
vextractf64x4 {idx, src1, dst {mask}|dst {mask}, src1, idx}
|
Note
|
Properties: mayStore |
VEXTRACTF64X4Zrri [HasAVX512]
vextractf64x4 {idx, src1, dst|dst, src1, idx}
VEXTRACTF64X4Zrrik [HasAVX512]
vextractf64x4 {idx, src1, dst {mask}|dst {mask}, src1, idx}
|
Note
|
Constraints: src0 = dst |
VEXTRACTF64X4Zrrikz [HasAVX512]
vextractf64x4 {idx, src1, dst {mask} {z}|dst {mask} {z}, src1, idx}
VEXTRACTI32X4Zmri [HasAVX512]
vextracti32x4 {idx, src1, dst|dst, src1, idx}
VEXTRACTI32X4Zmrik [HasAVX512]
vextracti32x4 {idx, src1, dst {mask}|dst {mask}, src1, idx}
|
Note
|
Properties: mayStore |
VEXTRACTI32X4Zrri [HasAVX512]
vextracti32x4 {idx, src1, dst|dst, src1, idx}
VEXTRACTI32X4Zrrik [HasAVX512]
vextracti32x4 {idx, src1, dst {mask}|dst {mask}, src1, idx}
|
Note
|
Constraints: src0 = dst |
VEXTRACTI32X4Zrrikz [HasAVX512]
vextracti32x4 {idx, src1, dst {mask} {z}|dst {mask} {z}, src1, idx}
VEXTRACTI64X4Zmri [HasAVX512]
vextracti64x4 {idx, src1, dst|dst, src1, idx}
VEXTRACTI64X4Zmrik [HasAVX512]
vextracti64x4 {idx, src1, dst {mask}|dst {mask}, src1, idx}
|
Note
|
Properties: mayStore |
VEXTRACTI64X4Zrri [HasAVX512]
vextracti64x4 {idx, src1, dst|dst, src1, idx}
VEXTRACTI64X4Zrrik [HasAVX512]
vextracti64x4 {idx, src1, dst {mask}|dst {mask}, src1, idx}
|
Note
|
Constraints: src0 = dst |
VEXTRACTI64X4Zrrikz [HasAVX512]
vextracti64x4 {idx, src1, dst {mask} {z}|dst {mask} {z}, src1, idx}
VEXTRACTPSZmri [HasAVX512]
vextractps {src2, src1, dst|dst, src1, src2}
VEXTRACTPSZrri [HasAVX512]
vextractps {src2, src1, dst|dst, src1, src2}
VFIXUPIMMPDZrmbi [HasAVX512]
vfixupimmpd {src4, src3{1to8}, src2, dst|dst, src2, src3{1to8}, src4}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMPDZrmbik [HasAVX512]
vfixupimmpd {src4, src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}, src4}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMPDZrmbikz [HasAVX512]
vfixupimmpd {src4, src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}, src4}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMPDZrmi [HasAVX512]
vfixupimmpd {src4, src3, src2, dst|dst, src2, src3, src4}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMPDZrmik [HasAVX512]
vfixupimmpd {src4, src3, src2, dst {mask}|dst {mask}, src2, src3, src4}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMPDZrmikz [HasAVX512]
vfixupimmpd {src4, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, src4}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMPDZrri [HasAVX512]
vfixupimmpd {src4, src3, src2, dst|dst, src2, src3, src4}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMPDZrrib [HasAVX512]
vfixupimmpd {src4, {sae}, src3, src2, dst|dst, src2, src3, {sae}, src4}
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMPDZrribk [HasAVX512]
vfixupimmpd {src4, {sae}, src3, src2, dst {mask}|dst {mask}, src2, src3, {sae}, src4}
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMPDZrribkz [HasAVX512]
vfixupimmpd {src4, {sae}, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, {sae}, src4}
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMPDZrrik [HasAVX512]
vfixupimmpd {src4, src3, src2, dst {mask}|dst {mask}, src2, src3, src4}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMPDZrrikz [HasAVX512]
vfixupimmpd {src4, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, src4}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMPSZrmbi [HasAVX512]
vfixupimmps {src4, src3{1to16}, src2, dst|dst, src2, src3{1to16}, src4}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMPSZrmbik [HasAVX512]
vfixupimmps {src4, src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}, src4}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMPSZrmbikz [HasAVX512]
vfixupimmps {src4, src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}, src4}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMPSZrmi [HasAVX512]
vfixupimmps {src4, src3, src2, dst|dst, src2, src3, src4}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMPSZrmik [HasAVX512]
vfixupimmps {src4, src3, src2, dst {mask}|dst {mask}, src2, src3, src4}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMPSZrmikz [HasAVX512]
vfixupimmps {src4, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, src4}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMPSZrri [HasAVX512]
vfixupimmps {src4, src3, src2, dst|dst, src2, src3, src4}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMPSZrrib [HasAVX512]
vfixupimmps {src4, {sae}, src3, src2, dst|dst, src2, src3, {sae}, src4}
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMPSZrribk [HasAVX512]
vfixupimmps {src4, {sae}, src3, src2, dst {mask}|dst {mask}, src2, src3, {sae}, src4}
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMPSZrribkz [HasAVX512]
vfixupimmps {src4, {sae}, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, {sae}, src4}
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMPSZrrik [HasAVX512]
vfixupimmps {src4, src3, src2, dst {mask}|dst {mask}, src2, src3, src4}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMPSZrrikz [HasAVX512]
vfixupimmps {src4, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, src4}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMSDZrmi [HasAVX512]
vfixupimmsd {src4, src3, src2, dst|dst, src2, src3, src4}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMSDZrmik [HasAVX512]
vfixupimmsd {src4, src3, src2, dst {mask}|dst {mask}, src2, src3, src4}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMSDZrmikz [HasAVX512]
vfixupimmsd {src4, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, src4}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMSDZrri [HasAVX512]
vfixupimmsd {src4, src3, src2, dst|dst, src2, src3, src4}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMSDZrrib [HasAVX512]
vfixupimmsd {src4, {sae}, src3, src2, dst|dst, src2, src3, {sae}, src4}
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMSDZrribk [HasAVX512]
vfixupimmsd {src4, {sae}, src3, src2, dst {mask}|dst {mask}, src2, src3, {sae}, src4}
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMSDZrribkz [HasAVX512]
vfixupimmsd {src4, {sae}, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, {sae}, src4}
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMSDZrrik [HasAVX512]
vfixupimmsd {src4, src3, src2, dst {mask}|dst {mask}, src2, src3, src4}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMSDZrrikz [HasAVX512]
vfixupimmsd {src4, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, src4}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMSSZrmi [HasAVX512]
vfixupimmss {src4, src3, src2, dst|dst, src2, src3, src4}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMSSZrmik [HasAVX512]
vfixupimmss {src4, src3, src2, dst {mask}|dst {mask}, src2, src3, src4}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMSSZrmikz [HasAVX512]
vfixupimmss {src4, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, src4}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMSSZrri [HasAVX512]
vfixupimmss {src4, src3, src2, dst|dst, src2, src3, src4}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMSSZrrib [HasAVX512]
vfixupimmss {src4, {sae}, src3, src2, dst|dst, src2, src3, {sae}, src4}
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMSSZrribk [HasAVX512]
vfixupimmss {src4, {sae}, src3, src2, dst {mask}|dst {mask}, src2, src3, {sae}, src4}
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMSSZrribkz [HasAVX512]
vfixupimmss {src4, {sae}, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, {sae}, src4}
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMSSZrrik [HasAVX512]
vfixupimmss {src4, src3, src2, dst {mask}|dst {mask}, src2, src3, src4}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFIXUPIMMSSZrrikz [HasAVX512]
vfixupimmss {src4, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, src4}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PDZm [HasAVX512]
vfmadd132pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PDZmb [HasAVX512]
vfmadd132pd {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PDZmbk [HasAVX512]
vfmadd132pd {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PDZmbkz [HasAVX512]
vfmadd132pd {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PDZmk [HasAVX512]
vfmadd132pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PDZmkz [HasAVX512]
vfmadd132pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PDZr [HasAVX512]
vfmadd132pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PDZrb [HasAVX512]
vfmadd132pd {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADD132PDZrbk [HasAVX512]
vfmadd132pd {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADD132PDZrbkz [HasAVX512]
vfmadd132pd {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADD132PDZrk [HasAVX512]
vfmadd132pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PDZrkz [HasAVX512]
vfmadd132pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PSZm [HasAVX512]
vfmadd132ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PSZmb [HasAVX512]
vfmadd132ps {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PSZmbk [HasAVX512]
vfmadd132ps {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PSZmbkz [HasAVX512]
vfmadd132ps {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PSZmk [HasAVX512]
vfmadd132ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PSZmkz [HasAVX512]
vfmadd132ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PSZr [HasAVX512]
vfmadd132ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PSZrb [HasAVX512]
vfmadd132ps {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADD132PSZrbk [HasAVX512]
vfmadd132ps {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADD132PSZrbkz [HasAVX512]
vfmadd132ps {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADD132PSZrk [HasAVX512]
vfmadd132ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PSZrkz [HasAVX512]
vfmadd132ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132SDZm_Int [HasAVX512]
vfmadd132sd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132SDZmk_Int [HasAVX512]
vfmadd132sd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132SDZmkz_Int [HasAVX512]
vfmadd132sd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132SDZr_Int [HasAVX512]
vfmadd132sd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132SDZrb_Int [HasAVX512]
vfmadd132sd {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADD132SDZrbk_Int [HasAVX512]
vfmadd132sd {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADD132SDZrbkz_Int [HasAVX512]
vfmadd132sd {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADD132SDZrk_Int [HasAVX512]
vfmadd132sd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132SDZrkz_Int [HasAVX512]
vfmadd132sd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132SSZm_Int [HasAVX512]
vfmadd132ss {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132SSZmk_Int [HasAVX512]
vfmadd132ss {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132SSZmkz_Int [HasAVX512]
vfmadd132ss {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132SSZr_Int [HasAVX512]
vfmadd132ss {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132SSZrb_Int [HasAVX512]
vfmadd132ss {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADD132SSZrbk_Int [HasAVX512]
vfmadd132ss {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADD132SSZrbkz_Int [HasAVX512]
vfmadd132ss {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADD132SSZrk_Int [HasAVX512]
vfmadd132ss {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132SSZrkz_Int [HasAVX512]
vfmadd132ss {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PDZm [HasAVX512]
vfmadd213pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PDZmb [HasAVX512]
vfmadd213pd {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PDZmbk [HasAVX512]
vfmadd213pd {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PDZmbkz [HasAVX512]
vfmadd213pd {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PDZmk [HasAVX512]
vfmadd213pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PDZmkz [HasAVX512]
vfmadd213pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PDZr [HasAVX512]
vfmadd213pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PDZrb [HasAVX512]
vfmadd213pd {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADD213PDZrbk [HasAVX512]
vfmadd213pd {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADD213PDZrbkz [HasAVX512]
vfmadd213pd {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADD213PDZrk [HasAVX512]
vfmadd213pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PDZrkz [HasAVX512]
vfmadd213pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PSZm [HasAVX512]
vfmadd213ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PSZmb [HasAVX512]
vfmadd213ps {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PSZmbk [HasAVX512]
vfmadd213ps {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PSZmbkz [HasAVX512]
vfmadd213ps {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PSZmk [HasAVX512]
vfmadd213ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PSZmkz [HasAVX512]
vfmadd213ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PSZr [HasAVX512]
vfmadd213ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PSZrb [HasAVX512]
vfmadd213ps {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADD213PSZrbk [HasAVX512]
vfmadd213ps {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADD213PSZrbkz [HasAVX512]
vfmadd213ps {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADD213PSZrk [HasAVX512]
vfmadd213ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PSZrkz [HasAVX512]
vfmadd213ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213SDZm_Int [HasAVX512]
vfmadd213sd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213SDZmk_Int [HasAVX512]
vfmadd213sd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213SDZmkz_Int [HasAVX512]
vfmadd213sd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213SDZr_Int [HasAVX512]
vfmadd213sd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213SDZrb_Int [HasAVX512]
vfmadd213sd {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADD213SDZrbk_Int [HasAVX512]
vfmadd213sd {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADD213SDZrbkz_Int [HasAVX512]
vfmadd213sd {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADD213SDZrk_Int [HasAVX512]
vfmadd213sd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213SDZrkz_Int [HasAVX512]
vfmadd213sd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213SSZm_Int [HasAVX512]
vfmadd213ss {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213SSZmk_Int [HasAVX512]
vfmadd213ss {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213SSZmkz_Int [HasAVX512]
vfmadd213ss {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213SSZr_Int [HasAVX512]
vfmadd213ss {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213SSZrb_Int [HasAVX512]
vfmadd213ss {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADD213SSZrbk_Int [HasAVX512]
vfmadd213ss {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADD213SSZrbkz_Int [HasAVX512]
vfmadd213ss {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADD213SSZrk_Int [HasAVX512]
vfmadd213ss {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213SSZrkz_Int [HasAVX512]
vfmadd213ss {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PDZm [HasAVX512]
vfmadd231pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PDZmb [HasAVX512]
vfmadd231pd {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PDZmbk [HasAVX512]
vfmadd231pd {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PDZmbkz [HasAVX512]
vfmadd231pd {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PDZmk [HasAVX512]
vfmadd231pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PDZmkz [HasAVX512]
vfmadd231pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PDZr [HasAVX512]
vfmadd231pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PDZrb [HasAVX512]
vfmadd231pd {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADD231PDZrbk [HasAVX512]
vfmadd231pd {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADD231PDZrbkz [HasAVX512]
vfmadd231pd {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADD231PDZrk [HasAVX512]
vfmadd231pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PDZrkz [HasAVX512]
vfmadd231pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PSZm [HasAVX512]
vfmadd231ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PSZmb [HasAVX512]
vfmadd231ps {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PSZmbk [HasAVX512]
vfmadd231ps {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PSZmbkz [HasAVX512]
vfmadd231ps {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PSZmk [HasAVX512]
vfmadd231ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PSZmkz [HasAVX512]
vfmadd231ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PSZr [HasAVX512]
vfmadd231ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PSZrb [HasAVX512]
vfmadd231ps {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADD231PSZrbk [HasAVX512]
vfmadd231ps {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADD231PSZrbkz [HasAVX512]
vfmadd231ps {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADD231PSZrk [HasAVX512]
vfmadd231ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PSZrkz [HasAVX512]
vfmadd231ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231SDZm_Int [HasAVX512]
vfmadd231sd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231SDZmk_Int [HasAVX512]
vfmadd231sd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231SDZmkz_Int [HasAVX512]
vfmadd231sd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231SDZr_Int [HasAVX512]
vfmadd231sd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231SDZrb_Int [HasAVX512]
vfmadd231sd {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADD231SDZrbk_Int [HasAVX512]
vfmadd231sd {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADD231SDZrbkz_Int [HasAVX512]
vfmadd231sd {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADD231SDZrk_Int [HasAVX512]
vfmadd231sd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231SDZrkz_Int [HasAVX512]
vfmadd231sd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231SSZm_Int [HasAVX512]
vfmadd231ss {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231SSZmk_Int [HasAVX512]
vfmadd231ss {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231SSZmkz_Int [HasAVX512]
vfmadd231ss {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231SSZr_Int [HasAVX512]
vfmadd231ss {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231SSZrb_Int [HasAVX512]
vfmadd231ss {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADD231SSZrbk_Int [HasAVX512]
vfmadd231ss {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADD231SSZrbkz_Int [HasAVX512]
vfmadd231ss {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADD231SSZrk_Int [HasAVX512]
vfmadd231ss {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231SSZrkz_Int [HasAVX512]
vfmadd231ss {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PDZm [HasAVX512]
vfmaddsub132pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PDZmb [HasAVX512]
vfmaddsub132pd {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PDZmbk [HasAVX512]
vfmaddsub132pd {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PDZmbkz [HasAVX512]
vfmaddsub132pd {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PDZmk [HasAVX512]
vfmaddsub132pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PDZmkz [HasAVX512]
vfmaddsub132pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PDZr [HasAVX512]
vfmaddsub132pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PDZrb [HasAVX512]
vfmaddsub132pd {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PDZrbk [HasAVX512]
vfmaddsub132pd {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PDZrbkz [HasAVX512]
vfmaddsub132pd {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PDZrk [HasAVX512]
vfmaddsub132pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PDZrkz [HasAVX512]
vfmaddsub132pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PSZm [HasAVX512]
vfmaddsub132ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PSZmb [HasAVX512]
vfmaddsub132ps {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PSZmbk [HasAVX512]
vfmaddsub132ps {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PSZmbkz [HasAVX512]
vfmaddsub132ps {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PSZmk [HasAVX512]
vfmaddsub132ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PSZmkz [HasAVX512]
vfmaddsub132ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PSZr [HasAVX512]
vfmaddsub132ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PSZrb [HasAVX512]
vfmaddsub132ps {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PSZrbk [HasAVX512]
vfmaddsub132ps {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PSZrbkz [HasAVX512]
vfmaddsub132ps {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PSZrk [HasAVX512]
vfmaddsub132ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PSZrkz [HasAVX512]
vfmaddsub132ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PDZm [HasAVX512]
vfmaddsub213pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PDZmb [HasAVX512]
vfmaddsub213pd {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PDZmbk [HasAVX512]
vfmaddsub213pd {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PDZmbkz [HasAVX512]
vfmaddsub213pd {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PDZmk [HasAVX512]
vfmaddsub213pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PDZmkz [HasAVX512]
vfmaddsub213pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PDZr [HasAVX512]
vfmaddsub213pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PDZrb [HasAVX512]
vfmaddsub213pd {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PDZrbk [HasAVX512]
vfmaddsub213pd {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PDZrbkz [HasAVX512]
vfmaddsub213pd {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PDZrk [HasAVX512]
vfmaddsub213pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PDZrkz [HasAVX512]
vfmaddsub213pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PSZm [HasAVX512]
vfmaddsub213ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PSZmb [HasAVX512]
vfmaddsub213ps {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PSZmbk [HasAVX512]
vfmaddsub213ps {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PSZmbkz [HasAVX512]
vfmaddsub213ps {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PSZmk [HasAVX512]
vfmaddsub213ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PSZmkz [HasAVX512]
vfmaddsub213ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PSZr [HasAVX512]
vfmaddsub213ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PSZrb [HasAVX512]
vfmaddsub213ps {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PSZrbk [HasAVX512]
vfmaddsub213ps {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PSZrbkz [HasAVX512]
vfmaddsub213ps {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PSZrk [HasAVX512]
vfmaddsub213ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PSZrkz [HasAVX512]
vfmaddsub213ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PDZm [HasAVX512]
vfmaddsub231pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PDZmb [HasAVX512]
vfmaddsub231pd {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PDZmbk [HasAVX512]
vfmaddsub231pd {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PDZmbkz [HasAVX512]
vfmaddsub231pd {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PDZmk [HasAVX512]
vfmaddsub231pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PDZmkz [HasAVX512]
vfmaddsub231pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PDZr [HasAVX512]
vfmaddsub231pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PDZrb [HasAVX512]
vfmaddsub231pd {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PDZrbk [HasAVX512]
vfmaddsub231pd {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PDZrbkz [HasAVX512]
vfmaddsub231pd {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PDZrk [HasAVX512]
vfmaddsub231pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PDZrkz [HasAVX512]
vfmaddsub231pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PSZm [HasAVX512]
vfmaddsub231ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PSZmb [HasAVX512]
vfmaddsub231ps {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PSZmbk [HasAVX512]
vfmaddsub231ps {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PSZmbkz [HasAVX512]
vfmaddsub231ps {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PSZmk [HasAVX512]
vfmaddsub231ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PSZmkz [HasAVX512]
vfmaddsub231ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PSZr [HasAVX512]
vfmaddsub231ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PSZrb [HasAVX512]
vfmaddsub231ps {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PSZrbk [HasAVX512]
vfmaddsub231ps {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PSZrbkz [HasAVX512]
vfmaddsub231ps {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PSZrk [HasAVX512]
vfmaddsub231ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PSZrkz [HasAVX512]
vfmaddsub231ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PDZm [HasAVX512]
vfmsub132pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PDZmb [HasAVX512]
vfmsub132pd {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PDZmbk [HasAVX512]
vfmsub132pd {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PDZmbkz [HasAVX512]
vfmsub132pd {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PDZmk [HasAVX512]
vfmsub132pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PDZmkz [HasAVX512]
vfmsub132pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PDZr [HasAVX512]
vfmsub132pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PDZrb [HasAVX512]
vfmsub132pd {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUB132PDZrbk [HasAVX512]
vfmsub132pd {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUB132PDZrbkz [HasAVX512]
vfmsub132pd {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUB132PDZrk [HasAVX512]
vfmsub132pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PDZrkz [HasAVX512]
vfmsub132pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PSZm [HasAVX512]
vfmsub132ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PSZmb [HasAVX512]
vfmsub132ps {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PSZmbk [HasAVX512]
vfmsub132ps {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PSZmbkz [HasAVX512]
vfmsub132ps {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PSZmk [HasAVX512]
vfmsub132ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PSZmkz [HasAVX512]
vfmsub132ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PSZr [HasAVX512]
vfmsub132ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PSZrb [HasAVX512]
vfmsub132ps {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUB132PSZrbk [HasAVX512]
vfmsub132ps {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUB132PSZrbkz [HasAVX512]
vfmsub132ps {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUB132PSZrk [HasAVX512]
vfmsub132ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PSZrkz [HasAVX512]
vfmsub132ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132SDZm_Int [HasAVX512]
vfmsub132sd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132SDZmk_Int [HasAVX512]
vfmsub132sd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132SDZmkz_Int [HasAVX512]
vfmsub132sd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132SDZr_Int [HasAVX512]
vfmsub132sd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132SDZrb_Int [HasAVX512]
vfmsub132sd {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUB132SDZrbk_Int [HasAVX512]
vfmsub132sd {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUB132SDZrbkz_Int [HasAVX512]
vfmsub132sd {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUB132SDZrk_Int [HasAVX512]
vfmsub132sd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132SDZrkz_Int [HasAVX512]
vfmsub132sd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132SSZm_Int [HasAVX512]
vfmsub132ss {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132SSZmk_Int [HasAVX512]
vfmsub132ss {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132SSZmkz_Int [HasAVX512]
vfmsub132ss {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132SSZr_Int [HasAVX512]
vfmsub132ss {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132SSZrb_Int [HasAVX512]
vfmsub132ss {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUB132SSZrbk_Int [HasAVX512]
vfmsub132ss {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUB132SSZrbkz_Int [HasAVX512]
vfmsub132ss {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUB132SSZrk_Int [HasAVX512]
vfmsub132ss {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132SSZrkz_Int [HasAVX512]
vfmsub132ss {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PDZm [HasAVX512]
vfmsub213pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PDZmb [HasAVX512]
vfmsub213pd {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PDZmbk [HasAVX512]
vfmsub213pd {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PDZmbkz [HasAVX512]
vfmsub213pd {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PDZmk [HasAVX512]
vfmsub213pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PDZmkz [HasAVX512]
vfmsub213pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PDZr [HasAVX512]
vfmsub213pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PDZrb [HasAVX512]
vfmsub213pd {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUB213PDZrbk [HasAVX512]
vfmsub213pd {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUB213PDZrbkz [HasAVX512]
vfmsub213pd {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUB213PDZrk [HasAVX512]
vfmsub213pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PDZrkz [HasAVX512]
vfmsub213pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PSZm [HasAVX512]
vfmsub213ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PSZmb [HasAVX512]
vfmsub213ps {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PSZmbk [HasAVX512]
vfmsub213ps {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PSZmbkz [HasAVX512]
vfmsub213ps {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PSZmk [HasAVX512]
vfmsub213ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PSZmkz [HasAVX512]
vfmsub213ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PSZr [HasAVX512]
vfmsub213ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PSZrb [HasAVX512]
vfmsub213ps {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUB213PSZrbk [HasAVX512]
vfmsub213ps {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUB213PSZrbkz [HasAVX512]
vfmsub213ps {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUB213PSZrk [HasAVX512]
vfmsub213ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PSZrkz [HasAVX512]
vfmsub213ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213SDZm_Int [HasAVX512]
vfmsub213sd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213SDZmk_Int [HasAVX512]
vfmsub213sd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213SDZmkz_Int [HasAVX512]
vfmsub213sd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213SDZr_Int [HasAVX512]
vfmsub213sd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213SDZrb_Int [HasAVX512]
vfmsub213sd {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUB213SDZrbk_Int [HasAVX512]
vfmsub213sd {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUB213SDZrbkz_Int [HasAVX512]
vfmsub213sd {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUB213SDZrk_Int [HasAVX512]
vfmsub213sd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213SDZrkz_Int [HasAVX512]
vfmsub213sd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213SSZm_Int [HasAVX512]
vfmsub213ss {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213SSZmk_Int [HasAVX512]
vfmsub213ss {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213SSZmkz_Int [HasAVX512]
vfmsub213ss {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213SSZr_Int [HasAVX512]
vfmsub213ss {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213SSZrb_Int [HasAVX512]
vfmsub213ss {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUB213SSZrbk_Int [HasAVX512]
vfmsub213ss {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUB213SSZrbkz_Int [HasAVX512]
vfmsub213ss {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUB213SSZrk_Int [HasAVX512]
vfmsub213ss {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213SSZrkz_Int [HasAVX512]
vfmsub213ss {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PDZm [HasAVX512]
vfmsub231pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PDZmb [HasAVX512]
vfmsub231pd {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PDZmbk [HasAVX512]
vfmsub231pd {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PDZmbkz [HasAVX512]
vfmsub231pd {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PDZmk [HasAVX512]
vfmsub231pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PDZmkz [HasAVX512]
vfmsub231pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PDZr [HasAVX512]
vfmsub231pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PDZrb [HasAVX512]
vfmsub231pd {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUB231PDZrbk [HasAVX512]
vfmsub231pd {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUB231PDZrbkz [HasAVX512]
vfmsub231pd {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUB231PDZrk [HasAVX512]
vfmsub231pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PDZrkz [HasAVX512]
vfmsub231pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PSZm [HasAVX512]
vfmsub231ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PSZmb [HasAVX512]
vfmsub231ps {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PSZmbk [HasAVX512]
vfmsub231ps {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PSZmbkz [HasAVX512]
vfmsub231ps {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PSZmk [HasAVX512]
vfmsub231ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PSZmkz [HasAVX512]
vfmsub231ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PSZr [HasAVX512]
vfmsub231ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PSZrb [HasAVX512]
vfmsub231ps {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUB231PSZrbk [HasAVX512]
vfmsub231ps {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUB231PSZrbkz [HasAVX512]
vfmsub231ps {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUB231PSZrk [HasAVX512]
vfmsub231ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PSZrkz [HasAVX512]
vfmsub231ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231SDZm_Int [HasAVX512]
vfmsub231sd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231SDZmk_Int [HasAVX512]
vfmsub231sd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231SDZmkz_Int [HasAVX512]
vfmsub231sd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231SDZr_Int [HasAVX512]
vfmsub231sd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231SDZrb_Int [HasAVX512]
vfmsub231sd {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUB231SDZrbk_Int [HasAVX512]
vfmsub231sd {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUB231SDZrbkz_Int [HasAVX512]
vfmsub231sd {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUB231SDZrk_Int [HasAVX512]
vfmsub231sd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231SDZrkz_Int [HasAVX512]
vfmsub231sd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231SSZm_Int [HasAVX512]
vfmsub231ss {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231SSZmk_Int [HasAVX512]
vfmsub231ss {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231SSZmkz_Int [HasAVX512]
vfmsub231ss {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231SSZr_Int [HasAVX512]
vfmsub231ss {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231SSZrb_Int [HasAVX512]
vfmsub231ss {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUB231SSZrbk_Int [HasAVX512]
vfmsub231ss {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUB231SSZrbkz_Int [HasAVX512]
vfmsub231ss {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUB231SSZrk_Int [HasAVX512]
vfmsub231ss {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231SSZrkz_Int [HasAVX512]
vfmsub231ss {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PDZm [HasAVX512]
vfmsubadd132pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PDZmb [HasAVX512]
vfmsubadd132pd {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PDZmbk [HasAVX512]
vfmsubadd132pd {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PDZmbkz [HasAVX512]
vfmsubadd132pd {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PDZmk [HasAVX512]
vfmsubadd132pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PDZmkz [HasAVX512]
vfmsubadd132pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PDZr [HasAVX512]
vfmsubadd132pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PDZrb [HasAVX512]
vfmsubadd132pd {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PDZrbk [HasAVX512]
vfmsubadd132pd {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PDZrbkz [HasAVX512]
vfmsubadd132pd {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PDZrk [HasAVX512]
vfmsubadd132pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PDZrkz [HasAVX512]
vfmsubadd132pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PSZm [HasAVX512]
vfmsubadd132ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PSZmb [HasAVX512]
vfmsubadd132ps {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PSZmbk [HasAVX512]
vfmsubadd132ps {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PSZmbkz [HasAVX512]
vfmsubadd132ps {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PSZmk [HasAVX512]
vfmsubadd132ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PSZmkz [HasAVX512]
vfmsubadd132ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PSZr [HasAVX512]
vfmsubadd132ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PSZrb [HasAVX512]
vfmsubadd132ps {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PSZrbk [HasAVX512]
vfmsubadd132ps {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PSZrbkz [HasAVX512]
vfmsubadd132ps {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PSZrk [HasAVX512]
vfmsubadd132ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PSZrkz [HasAVX512]
vfmsubadd132ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PDZm [HasAVX512]
vfmsubadd213pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PDZmb [HasAVX512]
vfmsubadd213pd {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PDZmbk [HasAVX512]
vfmsubadd213pd {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PDZmbkz [HasAVX512]
vfmsubadd213pd {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PDZmk [HasAVX512]
vfmsubadd213pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PDZmkz [HasAVX512]
vfmsubadd213pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PDZr [HasAVX512]
vfmsubadd213pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PDZrb [HasAVX512]
vfmsubadd213pd {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PDZrbk [HasAVX512]
vfmsubadd213pd {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PDZrbkz [HasAVX512]
vfmsubadd213pd {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PDZrk [HasAVX512]
vfmsubadd213pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PDZrkz [HasAVX512]
vfmsubadd213pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PSZm [HasAVX512]
vfmsubadd213ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PSZmb [HasAVX512]
vfmsubadd213ps {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PSZmbk [HasAVX512]
vfmsubadd213ps {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PSZmbkz [HasAVX512]
vfmsubadd213ps {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PSZmk [HasAVX512]
vfmsubadd213ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PSZmkz [HasAVX512]
vfmsubadd213ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PSZr [HasAVX512]
vfmsubadd213ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PSZrb [HasAVX512]
vfmsubadd213ps {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PSZrbk [HasAVX512]
vfmsubadd213ps {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PSZrbkz [HasAVX512]
vfmsubadd213ps {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PSZrk [HasAVX512]
vfmsubadd213ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PSZrkz [HasAVX512]
vfmsubadd213ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PDZm [HasAVX512]
vfmsubadd231pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PDZmb [HasAVX512]
vfmsubadd231pd {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PDZmbk [HasAVX512]
vfmsubadd231pd {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PDZmbkz [HasAVX512]
vfmsubadd231pd {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PDZmk [HasAVX512]
vfmsubadd231pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PDZmkz [HasAVX512]
vfmsubadd231pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PDZr [HasAVX512]
vfmsubadd231pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PDZrb [HasAVX512]
vfmsubadd231pd {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PDZrbk [HasAVX512]
vfmsubadd231pd {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PDZrbkz [HasAVX512]
vfmsubadd231pd {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PDZrk [HasAVX512]
vfmsubadd231pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PDZrkz [HasAVX512]
vfmsubadd231pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PSZm [HasAVX512]
vfmsubadd231ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PSZmb [HasAVX512]
vfmsubadd231ps {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PSZmbk [HasAVX512]
vfmsubadd231ps {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PSZmbkz [HasAVX512]
vfmsubadd231ps {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PSZmk [HasAVX512]
vfmsubadd231ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PSZmkz [HasAVX512]
vfmsubadd231ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PSZr [HasAVX512]
vfmsubadd231ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PSZrb [HasAVX512]
vfmsubadd231ps {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PSZrbk [HasAVX512]
vfmsubadd231ps {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PSZrbkz [HasAVX512]
vfmsubadd231ps {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PSZrk [HasAVX512]
vfmsubadd231ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PSZrkz [HasAVX512]
vfmsubadd231ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PDZm [HasAVX512]
vfnmadd132pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PDZmb [HasAVX512]
vfnmadd132pd {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PDZmbk [HasAVX512]
vfnmadd132pd {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PDZmbkz [HasAVX512]
vfnmadd132pd {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PDZmk [HasAVX512]
vfnmadd132pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PDZmkz [HasAVX512]
vfnmadd132pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PDZr [HasAVX512]
vfnmadd132pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PDZrb [HasAVX512]
vfnmadd132pd {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMADD132PDZrbk [HasAVX512]
vfnmadd132pd {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMADD132PDZrbkz [HasAVX512]
vfnmadd132pd {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMADD132PDZrk [HasAVX512]
vfnmadd132pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PDZrkz [HasAVX512]
vfnmadd132pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PSZm [HasAVX512]
vfnmadd132ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PSZmb [HasAVX512]
vfnmadd132ps {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PSZmbk [HasAVX512]
vfnmadd132ps {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PSZmbkz [HasAVX512]
vfnmadd132ps {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PSZmk [HasAVX512]
vfnmadd132ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PSZmkz [HasAVX512]
vfnmadd132ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PSZr [HasAVX512]
vfnmadd132ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PSZrb [HasAVX512]
vfnmadd132ps {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMADD132PSZrbk [HasAVX512]
vfnmadd132ps {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMADD132PSZrbkz [HasAVX512]
vfnmadd132ps {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMADD132PSZrk [HasAVX512]
vfnmadd132ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PSZrkz [HasAVX512]
vfnmadd132ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132SDZm_Int [HasAVX512]
vfnmadd132sd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132SDZmk_Int [HasAVX512]
vfnmadd132sd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132SDZmkz_Int [HasAVX512]
vfnmadd132sd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132SDZr_Int [HasAVX512]
vfnmadd132sd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132SDZrb_Int [HasAVX512]
vfnmadd132sd {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMADD132SDZrbk_Int [HasAVX512]
vfnmadd132sd {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMADD132SDZrbkz_Int [HasAVX512]
vfnmadd132sd {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMADD132SDZrk_Int [HasAVX512]
vfnmadd132sd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132SDZrkz_Int [HasAVX512]
vfnmadd132sd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132SSZm_Int [HasAVX512]
vfnmadd132ss {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132SSZmk_Int [HasAVX512]
vfnmadd132ss {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132SSZmkz_Int [HasAVX512]
vfnmadd132ss {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132SSZr_Int [HasAVX512]
vfnmadd132ss {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132SSZrb_Int [HasAVX512]
vfnmadd132ss {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMADD132SSZrbk_Int [HasAVX512]
vfnmadd132ss {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMADD132SSZrbkz_Int [HasAVX512]
vfnmadd132ss {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMADD132SSZrk_Int [HasAVX512]
vfnmadd132ss {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132SSZrkz_Int [HasAVX512]
vfnmadd132ss {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PDZm [HasAVX512]
vfnmadd213pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PDZmb [HasAVX512]
vfnmadd213pd {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PDZmbk [HasAVX512]
vfnmadd213pd {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PDZmbkz [HasAVX512]
vfnmadd213pd {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PDZmk [HasAVX512]
vfnmadd213pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PDZmkz [HasAVX512]
vfnmadd213pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PDZr [HasAVX512]
vfnmadd213pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PDZrb [HasAVX512]
vfnmadd213pd {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMADD213PDZrbk [HasAVX512]
vfnmadd213pd {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMADD213PDZrbkz [HasAVX512]
vfnmadd213pd {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMADD213PDZrk [HasAVX512]
vfnmadd213pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PDZrkz [HasAVX512]
vfnmadd213pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PSZm [HasAVX512]
vfnmadd213ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PSZmb [HasAVX512]
vfnmadd213ps {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PSZmbk [HasAVX512]
vfnmadd213ps {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PSZmbkz [HasAVX512]
vfnmadd213ps {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PSZmk [HasAVX512]
vfnmadd213ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PSZmkz [HasAVX512]
vfnmadd213ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PSZr [HasAVX512]
vfnmadd213ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PSZrb [HasAVX512]
vfnmadd213ps {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMADD213PSZrbk [HasAVX512]
vfnmadd213ps {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMADD213PSZrbkz [HasAVX512]
vfnmadd213ps {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMADD213PSZrk [HasAVX512]
vfnmadd213ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PSZrkz [HasAVX512]
vfnmadd213ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213SDZm_Int [HasAVX512]
vfnmadd213sd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213SDZmk_Int [HasAVX512]
vfnmadd213sd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213SDZmkz_Int [HasAVX512]
vfnmadd213sd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213SDZr_Int [HasAVX512]
vfnmadd213sd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213SDZrb_Int [HasAVX512]
vfnmadd213sd {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMADD213SDZrbk_Int [HasAVX512]
vfnmadd213sd {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMADD213SDZrbkz_Int [HasAVX512]
vfnmadd213sd {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMADD213SDZrk_Int [HasAVX512]
vfnmadd213sd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213SDZrkz_Int [HasAVX512]
vfnmadd213sd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213SSZm_Int [HasAVX512]
vfnmadd213ss {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213SSZmk_Int [HasAVX512]
vfnmadd213ss {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213SSZmkz_Int [HasAVX512]
vfnmadd213ss {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213SSZr_Int [HasAVX512]
vfnmadd213ss {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213SSZrb_Int [HasAVX512]
vfnmadd213ss {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMADD213SSZrbk_Int [HasAVX512]
vfnmadd213ss {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMADD213SSZrbkz_Int [HasAVX512]
vfnmadd213ss {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMADD213SSZrk_Int [HasAVX512]
vfnmadd213ss {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213SSZrkz_Int [HasAVX512]
vfnmadd213ss {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PDZm [HasAVX512]
vfnmadd231pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PDZmb [HasAVX512]
vfnmadd231pd {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PDZmbk [HasAVX512]
vfnmadd231pd {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PDZmbkz [HasAVX512]
vfnmadd231pd {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PDZmk [HasAVX512]
vfnmadd231pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PDZmkz [HasAVX512]
vfnmadd231pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PDZr [HasAVX512]
vfnmadd231pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PDZrb [HasAVX512]
vfnmadd231pd {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMADD231PDZrbk [HasAVX512]
vfnmadd231pd {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMADD231PDZrbkz [HasAVX512]
vfnmadd231pd {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMADD231PDZrk [HasAVX512]
vfnmadd231pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PDZrkz [HasAVX512]
vfnmadd231pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PSZm [HasAVX512]
vfnmadd231ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PSZmb [HasAVX512]
vfnmadd231ps {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PSZmbk [HasAVX512]
vfnmadd231ps {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PSZmbkz [HasAVX512]
vfnmadd231ps {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PSZmk [HasAVX512]
vfnmadd231ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PSZmkz [HasAVX512]
vfnmadd231ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PSZr [HasAVX512]
vfnmadd231ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PSZrb [HasAVX512]
vfnmadd231ps {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMADD231PSZrbk [HasAVX512]
vfnmadd231ps {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMADD231PSZrbkz [HasAVX512]
vfnmadd231ps {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMADD231PSZrk [HasAVX512]
vfnmadd231ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PSZrkz [HasAVX512]
vfnmadd231ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231SDZm_Int [HasAVX512]
vfnmadd231sd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231SDZmk_Int [HasAVX512]
vfnmadd231sd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231SDZmkz_Int [HasAVX512]
vfnmadd231sd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231SDZr_Int [HasAVX512]
vfnmadd231sd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231SDZrb_Int [HasAVX512]
vfnmadd231sd {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMADD231SDZrbk_Int [HasAVX512]
vfnmadd231sd {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMADD231SDZrbkz_Int [HasAVX512]
vfnmadd231sd {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMADD231SDZrk_Int [HasAVX512]
vfnmadd231sd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231SDZrkz_Int [HasAVX512]
vfnmadd231sd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231SSZm_Int [HasAVX512]
vfnmadd231ss {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231SSZmk_Int [HasAVX512]
vfnmadd231ss {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231SSZmkz_Int [HasAVX512]
vfnmadd231ss {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231SSZr_Int [HasAVX512]
vfnmadd231ss {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231SSZrb_Int [HasAVX512]
vfnmadd231ss {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMADD231SSZrbk_Int [HasAVX512]
vfnmadd231ss {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMADD231SSZrbkz_Int [HasAVX512]
vfnmadd231ss {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMADD231SSZrk_Int [HasAVX512]
vfnmadd231ss {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231SSZrkz_Int [HasAVX512]
vfnmadd231ss {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PDZm [HasAVX512]
vfnmsub132pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PDZmb [HasAVX512]
vfnmsub132pd {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PDZmbk [HasAVX512]
vfnmsub132pd {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PDZmbkz [HasAVX512]
vfnmsub132pd {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PDZmk [HasAVX512]
vfnmsub132pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PDZmkz [HasAVX512]
vfnmsub132pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PDZr [HasAVX512]
vfnmsub132pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PDZrb [HasAVX512]
vfnmsub132pd {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PDZrbk [HasAVX512]
vfnmsub132pd {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PDZrbkz [HasAVX512]
vfnmsub132pd {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PDZrk [HasAVX512]
vfnmsub132pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PDZrkz [HasAVX512]
vfnmsub132pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PSZm [HasAVX512]
vfnmsub132ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PSZmb [HasAVX512]
vfnmsub132ps {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PSZmbk [HasAVX512]
vfnmsub132ps {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PSZmbkz [HasAVX512]
vfnmsub132ps {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PSZmk [HasAVX512]
vfnmsub132ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PSZmkz [HasAVX512]
vfnmsub132ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PSZr [HasAVX512]
vfnmsub132ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PSZrb [HasAVX512]
vfnmsub132ps {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PSZrbk [HasAVX512]
vfnmsub132ps {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PSZrbkz [HasAVX512]
vfnmsub132ps {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PSZrk [HasAVX512]
vfnmsub132ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PSZrkz [HasAVX512]
vfnmsub132ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132SDZm_Int [HasAVX512]
vfnmsub132sd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132SDZmk_Int [HasAVX512]
vfnmsub132sd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132SDZmkz_Int [HasAVX512]
vfnmsub132sd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132SDZr_Int [HasAVX512]
vfnmsub132sd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132SDZrb_Int [HasAVX512]
vfnmsub132sd {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMSUB132SDZrbk_Int [HasAVX512]
vfnmsub132sd {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMSUB132SDZrbkz_Int [HasAVX512]
vfnmsub132sd {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMSUB132SDZrk_Int [HasAVX512]
vfnmsub132sd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132SDZrkz_Int [HasAVX512]
vfnmsub132sd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132SSZm_Int [HasAVX512]
vfnmsub132ss {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132SSZmk_Int [HasAVX512]
vfnmsub132ss {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132SSZmkz_Int [HasAVX512]
vfnmsub132ss {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132SSZr_Int [HasAVX512]
vfnmsub132ss {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132SSZrb_Int [HasAVX512]
vfnmsub132ss {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMSUB132SSZrbk_Int [HasAVX512]
vfnmsub132ss {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMSUB132SSZrbkz_Int [HasAVX512]
vfnmsub132ss {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMSUB132SSZrk_Int [HasAVX512]
vfnmsub132ss {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132SSZrkz_Int [HasAVX512]
vfnmsub132ss {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PDZm [HasAVX512]
vfnmsub213pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PDZmb [HasAVX512]
vfnmsub213pd {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PDZmbk [HasAVX512]
vfnmsub213pd {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PDZmbkz [HasAVX512]
vfnmsub213pd {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PDZmk [HasAVX512]
vfnmsub213pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PDZmkz [HasAVX512]
vfnmsub213pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PDZr [HasAVX512]
vfnmsub213pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PDZrb [HasAVX512]
vfnmsub213pd {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PDZrbk [HasAVX512]
vfnmsub213pd {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PDZrbkz [HasAVX512]
vfnmsub213pd {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PDZrk [HasAVX512]
vfnmsub213pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PDZrkz [HasAVX512]
vfnmsub213pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PSZm [HasAVX512]
vfnmsub213ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PSZmb [HasAVX512]
vfnmsub213ps {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PSZmbk [HasAVX512]
vfnmsub213ps {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PSZmbkz [HasAVX512]
vfnmsub213ps {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PSZmk [HasAVX512]
vfnmsub213ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PSZmkz [HasAVX512]
vfnmsub213ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PSZr [HasAVX512]
vfnmsub213ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PSZrb [HasAVX512]
vfnmsub213ps {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PSZrbk [HasAVX512]
vfnmsub213ps {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PSZrbkz [HasAVX512]
vfnmsub213ps {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PSZrk [HasAVX512]
vfnmsub213ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PSZrkz [HasAVX512]
vfnmsub213ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213SDZm_Int [HasAVX512]
vfnmsub213sd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213SDZmk_Int [HasAVX512]
vfnmsub213sd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213SDZmkz_Int [HasAVX512]
vfnmsub213sd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213SDZr_Int [HasAVX512]
vfnmsub213sd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213SDZrb_Int [HasAVX512]
vfnmsub213sd {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMSUB213SDZrbk_Int [HasAVX512]
vfnmsub213sd {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMSUB213SDZrbkz_Int [HasAVX512]
vfnmsub213sd {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMSUB213SDZrk_Int [HasAVX512]
vfnmsub213sd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213SDZrkz_Int [HasAVX512]
vfnmsub213sd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213SSZm_Int [HasAVX512]
vfnmsub213ss {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213SSZmk_Int [HasAVX512]
vfnmsub213ss {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213SSZmkz_Int [HasAVX512]
vfnmsub213ss {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213SSZr_Int [HasAVX512]
vfnmsub213ss {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213SSZrb_Int [HasAVX512]
vfnmsub213ss {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMSUB213SSZrbk_Int [HasAVX512]
vfnmsub213ss {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMSUB213SSZrbkz_Int [HasAVX512]
vfnmsub213ss {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMSUB213SSZrk_Int [HasAVX512]
vfnmsub213ss {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213SSZrkz_Int [HasAVX512]
vfnmsub213ss {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PDZm [HasAVX512]
vfnmsub231pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PDZmb [HasAVX512]
vfnmsub231pd {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PDZmbk [HasAVX512]
vfnmsub231pd {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PDZmbkz [HasAVX512]
vfnmsub231pd {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PDZmk [HasAVX512]
vfnmsub231pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PDZmkz [HasAVX512]
vfnmsub231pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PDZr [HasAVX512]
vfnmsub231pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PDZrb [HasAVX512]
vfnmsub231pd {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PDZrbk [HasAVX512]
vfnmsub231pd {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PDZrbkz [HasAVX512]
vfnmsub231pd {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PDZrk [HasAVX512]
vfnmsub231pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PDZrkz [HasAVX512]
vfnmsub231pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PSZm [HasAVX512]
vfnmsub231ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PSZmb [HasAVX512]
vfnmsub231ps {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PSZmbk [HasAVX512]
vfnmsub231ps {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PSZmbkz [HasAVX512]
vfnmsub231ps {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PSZmk [HasAVX512]
vfnmsub231ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PSZmkz [HasAVX512]
vfnmsub231ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PSZr [HasAVX512]
vfnmsub231ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PSZrb [HasAVX512]
vfnmsub231ps {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PSZrbk [HasAVX512]
vfnmsub231ps {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PSZrbkz [HasAVX512]
vfnmsub231ps {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PSZrk [HasAVX512]
vfnmsub231ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PSZrkz [HasAVX512]
vfnmsub231ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231SDZm_Int [HasAVX512]
vfnmsub231sd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231SDZmk_Int [HasAVX512]
vfnmsub231sd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231SDZmkz_Int [HasAVX512]
vfnmsub231sd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231SDZr_Int [HasAVX512]
vfnmsub231sd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231SDZrb_Int [HasAVX512]
vfnmsub231sd {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMSUB231SDZrbk_Int [HasAVX512]
vfnmsub231sd {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMSUB231SDZrbkz_Int [HasAVX512]
vfnmsub231sd {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMSUB231SDZrk_Int [HasAVX512]
vfnmsub231sd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231SDZrkz_Int [HasAVX512]
vfnmsub231sd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231SSZm_Int [HasAVX512]
vfnmsub231ss {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231SSZmk_Int [HasAVX512]
vfnmsub231ss {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231SSZmkz_Int [HasAVX512]
vfnmsub231ss {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231SSZr_Int [HasAVX512]
vfnmsub231ss {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231SSZrb_Int [HasAVX512]
vfnmsub231ss {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMSUB231SSZrbk_Int [HasAVX512]
vfnmsub231ss {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMSUB231SSZrbkz_Int [HasAVX512]
vfnmsub231ss {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMSUB231SSZrk_Int [HasAVX512]
vfnmsub231ss {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231SSZrkz_Int [HasAVX512]
vfnmsub231ss {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VGATHERDPDZrm [HasAVX512]
vgatherdpd {src2, dst {mask}|dst {mask}, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst, src1 = dst, mask = mask_wb |
VGATHERDPSZrm [HasAVX512]
vgatherdps {src2, dst {mask}|dst {mask}, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst, src1 = dst, mask = mask_wb |
VGATHERPF0DPDm [HasAVX512]
vgatherpf0dpd {src {mask}|{mask}, src}
|
Note
|
Properties: mayLoad, mayStore |
VGATHERPF0DPSm [HasAVX512]
vgatherpf0dps {src {mask}|{mask}, src}
|
Note
|
Properties: mayLoad, mayStore |
VGATHERPF0QPDm [HasAVX512]
vgatherpf0qpd {src {mask}|{mask}, src}
|
Note
|
Properties: mayLoad, mayStore |
VGATHERPF0QPSm [HasAVX512]
vgatherpf0qps {src {mask}|{mask}, src}
|
Note
|
Properties: mayLoad, mayStore |
VGATHERPF1DPDm [HasAVX512]
vgatherpf1dpd {src {mask}|{mask}, src}
|
Note
|
Properties: mayLoad, mayStore |
VGATHERPF1DPSm [HasAVX512]
vgatherpf1dps {src {mask}|{mask}, src}
|
Note
|
Properties: mayLoad, mayStore |
VGATHERPF1QPDm [HasAVX512]
vgatherpf1qpd {src {mask}|{mask}, src}
|
Note
|
Properties: mayLoad, mayStore |
VGATHERPF1QPSm [HasAVX512]
vgatherpf1qps {src {mask}|{mask}, src}
|
Note
|
Properties: mayLoad, mayStore |
VGATHERQPDZrm [HasAVX512]
vgatherqpd {src2, dst {mask}|dst {mask}, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst, src1 = dst, mask = mask_wb |
VGATHERQPSZrm [HasAVX512]
vgatherqps {src2, dst {mask}|dst {mask}, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst, src1 = dst, mask = mask_wb |
VGETEXPPDZm [HasAVX512]
vgetexppd {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VGETEXPPDZmb [HasAVX512]
vgetexppd {src{1to8}, dst|dst, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VGETEXPPDZmbk [HasAVX512]
vgetexppd {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VGETEXPPDZmbkz [HasAVX512]
vgetexppd {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VGETEXPPDZmk [HasAVX512]
vgetexppd {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VGETEXPPDZmkz [HasAVX512]
vgetexppd {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VGETEXPPDZr [HasAVX512]
vgetexppd {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VGETEXPPDZrb [HasAVX512]
vgetexppd {{sae}, src, dst|dst, src, {sae}}
VGETEXPPDZrbk [HasAVX512]
vgetexppd {{sae}, src, dst {mask}|dst {mask}, src, {sae}}
|
Note
|
Constraints: src0 = dst |
VGETEXPPDZrbkz [HasAVX512]
vgetexppd {{sae}, src, dst {mask} {z}|dst {mask} {z}, src, {sae}}
VGETEXPPDZrk [HasAVX512]
vgetexppd {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VGETEXPPDZrkz [HasAVX512]
vgetexppd {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VGETEXPPSZm [HasAVX512]
vgetexpps {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VGETEXPPSZmb [HasAVX512]
vgetexpps {src{1to16}, dst|dst, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
VGETEXPPSZmbk [HasAVX512]
vgetexpps {src{1to16}, dst {mask}|dst {mask}, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VGETEXPPSZmbkz [HasAVX512]
vgetexpps {src{1to16}, dst {mask} {z}|dst {mask} {z}, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
VGETEXPPSZmk [HasAVX512]
vgetexpps {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VGETEXPPSZmkz [HasAVX512]
vgetexpps {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VGETEXPPSZr [HasAVX512]
vgetexpps {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VGETEXPPSZrb [HasAVX512]
vgetexpps {{sae}, src, dst|dst, src, {sae}}
VGETEXPPSZrbk [HasAVX512]
vgetexpps {{sae}, src, dst {mask}|dst {mask}, src, {sae}}
|
Note
|
Constraints: src0 = dst |
VGETEXPPSZrbkz [HasAVX512]
vgetexpps {{sae}, src, dst {mask} {z}|dst {mask} {z}, src, {sae}}
VGETEXPPSZrk [HasAVX512]
vgetexpps {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VGETEXPPSZrkz [HasAVX512]
vgetexpps {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VGETEXPSDZm [HasAVX512]
vgetexpsd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VGETEXPSDZmk [HasAVX512]
vgetexpsd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VGETEXPSDZmkz [HasAVX512]
vgetexpsd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VGETEXPSDZr [HasAVX512]
vgetexpsd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VGETEXPSDZrb [HasAVX512]
vgetexpsd {{sae}, src2, src1, dst|dst, src1, src2, {sae}}
VGETEXPSDZrbk [HasAVX512]
vgetexpsd {{sae}, src2, src1, dst {mask}|dst {mask}, src1, src2, {sae}}
|
Note
|
Constraints: src0 = dst |
VGETEXPSDZrbkz [HasAVX512]
vgetexpsd {{sae}, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, {sae}}
VGETEXPSDZrk [HasAVX512]
vgetexpsd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VGETEXPSDZrkz [HasAVX512]
vgetexpsd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VGETEXPSSZm [HasAVX512]
vgetexpss {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VGETEXPSSZmk [HasAVX512]
vgetexpss {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VGETEXPSSZmkz [HasAVX512]
vgetexpss {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VGETEXPSSZr [HasAVX512]
vgetexpss {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VGETEXPSSZrb [HasAVX512]
vgetexpss {{sae}, src2, src1, dst|dst, src1, src2, {sae}}
VGETEXPSSZrbk [HasAVX512]
vgetexpss {{sae}, src2, src1, dst {mask}|dst {mask}, src1, src2, {sae}}
|
Note
|
Constraints: src0 = dst |
VGETEXPSSZrbkz [HasAVX512]
vgetexpss {{sae}, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, {sae}}
VGETEXPSSZrk [HasAVX512]
vgetexpss {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VGETEXPSSZrkz [HasAVX512]
vgetexpss {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VGETMANTPDZrmbi [HasAVX512]
vgetmantpd {src2, src1{1to8}, dst|dst, src1{1to8}, src2}
|
Note
|
Properties: mayRaiseFPException |
VGETMANTPDZrmbik [HasAVX512]
vgetmantpd {src2, src1{1to8}, dst {mask}|dst {mask}, src1{1to8}, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VGETMANTPDZrmbikz [HasAVX512]
vgetmantpd {src2, src1{1to8}, dst {mask} {z}|dst {mask} {z}, src1{1to8}, src2}
|
Note
|
Properties: mayRaiseFPException |
VGETMANTPDZrmi [HasAVX512]
vgetmantpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VGETMANTPDZrmik [HasAVX512]
vgetmantpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VGETMANTPDZrmikz [HasAVX512]
vgetmantpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VGETMANTPDZrri [HasAVX512]
vgetmantpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VGETMANTPDZrrib [HasAVX512]
vgetmantpd {src2, {sae}, src1, dst|dst, src1, {sae}, src2}
VGETMANTPDZrribk [HasAVX512]
vgetmantpd {src2, {sae}, src1, dst {mask}|dst {mask}, src1, {sae}, src2}
|
Note
|
Constraints: src0 = dst |
VGETMANTPDZrribkz [HasAVX512]
vgetmantpd {src2, {sae}, src1, dst {mask} {z}|dst {mask} {z}, src1, {sae}, src2}
VGETMANTPDZrrik [HasAVX512]
vgetmantpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VGETMANTPDZrrikz [HasAVX512]
vgetmantpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VGETMANTPSZrmbi [HasAVX512]
vgetmantps {src2, src1{1to16}, dst|dst, src1{1to16}, src2}
|
Note
|
Properties: mayRaiseFPException |
VGETMANTPSZrmbik [HasAVX512]
vgetmantps {src2, src1{1to16}, dst {mask}|dst {mask}, src1{1to16}, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VGETMANTPSZrmbikz [HasAVX512]
vgetmantps {src2, src1{1to16}, dst {mask} {z}|dst {mask} {z}, src1{1to16}, src2}
|
Note
|
Properties: mayRaiseFPException |
VGETMANTPSZrmi [HasAVX512]
vgetmantps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VGETMANTPSZrmik [HasAVX512]
vgetmantps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VGETMANTPSZrmikz [HasAVX512]
vgetmantps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VGETMANTPSZrri [HasAVX512]
vgetmantps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VGETMANTPSZrrib [HasAVX512]
vgetmantps {src2, {sae}, src1, dst|dst, src1, {sae}, src2}
VGETMANTPSZrribk [HasAVX512]
vgetmantps {src2, {sae}, src1, dst {mask}|dst {mask}, src1, {sae}, src2}
|
Note
|
Constraints: src0 = dst |
VGETMANTPSZrribkz [HasAVX512]
vgetmantps {src2, {sae}, src1, dst {mask} {z}|dst {mask} {z}, src1, {sae}, src2}
VGETMANTPSZrrik [HasAVX512]
vgetmantps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VGETMANTPSZrrikz [HasAVX512]
vgetmantps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VGETMANTSDZrmi [HasAVX512]
vgetmantsd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VGETMANTSDZrmik [HasAVX512]
vgetmantsd {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VGETMANTSDZrmikz [HasAVX512]
vgetmantsd {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VGETMANTSDZrri [HasAVX512]
vgetmantsd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VGETMANTSDZrrib [HasAVX512]
vgetmantsd {src3, {sae}, src2, src1, dst|dst, src1, src2, {sae}, src3}
VGETMANTSDZrribk [HasAVX512]
vgetmantsd {src3, {sae}, src2, src1, dst {mask}|dst {mask}, src1, src2, {sae}, src3}
|
Note
|
Constraints: src0 = dst |
VGETMANTSDZrribkz [HasAVX512]
vgetmantsd {src3, {sae}, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, {sae}, src3}
VGETMANTSDZrrik [HasAVX512]
vgetmantsd {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VGETMANTSDZrrikz [HasAVX512]
vgetmantsd {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VGETMANTSSZrmi [HasAVX512]
vgetmantss {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VGETMANTSSZrmik [HasAVX512]
vgetmantss {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VGETMANTSSZrmikz [HasAVX512]
vgetmantss {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VGETMANTSSZrri [HasAVX512]
vgetmantss {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VGETMANTSSZrrib [HasAVX512]
vgetmantss {src3, {sae}, src2, src1, dst|dst, src1, src2, {sae}, src3}
VGETMANTSSZrribk [HasAVX512]
vgetmantss {src3, {sae}, src2, src1, dst {mask}|dst {mask}, src1, src2, {sae}, src3}
|
Note
|
Constraints: src0 = dst |
VGETMANTSSZrribkz [HasAVX512]
vgetmantss {src3, {sae}, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, {sae}, src3}
VGETMANTSSZrrik [HasAVX512]
vgetmantss {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VGETMANTSSZrrikz [HasAVX512]
vgetmantss {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VINSERTF32X4Zrmi [HasAVX512]
vinsertf32x4 {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayLoad |
VINSERTF32X4Zrmik [HasAVX512]
vinsertf32x4 {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VINSERTF32X4Zrmikz [HasAVX512]
vinsertf32x4 {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
|
Note
|
Properties: mayLoad |
VINSERTF32X4Zrri [HasAVX512]
vinsertf32x4 {src3, src2, src1, dst|dst, src1, src2, src3}
VINSERTF32X4Zrrik [HasAVX512]
vinsertf32x4 {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VINSERTF32X4Zrrikz [HasAVX512]
vinsertf32x4 {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VINSERTF64X4Zrmi [HasAVX512]
vinsertf64x4 {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayLoad |
VINSERTF64X4Zrmik [HasAVX512]
vinsertf64x4 {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VINSERTF64X4Zrmikz [HasAVX512]
vinsertf64x4 {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
|
Note
|
Properties: mayLoad |
VINSERTF64X4Zrri [HasAVX512]
vinsertf64x4 {src3, src2, src1, dst|dst, src1, src2, src3}
VINSERTF64X4Zrrik [HasAVX512]
vinsertf64x4 {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VINSERTF64X4Zrrikz [HasAVX512]
vinsertf64x4 {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VINSERTI32X4Zrmi [HasAVX512]
vinserti32x4 {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayLoad |
VINSERTI32X4Zrmik [HasAVX512]
vinserti32x4 {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VINSERTI32X4Zrmikz [HasAVX512]
vinserti32x4 {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
|
Note
|
Properties: mayLoad |
VINSERTI32X4Zrri [HasAVX512]
vinserti32x4 {src3, src2, src1, dst|dst, src1, src2, src3}
VINSERTI32X4Zrrik [HasAVX512]
vinserti32x4 {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VINSERTI32X4Zrrikz [HasAVX512]
vinserti32x4 {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VINSERTI64X4Zrmi [HasAVX512]
vinserti64x4 {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayLoad |
VINSERTI64X4Zrmik [HasAVX512]
vinserti64x4 {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VINSERTI64X4Zrmikz [HasAVX512]
vinserti64x4 {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
|
Note
|
Properties: mayLoad |
VINSERTI64X4Zrri [HasAVX512]
vinserti64x4 {src3, src2, src1, dst|dst, src1, src2, src3}
VINSERTI64X4Zrrik [HasAVX512]
vinserti64x4 {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VINSERTI64X4Zrrikz [HasAVX512]
vinserti64x4 {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VINSERTPSZrmi [HasAVX512]
vinsertps {src3, src2, src1, dst|dst, src1, src2, src3}
VINSERTPSZrri [HasAVX512]
vinsertps {src3, src2, src1, dst|dst, src1, src2, src3}
VMAXPDZrm [HasAVX512]
vmaxpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMAXPDZrmb [HasAVX512]
vmaxpd {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMAXPDZrmbk [HasAVX512]
vmaxpd {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMAXPDZrmbkz [HasAVX512]
vmaxpd {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMAXPDZrmk [HasAVX512]
vmaxpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMAXPDZrmkz [HasAVX512]
vmaxpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMAXPDZrr [HasAVX512]
vmaxpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMAXPDZrrb [HasAVX512]
vmaxpd {{sae}, src2, src1, dst|dst, src1, src2, {sae}}
VMAXPDZrrbk [HasAVX512]
vmaxpd {{sae}, src2, src1, dst {mask}|dst {mask}, src1, src2, {sae}}
|
Note
|
Constraints: src0 = dst |
VMAXPDZrrbkz [HasAVX512]
vmaxpd {{sae}, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, {sae}}
VMAXPDZrrk [HasAVX512]
vmaxpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMAXPDZrrkz [HasAVX512]
vmaxpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMAXPSZrm [HasAVX512]
vmaxps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMAXPSZrmb [HasAVX512]
vmaxps {src2{1to16}, src1, dst|dst, src1, src2{1to16}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMAXPSZrmbk [HasAVX512]
vmaxps {src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMAXPSZrmbkz [HasAVX512]
vmaxps {src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMAXPSZrmk [HasAVX512]
vmaxps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMAXPSZrmkz [HasAVX512]
vmaxps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMAXPSZrr [HasAVX512]
vmaxps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMAXPSZrrb [HasAVX512]
vmaxps {{sae}, src2, src1, dst|dst, src1, src2, {sae}}
VMAXPSZrrbk [HasAVX512]
vmaxps {{sae}, src2, src1, dst {mask}|dst {mask}, src1, src2, {sae}}
|
Note
|
Constraints: src0 = dst |
VMAXPSZrrbkz [HasAVX512]
vmaxps {{sae}, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, {sae}}
VMAXPSZrrk [HasAVX512]
vmaxps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMAXPSZrrkz [HasAVX512]
vmaxps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMAXSDZrm_Int [HasAVX512]
vmaxsd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMAXSDZrmk_Int [HasAVX512]
vmaxsd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMAXSDZrmkz_Int [HasAVX512]
vmaxsd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMAXSDZrr_Int [HasAVX512]
vmaxsd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMAXSDZrrb_Int [HasAVX512]
vmaxsd {{sae}, src2, src1, dst|dst, src1, src2, {sae}}
VMAXSDZrrbk_Int [HasAVX512]
vmaxsd {{sae}, src2, src1, dst {mask}|dst {mask}, src1, src2, {sae}}
|
Note
|
Constraints: src0 = dst |
VMAXSDZrrbkz_Int [HasAVX512]
vmaxsd {{sae}, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, {sae}}
VMAXSDZrrk_Int [HasAVX512]
vmaxsd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMAXSDZrrkz_Int [HasAVX512]
vmaxsd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMAXSSZrm_Int [HasAVX512]
vmaxss {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMAXSSZrmk_Int [HasAVX512]
vmaxss {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMAXSSZrmkz_Int [HasAVX512]
vmaxss {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMAXSSZrr_Int [HasAVX512]
vmaxss {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMAXSSZrrb_Int [HasAVX512]
vmaxss {{sae}, src2, src1, dst|dst, src1, src2, {sae}}
VMAXSSZrrbk_Int [HasAVX512]
vmaxss {{sae}, src2, src1, dst {mask}|dst {mask}, src1, src2, {sae}}
|
Note
|
Constraints: src0 = dst |
VMAXSSZrrbkz_Int [HasAVX512]
vmaxss {{sae}, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, {sae}}
VMAXSSZrrk_Int [HasAVX512]
vmaxss {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMAXSSZrrkz_Int [HasAVX512]
vmaxss {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMINMAXPDZrrib [HasAVX512]
vminmaxpd {src3, {sae}, src2, src1, dst|dst, src1, src2, {sae}, src3}
VMINMAXPDZrribk [HasAVX512]
vminmaxpd {src3, {sae}, src2, src1, dst {mask}|dst {mask}, src1, src2, {sae}, src3}
|
Note
|
Constraints: src0 = dst |
VMINMAXPDZrribkz [HasAVX512]
vminmaxpd {src3, {sae}, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, {sae}, src3}
VMINMAXPHZrrib [HasAVX512]
vminmaxph {src3, {sae}, src2, src1, dst|dst, src1, src2, {sae}, src3}
VMINMAXPHZrribk [HasAVX512]
vminmaxph {src3, {sae}, src2, src1, dst {mask}|dst {mask}, src1, src2, {sae}, src3}
|
Note
|
Constraints: src0 = dst |
VMINMAXPHZrribkz [HasAVX512]
vminmaxph {src3, {sae}, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, {sae}, src3}
VMINMAXPSZrrib [HasAVX512]
vminmaxps {src3, {sae}, src2, src1, dst|dst, src1, src2, {sae}, src3}
VMINMAXPSZrribk [HasAVX512]
vminmaxps {src3, {sae}, src2, src1, dst {mask}|dst {mask}, src1, src2, {sae}, src3}
|
Note
|
Constraints: src0 = dst |
VMINMAXPSZrribkz [HasAVX512]
vminmaxps {src3, {sae}, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, {sae}, src3}
VMINPDZrm [HasAVX512]
vminpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMINPDZrmb [HasAVX512]
vminpd {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMINPDZrmbk [HasAVX512]
vminpd {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMINPDZrmbkz [HasAVX512]
vminpd {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMINPDZrmk [HasAVX512]
vminpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMINPDZrmkz [HasAVX512]
vminpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMINPDZrr [HasAVX512]
vminpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMINPDZrrb [HasAVX512]
vminpd {{sae}, src2, src1, dst|dst, src1, src2, {sae}}
VMINPDZrrbk [HasAVX512]
vminpd {{sae}, src2, src1, dst {mask}|dst {mask}, src1, src2, {sae}}
|
Note
|
Constraints: src0 = dst |
VMINPDZrrbkz [HasAVX512]
vminpd {{sae}, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, {sae}}
VMINPDZrrk [HasAVX512]
vminpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMINPDZrrkz [HasAVX512]
vminpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMINPSZrm [HasAVX512]
vminps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMINPSZrmb [HasAVX512]
vminps {src2{1to16}, src1, dst|dst, src1, src2{1to16}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMINPSZrmbk [HasAVX512]
vminps {src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMINPSZrmbkz [HasAVX512]
vminps {src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMINPSZrmk [HasAVX512]
vminps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMINPSZrmkz [HasAVX512]
vminps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMINPSZrr [HasAVX512]
vminps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMINPSZrrb [HasAVX512]
vminps {{sae}, src2, src1, dst|dst, src1, src2, {sae}}
VMINPSZrrbk [HasAVX512]
vminps {{sae}, src2, src1, dst {mask}|dst {mask}, src1, src2, {sae}}
|
Note
|
Constraints: src0 = dst |
VMINPSZrrbkz [HasAVX512]
vminps {{sae}, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, {sae}}
VMINPSZrrk [HasAVX512]
vminps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMINPSZrrkz [HasAVX512]
vminps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMINSDZrm_Int [HasAVX512]
vminsd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMINSDZrmk_Int [HasAVX512]
vminsd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMINSDZrmkz_Int [HasAVX512]
vminsd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMINSDZrr_Int [HasAVX512]
vminsd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMINSDZrrb_Int [HasAVX512]
vminsd {{sae}, src2, src1, dst|dst, src1, src2, {sae}}
VMINSDZrrbk_Int [HasAVX512]
vminsd {{sae}, src2, src1, dst {mask}|dst {mask}, src1, src2, {sae}}
|
Note
|
Constraints: src0 = dst |
VMINSDZrrbkz_Int [HasAVX512]
vminsd {{sae}, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, {sae}}
VMINSDZrrk_Int [HasAVX512]
vminsd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMINSDZrrkz_Int [HasAVX512]
vminsd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMINSSZrm_Int [HasAVX512]
vminss {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMINSSZrmk_Int [HasAVX512]
vminss {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMINSSZrmkz_Int [HasAVX512]
vminss {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMINSSZrr_Int [HasAVX512]
vminss {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMINSSZrrb_Int [HasAVX512]
vminss {{sae}, src2, src1, dst|dst, src1, src2, {sae}}
VMINSSZrrbk_Int [HasAVX512]
vminss {{sae}, src2, src1, dst {mask}|dst {mask}, src1, src2, {sae}}
|
Note
|
Constraints: src0 = dst |
VMINSSZrrbkz_Int [HasAVX512]
vminss {{sae}, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, {sae}}
VMINSSZrrk_Int [HasAVX512]
vminss {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMINSSZrrkz_Int [HasAVX512]
vminss {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMOV64toPQIZrr [HasAVX512]
vmovq {src, dst|dst, src}
VMOVAPDZmr [HasAVX512]
vmovapd {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VMOVAPDZmrk [HasAVX512]
vmovapd {src, dst {mask}|dst {mask}, src}
VMOVAPDZrm [HasAVX512]
vmovapd {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
VMOVAPDZrmk [HasAVX512]
vmovapd {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVAPDZrmkz [HasAVX512]
vmovapd {src, dst {mask} {z}|dst {mask} {z}, src}
VMOVAPDZrr [HasAVX512]
vmovapd {src, dst|dst, src}
|
Note
|
Properties: isMoveReg |
VMOVAPDZrrk [HasAVX512]
vmovapd {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVAPDZrrkz [HasAVX512]
vmovapd {src, dst {mask} {z}|dst {mask} {z}, src}
VMOVAPSZmr [HasAVX512]
vmovaps {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VMOVAPSZmrk [HasAVX512]
vmovaps {src, dst {mask}|dst {mask}, src}
VMOVAPSZrm [HasAVX512]
vmovaps {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
VMOVAPSZrmk [HasAVX512]
vmovaps {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVAPSZrmkz [HasAVX512]
vmovaps {src, dst {mask} {z}|dst {mask} {z}, src}
VMOVAPSZrr [HasAVX512]
vmovaps {src, dst|dst, src}
|
Note
|
Properties: isMoveReg |
VMOVAPSZrrk [HasAVX512]
vmovaps {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVAPSZrrkz [HasAVX512]
vmovaps {src, dst {mask} {z}|dst {mask} {z}, src}
VMOVDDUPZrm [HasAVX512]
vmovddup {src1, dst|dst, src1}
VMOVDDUPZrmk [HasAVX512]
vmovddup {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVDDUPZrmkz [HasAVX512]
vmovddup {src1, dst {mask} {z}|dst {mask} {z}, src1}
VMOVDDUPZrr [HasAVX512]
vmovddup {src1, dst|dst, src1}
VMOVDDUPZrrk [HasAVX512]
vmovddup {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVDDUPZrrkz [HasAVX512]
vmovddup {src1, dst {mask} {z}|dst {mask} {z}, src1}
VMOVDI2PDIZrm [HasAVX512]
vmovd {src, dst|dst, src}
VMOVDI2PDIZrr [HasAVX512]
vmovd {src, dst|dst, src}
VMOVDQA32Zmr [HasAVX512]
vmovdqa32 {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VMOVDQA32Zmrk [HasAVX512]
vmovdqa32 {src, dst {mask}|dst {mask}, src}
VMOVDQA32Zrm [HasAVX512]
vmovdqa32 {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
VMOVDQA32Zrmk [HasAVX512]
vmovdqa32 {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVDQA32Zrmkz [HasAVX512]
vmovdqa32 {src, dst {mask} {z}|dst {mask} {z}, src}
VMOVDQA32Zrr [HasAVX512]
vmovdqa32 {src, dst|dst, src}
|
Note
|
Properties: isMoveReg |
VMOVDQA32Zrrk [HasAVX512]
vmovdqa32 {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVDQA32Zrrkz [HasAVX512]
vmovdqa32 {src, dst {mask} {z}|dst {mask} {z}, src}
VMOVDQA64Zmr [HasAVX512]
vmovdqa64 {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VMOVDQA64Zmrk [HasAVX512]
vmovdqa64 {src, dst {mask}|dst {mask}, src}
VMOVDQA64Zrm [HasAVX512]
vmovdqa64 {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
VMOVDQA64Zrmk [HasAVX512]
vmovdqa64 {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVDQA64Zrmkz [HasAVX512]
vmovdqa64 {src, dst {mask} {z}|dst {mask} {z}, src}
VMOVDQA64Zrr [HasAVX512]
vmovdqa64 {src, dst|dst, src}
|
Note
|
Properties: isMoveReg |
VMOVDQA64Zrrk [HasAVX512]
vmovdqa64 {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVDQA64Zrrkz [HasAVX512]
vmovdqa64 {src, dst {mask} {z}|dst {mask} {z}, src}
VMOVDQU32Zmr [HasAVX512]
vmovdqu32 {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VMOVDQU32Zmrk [HasAVX512]
vmovdqu32 {src, dst {mask}|dst {mask}, src}
VMOVDQU32Zrm [HasAVX512]
vmovdqu32 {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
VMOVDQU32Zrmk [HasAVX512]
vmovdqu32 {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVDQU32Zrmkz [HasAVX512]
vmovdqu32 {src, dst {mask} {z}|dst {mask} {z}, src}
VMOVDQU32Zrr [HasAVX512]
vmovdqu32 {src, dst|dst, src}
|
Note
|
Properties: isMoveReg |
VMOVDQU32Zrrk [HasAVX512]
vmovdqu32 {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVDQU32Zrrkz [HasAVX512]
vmovdqu32 {src, dst {mask} {z}|dst {mask} {z}, src}
VMOVDQU64Zmr [HasAVX512]
vmovdqu64 {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VMOVDQU64Zmrk [HasAVX512]
vmovdqu64 {src, dst {mask}|dst {mask}, src}
VMOVDQU64Zrm [HasAVX512]
vmovdqu64 {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
VMOVDQU64Zrmk [HasAVX512]
vmovdqu64 {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVDQU64Zrmkz [HasAVX512]
vmovdqu64 {src, dst {mask} {z}|dst {mask} {z}, src}
VMOVDQU64Zrr [HasAVX512]
vmovdqu64 {src, dst|dst, src}
|
Note
|
Properties: isMoveReg |
VMOVDQU64Zrrk [HasAVX512]
vmovdqu64 {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVDQU64Zrrkz [HasAVX512]
vmovdqu64 {src, dst {mask} {z}|dst {mask} {z}, src}
VMOVHLPSZrr [HasAVX512]
vmovhlps {src2, src1, dst|dst, src1, src2}
VMOVHPDZ128mr [HasAVX512]
vmovhpd {src, dst|dst, src}
VMOVHPDZ128rm [HasAVX512]
vmovhpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VMOVHPSZ128mr [HasAVX512]
vmovhps {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VMOVHPSZ128rm [HasAVX512]
vmovhps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VMOVLHPSZrr [HasAVX512]
vmovlhps {src2, src1, dst|dst, src1, src2}
VMOVLPDZ128mr [HasAVX512]
vmovlpd {src, dst|dst, src}
VMOVLPDZ128rm [HasAVX512]
vmovlpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VMOVLPSZ128mr [HasAVX512]
vmovlps {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VMOVLPSZ128rm [HasAVX512]
vmovlps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VMOVNTDQAZrm [HasAVX512]
vmovntdqa {src, dst|dst, src}
VMOVNTDQZmr [HasAVX512]
vmovntdq {src, dst|dst, src}
VMOVNTPDZmr [HasAVX512]
vmovntpd {src, dst|dst, src}
VMOVNTPSZmr [HasAVX512]
vmovntps {src, dst|dst, src}
VMOVPDI2DIZmr [HasAVX512]
vmovd {src, dst|dst, src}
VMOVPDI2DIZrr [HasAVX512]
vmovd {src, dst|dst, src}
VMOVPQI2QIZmr [HasAVX512]
vmovq {src, dst|dst, src}
VMOVPQIto64Zrr [HasAVX512]
vmovq {src, dst|dst, src}
VMOVQI2PQIZrm [HasAVX512]
vmovq {src, dst|dst, src}
VMOVSDZmr [HasAVX512]
vmovsd {src, dst|dst, src}
VMOVSDZmrk [HasAVX512]
vmovsd {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
VMOVSDZrm [HasAVX512]
vmovsd {src, dst|dst, src}
VMOVSDZrmk [HasAVX512]
vmovsd {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VMOVSDZrmkz [HasAVX512]
vmovsd {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayLoad |
VMOVSDZrrk [HasAVX512]
vmovsd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VMOVSDZrrkz [HasAVX512]
vmovsd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VMOVSHDUPZrm [HasAVX512]
vmovshdup {src1, dst|dst, src1}
VMOVSHDUPZrmk [HasAVX512]
vmovshdup {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVSHDUPZrmkz [HasAVX512]
vmovshdup {src1, dst {mask} {z}|dst {mask} {z}, src1}
VMOVSHDUPZrr [HasAVX512]
vmovshdup {src1, dst|dst, src1}
VMOVSHDUPZrrk [HasAVX512]
vmovshdup {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVSHDUPZrrkz [HasAVX512]
vmovshdup {src1, dst {mask} {z}|dst {mask} {z}, src1}
VMOVSLDUPZrm [HasAVX512]
vmovsldup {src1, dst|dst, src1}
VMOVSLDUPZrmk [HasAVX512]
vmovsldup {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVSLDUPZrmkz [HasAVX512]
vmovsldup {src1, dst {mask} {z}|dst {mask} {z}, src1}
VMOVSLDUPZrr [HasAVX512]
vmovsldup {src1, dst|dst, src1}
VMOVSLDUPZrrk [HasAVX512]
vmovsldup {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVSLDUPZrrkz [HasAVX512]
vmovsldup {src1, dst {mask} {z}|dst {mask} {z}, src1}
VMOVSSZmr [HasAVX512]
vmovss {src, dst|dst, src}
VMOVSSZmrk [HasAVX512]
vmovss {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
VMOVSSZrm [HasAVX512]
vmovss {src, dst|dst, src}
VMOVSSZrmk [HasAVX512]
vmovss {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VMOVSSZrmkz [HasAVX512]
vmovss {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayLoad |
VMOVSSZrrk [HasAVX512]
vmovss {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VMOVSSZrrkz [HasAVX512]
vmovss {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VMOVUPDZmr [HasAVX512]
vmovupd {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VMOVUPDZmrk [HasAVX512]
vmovupd {src, dst {mask}|dst {mask}, src}
VMOVUPDZrm [HasAVX512]
vmovupd {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
VMOVUPDZrmk [HasAVX512]
vmovupd {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVUPDZrmkz [HasAVX512]
vmovupd {src, dst {mask} {z}|dst {mask} {z}, src}
VMOVUPDZrr [HasAVX512]
vmovupd {src, dst|dst, src}
|
Note
|
Properties: isMoveReg |
VMOVUPDZrrk [HasAVX512]
vmovupd {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVUPDZrrkz [HasAVX512]
vmovupd {src, dst {mask} {z}|dst {mask} {z}, src}
VMOVUPSZmr [HasAVX512]
vmovups {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VMOVUPSZmrk [HasAVX512]
vmovups {src, dst {mask}|dst {mask}, src}
VMOVUPSZrm [HasAVX512]
vmovups {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
VMOVUPSZrmk [HasAVX512]
vmovups {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVUPSZrmkz [HasAVX512]
vmovups {src, dst {mask} {z}|dst {mask} {z}, src}
VMOVUPSZrr [HasAVX512]
vmovups {src, dst|dst, src}
|
Note
|
Properties: isMoveReg |
VMOVUPSZrrk [HasAVX512]
vmovups {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVUPSZrrkz [HasAVX512]
vmovups {src, dst {mask} {z}|dst {mask} {z}, src}
VMOVZPQILo2PQIZrr [HasAVX512]
vmovq {src, dst|dst, src}
VMULPDZrm [HasAVX512]
vmulpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMULPDZrmb [HasAVX512]
vmulpd {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMULPDZrmbk [HasAVX512]
vmulpd {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMULPDZrmbkz [HasAVX512]
vmulpd {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMULPDZrmk [HasAVX512]
vmulpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMULPDZrmkz [HasAVX512]
vmulpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMULPDZrr [HasAVX512]
vmulpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMULPDZrrb [HasAVX512]
vmulpd {rc, src2, src1, dst|dst, src1, src2, rc}
VMULPDZrrbk [HasAVX512]
vmulpd {rc, src2, src1, dst {mask}|dst {mask}, src1, src2, rc}
|
Note
|
Constraints: src0 = dst |
VMULPDZrrbkz [HasAVX512]
vmulpd {rc, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, rc}
VMULPDZrrk [HasAVX512]
vmulpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMULPDZrrkz [HasAVX512]
vmulpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMULPSZrm [HasAVX512]
vmulps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMULPSZrmb [HasAVX512]
vmulps {src2{1to16}, src1, dst|dst, src1, src2{1to16}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMULPSZrmbk [HasAVX512]
vmulps {src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMULPSZrmbkz [HasAVX512]
vmulps {src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMULPSZrmk [HasAVX512]
vmulps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMULPSZrmkz [HasAVX512]
vmulps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMULPSZrr [HasAVX512]
vmulps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMULPSZrrb [HasAVX512]
vmulps {rc, src2, src1, dst|dst, src1, src2, rc}
VMULPSZrrbk [HasAVX512]
vmulps {rc, src2, src1, dst {mask}|dst {mask}, src1, src2, rc}
|
Note
|
Constraints: src0 = dst |
VMULPSZrrbkz [HasAVX512]
vmulps {rc, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, rc}
VMULPSZrrk [HasAVX512]
vmulps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMULPSZrrkz [HasAVX512]
vmulps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMULSDZrm_Int [HasAVX512]
vmulsd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMULSDZrmk_Int [HasAVX512]
vmulsd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMULSDZrmkz_Int [HasAVX512]
vmulsd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMULSDZrr_Int [HasAVX512]
vmulsd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMULSDZrrb_Int [HasAVX512]
vmulsd {rc, src2, src1, dst|dst, src1, src2, rc}
VMULSDZrrbk_Int [HasAVX512]
vmulsd {rc, src2, src1, dst {mask}|dst {mask}, src1, src2, rc}
|
Note
|
Constraints: src0 = dst |
VMULSDZrrbkz_Int [HasAVX512]
vmulsd {rc, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, rc}
VMULSDZrrk_Int [HasAVX512]
vmulsd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMULSDZrrkz_Int [HasAVX512]
vmulsd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMULSSZrm_Int [HasAVX512]
vmulss {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMULSSZrmk_Int [HasAVX512]
vmulss {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMULSSZrmkz_Int [HasAVX512]
vmulss {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMULSSZrr_Int [HasAVX512]
vmulss {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMULSSZrrb_Int [HasAVX512]
vmulss {rc, src2, src1, dst|dst, src1, src2, rc}
VMULSSZrrbk_Int [HasAVX512]
vmulss {rc, src2, src1, dst {mask}|dst {mask}, src1, src2, rc}
|
Note
|
Constraints: src0 = dst |
VMULSSZrrbkz_Int [HasAVX512]
vmulss {rc, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, rc}
VMULSSZrrk_Int [HasAVX512]
vmulss {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMULSSZrrkz_Int [HasAVX512]
vmulss {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VP4DPWSSDSrm [HasAVX512]
vp4dpwssds {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VP4DPWSSDSrmk [HasAVX512]
vp4dpwssds {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VP4DPWSSDSrmkz [HasAVX512]
vp4dpwssds {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VP4DPWSSDrm [HasAVX512]
vp4dpwssd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VP4DPWSSDrmk [HasAVX512]
vp4dpwssd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VP4DPWSSDrmkz [HasAVX512]
vp4dpwssd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPABSDZrm [HasAVX512]
vpabsd {src1, dst|dst, src1}
VPABSDZrmb [HasAVX512]
vpabsd {src1{1to16}, dst|dst, src1{1to16}}
VPABSDZrmbk [HasAVX512]
vpabsd {src1{1to16}, dst {mask}|dst {mask}, src1{1to16}}
|
Note
|
Constraints: src0 = dst |
VPABSDZrmbkz [HasAVX512]
vpabsd {src1{1to16}, dst {mask} {z}|dst {mask} {z}, src1{1to16}}
VPABSDZrmk [HasAVX512]
vpabsd {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPABSDZrmkz [HasAVX512]
vpabsd {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPABSDZrr [HasAVX512]
vpabsd {src1, dst|dst, src1}
VPABSDZrrk [HasAVX512]
vpabsd {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPABSDZrrkz [HasAVX512]
vpabsd {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPABSQZrm [HasAVX512]
vpabsq {src1, dst|dst, src1}
VPABSQZrmb [HasAVX512]
vpabsq {src1{1to8}, dst|dst, src1{1to8}}
VPABSQZrmbk [HasAVX512]
vpabsq {src1{1to8}, dst {mask}|dst {mask}, src1{1to8}}
|
Note
|
Constraints: src0 = dst |
VPABSQZrmbkz [HasAVX512]
vpabsq {src1{1to8}, dst {mask} {z}|dst {mask} {z}, src1{1to8}}
VPABSQZrmk [HasAVX512]
vpabsq {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPABSQZrmkz [HasAVX512]
vpabsq {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPABSQZrr [HasAVX512]
vpabsq {src1, dst|dst, src1}
VPABSQZrrk [HasAVX512]
vpabsq {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPABSQZrrkz [HasAVX512]
vpabsq {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPADDDZrm [HasAVX512]
vpaddd {src2, src1, dst|dst, src1, src2}
VPADDDZrmb [HasAVX512]
vpaddd {src2{1to16}, src1, dst|dst, src1, src2{1to16}}
VPADDDZrmbk [HasAVX512]
vpaddd {src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}}
|
Note
|
Constraints: src0 = dst |
VPADDDZrmbkz [HasAVX512]
vpaddd {src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}}
VPADDDZrmk [HasAVX512]
vpaddd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPADDDZrmkz [HasAVX512]
vpaddd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPADDDZrr [HasAVX512]
vpaddd {src2, src1, dst|dst, src1, src2}
VPADDDZrrk [HasAVX512]
vpaddd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPADDDZrrkz [HasAVX512]
vpaddd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPADDQZrm [HasAVX512]
vpaddq {src2, src1, dst|dst, src1, src2}
VPADDQZrmb [HasAVX512]
vpaddq {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
VPADDQZrmbk [HasAVX512]
vpaddq {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Constraints: src0 = dst |
VPADDQZrmbkz [HasAVX512]
vpaddq {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
VPADDQZrmk [HasAVX512]
vpaddq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPADDQZrmkz [HasAVX512]
vpaddq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPADDQZrr [HasAVX512]
vpaddq {src2, src1, dst|dst, src1, src2}
VPADDQZrrk [HasAVX512]
vpaddq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPADDQZrrkz [HasAVX512]
vpaddq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPANDDZrm [HasAVX512]
vpandd {src2, src1, dst|dst, src1, src2}
VPANDDZrmb [HasAVX512]
vpandd {src2{1to16}, src1, dst|dst, src1, src2{1to16}}
VPANDDZrmbk [HasAVX512]
vpandd {src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}}
|
Note
|
Constraints: src0 = dst |
VPANDDZrmbkz [HasAVX512]
vpandd {src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}}
VPANDDZrmk [HasAVX512]
vpandd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPANDDZrmkz [HasAVX512]
vpandd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPANDDZrr [HasAVX512]
vpandd {src2, src1, dst|dst, src1, src2}
VPANDDZrrk [HasAVX512]
vpandd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPANDDZrrkz [HasAVX512]
vpandd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPANDNDZrm [HasAVX512]
vpandnd {src2, src1, dst|dst, src1, src2}
VPANDNDZrmb [HasAVX512]
vpandnd {src2{1to16}, src1, dst|dst, src1, src2{1to16}}
VPANDNDZrmbk [HasAVX512]
vpandnd {src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}}
|
Note
|
Constraints: src0 = dst |
VPANDNDZrmbkz [HasAVX512]
vpandnd {src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}}
VPANDNDZrmk [HasAVX512]
vpandnd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPANDNDZrmkz [HasAVX512]
vpandnd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPANDNDZrr [HasAVX512]
vpandnd {src2, src1, dst|dst, src1, src2}
VPANDNDZrrk [HasAVX512]
vpandnd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPANDNDZrrkz [HasAVX512]
vpandnd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPANDNQZrm [HasAVX512]
vpandnq {src2, src1, dst|dst, src1, src2}
VPANDNQZrmb [HasAVX512]
vpandnq {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
VPANDNQZrmbk [HasAVX512]
vpandnq {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Constraints: src0 = dst |
VPANDNQZrmbkz [HasAVX512]
vpandnq {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
VPANDNQZrmk [HasAVX512]
vpandnq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPANDNQZrmkz [HasAVX512]
vpandnq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPANDNQZrr [HasAVX512]
vpandnq {src2, src1, dst|dst, src1, src2}
VPANDNQZrrk [HasAVX512]
vpandnq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPANDNQZrrkz [HasAVX512]
vpandnq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPANDQZrm [HasAVX512]
vpandq {src2, src1, dst|dst, src1, src2}
VPANDQZrmb [HasAVX512]
vpandq {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
VPANDQZrmbk [HasAVX512]
vpandq {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Constraints: src0 = dst |
VPANDQZrmbkz [HasAVX512]
vpandq {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
VPANDQZrmk [HasAVX512]
vpandq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPANDQZrmkz [HasAVX512]
vpandq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPANDQZrr [HasAVX512]
vpandq {src2, src1, dst|dst, src1, src2}
VPANDQZrrk [HasAVX512]
vpandq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPANDQZrrkz [HasAVX512]
vpandq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPBLENDMDZrm [HasAVX512]
vpblendmd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VPBLENDMDZrmb [HasAVX512]
vpblendmd {src2{1to16}, src1, dst|dst, src1, src2{1to16}}
|
Note
|
Properties: mayLoad |
VPBLENDMDZrmbk [HasAVX512]
vpblendmd {src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}}
|
Note
|
Properties: mayLoad |
VPBLENDMDZrmbkz [HasAVX512]
vpblendmd {src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}}
|
Note
|
Properties: mayLoad |
VPBLENDMDZrmk [HasAVX512]
vpblendmd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
VPBLENDMDZrmkz [HasAVX512]
vpblendmd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VPBLENDMDZrr [HasAVX512]
vpblendmd {src2, src1, dst|dst, src1, src2}
VPBLENDMDZrrk [HasAVX512]
vpblendmd {src2, src1, dst {mask}|dst {mask}, src1, src2}
VPBLENDMDZrrkz [HasAVX512]
vpblendmd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPBLENDMQZrm [HasAVX512]
vpblendmq {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VPBLENDMQZrmb [HasAVX512]
vpblendmq {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
VPBLENDMQZrmbk [HasAVX512]
vpblendmq {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
VPBLENDMQZrmbkz [HasAVX512]
vpblendmq {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
VPBLENDMQZrmk [HasAVX512]
vpblendmq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
VPBLENDMQZrmkz [HasAVX512]
vpblendmq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VPBLENDMQZrr [HasAVX512]
vpblendmq {src2, src1, dst|dst, src1, src2}
VPBLENDMQZrrk [HasAVX512]
vpblendmq {src2, src1, dst {mask}|dst {mask}, src1, src2}
VPBLENDMQZrrkz [HasAVX512]
vpblendmq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPBROADCASTDZrm [HasAVX512]
vpbroadcastd {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
VPBROADCASTDZrmk [HasAVX512]
vpbroadcastd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPBROADCASTDZrmkz [HasAVX512]
vpbroadcastd {src, dst {mask} {z}|dst {mask} {z}, src}
VPBROADCASTDZrr [HasAVX512]
vpbroadcastd {src, dst|dst, src}
VPBROADCASTDZrrk [HasAVX512]
vpbroadcastd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPBROADCASTDZrrkz [HasAVX512]
vpbroadcastd {src, dst {mask} {z}|dst {mask} {z}, src}
VPBROADCASTDrZrr [HasAVX512]
vpbroadcastd {src, dst|dst, src}
VPBROADCASTDrZrrk [HasAVX512]
vpbroadcastd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPBROADCASTDrZrrkz [HasAVX512]
vpbroadcastd {src, dst {mask} {z}|dst {mask} {z}, src}
VPBROADCASTQZrm [HasAVX512]
vpbroadcastq {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
VPBROADCASTQZrmk [HasAVX512]
vpbroadcastq {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPBROADCASTQZrmkz [HasAVX512]
vpbroadcastq {src, dst {mask} {z}|dst {mask} {z}, src}
VPBROADCASTQZrr [HasAVX512]
vpbroadcastq {src, dst|dst, src}
VPBROADCASTQZrrk [HasAVX512]
vpbroadcastq {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPBROADCASTQZrrkz [HasAVX512]
vpbroadcastq {src, dst {mask} {z}|dst {mask} {z}, src}
VPBROADCASTQrZrr [HasAVX512]
vpbroadcastq {src, dst|dst, src}
VPBROADCASTQrZrrk [HasAVX512]
vpbroadcastq {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPBROADCASTQrZrrkz [HasAVX512]
vpbroadcastq {src, dst {mask} {z}|dst {mask} {z}, src}
VPCMPDZrmbi [HasAVX512]
vpcmpd {cc, src2{1to16}, src1, dst|dst, src1, src2{1to16}, cc}
VPCMPDZrmbik [HasAVX512]
vpcmpd {cc, src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}, cc}
VPCMPDZrmi [HasAVX512]
vpcmpd {cc, src2, src1, dst|dst, src1, src2, cc}
VPCMPDZrmik [HasAVX512]
vpcmpd {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
VPCMPDZrri [HasAVX512]
vpcmpd {cc, src2, src1, dst|dst, src1, src2, cc}
VPCMPDZrrik [HasAVX512]
vpcmpd {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
VPCMPEQDZrm [HasAVX512]
vpcmpeqd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VPCMPEQDZrmb [HasAVX512]
vpcmpeqd {src2{1to16}, src1, dst|dst, src1, src2{1to16}}
|
Note
|
Properties: mayLoad |
VPCMPEQDZrmbk [HasAVX512]
vpcmpeqd {src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}}
|
Note
|
Properties: mayLoad |
VPCMPEQDZrmk [HasAVX512]
vpcmpeqd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
VPCMPEQDZrr [HasAVX512]
vpcmpeqd {src2, src1, dst|dst, src1, src2}
VPCMPEQDZrrk [HasAVX512]
vpcmpeqd {src2, src1, dst {mask}|dst {mask}, src1, src2}
VPCMPEQQZrm [HasAVX512]
vpcmpeqq {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VPCMPEQQZrmb [HasAVX512]
vpcmpeqq {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
VPCMPEQQZrmbk [HasAVX512]
vpcmpeqq {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
VPCMPEQQZrmk [HasAVX512]
vpcmpeqq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
VPCMPEQQZrr [HasAVX512]
vpcmpeqq {src2, src1, dst|dst, src1, src2}
VPCMPEQQZrrk [HasAVX512]
vpcmpeqq {src2, src1, dst {mask}|dst {mask}, src1, src2}
VPCMPGTDZrm [HasAVX512]
vpcmpgtd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VPCMPGTDZrmb [HasAVX512]
vpcmpgtd {src2{1to16}, src1, dst|dst, src1, src2{1to16}}
|
Note
|
Properties: mayLoad |
VPCMPGTDZrmbk [HasAVX512]
vpcmpgtd {src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}}
|
Note
|
Properties: mayLoad |
VPCMPGTDZrmk [HasAVX512]
vpcmpgtd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
VPCMPGTDZrr [HasAVX512]
vpcmpgtd {src2, src1, dst|dst, src1, src2}
VPCMPGTDZrrk [HasAVX512]
vpcmpgtd {src2, src1, dst {mask}|dst {mask}, src1, src2}
VPCMPGTQZrm [HasAVX512]
vpcmpgtq {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VPCMPGTQZrmb [HasAVX512]
vpcmpgtq {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
VPCMPGTQZrmbk [HasAVX512]
vpcmpgtq {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
VPCMPGTQZrmk [HasAVX512]
vpcmpgtq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
VPCMPGTQZrr [HasAVX512]
vpcmpgtq {src2, src1, dst|dst, src1, src2}
VPCMPGTQZrrk [HasAVX512]
vpcmpgtq {src2, src1, dst {mask}|dst {mask}, src1, src2}
VPCMPQZrmbi [HasAVX512]
vpcmpq {cc, src2{1to8}, src1, dst|dst, src1, src2{1to8}, cc}
VPCMPQZrmbik [HasAVX512]
vpcmpq {cc, src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}, cc}
VPCMPQZrmi [HasAVX512]
vpcmpq {cc, src2, src1, dst|dst, src1, src2, cc}
VPCMPQZrmik [HasAVX512]
vpcmpq {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
VPCMPQZrri [HasAVX512]
vpcmpq {cc, src2, src1, dst|dst, src1, src2, cc}
VPCMPQZrrik [HasAVX512]
vpcmpq {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
VPCMPUDZrmbi [HasAVX512]
vpcmpud {cc, src2{1to16}, src1, dst|dst, src1, src2{1to16}, cc}
VPCMPUDZrmbik [HasAVX512]
vpcmpud {cc, src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}, cc}
VPCMPUDZrmi [HasAVX512]
vpcmpud {cc, src2, src1, dst|dst, src1, src2, cc}
VPCMPUDZrmik [HasAVX512]
vpcmpud {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
VPCMPUDZrri [HasAVX512]
vpcmpud {cc, src2, src1, dst|dst, src1, src2, cc}
VPCMPUDZrrik [HasAVX512]
vpcmpud {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
VPCMPUQZrmbi [HasAVX512]
vpcmpuq {cc, src2{1to8}, src1, dst|dst, src1, src2{1to8}, cc}
VPCMPUQZrmbik [HasAVX512]
vpcmpuq {cc, src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}, cc}
VPCMPUQZrmi [HasAVX512]
vpcmpuq {cc, src2, src1, dst|dst, src1, src2, cc}
VPCMPUQZrmik [HasAVX512]
vpcmpuq {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
VPCMPUQZrri [HasAVX512]
vpcmpuq {cc, src2, src1, dst|dst, src1, src2, cc}
VPCMPUQZrrik [HasAVX512]
vpcmpuq {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
VPCOMPRESSDZmr [HasAVX512]
vpcompressd {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VPCOMPRESSDZmrk [HasAVX512]
vpcompressd {src, dst {mask}|dst {mask}, src}
VPCOMPRESSDZrr [HasAVX512]
vpcompressd {src1, dst|dst, src1}
VPCOMPRESSDZrrk [HasAVX512]
vpcompressd {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPCOMPRESSDZrrkz [HasAVX512]
vpcompressd {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPCOMPRESSQZmr [HasAVX512]
vpcompressq {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VPCOMPRESSQZmrk [HasAVX512]
vpcompressq {src, dst {mask}|dst {mask}, src}
VPCOMPRESSQZrr [HasAVX512]
vpcompressq {src1, dst|dst, src1}
VPCOMPRESSQZrrk [HasAVX512]
vpcompressq {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPCOMPRESSQZrrkz [HasAVX512]
vpcompressq {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPERMDZrm [HasAVX512]
vpermd {src2, src1, dst|dst, src1, src2}
VPERMDZrmb [HasAVX512]
vpermd {src2{1to16}, src1, dst|dst, src1, src2{1to16}}
VPERMDZrmbk [HasAVX512]
vpermd {src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}}
|
Note
|
Constraints: src0 = dst |
VPERMDZrmbkz [HasAVX512]
vpermd {src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}}
VPERMDZrmk [HasAVX512]
vpermd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPERMDZrmkz [HasAVX512]
vpermd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPERMDZrr [HasAVX512]
vpermd {src2, src1, dst|dst, src1, src2}
VPERMDZrrk [HasAVX512]
vpermd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPERMDZrrkz [HasAVX512]
vpermd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPERMI2DZrm [HasAVX512]
vpermi2d {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2DZrmb [HasAVX512]
vpermi2d {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2DZrmbk [HasAVX512]
vpermi2d {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2DZrmbkz [HasAVX512]
vpermi2d {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2DZrmk [HasAVX512]
vpermi2d {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2DZrmkz [HasAVX512]
vpermi2d {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2DZrr [HasAVX512]
vpermi2d {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMI2DZrrk [HasAVX512]
vpermi2d {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMI2DZrrkz [HasAVX512]
vpermi2d {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMI2PDZrm [HasAVX512]
vpermi2pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2PDZrmb [HasAVX512]
vpermi2pd {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2PDZrmbk [HasAVX512]
vpermi2pd {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2PDZrmbkz [HasAVX512]
vpermi2pd {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2PDZrmk [HasAVX512]
vpermi2pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2PDZrmkz [HasAVX512]
vpermi2pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2PDZrr [HasAVX512]
vpermi2pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMI2PDZrrk [HasAVX512]
vpermi2pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMI2PDZrrkz [HasAVX512]
vpermi2pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMI2PSZrm [HasAVX512]
vpermi2ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2PSZrmb [HasAVX512]
vpermi2ps {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2PSZrmbk [HasAVX512]
vpermi2ps {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2PSZrmbkz [HasAVX512]
vpermi2ps {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2PSZrmk [HasAVX512]
vpermi2ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2PSZrmkz [HasAVX512]
vpermi2ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2PSZrr [HasAVX512]
vpermi2ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMI2PSZrrk [HasAVX512]
vpermi2ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMI2PSZrrkz [HasAVX512]
vpermi2ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMI2QZrm [HasAVX512]
vpermi2q {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2QZrmb [HasAVX512]
vpermi2q {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2QZrmbk [HasAVX512]
vpermi2q {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2QZrmbkz [HasAVX512]
vpermi2q {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2QZrmk [HasAVX512]
vpermi2q {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2QZrmkz [HasAVX512]
vpermi2q {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2QZrr [HasAVX512]
vpermi2q {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMI2QZrrk [HasAVX512]
vpermi2q {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMI2QZrrkz [HasAVX512]
vpermi2q {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMILPDZmbi [HasAVX512]
vpermilpd {src2, src1{1to8}, dst|dst, src1{1to8}, src2}
VPERMILPDZmbik [HasAVX512]
vpermilpd {src2, src1{1to8}, dst {mask}|dst {mask}, src1{1to8}, src2}
|
Note
|
Constraints: src0 = dst |
VPERMILPDZmbikz [HasAVX512]
vpermilpd {src2, src1{1to8}, dst {mask} {z}|dst {mask} {z}, src1{1to8}, src2}
VPERMILPDZmi [HasAVX512]
vpermilpd {src2, src1, dst|dst, src1, src2}
VPERMILPDZmik [HasAVX512]
vpermilpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPERMILPDZmikz [HasAVX512]
vpermilpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPERMILPDZri [HasAVX512]
vpermilpd {src2, src1, dst|dst, src1, src2}
VPERMILPDZrik [HasAVX512]
vpermilpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPERMILPDZrikz [HasAVX512]
vpermilpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPERMILPDZrm [HasAVX512]
vpermilpd {src2, src1, dst|dst, src1, src2}
VPERMILPDZrmb [HasAVX512]
vpermilpd {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
VPERMILPDZrmbk [HasAVX512]
vpermilpd {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Constraints: src0 = dst |
VPERMILPDZrmbkz [HasAVX512]
vpermilpd {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
VPERMILPDZrmk [HasAVX512]
vpermilpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPERMILPDZrmkz [HasAVX512]
vpermilpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPERMILPDZrr [HasAVX512]
vpermilpd {src2, src1, dst|dst, src1, src2}
VPERMILPDZrrk [HasAVX512]
vpermilpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPERMILPDZrrkz [HasAVX512]
vpermilpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPERMILPSZmbi [HasAVX512]
vpermilps {src2, src1{1to16}, dst|dst, src1{1to16}, src2}
VPERMILPSZmbik [HasAVX512]
vpermilps {src2, src1{1to16}, dst {mask}|dst {mask}, src1{1to16}, src2}
|
Note
|
Constraints: src0 = dst |
VPERMILPSZmbikz [HasAVX512]
vpermilps {src2, src1{1to16}, dst {mask} {z}|dst {mask} {z}, src1{1to16}, src2}
VPERMILPSZmi [HasAVX512]
vpermilps {src2, src1, dst|dst, src1, src2}
VPERMILPSZmik [HasAVX512]
vpermilps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPERMILPSZmikz [HasAVX512]
vpermilps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPERMILPSZri [HasAVX512]
vpermilps {src2, src1, dst|dst, src1, src2}
VPERMILPSZrik [HasAVX512]
vpermilps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPERMILPSZrikz [HasAVX512]
vpermilps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPERMILPSZrm [HasAVX512]
vpermilps {src2, src1, dst|dst, src1, src2}
VPERMILPSZrmb [HasAVX512]
vpermilps {src2{1to16}, src1, dst|dst, src1, src2{1to16}}
VPERMILPSZrmbk [HasAVX512]
vpermilps {src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}}
|
Note
|
Constraints: src0 = dst |
VPERMILPSZrmbkz [HasAVX512]
vpermilps {src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}}
VPERMILPSZrmk [HasAVX512]
vpermilps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPERMILPSZrmkz [HasAVX512]
vpermilps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPERMILPSZrr [HasAVX512]
vpermilps {src2, src1, dst|dst, src1, src2}
VPERMILPSZrrk [HasAVX512]
vpermilps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPERMILPSZrrkz [HasAVX512]
vpermilps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPERMPDZmbi [HasAVX512]
vpermpd {src2, src1{1to8}, dst|dst, src1{1to8}, src2}
VPERMPDZmbik [HasAVX512]
vpermpd {src2, src1{1to8}, dst {mask}|dst {mask}, src1{1to8}, src2}
|
Note
|
Constraints: src0 = dst |
VPERMPDZmbikz [HasAVX512]
vpermpd {src2, src1{1to8}, dst {mask} {z}|dst {mask} {z}, src1{1to8}, src2}
VPERMPDZmi [HasAVX512]
vpermpd {src2, src1, dst|dst, src1, src2}
VPERMPDZmik [HasAVX512]
vpermpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPERMPDZmikz [HasAVX512]
vpermpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPERMPDZri [HasAVX512]
vpermpd {src2, src1, dst|dst, src1, src2}
VPERMPDZrik [HasAVX512]
vpermpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPERMPDZrikz [HasAVX512]
vpermpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPERMPDZrm [HasAVX512]
vpermpd {src2, src1, dst|dst, src1, src2}
VPERMPDZrmb [HasAVX512]
vpermpd {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
VPERMPDZrmbk [HasAVX512]
vpermpd {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Constraints: src0 = dst |
VPERMPDZrmbkz [HasAVX512]
vpermpd {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
VPERMPDZrmk [HasAVX512]
vpermpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPERMPDZrmkz [HasAVX512]
vpermpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPERMPDZrr [HasAVX512]
vpermpd {src2, src1, dst|dst, src1, src2}
VPERMPDZrrk [HasAVX512]
vpermpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPERMPDZrrkz [HasAVX512]
vpermpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPERMPSZrm [HasAVX512]
vpermps {src2, src1, dst|dst, src1, src2}
VPERMPSZrmb [HasAVX512]
vpermps {src2{1to16}, src1, dst|dst, src1, src2{1to16}}
VPERMPSZrmbk [HasAVX512]
vpermps {src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}}
|
Note
|
Constraints: src0 = dst |
VPERMPSZrmbkz [HasAVX512]
vpermps {src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}}
VPERMPSZrmk [HasAVX512]
vpermps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPERMPSZrmkz [HasAVX512]
vpermps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPERMPSZrr [HasAVX512]
vpermps {src2, src1, dst|dst, src1, src2}
VPERMPSZrrk [HasAVX512]
vpermps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPERMPSZrrkz [HasAVX512]
vpermps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPERMQZmbi [HasAVX512]
vpermq {src2, src1{1to8}, dst|dst, src1{1to8}, src2}
VPERMQZmbik [HasAVX512]
vpermq {src2, src1{1to8}, dst {mask}|dst {mask}, src1{1to8}, src2}
|
Note
|
Constraints: src0 = dst |
VPERMQZmbikz [HasAVX512]
vpermq {src2, src1{1to8}, dst {mask} {z}|dst {mask} {z}, src1{1to8}, src2}
VPERMQZmi [HasAVX512]
vpermq {src2, src1, dst|dst, src1, src2}
VPERMQZmik [HasAVX512]
vpermq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPERMQZmikz [HasAVX512]
vpermq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPERMQZri [HasAVX512]
vpermq {src2, src1, dst|dst, src1, src2}
VPERMQZrik [HasAVX512]
vpermq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPERMQZrikz [HasAVX512]
vpermq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPERMQZrm [HasAVX512]
vpermq {src2, src1, dst|dst, src1, src2}
VPERMQZrmb [HasAVX512]
vpermq {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
VPERMQZrmbk [HasAVX512]
vpermq {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Constraints: src0 = dst |
VPERMQZrmbkz [HasAVX512]
vpermq {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
VPERMQZrmk [HasAVX512]
vpermq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPERMQZrmkz [HasAVX512]
vpermq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPERMQZrr [HasAVX512]
vpermq {src2, src1, dst|dst, src1, src2}
VPERMQZrrk [HasAVX512]
vpermq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPERMQZrrkz [HasAVX512]
vpermq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPERMT2DZrm [HasAVX512]
vpermt2d {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2DZrmb [HasAVX512]
vpermt2d {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VPERMT2DZrmbk [HasAVX512]
vpermt2d {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VPERMT2DZrmbkz [HasAVX512]
vpermt2d {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VPERMT2DZrmk [HasAVX512]
vpermt2d {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2DZrmkz [HasAVX512]
vpermt2d {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2DZrr [HasAVX512]
vpermt2d {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2DZrrk [HasAVX512]
vpermt2d {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2DZrrkz [HasAVX512]
vpermt2d {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2PDZrm [HasAVX512]
vpermt2pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2PDZrmb [HasAVX512]
vpermt2pd {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPERMT2PDZrmbk [HasAVX512]
vpermt2pd {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPERMT2PDZrmbkz [HasAVX512]
vpermt2pd {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPERMT2PDZrmk [HasAVX512]
vpermt2pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2PDZrmkz [HasAVX512]
vpermt2pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2PDZrr [HasAVX512]
vpermt2pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2PDZrrk [HasAVX512]
vpermt2pd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2PDZrrkz [HasAVX512]
vpermt2pd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2PSZrm [HasAVX512]
vpermt2ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2PSZrmb [HasAVX512]
vpermt2ps {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VPERMT2PSZrmbk [HasAVX512]
vpermt2ps {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VPERMT2PSZrmbkz [HasAVX512]
vpermt2ps {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VPERMT2PSZrmk [HasAVX512]
vpermt2ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2PSZrmkz [HasAVX512]
vpermt2ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2PSZrr [HasAVX512]
vpermt2ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2PSZrrk [HasAVX512]
vpermt2ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2PSZrrkz [HasAVX512]
vpermt2ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2QZrm [HasAVX512]
vpermt2q {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2QZrmb [HasAVX512]
vpermt2q {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPERMT2QZrmbk [HasAVX512]
vpermt2q {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPERMT2QZrmbkz [HasAVX512]
vpermt2q {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPERMT2QZrmk [HasAVX512]
vpermt2q {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2QZrmkz [HasAVX512]
vpermt2q {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2QZrr [HasAVX512]
vpermt2q {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2QZrrk [HasAVX512]
vpermt2q {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2QZrrkz [HasAVX512]
vpermt2q {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPEXPANDDZrm [HasAVX512]
vpexpandd {src1, dst|dst, src1}
VPEXPANDDZrmk [HasAVX512]
vpexpandd {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPEXPANDDZrmkz [HasAVX512]
vpexpandd {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPEXPANDDZrr [HasAVX512]
vpexpandd {src1, dst|dst, src1}
VPEXPANDDZrrk [HasAVX512]
vpexpandd {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPEXPANDDZrrkz [HasAVX512]
vpexpandd {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPEXPANDQZrm [HasAVX512]
vpexpandq {src1, dst|dst, src1}
VPEXPANDQZrmk [HasAVX512]
vpexpandq {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPEXPANDQZrmkz [HasAVX512]
vpexpandq {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPEXPANDQZrr [HasAVX512]
vpexpandq {src1, dst|dst, src1}
VPEXPANDQZrrk [HasAVX512]
vpexpandq {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPEXPANDQZrrkz [HasAVX512]
vpexpandq {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPGATHERDDZrm [HasAVX512]
vpgatherdd {src2, dst {mask}|dst {mask}, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst, src1 = dst, mask = mask_wb |
VPGATHERDQZrm [HasAVX512]
vpgatherdq {src2, dst {mask}|dst {mask}, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst, src1 = dst, mask = mask_wb |
VPGATHERQDZrm [HasAVX512]
vpgatherqd {src2, dst {mask}|dst {mask}, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst, src1 = dst, mask = mask_wb |
VPGATHERQQZrm [HasAVX512]
vpgatherqq {src2, dst {mask}|dst {mask}, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst, src1 = dst, mask = mask_wb |
VPMAXSDZrm [HasAVX512]
vpmaxsd {src2, src1, dst|dst, src1, src2}
VPMAXSDZrmb [HasAVX512]
vpmaxsd {src2{1to16}, src1, dst|dst, src1, src2{1to16}}
VPMAXSDZrmbk [HasAVX512]
vpmaxsd {src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}}
|
Note
|
Constraints: src0 = dst |
VPMAXSDZrmbkz [HasAVX512]
vpmaxsd {src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}}
VPMAXSDZrmk [HasAVX512]
vpmaxsd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMAXSDZrmkz [HasAVX512]
vpmaxsd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMAXSDZrr [HasAVX512]
vpmaxsd {src2, src1, dst|dst, src1, src2}
VPMAXSDZrrk [HasAVX512]
vpmaxsd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMAXSDZrrkz [HasAVX512]
vpmaxsd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMAXSQZrm [HasAVX512]
vpmaxsq {src2, src1, dst|dst, src1, src2}
VPMAXSQZrmb [HasAVX512]
vpmaxsq {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
VPMAXSQZrmbk [HasAVX512]
vpmaxsq {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Constraints: src0 = dst |
VPMAXSQZrmbkz [HasAVX512]
vpmaxsq {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
VPMAXSQZrmk [HasAVX512]
vpmaxsq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMAXSQZrmkz [HasAVX512]
vpmaxsq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMAXSQZrr [HasAVX512]
vpmaxsq {src2, src1, dst|dst, src1, src2}
VPMAXSQZrrk [HasAVX512]
vpmaxsq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMAXSQZrrkz [HasAVX512]
vpmaxsq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMAXUDZrm [HasAVX512]
vpmaxud {src2, src1, dst|dst, src1, src2}
VPMAXUDZrmb [HasAVX512]
vpmaxud {src2{1to16}, src1, dst|dst, src1, src2{1to16}}
VPMAXUDZrmbk [HasAVX512]
vpmaxud {src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}}
|
Note
|
Constraints: src0 = dst |
VPMAXUDZrmbkz [HasAVX512]
vpmaxud {src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}}
VPMAXUDZrmk [HasAVX512]
vpmaxud {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMAXUDZrmkz [HasAVX512]
vpmaxud {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMAXUDZrr [HasAVX512]
vpmaxud {src2, src1, dst|dst, src1, src2}
VPMAXUDZrrk [HasAVX512]
vpmaxud {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMAXUDZrrkz [HasAVX512]
vpmaxud {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMAXUQZrm [HasAVX512]
vpmaxuq {src2, src1, dst|dst, src1, src2}
VPMAXUQZrmb [HasAVX512]
vpmaxuq {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
VPMAXUQZrmbk [HasAVX512]
vpmaxuq {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Constraints: src0 = dst |
VPMAXUQZrmbkz [HasAVX512]
vpmaxuq {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
VPMAXUQZrmk [HasAVX512]
vpmaxuq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMAXUQZrmkz [HasAVX512]
vpmaxuq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMAXUQZrr [HasAVX512]
vpmaxuq {src2, src1, dst|dst, src1, src2}
VPMAXUQZrrk [HasAVX512]
vpmaxuq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMAXUQZrrkz [HasAVX512]
vpmaxuq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMINSDZrm [HasAVX512]
vpminsd {src2, src1, dst|dst, src1, src2}
VPMINSDZrmb [HasAVX512]
vpminsd {src2{1to16}, src1, dst|dst, src1, src2{1to16}}
VPMINSDZrmbk [HasAVX512]
vpminsd {src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}}
|
Note
|
Constraints: src0 = dst |
VPMINSDZrmbkz [HasAVX512]
vpminsd {src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}}
VPMINSDZrmk [HasAVX512]
vpminsd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMINSDZrmkz [HasAVX512]
vpminsd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMINSDZrr [HasAVX512]
vpminsd {src2, src1, dst|dst, src1, src2}
VPMINSDZrrk [HasAVX512]
vpminsd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMINSDZrrkz [HasAVX512]
vpminsd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMINSQZrm [HasAVX512]
vpminsq {src2, src1, dst|dst, src1, src2}
VPMINSQZrmb [HasAVX512]
vpminsq {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
VPMINSQZrmbk [HasAVX512]
vpminsq {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Constraints: src0 = dst |
VPMINSQZrmbkz [HasAVX512]
vpminsq {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
VPMINSQZrmk [HasAVX512]
vpminsq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMINSQZrmkz [HasAVX512]
vpminsq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMINSQZrr [HasAVX512]
vpminsq {src2, src1, dst|dst, src1, src2}
VPMINSQZrrk [HasAVX512]
vpminsq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMINSQZrrkz [HasAVX512]
vpminsq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMINUDZrm [HasAVX512]
vpminud {src2, src1, dst|dst, src1, src2}
VPMINUDZrmb [HasAVX512]
vpminud {src2{1to16}, src1, dst|dst, src1, src2{1to16}}
VPMINUDZrmbk [HasAVX512]
vpminud {src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}}
|
Note
|
Constraints: src0 = dst |
VPMINUDZrmbkz [HasAVX512]
vpminud {src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}}
VPMINUDZrmk [HasAVX512]
vpminud {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMINUDZrmkz [HasAVX512]
vpminud {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMINUDZrr [HasAVX512]
vpminud {src2, src1, dst|dst, src1, src2}
VPMINUDZrrk [HasAVX512]
vpminud {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMINUDZrrkz [HasAVX512]
vpminud {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMINUQZrm [HasAVX512]
vpminuq {src2, src1, dst|dst, src1, src2}
VPMINUQZrmb [HasAVX512]
vpminuq {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
VPMINUQZrmbk [HasAVX512]
vpminuq {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Constraints: src0 = dst |
VPMINUQZrmbkz [HasAVX512]
vpminuq {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
VPMINUQZrmk [HasAVX512]
vpminuq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMINUQZrmkz [HasAVX512]
vpminuq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMINUQZrr [HasAVX512]
vpminuq {src2, src1, dst|dst, src1, src2}
VPMINUQZrrk [HasAVX512]
vpminuq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMINUQZrrkz [HasAVX512]
vpminuq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMOVDBZmr [HasAVX512]
vpmovdb {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VPMOVDBZmrk [HasAVX512]
vpmovdb {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
VPMOVDBZrr [HasAVX512]
vpmovdb {src, dst|dst, src}
VPMOVDBZrrk [HasAVX512]
vpmovdb {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVDBZrrkz [HasAVX512]
vpmovdb {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVDWZmr [HasAVX512]
vpmovdw {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VPMOVDWZmrk [HasAVX512]
vpmovdw {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
VPMOVDWZrr [HasAVX512]
vpmovdw {src, dst|dst, src}
VPMOVDWZrrk [HasAVX512]
vpmovdw {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVDWZrrkz [HasAVX512]
vpmovdw {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVQBZmr [HasAVX512]
vpmovqb {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VPMOVQBZmrk [HasAVX512]
vpmovqb {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
VPMOVQBZrr [HasAVX512]
vpmovqb {src, dst|dst, src}
VPMOVQBZrrk [HasAVX512]
vpmovqb {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVQBZrrkz [HasAVX512]
vpmovqb {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVQDZmr [HasAVX512]
vpmovqd {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VPMOVQDZmrk [HasAVX512]
vpmovqd {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
VPMOVQDZrr [HasAVX512]
vpmovqd {src, dst|dst, src}
VPMOVQDZrrk [HasAVX512]
vpmovqd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVQDZrrkz [HasAVX512]
vpmovqd {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVQWZmr [HasAVX512]
vpmovqw {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VPMOVQWZmrk [HasAVX512]
vpmovqw {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
VPMOVQWZrr [HasAVX512]
vpmovqw {src, dst|dst, src}
VPMOVQWZrrk [HasAVX512]
vpmovqw {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVQWZrrkz [HasAVX512]
vpmovqw {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVSDBZmr [HasAVX512]
vpmovsdb {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VPMOVSDBZmrk [HasAVX512]
vpmovsdb {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
VPMOVSDBZrr [HasAVX512]
vpmovsdb {src, dst|dst, src}
VPMOVSDBZrrk [HasAVX512]
vpmovsdb {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVSDBZrrkz [HasAVX512]
vpmovsdb {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVSDWZmr [HasAVX512]
vpmovsdw {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VPMOVSDWZmrk [HasAVX512]
vpmovsdw {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
VPMOVSDWZrr [HasAVX512]
vpmovsdw {src, dst|dst, src}
VPMOVSDWZrrk [HasAVX512]
vpmovsdw {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVSDWZrrkz [HasAVX512]
vpmovsdw {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVSQBZmr [HasAVX512]
vpmovsqb {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VPMOVSQBZmrk [HasAVX512]
vpmovsqb {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
VPMOVSQBZrr [HasAVX512]
vpmovsqb {src, dst|dst, src}
VPMOVSQBZrrk [HasAVX512]
vpmovsqb {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVSQBZrrkz [HasAVX512]
vpmovsqb {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVSQDZmr [HasAVX512]
vpmovsqd {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VPMOVSQDZmrk [HasAVX512]
vpmovsqd {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
VPMOVSQDZrr [HasAVX512]
vpmovsqd {src, dst|dst, src}
VPMOVSQDZrrk [HasAVX512]
vpmovsqd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVSQDZrrkz [HasAVX512]
vpmovsqd {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVSQWZmr [HasAVX512]
vpmovsqw {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VPMOVSQWZmrk [HasAVX512]
vpmovsqw {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
VPMOVSQWZrr [HasAVX512]
vpmovsqw {src, dst|dst, src}
VPMOVSQWZrrk [HasAVX512]
vpmovsqw {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVSQWZrrkz [HasAVX512]
vpmovsqw {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVSXBDZrm [HasAVX512]
vpmovsxbd {src, dst|dst, src}
VPMOVSXBDZrmk [HasAVX512]
vpmovsxbd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVSXBDZrmkz [HasAVX512]
vpmovsxbd {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVSXBDZrr [HasAVX512]
vpmovsxbd {src, dst|dst, src}
VPMOVSXBDZrrk [HasAVX512]
vpmovsxbd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVSXBDZrrkz [HasAVX512]
vpmovsxbd {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVSXBQZrm [HasAVX512]
vpmovsxbq {src, dst|dst, src}
VPMOVSXBQZrmk [HasAVX512]
vpmovsxbq {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVSXBQZrmkz [HasAVX512]
vpmovsxbq {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVSXBQZrr [HasAVX512]
vpmovsxbq {src, dst|dst, src}
VPMOVSXBQZrrk [HasAVX512]
vpmovsxbq {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVSXBQZrrkz [HasAVX512]
vpmovsxbq {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVSXDQZrm [HasAVX512]
vpmovsxdq {src, dst|dst, src}
VPMOVSXDQZrmk [HasAVX512]
vpmovsxdq {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVSXDQZrmkz [HasAVX512]
vpmovsxdq {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVSXDQZrr [HasAVX512]
vpmovsxdq {src, dst|dst, src}
VPMOVSXDQZrrk [HasAVX512]
vpmovsxdq {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVSXDQZrrkz [HasAVX512]
vpmovsxdq {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVSXWDZrm [HasAVX512]
vpmovsxwd {src, dst|dst, src}
VPMOVSXWDZrmk [HasAVX512]
vpmovsxwd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVSXWDZrmkz [HasAVX512]
vpmovsxwd {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVSXWDZrr [HasAVX512]
vpmovsxwd {src, dst|dst, src}
VPMOVSXWDZrrk [HasAVX512]
vpmovsxwd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVSXWDZrrkz [HasAVX512]
vpmovsxwd {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVSXWQZrm [HasAVX512]
vpmovsxwq {src, dst|dst, src}
VPMOVSXWQZrmk [HasAVX512]
vpmovsxwq {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVSXWQZrmkz [HasAVX512]
vpmovsxwq {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVSXWQZrr [HasAVX512]
vpmovsxwq {src, dst|dst, src}
VPMOVSXWQZrrk [HasAVX512]
vpmovsxwq {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVSXWQZrrkz [HasAVX512]
vpmovsxwq {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVUSDBZmr [HasAVX512]
vpmovusdb {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VPMOVUSDBZmrk [HasAVX512]
vpmovusdb {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
VPMOVUSDBZrr [HasAVX512]
vpmovusdb {src, dst|dst, src}
VPMOVUSDBZrrk [HasAVX512]
vpmovusdb {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVUSDBZrrkz [HasAVX512]
vpmovusdb {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVUSDWZmr [HasAVX512]
vpmovusdw {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VPMOVUSDWZmrk [HasAVX512]
vpmovusdw {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
VPMOVUSDWZrr [HasAVX512]
vpmovusdw {src, dst|dst, src}
VPMOVUSDWZrrk [HasAVX512]
vpmovusdw {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVUSDWZrrkz [HasAVX512]
vpmovusdw {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVUSQBZmr [HasAVX512]
vpmovusqb {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VPMOVUSQBZmrk [HasAVX512]
vpmovusqb {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
VPMOVUSQBZrr [HasAVX512]
vpmovusqb {src, dst|dst, src}
VPMOVUSQBZrrk [HasAVX512]
vpmovusqb {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVUSQBZrrkz [HasAVX512]
vpmovusqb {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVUSQDZmr [HasAVX512]
vpmovusqd {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VPMOVUSQDZmrk [HasAVX512]
vpmovusqd {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
VPMOVUSQDZrr [HasAVX512]
vpmovusqd {src, dst|dst, src}
VPMOVUSQDZrrk [HasAVX512]
vpmovusqd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVUSQDZrrkz [HasAVX512]
vpmovusqd {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVUSQWZmr [HasAVX512]
vpmovusqw {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VPMOVUSQWZmrk [HasAVX512]
vpmovusqw {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
VPMOVUSQWZrr [HasAVX512]
vpmovusqw {src, dst|dst, src}
VPMOVUSQWZrrk [HasAVX512]
vpmovusqw {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVUSQWZrrkz [HasAVX512]
vpmovusqw {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVZXBDZrm [HasAVX512]
vpmovzxbd {src, dst|dst, src}
VPMOVZXBDZrmk [HasAVX512]
vpmovzxbd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVZXBDZrmkz [HasAVX512]
vpmovzxbd {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVZXBDZrr [HasAVX512]
vpmovzxbd {src, dst|dst, src}
VPMOVZXBDZrrk [HasAVX512]
vpmovzxbd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVZXBDZrrkz [HasAVX512]
vpmovzxbd {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVZXBQZrm [HasAVX512]
vpmovzxbq {src, dst|dst, src}
VPMOVZXBQZrmk [HasAVX512]
vpmovzxbq {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVZXBQZrmkz [HasAVX512]
vpmovzxbq {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVZXBQZrr [HasAVX512]
vpmovzxbq {src, dst|dst, src}
VPMOVZXBQZrrk [HasAVX512]
vpmovzxbq {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVZXBQZrrkz [HasAVX512]
vpmovzxbq {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVZXDQZrm [HasAVX512]
vpmovzxdq {src, dst|dst, src}
VPMOVZXDQZrmk [HasAVX512]
vpmovzxdq {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVZXDQZrmkz [HasAVX512]
vpmovzxdq {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVZXDQZrr [HasAVX512]
vpmovzxdq {src, dst|dst, src}
VPMOVZXDQZrrk [HasAVX512]
vpmovzxdq {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVZXDQZrrkz [HasAVX512]
vpmovzxdq {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVZXWDZrm [HasAVX512]
vpmovzxwd {src, dst|dst, src}
VPMOVZXWDZrmk [HasAVX512]
vpmovzxwd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVZXWDZrmkz [HasAVX512]
vpmovzxwd {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVZXWDZrr [HasAVX512]
vpmovzxwd {src, dst|dst, src}
VPMOVZXWDZrrk [HasAVX512]
vpmovzxwd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVZXWDZrrkz [HasAVX512]
vpmovzxwd {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVZXWQZrm [HasAVX512]
vpmovzxwq {src, dst|dst, src}
VPMOVZXWQZrmk [HasAVX512]
vpmovzxwq {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVZXWQZrmkz [HasAVX512]
vpmovzxwq {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVZXWQZrr [HasAVX512]
vpmovzxwq {src, dst|dst, src}
VPMOVZXWQZrrk [HasAVX512]
vpmovzxwq {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVZXWQZrrkz [HasAVX512]
vpmovzxwq {src, dst {mask} {z}|dst {mask} {z}, src}
VPMULDQZrm [HasAVX512]
vpmuldq {src2, src1, dst|dst, src1, src2}
VPMULDQZrmb [HasAVX512]
vpmuldq {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
VPMULDQZrmbk [HasAVX512]
vpmuldq {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Constraints: src0 = dst |
VPMULDQZrmbkz [HasAVX512]
vpmuldq {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
VPMULDQZrmk [HasAVX512]
vpmuldq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMULDQZrmkz [HasAVX512]
vpmuldq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMULDQZrr [HasAVX512]
vpmuldq {src2, src1, dst|dst, src1, src2}
VPMULDQZrrk [HasAVX512]
vpmuldq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMULDQZrrkz [HasAVX512]
vpmuldq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMULLDZrm [HasAVX512]
vpmulld {src2, src1, dst|dst, src1, src2}
VPMULLDZrmb [HasAVX512]
vpmulld {src2{1to16}, src1, dst|dst, src1, src2{1to16}}
VPMULLDZrmbk [HasAVX512]
vpmulld {src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}}
|
Note
|
Constraints: src0 = dst |
VPMULLDZrmbkz [HasAVX512]
vpmulld {src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}}
VPMULLDZrmk [HasAVX512]
vpmulld {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMULLDZrmkz [HasAVX512]
vpmulld {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMULLDZrr [HasAVX512]
vpmulld {src2, src1, dst|dst, src1, src2}
VPMULLDZrrk [HasAVX512]
vpmulld {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMULLDZrrkz [HasAVX512]
vpmulld {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMULUDQZrm [HasAVX512]
vpmuludq {src2, src1, dst|dst, src1, src2}
VPMULUDQZrmb [HasAVX512]
vpmuludq {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
VPMULUDQZrmbk [HasAVX512]
vpmuludq {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Constraints: src0 = dst |
VPMULUDQZrmbkz [HasAVX512]
vpmuludq {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
VPMULUDQZrmk [HasAVX512]
vpmuludq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMULUDQZrmkz [HasAVX512]
vpmuludq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMULUDQZrr [HasAVX512]
vpmuludq {src2, src1, dst|dst, src1, src2}
VPMULUDQZrrk [HasAVX512]
vpmuludq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMULUDQZrrkz [HasAVX512]
vpmuludq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPORDZrm [HasAVX512]
vpord {src2, src1, dst|dst, src1, src2}
VPORDZrmb [HasAVX512]
vpord {src2{1to16}, src1, dst|dst, src1, src2{1to16}}
VPORDZrmbk [HasAVX512]
vpord {src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}}
|
Note
|
Constraints: src0 = dst |
VPORDZrmbkz [HasAVX512]
vpord {src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}}
VPORDZrmk [HasAVX512]
vpord {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPORDZrmkz [HasAVX512]
vpord {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPORDZrr [HasAVX512]
vpord {src2, src1, dst|dst, src1, src2}
VPORDZrrk [HasAVX512]
vpord {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPORDZrrkz [HasAVX512]
vpord {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPORQZrm [HasAVX512]
vporq {src2, src1, dst|dst, src1, src2}
VPORQZrmb [HasAVX512]
vporq {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
VPORQZrmbk [HasAVX512]
vporq {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Constraints: src0 = dst |
VPORQZrmbkz [HasAVX512]
vporq {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
VPORQZrmk [HasAVX512]
vporq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPORQZrmkz [HasAVX512]
vporq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPORQZrr [HasAVX512]
vporq {src2, src1, dst|dst, src1, src2}
VPORQZrrk [HasAVX512]
vporq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPORQZrrkz [HasAVX512]
vporq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPROLDZmbi [HasAVX512]
vprold {src2, src1{1to16}, dst|dst, src1{1to16}, src2}
VPROLDZmbik [HasAVX512]
vprold {src2, src1{1to16}, dst {mask}|dst {mask}, src1{1to16}, src2}
|
Note
|
Constraints: src0 = dst |
VPROLDZmbikz [HasAVX512]
vprold {src2, src1{1to16}, dst {mask} {z}|dst {mask} {z}, src1{1to16}, src2}
VPROLDZmi [HasAVX512]
vprold {src2, src1, dst|dst, src1, src2}
VPROLDZmik [HasAVX512]
vprold {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPROLDZmikz [HasAVX512]
vprold {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPROLDZri [HasAVX512]
vprold {src2, src1, dst|dst, src1, src2}
VPROLDZrik [HasAVX512]
vprold {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPROLDZrikz [HasAVX512]
vprold {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPROLQZmbi [HasAVX512]
vprolq {src2, src1{1to8}, dst|dst, src1{1to8}, src2}
VPROLQZmbik [HasAVX512]
vprolq {src2, src1{1to8}, dst {mask}|dst {mask}, src1{1to8}, src2}
|
Note
|
Constraints: src0 = dst |
VPROLQZmbikz [HasAVX512]
vprolq {src2, src1{1to8}, dst {mask} {z}|dst {mask} {z}, src1{1to8}, src2}
VPROLQZmi [HasAVX512]
vprolq {src2, src1, dst|dst, src1, src2}
VPROLQZmik [HasAVX512]
vprolq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPROLQZmikz [HasAVX512]
vprolq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPROLQZri [HasAVX512]
vprolq {src2, src1, dst|dst, src1, src2}
VPROLQZrik [HasAVX512]
vprolq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPROLQZrikz [HasAVX512]
vprolq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPROLVDZrm [HasAVX512]
vprolvd {src2, src1, dst|dst, src1, src2}
VPROLVDZrmb [HasAVX512]
vprolvd {src2{1to16}, src1, dst|dst, src1, src2{1to16}}
VPROLVDZrmbk [HasAVX512]
vprolvd {src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}}
|
Note
|
Constraints: src0 = dst |
VPROLVDZrmbkz [HasAVX512]
vprolvd {src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}}
VPROLVDZrmk [HasAVX512]
vprolvd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPROLVDZrmkz [HasAVX512]
vprolvd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPROLVDZrr [HasAVX512]
vprolvd {src2, src1, dst|dst, src1, src2}
VPROLVDZrrk [HasAVX512]
vprolvd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPROLVDZrrkz [HasAVX512]
vprolvd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPROLVQZrm [HasAVX512]
vprolvq {src2, src1, dst|dst, src1, src2}
VPROLVQZrmb [HasAVX512]
vprolvq {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
VPROLVQZrmbk [HasAVX512]
vprolvq {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Constraints: src0 = dst |
VPROLVQZrmbkz [HasAVX512]
vprolvq {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
VPROLVQZrmk [HasAVX512]
vprolvq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPROLVQZrmkz [HasAVX512]
vprolvq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPROLVQZrr [HasAVX512]
vprolvq {src2, src1, dst|dst, src1, src2}
VPROLVQZrrk [HasAVX512]
vprolvq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPROLVQZrrkz [HasAVX512]
vprolvq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPRORDZmbi [HasAVX512]
vprord {src2, src1{1to16}, dst|dst, src1{1to16}, src2}
VPRORDZmbik [HasAVX512]
vprord {src2, src1{1to16}, dst {mask}|dst {mask}, src1{1to16}, src2}
|
Note
|
Constraints: src0 = dst |
VPRORDZmbikz [HasAVX512]
vprord {src2, src1{1to16}, dst {mask} {z}|dst {mask} {z}, src1{1to16}, src2}
VPRORDZmi [HasAVX512]
vprord {src2, src1, dst|dst, src1, src2}
VPRORDZmik [HasAVX512]
vprord {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPRORDZmikz [HasAVX512]
vprord {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPRORDZri [HasAVX512]
vprord {src2, src1, dst|dst, src1, src2}
VPRORDZrik [HasAVX512]
vprord {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPRORDZrikz [HasAVX512]
vprord {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPRORQZmbi [HasAVX512]
vprorq {src2, src1{1to8}, dst|dst, src1{1to8}, src2}
VPRORQZmbik [HasAVX512]
vprorq {src2, src1{1to8}, dst {mask}|dst {mask}, src1{1to8}, src2}
|
Note
|
Constraints: src0 = dst |
VPRORQZmbikz [HasAVX512]
vprorq {src2, src1{1to8}, dst {mask} {z}|dst {mask} {z}, src1{1to8}, src2}
VPRORQZmi [HasAVX512]
vprorq {src2, src1, dst|dst, src1, src2}
VPRORQZmik [HasAVX512]
vprorq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPRORQZmikz [HasAVX512]
vprorq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPRORQZri [HasAVX512]
vprorq {src2, src1, dst|dst, src1, src2}
VPRORQZrik [HasAVX512]
vprorq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPRORQZrikz [HasAVX512]
vprorq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPRORVDZrm [HasAVX512]
vprorvd {src2, src1, dst|dst, src1, src2}
VPRORVDZrmb [HasAVX512]
vprorvd {src2{1to16}, src1, dst|dst, src1, src2{1to16}}
VPRORVDZrmbk [HasAVX512]
vprorvd {src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}}
|
Note
|
Constraints: src0 = dst |
VPRORVDZrmbkz [HasAVX512]
vprorvd {src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}}
VPRORVDZrmk [HasAVX512]
vprorvd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPRORVDZrmkz [HasAVX512]
vprorvd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPRORVDZrr [HasAVX512]
vprorvd {src2, src1, dst|dst, src1, src2}
VPRORVDZrrk [HasAVX512]
vprorvd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPRORVDZrrkz [HasAVX512]
vprorvd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPRORVQZrm [HasAVX512]
vprorvq {src2, src1, dst|dst, src1, src2}
VPRORVQZrmb [HasAVX512]
vprorvq {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
VPRORVQZrmbk [HasAVX512]
vprorvq {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Constraints: src0 = dst |
VPRORVQZrmbkz [HasAVX512]
vprorvq {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
VPRORVQZrmk [HasAVX512]
vprorvq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPRORVQZrmkz [HasAVX512]
vprorvq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPRORVQZrr [HasAVX512]
vprorvq {src2, src1, dst|dst, src1, src2}
VPRORVQZrrk [HasAVX512]
vprorvq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPRORVQZrrkz [HasAVX512]
vprorvq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSCATTERDDZmr [HasAVX512]
vpscatterdd {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
|
Note
|
Constraints: mask = mask_wb |
VPSCATTERDQZmr [HasAVX512]
vpscatterdq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
|
Note
|
Constraints: mask = mask_wb |
VPSCATTERQDZmr [HasAVX512]
vpscatterqd {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
|
Note
|
Constraints: mask = mask_wb |
VPSCATTERQQZmr [HasAVX512]
vpscatterqq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
|
Note
|
Constraints: mask = mask_wb |
VPSHUFDZmbi [HasAVX512]
vpshufd {src2, src1{1to16}, dst|dst, src1{1to16}, src2}
VPSHUFDZmbik [HasAVX512]
vpshufd {src2, src1{1to16}, dst {mask}|dst {mask}, src1{1to16}, src2}
|
Note
|
Constraints: src0 = dst |
VPSHUFDZmbikz [HasAVX512]
vpshufd {src2, src1{1to16}, dst {mask} {z}|dst {mask} {z}, src1{1to16}, src2}
VPSHUFDZmi [HasAVX512]
vpshufd {src2, src1, dst|dst, src1, src2}
VPSHUFDZmik [HasAVX512]
vpshufd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSHUFDZmikz [HasAVX512]
vpshufd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSHUFDZri [HasAVX512]
vpshufd {src2, src1, dst|dst, src1, src2}
VPSHUFDZrik [HasAVX512]
vpshufd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSHUFDZrikz [HasAVX512]
vpshufd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSLLDZmbi [HasAVX512]
vpslld {src2, src1{1to16}, dst|dst, src1{1to16}, src2}
VPSLLDZmbik [HasAVX512]
vpslld {src2, src1{1to16}, dst {mask}|dst {mask}, src1{1to16}, src2}
|
Note
|
Constraints: src0 = dst |
VPSLLDZmbikz [HasAVX512]
vpslld {src2, src1{1to16}, dst {mask} {z}|dst {mask} {z}, src1{1to16}, src2}
VPSLLDZmi [HasAVX512]
vpslld {src2, src1, dst|dst, src1, src2}
VPSLLDZmik [HasAVX512]
vpslld {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSLLDZmikz [HasAVX512]
vpslld {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSLLDZri [HasAVX512]
vpslld {src2, src1, dst|dst, src1, src2}
VPSLLDZrik [HasAVX512]
vpslld {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSLLDZrikz [HasAVX512]
vpslld {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSLLDZrm [HasAVX512]
vpslld {src2, src1, dst|dst, src1, src2}
VPSLLDZrmk [HasAVX512]
vpslld {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSLLDZrmkz [HasAVX512]
vpslld {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSLLDZrr [HasAVX512]
vpslld {src2, src1, dst|dst, src1, src2}
VPSLLDZrrk [HasAVX512]
vpslld {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSLLDZrrkz [HasAVX512]
vpslld {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSLLQZmbi [HasAVX512]
vpsllq {src2, src1{1to8}, dst|dst, src1{1to8}, src2}
VPSLLQZmbik [HasAVX512]
vpsllq {src2, src1{1to8}, dst {mask}|dst {mask}, src1{1to8}, src2}
|
Note
|
Constraints: src0 = dst |
VPSLLQZmbikz [HasAVX512]
vpsllq {src2, src1{1to8}, dst {mask} {z}|dst {mask} {z}, src1{1to8}, src2}
VPSLLQZmi [HasAVX512]
vpsllq {src2, src1, dst|dst, src1, src2}
VPSLLQZmik [HasAVX512]
vpsllq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSLLQZmikz [HasAVX512]
vpsllq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSLLQZri [HasAVX512]
vpsllq {src2, src1, dst|dst, src1, src2}
VPSLLQZrik [HasAVX512]
vpsllq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSLLQZrikz [HasAVX512]
vpsllq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSLLQZrm [HasAVX512]
vpsllq {src2, src1, dst|dst, src1, src2}
VPSLLQZrmk [HasAVX512]
vpsllq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSLLQZrmkz [HasAVX512]
vpsllq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSLLQZrr [HasAVX512]
vpsllq {src2, src1, dst|dst, src1, src2}
VPSLLQZrrk [HasAVX512]
vpsllq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSLLQZrrkz [HasAVX512]
vpsllq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSLLVDZrm [HasAVX512]
vpsllvd {src2, src1, dst|dst, src1, src2}
VPSLLVDZrmb [HasAVX512]
vpsllvd {src2{1to16}, src1, dst|dst, src1, src2{1to16}}
VPSLLVDZrmbk [HasAVX512]
vpsllvd {src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}}
|
Note
|
Constraints: src0 = dst |
VPSLLVDZrmbkz [HasAVX512]
vpsllvd {src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}}
VPSLLVDZrmk [HasAVX512]
vpsllvd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSLLVDZrmkz [HasAVX512]
vpsllvd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSLLVDZrr [HasAVX512]
vpsllvd {src2, src1, dst|dst, src1, src2}
VPSLLVDZrrk [HasAVX512]
vpsllvd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSLLVDZrrkz [HasAVX512]
vpsllvd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSLLVQZrm [HasAVX512]
vpsllvq {src2, src1, dst|dst, src1, src2}
VPSLLVQZrmb [HasAVX512]
vpsllvq {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
VPSLLVQZrmbk [HasAVX512]
vpsllvq {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Constraints: src0 = dst |
VPSLLVQZrmbkz [HasAVX512]
vpsllvq {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
VPSLLVQZrmk [HasAVX512]
vpsllvq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSLLVQZrmkz [HasAVX512]
vpsllvq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSLLVQZrr [HasAVX512]
vpsllvq {src2, src1, dst|dst, src1, src2}
VPSLLVQZrrk [HasAVX512]
vpsllvq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSLLVQZrrkz [HasAVX512]
vpsllvq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRADZmbi [HasAVX512]
vpsrad {src2, src1{1to16}, dst|dst, src1{1to16}, src2}
VPSRADZmbik [HasAVX512]
vpsrad {src2, src1{1to16}, dst {mask}|dst {mask}, src1{1to16}, src2}
|
Note
|
Constraints: src0 = dst |
VPSRADZmbikz [HasAVX512]
vpsrad {src2, src1{1to16}, dst {mask} {z}|dst {mask} {z}, src1{1to16}, src2}
VPSRADZmi [HasAVX512]
vpsrad {src2, src1, dst|dst, src1, src2}
VPSRADZmik [HasAVX512]
vpsrad {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRADZmikz [HasAVX512]
vpsrad {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRADZri [HasAVX512]
vpsrad {src2, src1, dst|dst, src1, src2}
VPSRADZrik [HasAVX512]
vpsrad {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRADZrikz [HasAVX512]
vpsrad {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRADZrm [HasAVX512]
vpsrad {src2, src1, dst|dst, src1, src2}
VPSRADZrmk [HasAVX512]
vpsrad {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRADZrmkz [HasAVX512]
vpsrad {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRADZrr [HasAVX512]
vpsrad {src2, src1, dst|dst, src1, src2}
VPSRADZrrk [HasAVX512]
vpsrad {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRADZrrkz [HasAVX512]
vpsrad {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRAQZmbi [HasAVX512]
vpsraq {src2, src1{1to8}, dst|dst, src1{1to8}, src2}
VPSRAQZmbik [HasAVX512]
vpsraq {src2, src1{1to8}, dst {mask}|dst {mask}, src1{1to8}, src2}
|
Note
|
Constraints: src0 = dst |
VPSRAQZmbikz [HasAVX512]
vpsraq {src2, src1{1to8}, dst {mask} {z}|dst {mask} {z}, src1{1to8}, src2}
VPSRAQZmi [HasAVX512]
vpsraq {src2, src1, dst|dst, src1, src2}
VPSRAQZmik [HasAVX512]
vpsraq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRAQZmikz [HasAVX512]
vpsraq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRAQZri [HasAVX512]
vpsraq {src2, src1, dst|dst, src1, src2}
VPSRAQZrik [HasAVX512]
vpsraq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRAQZrikz [HasAVX512]
vpsraq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRAQZrm [HasAVX512]
vpsraq {src2, src1, dst|dst, src1, src2}
VPSRAQZrmk [HasAVX512]
vpsraq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRAQZrmkz [HasAVX512]
vpsraq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRAQZrr [HasAVX512]
vpsraq {src2, src1, dst|dst, src1, src2}
VPSRAQZrrk [HasAVX512]
vpsraq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRAQZrrkz [HasAVX512]
vpsraq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRAVDZrm [HasAVX512]
vpsravd {src2, src1, dst|dst, src1, src2}
VPSRAVDZrmb [HasAVX512]
vpsravd {src2{1to16}, src1, dst|dst, src1, src2{1to16}}
VPSRAVDZrmbk [HasAVX512]
vpsravd {src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}}
|
Note
|
Constraints: src0 = dst |
VPSRAVDZrmbkz [HasAVX512]
vpsravd {src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}}
VPSRAVDZrmk [HasAVX512]
vpsravd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRAVDZrmkz [HasAVX512]
vpsravd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRAVDZrr [HasAVX512]
vpsravd {src2, src1, dst|dst, src1, src2}
VPSRAVDZrrk [HasAVX512]
vpsravd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRAVDZrrkz [HasAVX512]
vpsravd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRAVQZrm [HasAVX512]
vpsravq {src2, src1, dst|dst, src1, src2}
VPSRAVQZrmb [HasAVX512]
vpsravq {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
VPSRAVQZrmbk [HasAVX512]
vpsravq {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Constraints: src0 = dst |
VPSRAVQZrmbkz [HasAVX512]
vpsravq {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
VPSRAVQZrmk [HasAVX512]
vpsravq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRAVQZrmkz [HasAVX512]
vpsravq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRAVQZrr [HasAVX512]
vpsravq {src2, src1, dst|dst, src1, src2}
VPSRAVQZrrk [HasAVX512]
vpsravq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRAVQZrrkz [HasAVX512]
vpsravq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRLDZmbi [HasAVX512]
vpsrld {src2, src1{1to16}, dst|dst, src1{1to16}, src2}
VPSRLDZmbik [HasAVX512]
vpsrld {src2, src1{1to16}, dst {mask}|dst {mask}, src1{1to16}, src2}
|
Note
|
Constraints: src0 = dst |
VPSRLDZmbikz [HasAVX512]
vpsrld {src2, src1{1to16}, dst {mask} {z}|dst {mask} {z}, src1{1to16}, src2}
VPSRLDZmi [HasAVX512]
vpsrld {src2, src1, dst|dst, src1, src2}
VPSRLDZmik [HasAVX512]
vpsrld {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRLDZmikz [HasAVX512]
vpsrld {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRLDZri [HasAVX512]
vpsrld {src2, src1, dst|dst, src1, src2}
VPSRLDZrik [HasAVX512]
vpsrld {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRLDZrikz [HasAVX512]
vpsrld {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRLDZrm [HasAVX512]
vpsrld {src2, src1, dst|dst, src1, src2}
VPSRLDZrmk [HasAVX512]
vpsrld {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRLDZrmkz [HasAVX512]
vpsrld {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRLDZrr [HasAVX512]
vpsrld {src2, src1, dst|dst, src1, src2}
VPSRLDZrrk [HasAVX512]
vpsrld {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRLDZrrkz [HasAVX512]
vpsrld {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRLQZmbi [HasAVX512]
vpsrlq {src2, src1{1to8}, dst|dst, src1{1to8}, src2}
VPSRLQZmbik [HasAVX512]
vpsrlq {src2, src1{1to8}, dst {mask}|dst {mask}, src1{1to8}, src2}
|
Note
|
Constraints: src0 = dst |
VPSRLQZmbikz [HasAVX512]
vpsrlq {src2, src1{1to8}, dst {mask} {z}|dst {mask} {z}, src1{1to8}, src2}
VPSRLQZmi [HasAVX512]
vpsrlq {src2, src1, dst|dst, src1, src2}
VPSRLQZmik [HasAVX512]
vpsrlq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRLQZmikz [HasAVX512]
vpsrlq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRLQZri [HasAVX512]
vpsrlq {src2, src1, dst|dst, src1, src2}
VPSRLQZrik [HasAVX512]
vpsrlq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRLQZrikz [HasAVX512]
vpsrlq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRLQZrm [HasAVX512]
vpsrlq {src2, src1, dst|dst, src1, src2}
VPSRLQZrmk [HasAVX512]
vpsrlq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRLQZrmkz [HasAVX512]
vpsrlq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRLQZrr [HasAVX512]
vpsrlq {src2, src1, dst|dst, src1, src2}
VPSRLQZrrk [HasAVX512]
vpsrlq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRLQZrrkz [HasAVX512]
vpsrlq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRLVDZrm [HasAVX512]
vpsrlvd {src2, src1, dst|dst, src1, src2}
VPSRLVDZrmb [HasAVX512]
vpsrlvd {src2{1to16}, src1, dst|dst, src1, src2{1to16}}
VPSRLVDZrmbk [HasAVX512]
vpsrlvd {src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}}
|
Note
|
Constraints: src0 = dst |
VPSRLVDZrmbkz [HasAVX512]
vpsrlvd {src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}}
VPSRLVDZrmk [HasAVX512]
vpsrlvd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRLVDZrmkz [HasAVX512]
vpsrlvd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRLVDZrr [HasAVX512]
vpsrlvd {src2, src1, dst|dst, src1, src2}
VPSRLVDZrrk [HasAVX512]
vpsrlvd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRLVDZrrkz [HasAVX512]
vpsrlvd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRLVQZrm [HasAVX512]
vpsrlvq {src2, src1, dst|dst, src1, src2}
VPSRLVQZrmb [HasAVX512]
vpsrlvq {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
VPSRLVQZrmbk [HasAVX512]
vpsrlvq {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Constraints: src0 = dst |
VPSRLVQZrmbkz [HasAVX512]
vpsrlvq {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
VPSRLVQZrmk [HasAVX512]
vpsrlvq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRLVQZrmkz [HasAVX512]
vpsrlvq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRLVQZrr [HasAVX512]
vpsrlvq {src2, src1, dst|dst, src1, src2}
VPSRLVQZrrk [HasAVX512]
vpsrlvq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRLVQZrrkz [HasAVX512]
vpsrlvq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSUBDZrm [HasAVX512]
vpsubd {src2, src1, dst|dst, src1, src2}
VPSUBDZrmb [HasAVX512]
vpsubd {src2{1to16}, src1, dst|dst, src1, src2{1to16}}
VPSUBDZrmbk [HasAVX512]
vpsubd {src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}}
|
Note
|
Constraints: src0 = dst |
VPSUBDZrmbkz [HasAVX512]
vpsubd {src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}}
VPSUBDZrmk [HasAVX512]
vpsubd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSUBDZrmkz [HasAVX512]
vpsubd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSUBDZrr [HasAVX512]
vpsubd {src2, src1, dst|dst, src1, src2}
VPSUBDZrrk [HasAVX512]
vpsubd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSUBDZrrkz [HasAVX512]
vpsubd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSUBQZrm [HasAVX512]
vpsubq {src2, src1, dst|dst, src1, src2}
VPSUBQZrmb [HasAVX512]
vpsubq {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
VPSUBQZrmbk [HasAVX512]
vpsubq {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Constraints: src0 = dst |
VPSUBQZrmbkz [HasAVX512]
vpsubq {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
VPSUBQZrmk [HasAVX512]
vpsubq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSUBQZrmkz [HasAVX512]
vpsubq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSUBQZrr [HasAVX512]
vpsubq {src2, src1, dst|dst, src1, src2}
VPSUBQZrrk [HasAVX512]
vpsubq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSUBQZrrkz [HasAVX512]
vpsubq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPTERNLOGDZrmbi [HasAVX512]
vpternlogd {src4, src3{1to16}, src2, dst|dst, src2, src3{1to16}, src4}
|
Note
|
Constraints: src1 = dst |
VPTERNLOGDZrmbik [HasAVX512]
vpternlogd {src4, src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}, src4}
|
Note
|
Constraints: src1 = dst |
VPTERNLOGDZrmbikz [HasAVX512]
vpternlogd {src4, src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}, src4}
|
Note
|
Constraints: src1 = dst |
VPTERNLOGDZrmi [HasAVX512]
vpternlogd {src4, src3, src2, dst|dst, src2, src3, src4}
|
Note
|
Constraints: src1 = dst |
VPTERNLOGDZrmik [HasAVX512]
vpternlogd {src4, src3, src2, dst {mask}|dst {mask}, src2, src3, src4}
|
Note
|
Constraints: src1 = dst |
VPTERNLOGDZrmikz [HasAVX512]
vpternlogd {src4, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, src4}
|
Note
|
Constraints: src1 = dst |
VPTERNLOGDZrri [HasAVX512]
vpternlogd {src4, src3, src2, dst|dst, src2, src3, src4}
|
Note
|
Constraints: src1 = dst |
VPTERNLOGDZrrik [HasAVX512]
vpternlogd {src4, src3, src2, dst {mask}|dst {mask}, src2, src3, src4}
|
Note
|
Constraints: src1 = dst |
VPTERNLOGDZrrikz [HasAVX512]
vpternlogd {src4, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, src4}
|
Note
|
Constraints: src1 = dst |
VPTERNLOGQZrmbi [HasAVX512]
vpternlogq {src4, src3{1to8}, src2, dst|dst, src2, src3{1to8}, src4}
|
Note
|
Constraints: src1 = dst |
VPTERNLOGQZrmbik [HasAVX512]
vpternlogq {src4, src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}, src4}
|
Note
|
Constraints: src1 = dst |
VPTERNLOGQZrmbikz [HasAVX512]
vpternlogq {src4, src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}, src4}
|
Note
|
Constraints: src1 = dst |
VPTERNLOGQZrmi [HasAVX512]
vpternlogq {src4, src3, src2, dst|dst, src2, src3, src4}
|
Note
|
Constraints: src1 = dst |
VPTERNLOGQZrmik [HasAVX512]
vpternlogq {src4, src3, src2, dst {mask}|dst {mask}, src2, src3, src4}
|
Note
|
Constraints: src1 = dst |
VPTERNLOGQZrmikz [HasAVX512]
vpternlogq {src4, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, src4}
|
Note
|
Constraints: src1 = dst |
VPTERNLOGQZrri [HasAVX512]
vpternlogq {src4, src3, src2, dst|dst, src2, src3, src4}
|
Note
|
Constraints: src1 = dst |
VPTERNLOGQZrrik [HasAVX512]
vpternlogq {src4, src3, src2, dst {mask}|dst {mask}, src2, src3, src4}
|
Note
|
Constraints: src1 = dst |
VPTERNLOGQZrrikz [HasAVX512]
vpternlogq {src4, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, src4}
|
Note
|
Constraints: src1 = dst |
VPTESTMDZrm [HasAVX512]
vptestmd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VPTESTMDZrmb [HasAVX512]
vptestmd {src2{1to16}, src1, dst|dst, src1, src2{1to16}}
|
Note
|
Properties: mayLoad |
VPTESTMDZrmbk [HasAVX512]
vptestmd {src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}}
|
Note
|
Properties: mayLoad |
VPTESTMDZrmk [HasAVX512]
vptestmd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
VPTESTMDZrr [HasAVX512]
vptestmd {src2, src1, dst|dst, src1, src2}
VPTESTMDZrrk [HasAVX512]
vptestmd {src2, src1, dst {mask}|dst {mask}, src1, src2}
VPTESTMQZrm [HasAVX512]
vptestmq {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VPTESTMQZrmb [HasAVX512]
vptestmq {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
VPTESTMQZrmbk [HasAVX512]
vptestmq {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
VPTESTMQZrmk [HasAVX512]
vptestmq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
VPTESTMQZrr [HasAVX512]
vptestmq {src2, src1, dst|dst, src1, src2}
VPTESTMQZrrk [HasAVX512]
vptestmq {src2, src1, dst {mask}|dst {mask}, src1, src2}
VPTESTNMDZrm [HasAVX512]
vptestnmd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VPTESTNMDZrmb [HasAVX512]
vptestnmd {src2{1to16}, src1, dst|dst, src1, src2{1to16}}
|
Note
|
Properties: mayLoad |
VPTESTNMDZrmbk [HasAVX512]
vptestnmd {src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}}
|
Note
|
Properties: mayLoad |
VPTESTNMDZrmk [HasAVX512]
vptestnmd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
VPTESTNMDZrr [HasAVX512]
vptestnmd {src2, src1, dst|dst, src1, src2}
VPTESTNMDZrrk [HasAVX512]
vptestnmd {src2, src1, dst {mask}|dst {mask}, src1, src2}
VPTESTNMQZrm [HasAVX512]
vptestnmq {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VPTESTNMQZrmb [HasAVX512]
vptestnmq {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
VPTESTNMQZrmbk [HasAVX512]
vptestnmq {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
VPTESTNMQZrmk [HasAVX512]
vptestnmq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
VPTESTNMQZrr [HasAVX512]
vptestnmq {src2, src1, dst|dst, src1, src2}
VPTESTNMQZrrk [HasAVX512]
vptestnmq {src2, src1, dst {mask}|dst {mask}, src1, src2}
VPUNPCKHDQZrm [HasAVX512]
vpunpckhdq {src2, src1, dst|dst, src1, src2}
VPUNPCKHDQZrmb [HasAVX512]
vpunpckhdq {src2{1to16}, src1, dst|dst, src1, src2{1to16}}
VPUNPCKHDQZrmbk [HasAVX512]
vpunpckhdq {src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}}
|
Note
|
Constraints: src0 = dst |
VPUNPCKHDQZrmbkz [HasAVX512]
vpunpckhdq {src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}}
VPUNPCKHDQZrmk [HasAVX512]
vpunpckhdq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPUNPCKHDQZrmkz [HasAVX512]
vpunpckhdq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPUNPCKHDQZrr [HasAVX512]
vpunpckhdq {src2, src1, dst|dst, src1, src2}
VPUNPCKHDQZrrk [HasAVX512]
vpunpckhdq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPUNPCKHDQZrrkz [HasAVX512]
vpunpckhdq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPUNPCKHQDQZrm [HasAVX512]
vpunpckhqdq {src2, src1, dst|dst, src1, src2}
VPUNPCKHQDQZrmb [HasAVX512]
vpunpckhqdq {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
VPUNPCKHQDQZrmbk [HasAVX512]
vpunpckhqdq {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Constraints: src0 = dst |
VPUNPCKHQDQZrmbkz [HasAVX512]
vpunpckhqdq {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
VPUNPCKHQDQZrmk [HasAVX512]
vpunpckhqdq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPUNPCKHQDQZrmkz [HasAVX512]
vpunpckhqdq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPUNPCKHQDQZrr [HasAVX512]
vpunpckhqdq {src2, src1, dst|dst, src1, src2}
VPUNPCKHQDQZrrk [HasAVX512]
vpunpckhqdq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPUNPCKHQDQZrrkz [HasAVX512]
vpunpckhqdq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPUNPCKLDQZrm [HasAVX512]
vpunpckldq {src2, src1, dst|dst, src1, src2}
VPUNPCKLDQZrmb [HasAVX512]
vpunpckldq {src2{1to16}, src1, dst|dst, src1, src2{1to16}}
VPUNPCKLDQZrmbk [HasAVX512]
vpunpckldq {src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}}
|
Note
|
Constraints: src0 = dst |
VPUNPCKLDQZrmbkz [HasAVX512]
vpunpckldq {src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}}
VPUNPCKLDQZrmk [HasAVX512]
vpunpckldq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPUNPCKLDQZrmkz [HasAVX512]
vpunpckldq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPUNPCKLDQZrr [HasAVX512]
vpunpckldq {src2, src1, dst|dst, src1, src2}
VPUNPCKLDQZrrk [HasAVX512]
vpunpckldq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPUNPCKLDQZrrkz [HasAVX512]
vpunpckldq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPUNPCKLQDQZrm [HasAVX512]
vpunpcklqdq {src2, src1, dst|dst, src1, src2}
VPUNPCKLQDQZrmb [HasAVX512]
vpunpcklqdq {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
VPUNPCKLQDQZrmbk [HasAVX512]
vpunpcklqdq {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Constraints: src0 = dst |
VPUNPCKLQDQZrmbkz [HasAVX512]
vpunpcklqdq {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
VPUNPCKLQDQZrmk [HasAVX512]
vpunpcklqdq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPUNPCKLQDQZrmkz [HasAVX512]
vpunpcklqdq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPUNPCKLQDQZrr [HasAVX512]
vpunpcklqdq {src2, src1, dst|dst, src1, src2}
VPUNPCKLQDQZrrk [HasAVX512]
vpunpcklqdq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPUNPCKLQDQZrrkz [HasAVX512]
vpunpcklqdq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPXORDZrm [HasAVX512]
vpxord {src2, src1, dst|dst, src1, src2}
VPXORDZrmb [HasAVX512]
vpxord {src2{1to16}, src1, dst|dst, src1, src2{1to16}}
VPXORDZrmbk [HasAVX512]
vpxord {src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}}
|
Note
|
Constraints: src0 = dst |
VPXORDZrmbkz [HasAVX512]
vpxord {src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}}
VPXORDZrmk [HasAVX512]
vpxord {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPXORDZrmkz [HasAVX512]
vpxord {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPXORDZrr [HasAVX512]
vpxord {src2, src1, dst|dst, src1, src2}
VPXORDZrrk [HasAVX512]
vpxord {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPXORDZrrkz [HasAVX512]
vpxord {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPXORQZrm [HasAVX512]
vpxorq {src2, src1, dst|dst, src1, src2}
VPXORQZrmb [HasAVX512]
vpxorq {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
VPXORQZrmbk [HasAVX512]
vpxorq {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Constraints: src0 = dst |
VPXORQZrmbkz [HasAVX512]
vpxorq {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
VPXORQZrmk [HasAVX512]
vpxorq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPXORQZrmkz [HasAVX512]
vpxorq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPXORQZrr [HasAVX512]
vpxorq {src2, src1, dst|dst, src1, src2}
VPXORQZrrk [HasAVX512]
vpxorq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPXORQZrrkz [HasAVX512]
vpxorq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VRCP14PDZm [HasAVX512]
vrcp14pd {src, dst|dst, src}
VRCP14PDZmb [HasAVX512]
vrcp14pd {src{1to8}, dst|dst, src{1to8}}
VRCP14PDZmbk [HasAVX512]
vrcp14pd {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Constraints: src0 = dst |
VRCP14PDZmbkz [HasAVX512]
vrcp14pd {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
VRCP14PDZmk [HasAVX512]
vrcp14pd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VRCP14PDZmkz [HasAVX512]
vrcp14pd {src, dst {mask} {z}|dst {mask} {z}, src}
VRCP14PDZr [HasAVX512]
vrcp14pd {src, dst|dst, src}
VRCP14PDZrk [HasAVX512]
vrcp14pd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VRCP14PDZrkz [HasAVX512]
vrcp14pd {src, dst {mask} {z}|dst {mask} {z}, src}
VRCP14PSZm [HasAVX512]
vrcp14ps {src, dst|dst, src}
VRCP14PSZmb [HasAVX512]
vrcp14ps {src{1to16}, dst|dst, src{1to16}}
VRCP14PSZmbk [HasAVX512]
vrcp14ps {src{1to16}, dst {mask}|dst {mask}, src{1to16}}
|
Note
|
Constraints: src0 = dst |
VRCP14PSZmbkz [HasAVX512]
vrcp14ps {src{1to16}, dst {mask} {z}|dst {mask} {z}, src{1to16}}
VRCP14PSZmk [HasAVX512]
vrcp14ps {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VRCP14PSZmkz [HasAVX512]
vrcp14ps {src, dst {mask} {z}|dst {mask} {z}, src}
VRCP14PSZr [HasAVX512]
vrcp14ps {src, dst|dst, src}
VRCP14PSZrk [HasAVX512]
vrcp14ps {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VRCP14PSZrkz [HasAVX512]
vrcp14ps {src, dst {mask} {z}|dst {mask} {z}, src}
VRCP14SDZrm [HasAVX512]
vrcp14sd {src2, src1, dst|dst, src1, src2}
VRCP14SDZrmk [HasAVX512]
vrcp14sd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VRCP14SDZrmkz [HasAVX512]
vrcp14sd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VRCP14SDZrr [HasAVX512]
vrcp14sd {src2, src1, dst|dst, src1, src2}
VRCP14SDZrrk [HasAVX512]
vrcp14sd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VRCP14SDZrrkz [HasAVX512]
vrcp14sd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VRCP14SSZrm [HasAVX512]
vrcp14ss {src2, src1, dst|dst, src1, src2}
VRCP14SSZrmk [HasAVX512]
vrcp14ss {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VRCP14SSZrmkz [HasAVX512]
vrcp14ss {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VRCP14SSZrr [HasAVX512]
vrcp14ss {src2, src1, dst|dst, src1, src2}
VRCP14SSZrrk [HasAVX512]
vrcp14ss {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VRCP14SSZrrkz [HasAVX512]
vrcp14ss {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VRCP28PDZm [HasAVX512]
vrcp28pd {src, dst|dst, src}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VRCP28PDZmb [HasAVX512]
vrcp28pd {src{1to8}, dst|dst, src{1to8}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VRCP28PDZmbk [HasAVX512]
vrcp28pd {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRCP28PDZmbkz [HasAVX512]
vrcp28pd {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VRCP28PDZmk [HasAVX512]
vrcp28pd {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRCP28PDZmkz [HasAVX512]
vrcp28pd {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VRCP28PDZr [HasAVX512]
vrcp28pd {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VRCP28PDZrb [HasAVX512]
vrcp28pd {{sae}, src, dst|dst, src, {sae}}
VRCP28PDZrbk [HasAVX512]
vrcp28pd {{sae}, src, dst {mask}|dst {mask}, src, {sae}}
|
Note
|
Constraints: src0 = dst |
VRCP28PDZrbkz [HasAVX512]
vrcp28pd {{sae}, src, dst {mask} {z}|dst {mask} {z}, src, {sae}}
VRCP28PDZrk [HasAVX512]
vrcp28pd {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRCP28PDZrkz [HasAVX512]
vrcp28pd {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VRCP28PSZm [HasAVX512]
vrcp28ps {src, dst|dst, src}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VRCP28PSZmb [HasAVX512]
vrcp28ps {src{1to16}, dst|dst, src{1to16}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VRCP28PSZmbk [HasAVX512]
vrcp28ps {src{1to16}, dst {mask}|dst {mask}, src{1to16}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRCP28PSZmbkz [HasAVX512]
vrcp28ps {src{1to16}, dst {mask} {z}|dst {mask} {z}, src{1to16}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VRCP28PSZmk [HasAVX512]
vrcp28ps {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRCP28PSZmkz [HasAVX512]
vrcp28ps {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VRCP28PSZr [HasAVX512]
vrcp28ps {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VRCP28PSZrb [HasAVX512]
vrcp28ps {{sae}, src, dst|dst, src, {sae}}
VRCP28PSZrbk [HasAVX512]
vrcp28ps {{sae}, src, dst {mask}|dst {mask}, src, {sae}}
|
Note
|
Constraints: src0 = dst |
VRCP28PSZrbkz [HasAVX512]
vrcp28ps {{sae}, src, dst {mask} {z}|dst {mask} {z}, src, {sae}}
VRCP28PSZrk [HasAVX512]
vrcp28ps {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRCP28PSZrkz [HasAVX512]
vrcp28ps {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VRCP28SDZm [HasAVX512]
vrcp28sd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VRCP28SDZmk [HasAVX512]
vrcp28sd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRCP28SDZmkz [HasAVX512]
vrcp28sd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VRCP28SDZr [HasAVX512]
vrcp28sd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VRCP28SDZrb [HasAVX512]
vrcp28sd {{sae}, src2, src1, dst|dst, src1, src2, {sae}}
VRCP28SDZrbk [HasAVX512]
vrcp28sd {{sae}, src2, src1, dst {mask}|dst {mask}, src1, src2, {sae}}
|
Note
|
Constraints: src0 = dst |
VRCP28SDZrbkz [HasAVX512]
vrcp28sd {{sae}, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, {sae}}
VRCP28SDZrk [HasAVX512]
vrcp28sd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRCP28SDZrkz [HasAVX512]
vrcp28sd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VRCP28SSZm [HasAVX512]
vrcp28ss {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VRCP28SSZmk [HasAVX512]
vrcp28ss {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRCP28SSZmkz [HasAVX512]
vrcp28ss {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VRCP28SSZr [HasAVX512]
vrcp28ss {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VRCP28SSZrb [HasAVX512]
vrcp28ss {{sae}, src2, src1, dst|dst, src1, src2, {sae}}
VRCP28SSZrbk [HasAVX512]
vrcp28ss {{sae}, src2, src1, dst {mask}|dst {mask}, src1, src2, {sae}}
|
Note
|
Constraints: src0 = dst |
VRCP28SSZrbkz [HasAVX512]
vrcp28ss {{sae}, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, {sae}}
VRCP28SSZrk [HasAVX512]
vrcp28ss {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRCP28SSZrkz [HasAVX512]
vrcp28ss {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VRNDSCALEPDZrmbi [HasAVX512]
vrndscalepd {src2, src1{1to8}, dst|dst, src1{1to8}, src2}
|
Note
|
Properties: mayRaiseFPException |
VRNDSCALEPDZrmbik [HasAVX512]
vrndscalepd {src2, src1{1to8}, dst {mask}|dst {mask}, src1{1to8}, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRNDSCALEPDZrmbikz [HasAVX512]
vrndscalepd {src2, src1{1to8}, dst {mask} {z}|dst {mask} {z}, src1{1to8}, src2}
|
Note
|
Properties: mayRaiseFPException |
VRNDSCALEPDZrmi [HasAVX512]
vrndscalepd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VRNDSCALEPDZrmik [HasAVX512]
vrndscalepd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRNDSCALEPDZrmikz [HasAVX512]
vrndscalepd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VRNDSCALEPDZrri [HasAVX512]
vrndscalepd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VRNDSCALEPDZrrib [HasAVX512]
vrndscalepd {src2, {sae}, src1, dst|dst, src1, {sae}, src2}
VRNDSCALEPDZrribk [HasAVX512]
vrndscalepd {src2, {sae}, src1, dst {mask}|dst {mask}, src1, {sae}, src2}
|
Note
|
Constraints: src0 = dst |
VRNDSCALEPDZrribkz [HasAVX512]
vrndscalepd {src2, {sae}, src1, dst {mask} {z}|dst {mask} {z}, src1, {sae}, src2}
VRNDSCALEPDZrrik [HasAVX512]
vrndscalepd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRNDSCALEPDZrrikz [HasAVX512]
vrndscalepd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VRNDSCALEPSZrmbi [HasAVX512]
vrndscaleps {src2, src1{1to16}, dst|dst, src1{1to16}, src2}
|
Note
|
Properties: mayRaiseFPException |
VRNDSCALEPSZrmbik [HasAVX512]
vrndscaleps {src2, src1{1to16}, dst {mask}|dst {mask}, src1{1to16}, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRNDSCALEPSZrmbikz [HasAVX512]
vrndscaleps {src2, src1{1to16}, dst {mask} {z}|dst {mask} {z}, src1{1to16}, src2}
|
Note
|
Properties: mayRaiseFPException |
VRNDSCALEPSZrmi [HasAVX512]
vrndscaleps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VRNDSCALEPSZrmik [HasAVX512]
vrndscaleps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRNDSCALEPSZrmikz [HasAVX512]
vrndscaleps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VRNDSCALEPSZrri [HasAVX512]
vrndscaleps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VRNDSCALEPSZrrib [HasAVX512]
vrndscaleps {src2, {sae}, src1, dst|dst, src1, {sae}, src2}
VRNDSCALEPSZrribk [HasAVX512]
vrndscaleps {src2, {sae}, src1, dst {mask}|dst {mask}, src1, {sae}, src2}
|
Note
|
Constraints: src0 = dst |
VRNDSCALEPSZrribkz [HasAVX512]
vrndscaleps {src2, {sae}, src1, dst {mask} {z}|dst {mask} {z}, src1, {sae}, src2}
VRNDSCALEPSZrrik [HasAVX512]
vrndscaleps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRNDSCALEPSZrrikz [HasAVX512]
vrndscaleps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VRNDSCALESDZrmi_Int [HasAVX512]
vrndscalesd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VRNDSCALESDZrmik_Int [HasAVX512]
vrndscalesd {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRNDSCALESDZrmikz_Int [HasAVX512]
vrndscalesd {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VRNDSCALESDZrri_Int [HasAVX512]
vrndscalesd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VRNDSCALESDZrrib_Int [HasAVX512]
vrndscalesd {src3, {sae}, src2, src1, dst|dst, src1, src2, {sae}, src3}
VRNDSCALESDZrribk_Int [HasAVX512]
vrndscalesd {src3, {sae}, src2, src1, dst {mask}|dst {mask}, src1, src2, {sae}, src3}
|
Note
|
Constraints: src0 = dst |
VRNDSCALESDZrribkz_Int [HasAVX512]
vrndscalesd {src3, {sae}, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, {sae}, src3}
VRNDSCALESDZrrik_Int [HasAVX512]
vrndscalesd {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRNDSCALESDZrrikz_Int [HasAVX512]
vrndscalesd {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VRNDSCALESSZrmi_Int [HasAVX512]
vrndscaless {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VRNDSCALESSZrmik_Int [HasAVX512]
vrndscaless {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRNDSCALESSZrmikz_Int [HasAVX512]
vrndscaless {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VRNDSCALESSZrri_Int [HasAVX512]
vrndscaless {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VRNDSCALESSZrrib_Int [HasAVX512]
vrndscaless {src3, {sae}, src2, src1, dst|dst, src1, src2, {sae}, src3}
VRNDSCALESSZrribk_Int [HasAVX512]
vrndscaless {src3, {sae}, src2, src1, dst {mask}|dst {mask}, src1, src2, {sae}, src3}
|
Note
|
Constraints: src0 = dst |
VRNDSCALESSZrribkz_Int [HasAVX512]
vrndscaless {src3, {sae}, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, {sae}, src3}
VRNDSCALESSZrrik_Int [HasAVX512]
vrndscaless {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRNDSCALESSZrrikz_Int [HasAVX512]
vrndscaless {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VRSQRT14PDZm [HasAVX512]
vrsqrt14pd {src, dst|dst, src}
VRSQRT14PDZmb [HasAVX512]
vrsqrt14pd {src{1to8}, dst|dst, src{1to8}}
VRSQRT14PDZmbk [HasAVX512]
vrsqrt14pd {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Constraints: src0 = dst |
VRSQRT14PDZmbkz [HasAVX512]
vrsqrt14pd {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
VRSQRT14PDZmk [HasAVX512]
vrsqrt14pd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VRSQRT14PDZmkz [HasAVX512]
vrsqrt14pd {src, dst {mask} {z}|dst {mask} {z}, src}
VRSQRT14PDZr [HasAVX512]
vrsqrt14pd {src, dst|dst, src}
VRSQRT14PDZrk [HasAVX512]
vrsqrt14pd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VRSQRT14PDZrkz [HasAVX512]
vrsqrt14pd {src, dst {mask} {z}|dst {mask} {z}, src}
VRSQRT14PSZm [HasAVX512]
vrsqrt14ps {src, dst|dst, src}
VRSQRT14PSZmb [HasAVX512]
vrsqrt14ps {src{1to16}, dst|dst, src{1to16}}
VRSQRT14PSZmbk [HasAVX512]
vrsqrt14ps {src{1to16}, dst {mask}|dst {mask}, src{1to16}}
|
Note
|
Constraints: src0 = dst |
VRSQRT14PSZmbkz [HasAVX512]
vrsqrt14ps {src{1to16}, dst {mask} {z}|dst {mask} {z}, src{1to16}}
VRSQRT14PSZmk [HasAVX512]
vrsqrt14ps {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VRSQRT14PSZmkz [HasAVX512]
vrsqrt14ps {src, dst {mask} {z}|dst {mask} {z}, src}
VRSQRT14PSZr [HasAVX512]
vrsqrt14ps {src, dst|dst, src}
VRSQRT14PSZrk [HasAVX512]
vrsqrt14ps {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VRSQRT14PSZrkz [HasAVX512]
vrsqrt14ps {src, dst {mask} {z}|dst {mask} {z}, src}
VRSQRT14SDZrm [HasAVX512]
vrsqrt14sd {src2, src1, dst|dst, src1, src2}
VRSQRT14SDZrmk [HasAVX512]
vrsqrt14sd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VRSQRT14SDZrmkz [HasAVX512]
vrsqrt14sd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VRSQRT14SDZrr [HasAVX512]
vrsqrt14sd {src2, src1, dst|dst, src1, src2}
VRSQRT14SDZrrk [HasAVX512]
vrsqrt14sd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VRSQRT14SDZrrkz [HasAVX512]
vrsqrt14sd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VRSQRT14SSZrm [HasAVX512]
vrsqrt14ss {src2, src1, dst|dst, src1, src2}
VRSQRT14SSZrmk [HasAVX512]
vrsqrt14ss {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VRSQRT14SSZrmkz [HasAVX512]
vrsqrt14ss {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VRSQRT14SSZrr [HasAVX512]
vrsqrt14ss {src2, src1, dst|dst, src1, src2}
VRSQRT14SSZrrk [HasAVX512]
vrsqrt14ss {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VRSQRT14SSZrrkz [HasAVX512]
vrsqrt14ss {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VRSQRT28PDZm [HasAVX512]
vrsqrt28pd {src, dst|dst, src}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VRSQRT28PDZmb [HasAVX512]
vrsqrt28pd {src{1to8}, dst|dst, src{1to8}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VRSQRT28PDZmbk [HasAVX512]
vrsqrt28pd {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRSQRT28PDZmbkz [HasAVX512]
vrsqrt28pd {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VRSQRT28PDZmk [HasAVX512]
vrsqrt28pd {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRSQRT28PDZmkz [HasAVX512]
vrsqrt28pd {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VRSQRT28PDZr [HasAVX512]
vrsqrt28pd {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VRSQRT28PDZrb [HasAVX512]
vrsqrt28pd {{sae}, src, dst|dst, src, {sae}}
VRSQRT28PDZrbk [HasAVX512]
vrsqrt28pd {{sae}, src, dst {mask}|dst {mask}, src, {sae}}
|
Note
|
Constraints: src0 = dst |
VRSQRT28PDZrbkz [HasAVX512]
vrsqrt28pd {{sae}, src, dst {mask} {z}|dst {mask} {z}, src, {sae}}
VRSQRT28PDZrk [HasAVX512]
vrsqrt28pd {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRSQRT28PDZrkz [HasAVX512]
vrsqrt28pd {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VRSQRT28PSZm [HasAVX512]
vrsqrt28ps {src, dst|dst, src}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VRSQRT28PSZmb [HasAVX512]
vrsqrt28ps {src{1to16}, dst|dst, src{1to16}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VRSQRT28PSZmbk [HasAVX512]
vrsqrt28ps {src{1to16}, dst {mask}|dst {mask}, src{1to16}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRSQRT28PSZmbkz [HasAVX512]
vrsqrt28ps {src{1to16}, dst {mask} {z}|dst {mask} {z}, src{1to16}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VRSQRT28PSZmk [HasAVX512]
vrsqrt28ps {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRSQRT28PSZmkz [HasAVX512]
vrsqrt28ps {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VRSQRT28PSZr [HasAVX512]
vrsqrt28ps {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VRSQRT28PSZrb [HasAVX512]
vrsqrt28ps {{sae}, src, dst|dst, src, {sae}}
VRSQRT28PSZrbk [HasAVX512]
vrsqrt28ps {{sae}, src, dst {mask}|dst {mask}, src, {sae}}
|
Note
|
Constraints: src0 = dst |
VRSQRT28PSZrbkz [HasAVX512]
vrsqrt28ps {{sae}, src, dst {mask} {z}|dst {mask} {z}, src, {sae}}
VRSQRT28PSZrk [HasAVX512]
vrsqrt28ps {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRSQRT28PSZrkz [HasAVX512]
vrsqrt28ps {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VRSQRT28SDZm [HasAVX512]
vrsqrt28sd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VRSQRT28SDZmk [HasAVX512]
vrsqrt28sd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRSQRT28SDZmkz [HasAVX512]
vrsqrt28sd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VRSQRT28SDZr [HasAVX512]
vrsqrt28sd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VRSQRT28SDZrb [HasAVX512]
vrsqrt28sd {{sae}, src2, src1, dst|dst, src1, src2, {sae}}
VRSQRT28SDZrbk [HasAVX512]
vrsqrt28sd {{sae}, src2, src1, dst {mask}|dst {mask}, src1, src2, {sae}}
|
Note
|
Constraints: src0 = dst |
VRSQRT28SDZrbkz [HasAVX512]
vrsqrt28sd {{sae}, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, {sae}}
VRSQRT28SDZrk [HasAVX512]
vrsqrt28sd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRSQRT28SDZrkz [HasAVX512]
vrsqrt28sd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VRSQRT28SSZm [HasAVX512]
vrsqrt28ss {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VRSQRT28SSZmk [HasAVX512]
vrsqrt28ss {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRSQRT28SSZmkz [HasAVX512]
vrsqrt28ss {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VRSQRT28SSZr [HasAVX512]
vrsqrt28ss {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VRSQRT28SSZrb [HasAVX512]
vrsqrt28ss {{sae}, src2, src1, dst|dst, src1, src2, {sae}}
VRSQRT28SSZrbk [HasAVX512]
vrsqrt28ss {{sae}, src2, src1, dst {mask}|dst {mask}, src1, src2, {sae}}
|
Note
|
Constraints: src0 = dst |
VRSQRT28SSZrbkz [HasAVX512]
vrsqrt28ss {{sae}, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, {sae}}
VRSQRT28SSZrk [HasAVX512]
vrsqrt28ss {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRSQRT28SSZrkz [HasAVX512]
vrsqrt28ss {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSCALEFPDZrm [HasAVX512]
vscalefpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSCALEFPDZrmb [HasAVX512]
vscalefpd {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VSCALEFPDZrmbk [HasAVX512]
vscalefpd {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSCALEFPDZrmbkz [HasAVX512]
vscalefpd {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VSCALEFPDZrmk [HasAVX512]
vscalefpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSCALEFPDZrmkz [HasAVX512]
vscalefpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSCALEFPDZrr [HasAVX512]
vscalefpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSCALEFPDZrrb [HasAVX512]
vscalefpd {rc, src2, src1, dst|dst, src1, src2, rc}
VSCALEFPDZrrbk [HasAVX512]
vscalefpd {rc, src2, src1, dst {mask}|dst {mask}, src1, src2, rc}
|
Note
|
Constraints: src0 = dst |
VSCALEFPDZrrbkz [HasAVX512]
vscalefpd {rc, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, rc}
VSCALEFPDZrrk [HasAVX512]
vscalefpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSCALEFPDZrrkz [HasAVX512]
vscalefpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSCALEFPSZrm [HasAVX512]
vscalefps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSCALEFPSZrmb [HasAVX512]
vscalefps {src2{1to16}, src1, dst|dst, src1, src2{1to16}}
|
Note
|
Properties: mayRaiseFPException |
VSCALEFPSZrmbk [HasAVX512]
vscalefps {src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSCALEFPSZrmbkz [HasAVX512]
vscalefps {src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}}
|
Note
|
Properties: mayRaiseFPException |
VSCALEFPSZrmk [HasAVX512]
vscalefps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSCALEFPSZrmkz [HasAVX512]
vscalefps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSCALEFPSZrr [HasAVX512]
vscalefps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSCALEFPSZrrb [HasAVX512]
vscalefps {rc, src2, src1, dst|dst, src1, src2, rc}
VSCALEFPSZrrbk [HasAVX512]
vscalefps {rc, src2, src1, dst {mask}|dst {mask}, src1, src2, rc}
|
Note
|
Constraints: src0 = dst |
VSCALEFPSZrrbkz [HasAVX512]
vscalefps {rc, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, rc}
VSCALEFPSZrrk [HasAVX512]
vscalefps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSCALEFPSZrrkz [HasAVX512]
vscalefps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSCALEFSDZrm [HasAVX512]
vscalefsd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSCALEFSDZrmk [HasAVX512]
vscalefsd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSCALEFSDZrmkz [HasAVX512]
vscalefsd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSCALEFSDZrr [HasAVX512]
vscalefsd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSCALEFSDZrrb_Int [HasAVX512]
vscalefsd {rc, src2, src1, dst|dst, src1, src2, rc}
VSCALEFSDZrrbk_Int [HasAVX512]
vscalefsd {rc, src2, src1, dst {mask}|dst {mask}, src1, src2, rc}
|
Note
|
Constraints: src0 = dst |
VSCALEFSDZrrbkz_Int [HasAVX512]
vscalefsd {rc, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, rc}
VSCALEFSDZrrk [HasAVX512]
vscalefsd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSCALEFSDZrrkz [HasAVX512]
vscalefsd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSCALEFSSZrm [HasAVX512]
vscalefss {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSCALEFSSZrmk [HasAVX512]
vscalefss {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSCALEFSSZrmkz [HasAVX512]
vscalefss {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSCALEFSSZrr [HasAVX512]
vscalefss {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSCALEFSSZrrb_Int [HasAVX512]
vscalefss {rc, src2, src1, dst|dst, src1, src2, rc}
VSCALEFSSZrrbk_Int [HasAVX512]
vscalefss {rc, src2, src1, dst {mask}|dst {mask}, src1, src2, rc}
|
Note
|
Constraints: src0 = dst |
VSCALEFSSZrrbkz_Int [HasAVX512]
vscalefss {rc, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, rc}
VSCALEFSSZrrk [HasAVX512]
vscalefss {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSCALEFSSZrrkz [HasAVX512]
vscalefss {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSCATTERDPDZmr [HasAVX512]
vscatterdpd {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
|
Note
|
Constraints: mask = mask_wb |
VSCATTERDPSZmr [HasAVX512]
vscatterdps {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
|
Note
|
Constraints: mask = mask_wb |
VSCATTERPF0DPDm [HasAVX512]
vscatterpf0dpd {src {mask}|{mask}, src}
|
Note
|
Properties: mayLoad, mayStore |
VSCATTERPF0DPSm [HasAVX512]
vscatterpf0dps {src {mask}|{mask}, src}
|
Note
|
Properties: mayLoad, mayStore |
VSCATTERPF0QPDm [HasAVX512]
vscatterpf0qpd {src {mask}|{mask}, src}
|
Note
|
Properties: mayLoad, mayStore |
VSCATTERPF0QPSm [HasAVX512]
vscatterpf0qps {src {mask}|{mask}, src}
|
Note
|
Properties: mayLoad, mayStore |
VSCATTERPF1DPDm [HasAVX512]
vscatterpf1dpd {src {mask}|{mask}, src}
|
Note
|
Properties: mayLoad, mayStore |
VSCATTERPF1DPSm [HasAVX512]
vscatterpf1dps {src {mask}|{mask}, src}
|
Note
|
Properties: mayLoad, mayStore |
VSCATTERPF1QPDm [HasAVX512]
vscatterpf1qpd {src {mask}|{mask}, src}
|
Note
|
Properties: mayLoad, mayStore |
VSCATTERPF1QPSm [HasAVX512]
vscatterpf1qps {src {mask}|{mask}, src}
|
Note
|
Properties: mayLoad, mayStore |
VSCATTERQPDZmr [HasAVX512]
vscatterqpd {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
|
Note
|
Constraints: mask = mask_wb |
VSCATTERQPSZmr [HasAVX512]
vscatterqps {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
|
Note
|
Constraints: mask = mask_wb |
VSHUFF32X4Zrmbi [HasAVX512]
vshuff32x4 {src3, src2{1to16}, src1, dst|dst, src1, src2{1to16}, src3}
VSHUFF32X4Zrmbik [HasAVX512]
vshuff32x4 {src3, src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}, src3}
|
Note
|
Constraints: src0 = dst |
VSHUFF32X4Zrmbikz [HasAVX512]
vshuff32x4 {src3, src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}, src3}
VSHUFF32X4Zrmi [HasAVX512]
vshuff32x4 {src3, src2, src1, dst|dst, src1, src2, src3}
VSHUFF32X4Zrmik [HasAVX512]
vshuff32x4 {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VSHUFF32X4Zrmikz [HasAVX512]
vshuff32x4 {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VSHUFF32X4Zrri [HasAVX512]
vshuff32x4 {src3, src2, src1, dst|dst, src1, src2, src3}
VSHUFF32X4Zrrik [HasAVX512]
vshuff32x4 {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VSHUFF32X4Zrrikz [HasAVX512]
vshuff32x4 {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VSHUFF64X2Zrmbi [HasAVX512]
vshuff64x2 {src3, src2{1to8}, src1, dst|dst, src1, src2{1to8}, src3}
VSHUFF64X2Zrmbik [HasAVX512]
vshuff64x2 {src3, src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}, src3}
|
Note
|
Constraints: src0 = dst |
VSHUFF64X2Zrmbikz [HasAVX512]
vshuff64x2 {src3, src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}, src3}
VSHUFF64X2Zrmi [HasAVX512]
vshuff64x2 {src3, src2, src1, dst|dst, src1, src2, src3}
VSHUFF64X2Zrmik [HasAVX512]
vshuff64x2 {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VSHUFF64X2Zrmikz [HasAVX512]
vshuff64x2 {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VSHUFF64X2Zrri [HasAVX512]
vshuff64x2 {src3, src2, src1, dst|dst, src1, src2, src3}
VSHUFF64X2Zrrik [HasAVX512]
vshuff64x2 {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VSHUFF64X2Zrrikz [HasAVX512]
vshuff64x2 {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VSHUFI32X4Zrmbi [HasAVX512]
vshufi32x4 {src3, src2{1to16}, src1, dst|dst, src1, src2{1to16}, src3}
VSHUFI32X4Zrmbik [HasAVX512]
vshufi32x4 {src3, src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}, src3}
|
Note
|
Constraints: src0 = dst |
VSHUFI32X4Zrmbikz [HasAVX512]
vshufi32x4 {src3, src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}, src3}
VSHUFI32X4Zrmi [HasAVX512]
vshufi32x4 {src3, src2, src1, dst|dst, src1, src2, src3}
VSHUFI32X4Zrmik [HasAVX512]
vshufi32x4 {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VSHUFI32X4Zrmikz [HasAVX512]
vshufi32x4 {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VSHUFI32X4Zrri [HasAVX512]
vshufi32x4 {src3, src2, src1, dst|dst, src1, src2, src3}
VSHUFI32X4Zrrik [HasAVX512]
vshufi32x4 {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VSHUFI32X4Zrrikz [HasAVX512]
vshufi32x4 {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VSHUFI64X2Zrmbi [HasAVX512]
vshufi64x2 {src3, src2{1to8}, src1, dst|dst, src1, src2{1to8}, src3}
VSHUFI64X2Zrmbik [HasAVX512]
vshufi64x2 {src3, src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}, src3}
|
Note
|
Constraints: src0 = dst |
VSHUFI64X2Zrmbikz [HasAVX512]
vshufi64x2 {src3, src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}, src3}
VSHUFI64X2Zrmi [HasAVX512]
vshufi64x2 {src3, src2, src1, dst|dst, src1, src2, src3}
VSHUFI64X2Zrmik [HasAVX512]
vshufi64x2 {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VSHUFI64X2Zrmikz [HasAVX512]
vshufi64x2 {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VSHUFI64X2Zrri [HasAVX512]
vshufi64x2 {src3, src2, src1, dst|dst, src1, src2, src3}
VSHUFI64X2Zrrik [HasAVX512]
vshufi64x2 {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VSHUFI64X2Zrrikz [HasAVX512]
vshufi64x2 {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VSHUFPDZrmbi [HasAVX512]
vshufpd {src3, src2{1to8}, src1, dst|dst, src1, src2{1to8}, src3}
VSHUFPDZrmbik [HasAVX512]
vshufpd {src3, src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}, src3}
|
Note
|
Constraints: src0 = dst |
VSHUFPDZrmbikz [HasAVX512]
vshufpd {src3, src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}, src3}
VSHUFPDZrmi [HasAVX512]
vshufpd {src3, src2, src1, dst|dst, src1, src2, src3}
VSHUFPDZrmik [HasAVX512]
vshufpd {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VSHUFPDZrmikz [HasAVX512]
vshufpd {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VSHUFPDZrri [HasAVX512]
vshufpd {src3, src2, src1, dst|dst, src1, src2, src3}
VSHUFPDZrrik [HasAVX512]
vshufpd {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VSHUFPDZrrikz [HasAVX512]
vshufpd {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VSHUFPSZrmbi [HasAVX512]
vshufps {src3, src2{1to16}, src1, dst|dst, src1, src2{1to16}, src3}
VSHUFPSZrmbik [HasAVX512]
vshufps {src3, src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}, src3}
|
Note
|
Constraints: src0 = dst |
VSHUFPSZrmbikz [HasAVX512]
vshufps {src3, src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}, src3}
VSHUFPSZrmi [HasAVX512]
vshufps {src3, src2, src1, dst|dst, src1, src2, src3}
VSHUFPSZrmik [HasAVX512]
vshufps {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VSHUFPSZrmikz [HasAVX512]
vshufps {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VSHUFPSZrri [HasAVX512]
vshufps {src3, src2, src1, dst|dst, src1, src2, src3}
VSHUFPSZrrik [HasAVX512]
vshufps {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VSHUFPSZrrikz [HasAVX512]
vshufps {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VSQRTPDZm [HasAVX512]
vsqrtpd {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VSQRTPDZmb [HasAVX512]
vsqrtpd {src{1to8}, dst|dst, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VSQRTPDZmbk [HasAVX512]
vsqrtpd {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSQRTPDZmbkz [HasAVX512]
vsqrtpd {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VSQRTPDZmk [HasAVX512]
vsqrtpd {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSQRTPDZmkz [HasAVX512]
vsqrtpd {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VSQRTPDZr [HasAVX512]
vsqrtpd {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VSQRTPDZrb [HasAVX512]
vsqrtpd {rc, src, dst|dst, src, rc}
VSQRTPDZrbk [HasAVX512]
vsqrtpd {rc, src, dst {mask}|dst {mask}, src, rc}
|
Note
|
Constraints: src0 = dst |
VSQRTPDZrbkz [HasAVX512]
vsqrtpd {rc, src, dst {mask} {z}|dst {mask} {z}, src, rc}
VSQRTPDZrk [HasAVX512]
vsqrtpd {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSQRTPDZrkz [HasAVX512]
vsqrtpd {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VSQRTPSZm [HasAVX512]
vsqrtps {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VSQRTPSZmb [HasAVX512]
vsqrtps {src{1to16}, dst|dst, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
VSQRTPSZmbk [HasAVX512]
vsqrtps {src{1to16}, dst {mask}|dst {mask}, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSQRTPSZmbkz [HasAVX512]
vsqrtps {src{1to16}, dst {mask} {z}|dst {mask} {z}, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
VSQRTPSZmk [HasAVX512]
vsqrtps {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSQRTPSZmkz [HasAVX512]
vsqrtps {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VSQRTPSZr [HasAVX512]
vsqrtps {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VSQRTPSZrb [HasAVX512]
vsqrtps {rc, src, dst|dst, src, rc}
VSQRTPSZrbk [HasAVX512]
vsqrtps {rc, src, dst {mask}|dst {mask}, src, rc}
|
Note
|
Constraints: src0 = dst |
VSQRTPSZrbkz [HasAVX512]
vsqrtps {rc, src, dst {mask} {z}|dst {mask} {z}, src, rc}
VSQRTPSZrk [HasAVX512]
vsqrtps {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSQRTPSZrkz [HasAVX512]
vsqrtps {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VSQRTSDZm_Int [HasAVX512]
vsqrtsd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSQRTSDZmk_Int [HasAVX512]
vsqrtsd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSQRTSDZmkz_Int [HasAVX512]
vsqrtsd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSQRTSDZr_Int [HasAVX512]
vsqrtsd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSQRTSDZrb_Int [HasAVX512]
vsqrtsd {rc, src2, src1, dst|dst, src1, src2, rc}
VSQRTSDZrbk_Int [HasAVX512]
vsqrtsd {rc, src2, src1, dst {mask}|dst {mask}, src1, src2, rc}
|
Note
|
Constraints: src0 = dst |
VSQRTSDZrbkz_Int [HasAVX512]
vsqrtsd {rc, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, rc}
VSQRTSDZrk_Int [HasAVX512]
vsqrtsd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSQRTSDZrkz_Int [HasAVX512]
vsqrtsd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSQRTSSZm_Int [HasAVX512]
vsqrtss {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSQRTSSZmk_Int [HasAVX512]
vsqrtss {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSQRTSSZmkz_Int [HasAVX512]
vsqrtss {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSQRTSSZr_Int [HasAVX512]
vsqrtss {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSQRTSSZrb_Int [HasAVX512]
vsqrtss {rc, src2, src1, dst|dst, src1, src2, rc}
VSQRTSSZrbk_Int [HasAVX512]
vsqrtss {rc, src2, src1, dst {mask}|dst {mask}, src1, src2, rc}
|
Note
|
Constraints: src0 = dst |
VSQRTSSZrbkz_Int [HasAVX512]
vsqrtss {rc, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, rc}
VSQRTSSZrk_Int [HasAVX512]
vsqrtss {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSQRTSSZrkz_Int [HasAVX512]
vsqrtss {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSUBPDZrm [HasAVX512]
vsubpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VSUBPDZrmb [HasAVX512]
vsubpd {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VSUBPDZrmbk [HasAVX512]
vsubpd {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSUBPDZrmbkz [HasAVX512]
vsubpd {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VSUBPDZrmk [HasAVX512]
vsubpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSUBPDZrmkz [HasAVX512]
vsubpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VSUBPDZrr [HasAVX512]
vsubpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSUBPDZrrb [HasAVX512]
vsubpd {rc, src2, src1, dst|dst, src1, src2, rc}
VSUBPDZrrbk [HasAVX512]
vsubpd {rc, src2, src1, dst {mask}|dst {mask}, src1, src2, rc}
|
Note
|
Constraints: src0 = dst |
VSUBPDZrrbkz [HasAVX512]
vsubpd {rc, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, rc}
VSUBPDZrrk [HasAVX512]
vsubpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSUBPDZrrkz [HasAVX512]
vsubpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSUBPSZrm [HasAVX512]
vsubps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VSUBPSZrmb [HasAVX512]
vsubps {src2{1to16}, src1, dst|dst, src1, src2{1to16}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VSUBPSZrmbk [HasAVX512]
vsubps {src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSUBPSZrmbkz [HasAVX512]
vsubps {src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VSUBPSZrmk [HasAVX512]
vsubps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSUBPSZrmkz [HasAVX512]
vsubps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VSUBPSZrr [HasAVX512]
vsubps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSUBPSZrrb [HasAVX512]
vsubps {rc, src2, src1, dst|dst, src1, src2, rc}
VSUBPSZrrbk [HasAVX512]
vsubps {rc, src2, src1, dst {mask}|dst {mask}, src1, src2, rc}
|
Note
|
Constraints: src0 = dst |
VSUBPSZrrbkz [HasAVX512]
vsubps {rc, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, rc}
VSUBPSZrrk [HasAVX512]
vsubps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSUBPSZrrkz [HasAVX512]
vsubps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSUBSDZrm_Int [HasAVX512]
vsubsd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSUBSDZrmk_Int [HasAVX512]
vsubsd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSUBSDZrmkz_Int [HasAVX512]
vsubsd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSUBSDZrr_Int [HasAVX512]
vsubsd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSUBSDZrrb_Int [HasAVX512]
vsubsd {rc, src2, src1, dst|dst, src1, src2, rc}
VSUBSDZrrbk_Int [HasAVX512]
vsubsd {rc, src2, src1, dst {mask}|dst {mask}, src1, src2, rc}
|
Note
|
Constraints: src0 = dst |
VSUBSDZrrbkz_Int [HasAVX512]
vsubsd {rc, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, rc}
VSUBSDZrrk_Int [HasAVX512]
vsubsd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSUBSDZrrkz_Int [HasAVX512]
vsubsd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSUBSSZrm_Int [HasAVX512]
vsubss {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSUBSSZrmk_Int [HasAVX512]
vsubss {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSUBSSZrmkz_Int [HasAVX512]
vsubss {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSUBSSZrr_Int [HasAVX512]
vsubss {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSUBSSZrrb_Int [HasAVX512]
vsubss {rc, src2, src1, dst|dst, src1, src2, rc}
VSUBSSZrrbk_Int [HasAVX512]
vsubss {rc, src2, src1, dst {mask}|dst {mask}, src1, src2, rc}
|
Note
|
Constraints: src0 = dst |
VSUBSSZrrbkz_Int [HasAVX512]
vsubss {rc, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, rc}
VSUBSSZrrk_Int [HasAVX512]
vsubss {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSUBSSZrrkz_Int [HasAVX512]
vsubss {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VUCOMISDZrm [HasAVX512]
vucomisd {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VUCOMISDZrr [HasAVX512]
vucomisd {src2, src1|src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VUCOMISDZrrb [HasAVX512]
vucomisd {{sae}, src2, src1|src1, src2, {sae}}
VUCOMISSZrm [HasAVX512]
vucomiss {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VUCOMISSZrr [HasAVX512]
vucomiss {src2, src1|src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VUCOMISSZrrb [HasAVX512]
vucomiss {{sae}, src2, src1|src1, src2, {sae}}
VUNPCKHPDZrm [HasAVX512]
vunpckhpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VUNPCKHPDZrmb [HasAVX512]
vunpckhpd {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
VUNPCKHPDZrmbk [HasAVX512]
vunpckhpd {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VUNPCKHPDZrmbkz [HasAVX512]
vunpckhpd {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
VUNPCKHPDZrmk [HasAVX512]
vunpckhpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VUNPCKHPDZrmkz [HasAVX512]
vunpckhpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VUNPCKHPDZrr [HasAVX512]
vunpckhpd {src2, src1, dst|dst, src1, src2}
VUNPCKHPDZrrk [HasAVX512]
vunpckhpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VUNPCKHPDZrrkz [HasAVX512]
vunpckhpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VUNPCKHPSZrm [HasAVX512]
vunpckhps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VUNPCKHPSZrmb [HasAVX512]
vunpckhps {src2{1to16}, src1, dst|dst, src1, src2{1to16}}
|
Note
|
Properties: mayLoad |
VUNPCKHPSZrmbk [HasAVX512]
vunpckhps {src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VUNPCKHPSZrmbkz [HasAVX512]
vunpckhps {src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}}
|
Note
|
Properties: mayLoad |
VUNPCKHPSZrmk [HasAVX512]
vunpckhps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VUNPCKHPSZrmkz [HasAVX512]
vunpckhps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VUNPCKHPSZrr [HasAVX512]
vunpckhps {src2, src1, dst|dst, src1, src2}
VUNPCKHPSZrrk [HasAVX512]
vunpckhps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VUNPCKHPSZrrkz [HasAVX512]
vunpckhps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VUNPCKLPDZrm [HasAVX512]
vunpcklpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VUNPCKLPDZrmb [HasAVX512]
vunpcklpd {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
VUNPCKLPDZrmbk [HasAVX512]
vunpcklpd {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VUNPCKLPDZrmbkz [HasAVX512]
vunpcklpd {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
VUNPCKLPDZrmk [HasAVX512]
vunpcklpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VUNPCKLPDZrmkz [HasAVX512]
vunpcklpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VUNPCKLPDZrr [HasAVX512]
vunpcklpd {src2, src1, dst|dst, src1, src2}
VUNPCKLPDZrrk [HasAVX512]
vunpcklpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VUNPCKLPDZrrkz [HasAVX512]
vunpcklpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VUNPCKLPSZrm [HasAVX512]
vunpcklps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VUNPCKLPSZrmb [HasAVX512]
vunpcklps {src2{1to16}, src1, dst|dst, src1, src2{1to16}}
|
Note
|
Properties: mayLoad |
VUNPCKLPSZrmbk [HasAVX512]
vunpcklps {src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VUNPCKLPSZrmbkz [HasAVX512]
vunpcklps {src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}}
|
Note
|
Properties: mayLoad |
VUNPCKLPSZrmk [HasAVX512]
vunpcklps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VUNPCKLPSZrmkz [HasAVX512]
vunpcklps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VUNPCKLPSZrr [HasAVX512]
vunpcklps {src2, src1, dst|dst, src1, src2}
VUNPCKLPSZrrk [HasAVX512]
vunpcklps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VUNPCKLPSZrrkz [HasAVX512]
vunpcklps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
KMOVWkk_EVEX [HasAVX512, In64BitMode, HasEGPR]
kmovw {src, dst|dst, src}
|
Note
|
Properties: isMoveReg |
KMOVWkm_EVEX [HasAVX512, In64BitMode, HasEGPR]
kmovw {src, dst|dst, src}
KMOVWkr_EVEX [HasAVX512, In64BitMode, HasEGPR]
kmovw {src, dst|dst, src}
KMOVWmk_EVEX [HasAVX512, In64BitMode, HasEGPR]
kmovw {src, dst|dst, src}
KMOVWrk_EVEX [HasAVX512, In64BitMode, HasEGPR]
kmovw {src, dst|dst, src}
KMOVWkk [HasAVX512, NoEGPR]
kmovw {src, dst|dst, src}
|
Note
|
Properties: isMoveReg |
KMOVWkm [HasAVX512, NoEGPR]
kmovw {src, dst|dst, src}
KMOVWkr [HasAVX512, NoEGPR]
kmovw {src, dst|dst, src}
KMOVWmk [HasAVX512, NoEGPR]
kmovw {src, dst|dst, src}
KMOVWrk [HasAVX512, NoEGPR]
kmovw {src, dst|dst, src}
VGF2P8AFFINEINVQBZrmbi [HasAVX512, HasGFNI]
vgf2p8affineinvqb {src3, src2{1to8}, src1, dst|dst, src1, src2{1to8}, src3}
VGF2P8AFFINEINVQBZrmbik [HasAVX512, HasGFNI]
vgf2p8affineinvqb {src3, src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}, src3}
|
Note
|
Constraints: src0 = dst |
VGF2P8AFFINEINVQBZrmbikz [HasAVX512, HasGFNI]
vgf2p8affineinvqb {src3, src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}, src3}
VGF2P8AFFINEINVQBZrmi [HasAVX512, HasGFNI]
vgf2p8affineinvqb {src3, src2, src1, dst|dst, src1, src2, src3}
VGF2P8AFFINEINVQBZrmik [HasAVX512, HasGFNI]
vgf2p8affineinvqb {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VGF2P8AFFINEINVQBZrmikz [HasAVX512, HasGFNI]
vgf2p8affineinvqb {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VGF2P8AFFINEINVQBZrri [HasAVX512, HasGFNI]
vgf2p8affineinvqb {src3, src2, src1, dst|dst, src1, src2, src3}
VGF2P8AFFINEINVQBZrrik [HasAVX512, HasGFNI]
vgf2p8affineinvqb {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VGF2P8AFFINEINVQBZrrikz [HasAVX512, HasGFNI]
vgf2p8affineinvqb {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VGF2P8AFFINEQBZrmbi [HasAVX512, HasGFNI]
vgf2p8affineqb {src3, src2{1to8}, src1, dst|dst, src1, src2{1to8}, src3}
VGF2P8AFFINEQBZrmbik [HasAVX512, HasGFNI]
vgf2p8affineqb {src3, src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}, src3}
|
Note
|
Constraints: src0 = dst |
VGF2P8AFFINEQBZrmbikz [HasAVX512, HasGFNI]
vgf2p8affineqb {src3, src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}, src3}
VGF2P8AFFINEQBZrmi [HasAVX512, HasGFNI]
vgf2p8affineqb {src3, src2, src1, dst|dst, src1, src2, src3}
VGF2P8AFFINEQBZrmik [HasAVX512, HasGFNI]
vgf2p8affineqb {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VGF2P8AFFINEQBZrmikz [HasAVX512, HasGFNI]
vgf2p8affineqb {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VGF2P8AFFINEQBZrri [HasAVX512, HasGFNI]
vgf2p8affineqb {src3, src2, src1, dst|dst, src1, src2, src3}
VGF2P8AFFINEQBZrrik [HasAVX512, HasGFNI]
vgf2p8affineqb {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VGF2P8AFFINEQBZrrikz [HasAVX512, HasGFNI]
vgf2p8affineqb {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VGF2P8MULBZrm [HasAVX512, HasGFNI]
vgf2p8mulb {src2, src1, dst|dst, src1, src2}
VGF2P8MULBZrmk [HasAVX512, HasGFNI]
vgf2p8mulb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VGF2P8MULBZrmkz [HasAVX512, HasGFNI]
vgf2p8mulb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VGF2P8MULBZrr [HasAVX512, HasGFNI]
vgf2p8mulb {src2, src1, dst|dst, src1, src2}
VGF2P8MULBZrrk [HasAVX512, HasGFNI]
vgf2p8mulb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VGF2P8MULBZrrkz [HasAVX512, HasGFNI]
vgf2p8mulb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VAESDECLASTZrm [HasAVX512, HasVAES]
vaesdeclast {src2, src1, dst|dst, src1, src2}
VAESDECLASTZrr [HasAVX512, HasVAES]
vaesdeclast {src2, src1, dst|dst, src1, src2}
VAESDECZrm [HasAVX512, HasVAES]
vaesdec {src2, src1, dst|dst, src1, src2}
VAESDECZrr [HasAVX512, HasVAES]
vaesdec {src2, src1, dst|dst, src1, src2}
VAESENCLASTZrm [HasAVX512, HasVAES]
vaesenclast {src2, src1, dst|dst, src1, src2}
VAESENCLASTZrr [HasAVX512, HasVAES]
vaesenclast {src2, src1, dst|dst, src1, src2}
VAESENCZrm [HasAVX512, HasVAES]
vaesenc {src2, src1, dst|dst, src1, src2}
VAESENCZrr [HasAVX512, HasVAES]
vaesenc {src2, src1, dst|dst, src1, src2}
VP2INTERSECTDZrm [HasAVX512, HasVP2INTERSECT]
vp2intersectd {src2, src1, dst|dst, src1, src2}
VP2INTERSECTDZrmb [HasAVX512, HasVP2INTERSECT]
vp2intersectd {src2{1to16}, src1, dst|dst, src1, src2{1to16}}
VP2INTERSECTDZrr [HasAVX512, HasVP2INTERSECT]
vp2intersectd {src2, src1, dst|dst, src1, src2}
VP2INTERSECTQZrm [HasAVX512, HasVP2INTERSECT]
vp2intersectq {src2, src1, dst|dst, src1, src2}
VP2INTERSECTQZrmb [HasAVX512, HasVP2INTERSECT]
vp2intersectq {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
VP2INTERSECTQZrr [HasAVX512, HasVP2INTERSECT]
vp2intersectq {src2, src1, dst|dst, src1, src2}
VPCLMULQDQZrmi [HasAVX512, HasVPCLMULQDQ]
vpclmulqdq {src3, src2, src1, dst|dst, src1, src2, src3}
VPCLMULQDQZrri [HasAVX512, HasVPCLMULQDQ]
vpclmulqdq {src3, src2, src1, dst|dst, src1, src2, src3}
VMOVSDZrr [HasAVX512, OptForSize]
vmovsd {src2, src1, dst|dst, src1, src2}
VMOVSSZrr [HasAVX512, OptForSize]
vmovss {src2, src1, dst|dst, src1, src2}
VADDPHZrm [HasFP16]
vaddph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VADDPHZrmb [HasFP16]
vaddph {src2{1to32}, src1, dst|dst, src1, src2{1to32}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VADDPHZrmbk [HasFP16]
vaddph {src2{1to32}, src1, dst {mask}|dst {mask}, src1, src2{1to32}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VADDPHZrmbkz [HasFP16]
vaddph {src2{1to32}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to32}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VADDPHZrmk [HasFP16]
vaddph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VADDPHZrmkz [HasFP16]
vaddph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VADDPHZrr [HasFP16]
vaddph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VADDPHZrrb [HasFP16]
vaddph {rc, src2, src1, dst|dst, src1, src2, rc}
VADDPHZrrbk [HasFP16]
vaddph {rc, src2, src1, dst {mask}|dst {mask}, src1, src2, rc}
|
Note
|
Constraints: src0 = dst |
VADDPHZrrbkz [HasFP16]
vaddph {rc, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, rc}
VADDPHZrrk [HasFP16]
vaddph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VADDPHZrrkz [HasFP16]
vaddph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VADDSHZrm_Int [HasFP16]
vaddsh {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VADDSHZrmk_Int [HasFP16]
vaddsh {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VADDSHZrmkz_Int [HasFP16]
vaddsh {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VADDSHZrr_Int [HasFP16]
vaddsh {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VADDSHZrrb_Int [HasFP16]
vaddsh {rc, src2, src1, dst|dst, src1, src2, rc}
VADDSHZrrbk_Int [HasFP16]
vaddsh {rc, src2, src1, dst {mask}|dst {mask}, src1, src2, rc}
|
Note
|
Constraints: src0 = dst |
VADDSHZrrbkz_Int [HasFP16]
vaddsh {rc, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, rc}
VADDSHZrrk_Int [HasFP16]
vaddsh {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VADDSHZrrkz_Int [HasFP16]
vaddsh {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VCMPPHZrmbi [HasFP16]
vcmpph {cc, src2{1to32}, src1, dst|dst, src1, src2{1to32}, cc}
|
Note
|
Properties: mayRaiseFPException |
VCMPPHZrmbik [HasFP16]
vcmpph {cc, src2{1to32}, src1, dst {mask}|dst {mask}, src1, src2{1to32}, cc}
|
Note
|
Properties: mayRaiseFPException |
VCMPPHZrmi [HasFP16]
vcmpph {cc, src2, src1, dst|dst, src1, src2, cc}
|
Note
|
Properties: mayRaiseFPException |
VCMPPHZrmik [HasFP16]
vcmpph {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
|
Note
|
Properties: mayRaiseFPException |
VCMPPHZrri [HasFP16]
vcmpph {cc, src2, src1, dst|dst, src1, src2, cc}
|
Note
|
Properties: mayRaiseFPException |
VCMPPHZrrib [HasFP16]
vcmpph {cc, {sae}, src2, src1, dst|dst, src1, src2, {sae}, cc}
VCMPPHZrribk [HasFP16]
vcmpph {cc, {sae}, src2, src1, dst {mask}|dst {mask}, src1, src2, {sae}, cc}
VCMPPHZrrik [HasFP16]
vcmpph {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
|
Note
|
Properties: mayRaiseFPException |
VCMPSHZrmi_Int [HasFP16]
vcmpsh {cc, src2, src1, dst|dst, src1, src2, cc}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VCMPSHZrmik_Int [HasFP16]
vcmpsh {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VCMPSHZrri_Int [HasFP16]
vcmpsh {cc, src2, src1, dst|dst, src1, src2, cc}
|
Note
|
Properties: mayRaiseFPException |
VCMPSHZrrib_Int [HasFP16]
vcmpsh {cc, {sae}, src2, src1, dst|dst, src1, src2, {sae}, cc}
VCMPSHZrribk_Int [HasFP16]
vcmpsh {cc, {sae}, src2, src1, dst {mask}|dst {mask}, src1, src2, {sae}, cc}
VCMPSHZrrik_Int [HasFP16]
vcmpsh {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
|
Note
|
Properties: mayRaiseFPException |
VCOMISHZrm [HasFP16]
vcomish {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VCOMISHZrr [HasFP16]
vcomish {src2, src1|src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VCOMISHZrrb [HasFP16]
vcomish {{sae}, src2, src1|src1, src2, {sae}}
VCVTDQ2PHZrm [HasFP16]
vcvtdq2ph {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTDQ2PHZrmb [HasFP16]
vcvtdq2ph {src{1to16}, dst|dst, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
VCVTDQ2PHZrmbk [HasFP16]
vcvtdq2ph {src{1to16}, dst {mask}|dst {mask}, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTDQ2PHZrmbkz [HasFP16]
vcvtdq2ph {src{1to16}, dst {mask} {z}|dst {mask} {z}, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
VCVTDQ2PHZrmk [HasFP16]
vcvtdq2ph {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTDQ2PHZrmkz [HasFP16]
vcvtdq2ph {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTDQ2PHZrr [HasFP16]
vcvtdq2ph {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTDQ2PHZrrb [HasFP16]
vcvtdq2ph {rc, src, dst|dst, src, rc}
VCVTDQ2PHZrrbk [HasFP16]
vcvtdq2ph {rc, src, dst {mask}|dst {mask}, src, rc}
|
Note
|
Constraints: src0 = dst |
VCVTDQ2PHZrrbkz [HasFP16]
vcvtdq2ph {rc, src, dst {mask} {z}|dst {mask} {z}, src, rc}
VCVTDQ2PHZrrk [HasFP16]
vcvtdq2ph {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTDQ2PHZrrkz [HasFP16]
vcvtdq2ph {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2PHZrm [HasFP16]
vcvtpd2ph{z} {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2PHZrmb [HasFP16]
vcvtpd2ph {src{1to8}, dst|dst, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2PHZrmbk [HasFP16]
vcvtpd2ph {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPD2PHZrmbkz [HasFP16]
vcvtpd2ph {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2PHZrmk [HasFP16]
vcvtpd2ph{z} {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPD2PHZrmkz [HasFP16]
vcvtpd2ph{z} {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2PHZrr [HasFP16]
vcvtpd2ph {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2PHZrrb [HasFP16]
vcvtpd2ph {rc, src, dst|dst, src, rc}
VCVTPD2PHZrrbk [HasFP16]
vcvtpd2ph {rc, src, dst {mask}|dst {mask}, src, rc}
|
Note
|
Constraints: src0 = dst |
VCVTPD2PHZrrbkz [HasFP16]
vcvtpd2ph {rc, src, dst {mask} {z}|dst {mask} {z}, src, rc}
VCVTPD2PHZrrk [HasFP16]
vcvtpd2ph {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPD2PHZrrkz [HasFP16]
vcvtpd2ph {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2DQZrm [HasFP16]
vcvtph2dq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2DQZrmb [HasFP16]
vcvtph2dq {src{1to16}, dst|dst, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2DQZrmbk [HasFP16]
vcvtph2dq {src{1to16}, dst {mask}|dst {mask}, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2DQZrmbkz [HasFP16]
vcvtph2dq {src{1to16}, dst {mask} {z}|dst {mask} {z}, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2DQZrmk [HasFP16]
vcvtph2dq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2DQZrmkz [HasFP16]
vcvtph2dq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2DQZrr [HasFP16]
vcvtph2dq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2DQZrrb [HasFP16]
vcvtph2dq {rc, src, dst|dst, src, rc}
VCVTPH2DQZrrbk [HasFP16]
vcvtph2dq {rc, src, dst {mask}|dst {mask}, src, rc}
|
Note
|
Constraints: src0 = dst |
VCVTPH2DQZrrbkz [HasFP16]
vcvtph2dq {rc, src, dst {mask} {z}|dst {mask} {z}, src, rc}
VCVTPH2DQZrrk [HasFP16]
vcvtph2dq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2DQZrrkz [HasFP16]
vcvtph2dq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2PDZrm [HasFP16]
vcvtph2pd {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2PDZrmb [HasFP16]
vcvtph2pd {src{1to8}, dst|dst, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2PDZrmbk [HasFP16]
vcvtph2pd {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2PDZrmbkz [HasFP16]
vcvtph2pd {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2PDZrmk [HasFP16]
vcvtph2pd {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2PDZrmkz [HasFP16]
vcvtph2pd {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2PDZrr [HasFP16]
vcvtph2pd {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2PDZrrb [HasFP16]
vcvtph2pd {{sae}, src, dst|dst, src, {sae}}
VCVTPH2PDZrrbk [HasFP16]
vcvtph2pd {{sae}, src, dst {mask}|dst {mask}, src, {sae}}
|
Note
|
Constraints: src0 = dst |
VCVTPH2PDZrrbkz [HasFP16]
vcvtph2pd {{sae}, src, dst {mask} {z}|dst {mask} {z}, src, {sae}}
VCVTPH2PDZrrk [HasFP16]
vcvtph2pd {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2PDZrrkz [HasFP16]
vcvtph2pd {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2PSXZrm [HasFP16]
vcvtph2psx {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2PSXZrmb [HasFP16]
vcvtph2psx {src{1to16}, dst|dst, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2PSXZrmbk [HasFP16]
vcvtph2psx {src{1to16}, dst {mask}|dst {mask}, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2PSXZrmbkz [HasFP16]
vcvtph2psx {src{1to16}, dst {mask} {z}|dst {mask} {z}, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2PSXZrmk [HasFP16]
vcvtph2psx {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2PSXZrmkz [HasFP16]
vcvtph2psx {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2PSXZrr [HasFP16]
vcvtph2psx {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2PSXZrrb [HasFP16]
vcvtph2psx {{sae}, src, dst|dst, src, {sae}}
VCVTPH2PSXZrrbk [HasFP16]
vcvtph2psx {{sae}, src, dst {mask}|dst {mask}, src, {sae}}
|
Note
|
Constraints: src0 = dst |
VCVTPH2PSXZrrbkz [HasFP16]
vcvtph2psx {{sae}, src, dst {mask} {z}|dst {mask} {z}, src, {sae}}
VCVTPH2PSXZrrk [HasFP16]
vcvtph2psx {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2PSXZrrkz [HasFP16]
vcvtph2psx {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2QQZrm [HasFP16]
vcvtph2qq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2QQZrmb [HasFP16]
vcvtph2qq {src{1to8}, dst|dst, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2QQZrmbk [HasFP16]
vcvtph2qq {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2QQZrmbkz [HasFP16]
vcvtph2qq {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2QQZrmk [HasFP16]
vcvtph2qq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2QQZrmkz [HasFP16]
vcvtph2qq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2QQZrr [HasFP16]
vcvtph2qq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2QQZrrb [HasFP16]
vcvtph2qq {rc, src, dst|dst, src, rc}
VCVTPH2QQZrrbk [HasFP16]
vcvtph2qq {rc, src, dst {mask}|dst {mask}, src, rc}
|
Note
|
Constraints: src0 = dst |
VCVTPH2QQZrrbkz [HasFP16]
vcvtph2qq {rc, src, dst {mask} {z}|dst {mask} {z}, src, rc}
VCVTPH2QQZrrk [HasFP16]
vcvtph2qq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2QQZrrkz [HasFP16]
vcvtph2qq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2UDQZrm [HasFP16]
vcvtph2udq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2UDQZrmb [HasFP16]
vcvtph2udq {src{1to16}, dst|dst, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2UDQZrmbk [HasFP16]
vcvtph2udq {src{1to16}, dst {mask}|dst {mask}, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2UDQZrmbkz [HasFP16]
vcvtph2udq {src{1to16}, dst {mask} {z}|dst {mask} {z}, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2UDQZrmk [HasFP16]
vcvtph2udq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2UDQZrmkz [HasFP16]
vcvtph2udq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2UDQZrr [HasFP16]
vcvtph2udq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2UDQZrrb [HasFP16]
vcvtph2udq {rc, src, dst|dst, src, rc}
VCVTPH2UDQZrrbk [HasFP16]
vcvtph2udq {rc, src, dst {mask}|dst {mask}, src, rc}
|
Note
|
Constraints: src0 = dst |
VCVTPH2UDQZrrbkz [HasFP16]
vcvtph2udq {rc, src, dst {mask} {z}|dst {mask} {z}, src, rc}
VCVTPH2UDQZrrk [HasFP16]
vcvtph2udq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2UDQZrrkz [HasFP16]
vcvtph2udq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2UQQZrm [HasFP16]
vcvtph2uqq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2UQQZrmb [HasFP16]
vcvtph2uqq {src{1to8}, dst|dst, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2UQQZrmbk [HasFP16]
vcvtph2uqq {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2UQQZrmbkz [HasFP16]
vcvtph2uqq {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2UQQZrmk [HasFP16]
vcvtph2uqq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2UQQZrmkz [HasFP16]
vcvtph2uqq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2UQQZrr [HasFP16]
vcvtph2uqq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2UQQZrrb [HasFP16]
vcvtph2uqq {rc, src, dst|dst, src, rc}
VCVTPH2UQQZrrbk [HasFP16]
vcvtph2uqq {rc, src, dst {mask}|dst {mask}, src, rc}
|
Note
|
Constraints: src0 = dst |
VCVTPH2UQQZrrbkz [HasFP16]
vcvtph2uqq {rc, src, dst {mask} {z}|dst {mask} {z}, src, rc}
VCVTPH2UQQZrrk [HasFP16]
vcvtph2uqq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2UQQZrrkz [HasFP16]
vcvtph2uqq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2UWZrm [HasFP16]
vcvtph2uw {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2UWZrmb [HasFP16]
vcvtph2uw {src{1to32}, dst|dst, src{1to32}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2UWZrmbk [HasFP16]
vcvtph2uw {src{1to32}, dst {mask}|dst {mask}, src{1to32}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2UWZrmbkz [HasFP16]
vcvtph2uw {src{1to32}, dst {mask} {z}|dst {mask} {z}, src{1to32}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2UWZrmk [HasFP16]
vcvtph2uw {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2UWZrmkz [HasFP16]
vcvtph2uw {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2UWZrr [HasFP16]
vcvtph2uw {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2UWZrrb [HasFP16]
vcvtph2uw {rc, src, dst|dst, src, rc}
VCVTPH2UWZrrbk [HasFP16]
vcvtph2uw {rc, src, dst {mask}|dst {mask}, src, rc}
|
Note
|
Constraints: src0 = dst |
VCVTPH2UWZrrbkz [HasFP16]
vcvtph2uw {rc, src, dst {mask} {z}|dst {mask} {z}, src, rc}
VCVTPH2UWZrrk [HasFP16]
vcvtph2uw {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2UWZrrkz [HasFP16]
vcvtph2uw {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2WZrm [HasFP16]
vcvtph2w {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2WZrmb [HasFP16]
vcvtph2w {src{1to32}, dst|dst, src{1to32}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2WZrmbk [HasFP16]
vcvtph2w {src{1to32}, dst {mask}|dst {mask}, src{1to32}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2WZrmbkz [HasFP16]
vcvtph2w {src{1to32}, dst {mask} {z}|dst {mask} {z}, src{1to32}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2WZrmk [HasFP16]
vcvtph2w {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2WZrmkz [HasFP16]
vcvtph2w {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2WZrr [HasFP16]
vcvtph2w {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2WZrrb [HasFP16]
vcvtph2w {rc, src, dst|dst, src, rc}
VCVTPH2WZrrbk [HasFP16]
vcvtph2w {rc, src, dst {mask}|dst {mask}, src, rc}
|
Note
|
Constraints: src0 = dst |
VCVTPH2WZrrbkz [HasFP16]
vcvtph2w {rc, src, dst {mask} {z}|dst {mask} {z}, src, rc}
VCVTPH2WZrrk [HasFP16]
vcvtph2w {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPH2WZrrkz [HasFP16]
vcvtph2w {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2PHXZrm [HasFP16]
vcvtps2phx {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2PHXZrmb [HasFP16]
vcvtps2phx {src{1to16}, dst|dst, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2PHXZrmbk [HasFP16]
vcvtps2phx {src{1to16}, dst {mask}|dst {mask}, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPS2PHXZrmbkz [HasFP16]
vcvtps2phx {src{1to16}, dst {mask} {z}|dst {mask} {z}, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2PHXZrmk [HasFP16]
vcvtps2phx {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPS2PHXZrmkz [HasFP16]
vcvtps2phx {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2PHXZrr [HasFP16]
vcvtps2phx {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2PHXZrrb [HasFP16]
vcvtps2phx {rc, src, dst|dst, src, rc}
VCVTPS2PHXZrrbk [HasFP16]
vcvtps2phx {rc, src, dst {mask}|dst {mask}, src, rc}
|
Note
|
Constraints: src0 = dst |
VCVTPS2PHXZrrbkz [HasFP16]
vcvtps2phx {rc, src, dst {mask} {z}|dst {mask} {z}, src, rc}
VCVTPS2PHXZrrk [HasFP16]
vcvtps2phx {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPS2PHXZrrkz [HasFP16]
vcvtps2phx {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTQQ2PHZrm [HasFP16]
vcvtqq2ph{z} {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTQQ2PHZrmb [HasFP16]
vcvtqq2ph {src{1to8}, dst|dst, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTQQ2PHZrmbk [HasFP16]
vcvtqq2ph {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTQQ2PHZrmbkz [HasFP16]
vcvtqq2ph {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTQQ2PHZrmk [HasFP16]
vcvtqq2ph{z} {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTQQ2PHZrmkz [HasFP16]
vcvtqq2ph{z} {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTQQ2PHZrr [HasFP16]
vcvtqq2ph {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTQQ2PHZrrb [HasFP16]
vcvtqq2ph {rc, src, dst|dst, src, rc}
VCVTQQ2PHZrrbk [HasFP16]
vcvtqq2ph {rc, src, dst {mask}|dst {mask}, src, rc}
|
Note
|
Constraints: src0 = dst |
VCVTQQ2PHZrrbkz [HasFP16]
vcvtqq2ph {rc, src, dst {mask} {z}|dst {mask} {z}, src, rc}
VCVTQQ2PHZrrk [HasFP16]
vcvtqq2ph {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTQQ2PHZrrkz [HasFP16]
vcvtqq2ph {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTSD2SHZrm_Int [HasFP16]
vcvtsd2sh {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VCVTSD2SHZrmk_Int [HasFP16]
vcvtsd2sh {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTSD2SHZrmkz_Int [HasFP16]
vcvtsd2sh {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VCVTSD2SHZrr_Int [HasFP16]
vcvtsd2sh {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VCVTSD2SHZrrb_Int [HasFP16]
vcvtsd2sh {rc, src2, src1, dst|dst, src1, src2, rc}
VCVTSD2SHZrrbk_Int [HasFP16]
vcvtsd2sh {rc, src2, src1, dst {mask}|dst {mask}, src1, src2, rc}
|
Note
|
Constraints: src0 = dst |
VCVTSD2SHZrrbkz_Int [HasFP16]
vcvtsd2sh {rc, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, rc}
VCVTSD2SHZrrk_Int [HasFP16]
vcvtsd2sh {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTSD2SHZrrkz_Int [HasFP16]
vcvtsd2sh {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VCVTSH2SDZrm_Int [HasFP16]
vcvtsh2sd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VCVTSH2SDZrmk_Int [HasFP16]
vcvtsh2sd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTSH2SDZrmkz_Int [HasFP16]
vcvtsh2sd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VCVTSH2SDZrr_Int [HasFP16]
vcvtsh2sd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VCVTSH2SDZrrb_Int [HasFP16]
vcvtsh2sd {{sae}, src2, src1, dst|dst, src1, src2, {sae}}
VCVTSH2SDZrrbk_Int [HasFP16]
vcvtsh2sd {{sae}, src2, src1, dst {mask}|dst {mask}, src1, src2, {sae}}
|
Note
|
Constraints: src0 = dst |
VCVTSH2SDZrrbkz_Int [HasFP16]
vcvtsh2sd {{sae}, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, {sae}}
VCVTSH2SDZrrk_Int [HasFP16]
vcvtsh2sd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTSH2SDZrrkz_Int [HasFP16]
vcvtsh2sd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VCVTSH2SI64Zrm_Int [HasFP16]
vcvtsh2si {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTSH2SI64Zrr_Int [HasFP16]
vcvtsh2si {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTSH2SI64Zrrb_Int [HasFP16]
vcvtsh2si {rc, src, dst|dst, src, rc}
VCVTSH2SIZrm_Int [HasFP16]
vcvtsh2si {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTSH2SIZrr_Int [HasFP16]
vcvtsh2si {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTSH2SIZrrb_Int [HasFP16]
vcvtsh2si {rc, src, dst|dst, src, rc}
VCVTSH2SSZrm_Int [HasFP16]
vcvtsh2ss {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VCVTSH2SSZrmk_Int [HasFP16]
vcvtsh2ss {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTSH2SSZrmkz_Int [HasFP16]
vcvtsh2ss {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VCVTSH2SSZrr_Int [HasFP16]
vcvtsh2ss {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VCVTSH2SSZrrb_Int [HasFP16]
vcvtsh2ss {{sae}, src2, src1, dst|dst, src1, src2, {sae}}
VCVTSH2SSZrrbk_Int [HasFP16]
vcvtsh2ss {{sae}, src2, src1, dst {mask}|dst {mask}, src1, src2, {sae}}
|
Note
|
Constraints: src0 = dst |
VCVTSH2SSZrrbkz_Int [HasFP16]
vcvtsh2ss {{sae}, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, {sae}}
VCVTSH2SSZrrk_Int [HasFP16]
vcvtsh2ss {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTSH2SSZrrkz_Int [HasFP16]
vcvtsh2ss {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VCVTSH2USI64Zrm_Int [HasFP16]
vcvtsh2usi {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTSH2USI64Zrr_Int [HasFP16]
vcvtsh2usi {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTSH2USI64Zrrb_Int [HasFP16]
vcvtsh2usi {rc, src, dst|dst, src, rc}
VCVTSH2USIZrm_Int [HasFP16]
vcvtsh2usi {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTSH2USIZrr_Int [HasFP16]
vcvtsh2usi {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTSH2USIZrrb_Int [HasFP16]
vcvtsh2usi {rc, src, dst|dst, src, rc}
VCVTSI2SHZrm_Int [HasFP16]
vcvtsi2sh{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VCVTSI2SHZrr_Int [HasFP16]
vcvtsi2sh {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VCVTSI2SHZrrb_Int [HasFP16]
vcvtsi2sh {src2, rc, src1, dst|dst, src1, rc, src2}
VCVTSI642SHZrm_Int [HasFP16]
vcvtsi2sh{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VCVTSI642SHZrr_Int [HasFP16]
vcvtsi2sh {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VCVTSI642SHZrrb_Int [HasFP16]
vcvtsi2sh {src2, rc, src1, dst|dst, src1, rc, src2}
VCVTSS2SHZrm_Int [HasFP16]
vcvtss2sh {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VCVTSS2SHZrmk_Int [HasFP16]
vcvtss2sh {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTSS2SHZrmkz_Int [HasFP16]
vcvtss2sh {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VCVTSS2SHZrr_Int [HasFP16]
vcvtss2sh {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VCVTSS2SHZrrb_Int [HasFP16]
vcvtss2sh {rc, src2, src1, dst|dst, src1, src2, rc}
VCVTSS2SHZrrbk_Int [HasFP16]
vcvtss2sh {rc, src2, src1, dst {mask}|dst {mask}, src1, src2, rc}
|
Note
|
Constraints: src0 = dst |
VCVTSS2SHZrrbkz_Int [HasFP16]
vcvtss2sh {rc, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, rc}
VCVTSS2SHZrrk_Int [HasFP16]
vcvtss2sh {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTSS2SHZrrkz_Int [HasFP16]
vcvtss2sh {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2DQZrm [HasFP16]
vcvttph2dq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2DQZrmb [HasFP16]
vcvttph2dq {src{1to16}, dst|dst, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2DQZrmbk [HasFP16]
vcvttph2dq {src{1to16}, dst {mask}|dst {mask}, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPH2DQZrmbkz [HasFP16]
vcvttph2dq {src{1to16}, dst {mask} {z}|dst {mask} {z}, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2DQZrmk [HasFP16]
vcvttph2dq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPH2DQZrmkz [HasFP16]
vcvttph2dq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2DQZrr [HasFP16]
vcvttph2dq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2DQZrrb [HasFP16]
vcvttph2dq {{sae}, src, dst|dst, src, {sae}}
VCVTTPH2DQZrrbk [HasFP16]
vcvttph2dq {{sae}, src, dst {mask}|dst {mask}, src, {sae}}
|
Note
|
Constraints: src0 = dst |
VCVTTPH2DQZrrbkz [HasFP16]
vcvttph2dq {{sae}, src, dst {mask} {z}|dst {mask} {z}, src, {sae}}
VCVTTPH2DQZrrk [HasFP16]
vcvttph2dq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPH2DQZrrkz [HasFP16]
vcvttph2dq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2QQZrm [HasFP16]
vcvttph2qq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2QQZrmb [HasFP16]
vcvttph2qq {src{1to8}, dst|dst, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2QQZrmbk [HasFP16]
vcvttph2qq {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPH2QQZrmbkz [HasFP16]
vcvttph2qq {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2QQZrmk [HasFP16]
vcvttph2qq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPH2QQZrmkz [HasFP16]
vcvttph2qq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2QQZrr [HasFP16]
vcvttph2qq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2QQZrrb [HasFP16]
vcvttph2qq {{sae}, src, dst|dst, src, {sae}}
VCVTTPH2QQZrrbk [HasFP16]
vcvttph2qq {{sae}, src, dst {mask}|dst {mask}, src, {sae}}
|
Note
|
Constraints: src0 = dst |
VCVTTPH2QQZrrbkz [HasFP16]
vcvttph2qq {{sae}, src, dst {mask} {z}|dst {mask} {z}, src, {sae}}
VCVTTPH2QQZrrk [HasFP16]
vcvttph2qq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPH2QQZrrkz [HasFP16]
vcvttph2qq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2UDQZrm [HasFP16]
vcvttph2udq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2UDQZrmb [HasFP16]
vcvttph2udq {src{1to16}, dst|dst, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2UDQZrmbk [HasFP16]
vcvttph2udq {src{1to16}, dst {mask}|dst {mask}, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPH2UDQZrmbkz [HasFP16]
vcvttph2udq {src{1to16}, dst {mask} {z}|dst {mask} {z}, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2UDQZrmk [HasFP16]
vcvttph2udq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPH2UDQZrmkz [HasFP16]
vcvttph2udq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2UDQZrr [HasFP16]
vcvttph2udq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2UDQZrrb [HasFP16]
vcvttph2udq {{sae}, src, dst|dst, src, {sae}}
VCVTTPH2UDQZrrbk [HasFP16]
vcvttph2udq {{sae}, src, dst {mask}|dst {mask}, src, {sae}}
|
Note
|
Constraints: src0 = dst |
VCVTTPH2UDQZrrbkz [HasFP16]
vcvttph2udq {{sae}, src, dst {mask} {z}|dst {mask} {z}, src, {sae}}
VCVTTPH2UDQZrrk [HasFP16]
vcvttph2udq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPH2UDQZrrkz [HasFP16]
vcvttph2udq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2UQQZrm [HasFP16]
vcvttph2uqq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2UQQZrmb [HasFP16]
vcvttph2uqq {src{1to8}, dst|dst, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2UQQZrmbk [HasFP16]
vcvttph2uqq {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPH2UQQZrmbkz [HasFP16]
vcvttph2uqq {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2UQQZrmk [HasFP16]
vcvttph2uqq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPH2UQQZrmkz [HasFP16]
vcvttph2uqq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2UQQZrr [HasFP16]
vcvttph2uqq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2UQQZrrb [HasFP16]
vcvttph2uqq {{sae}, src, dst|dst, src, {sae}}
VCVTTPH2UQQZrrbk [HasFP16]
vcvttph2uqq {{sae}, src, dst {mask}|dst {mask}, src, {sae}}
|
Note
|
Constraints: src0 = dst |
VCVTTPH2UQQZrrbkz [HasFP16]
vcvttph2uqq {{sae}, src, dst {mask} {z}|dst {mask} {z}, src, {sae}}
VCVTTPH2UQQZrrk [HasFP16]
vcvttph2uqq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPH2UQQZrrkz [HasFP16]
vcvttph2uqq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2UWZrm [HasFP16]
vcvttph2uw {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2UWZrmb [HasFP16]
vcvttph2uw {src{1to32}, dst|dst, src{1to32}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2UWZrmbk [HasFP16]
vcvttph2uw {src{1to32}, dst {mask}|dst {mask}, src{1to32}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPH2UWZrmbkz [HasFP16]
vcvttph2uw {src{1to32}, dst {mask} {z}|dst {mask} {z}, src{1to32}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2UWZrmk [HasFP16]
vcvttph2uw {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPH2UWZrmkz [HasFP16]
vcvttph2uw {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2UWZrr [HasFP16]
vcvttph2uw {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2UWZrrb [HasFP16]
vcvttph2uw {{sae}, src, dst|dst, src, {sae}}
VCVTTPH2UWZrrbk [HasFP16]
vcvttph2uw {{sae}, src, dst {mask}|dst {mask}, src, {sae}}
|
Note
|
Constraints: src0 = dst |
VCVTTPH2UWZrrbkz [HasFP16]
vcvttph2uw {{sae}, src, dst {mask} {z}|dst {mask} {z}, src, {sae}}
VCVTTPH2UWZrrk [HasFP16]
vcvttph2uw {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPH2UWZrrkz [HasFP16]
vcvttph2uw {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2WZrm [HasFP16]
vcvttph2w {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2WZrmb [HasFP16]
vcvttph2w {src{1to32}, dst|dst, src{1to32}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2WZrmbk [HasFP16]
vcvttph2w {src{1to32}, dst {mask}|dst {mask}, src{1to32}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPH2WZrmbkz [HasFP16]
vcvttph2w {src{1to32}, dst {mask} {z}|dst {mask} {z}, src{1to32}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2WZrmk [HasFP16]
vcvttph2w {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPH2WZrmkz [HasFP16]
vcvttph2w {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2WZrr [HasFP16]
vcvttph2w {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2WZrrb [HasFP16]
vcvttph2w {{sae}, src, dst|dst, src, {sae}}
VCVTTPH2WZrrbk [HasFP16]
vcvttph2w {{sae}, src, dst {mask}|dst {mask}, src, {sae}}
|
Note
|
Constraints: src0 = dst |
VCVTTPH2WZrrbkz [HasFP16]
vcvttph2w {{sae}, src, dst {mask} {z}|dst {mask} {z}, src, {sae}}
VCVTTPH2WZrrk [HasFP16]
vcvttph2w {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPH2WZrrkz [HasFP16]
vcvttph2w {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTSH2SI64Zrm_Int [HasFP16]
vcvttsh2si {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTSH2SI64Zrr_Int [HasFP16]
vcvttsh2si {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTSH2SI64Zrrb_Int [HasFP16]
vcvttsh2si {{sae}, src, dst|dst, src, {sae}}
VCVTTSH2SIZrm_Int [HasFP16]
vcvttsh2si {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTSH2SIZrr_Int [HasFP16]
vcvttsh2si {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTSH2SIZrrb_Int [HasFP16]
vcvttsh2si {{sae}, src, dst|dst, src, {sae}}
VCVTTSH2USI64Zrm_Int [HasFP16]
vcvttsh2usi {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTSH2USI64Zrr_Int [HasFP16]
vcvttsh2usi {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTSH2USI64Zrrb_Int [HasFP16]
vcvttsh2usi {{sae}, src, dst|dst, src, {sae}}
VCVTTSH2USIZrm_Int [HasFP16]
vcvttsh2usi {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTSH2USIZrr_Int [HasFP16]
vcvttsh2usi {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTSH2USIZrrb_Int [HasFP16]
vcvttsh2usi {{sae}, src, dst|dst, src, {sae}}
VCVTUDQ2PHZrm [HasFP16]
vcvtudq2ph {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTUDQ2PHZrmb [HasFP16]
vcvtudq2ph {src{1to16}, dst|dst, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
VCVTUDQ2PHZrmbk [HasFP16]
vcvtudq2ph {src{1to16}, dst {mask}|dst {mask}, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTUDQ2PHZrmbkz [HasFP16]
vcvtudq2ph {src{1to16}, dst {mask} {z}|dst {mask} {z}, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
VCVTUDQ2PHZrmk [HasFP16]
vcvtudq2ph {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTUDQ2PHZrmkz [HasFP16]
vcvtudq2ph {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTUDQ2PHZrr [HasFP16]
vcvtudq2ph {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTUDQ2PHZrrb [HasFP16]
vcvtudq2ph {rc, src, dst|dst, src, rc}
VCVTUDQ2PHZrrbk [HasFP16]
vcvtudq2ph {rc, src, dst {mask}|dst {mask}, src, rc}
|
Note
|
Constraints: src0 = dst |
VCVTUDQ2PHZrrbkz [HasFP16]
vcvtudq2ph {rc, src, dst {mask} {z}|dst {mask} {z}, src, rc}
VCVTUDQ2PHZrrk [HasFP16]
vcvtudq2ph {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTUDQ2PHZrrkz [HasFP16]
vcvtudq2ph {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTUQQ2PHZrm [HasFP16]
vcvtuqq2ph{z} {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTUQQ2PHZrmb [HasFP16]
vcvtuqq2ph {src{1to8}, dst|dst, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTUQQ2PHZrmbk [HasFP16]
vcvtuqq2ph {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTUQQ2PHZrmbkz [HasFP16]
vcvtuqq2ph {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTUQQ2PHZrmk [HasFP16]
vcvtuqq2ph{z} {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTUQQ2PHZrmkz [HasFP16]
vcvtuqq2ph{z} {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTUQQ2PHZrr [HasFP16]
vcvtuqq2ph {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTUQQ2PHZrrb [HasFP16]
vcvtuqq2ph {rc, src, dst|dst, src, rc}
VCVTUQQ2PHZrrbk [HasFP16]
vcvtuqq2ph {rc, src, dst {mask}|dst {mask}, src, rc}
|
Note
|
Constraints: src0 = dst |
VCVTUQQ2PHZrrbkz [HasFP16]
vcvtuqq2ph {rc, src, dst {mask} {z}|dst {mask} {z}, src, rc}
VCVTUQQ2PHZrrk [HasFP16]
vcvtuqq2ph {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTUQQ2PHZrrkz [HasFP16]
vcvtuqq2ph {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTUSI2SHZrm_Int [HasFP16]
vcvtusi2sh{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VCVTUSI2SHZrr_Int [HasFP16]
vcvtusi2sh {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VCVTUSI2SHZrrb_Int [HasFP16]
vcvtusi2sh {src2, rc, src1, dst|dst, src1, rc, src2}
VCVTUSI642SHZrm_Int [HasFP16]
vcvtusi2sh{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VCVTUSI642SHZrr_Int [HasFP16]
vcvtusi2sh {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VCVTUSI642SHZrrb_Int [HasFP16]
vcvtusi2sh {src2, rc, src1, dst|dst, src1, rc, src2}
VCVTUW2PHZrm [HasFP16]
vcvtuw2ph {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTUW2PHZrmb [HasFP16]
vcvtuw2ph {src{1to32}, dst|dst, src{1to32}}
|
Note
|
Properties: mayRaiseFPException |
VCVTUW2PHZrmbk [HasFP16]
vcvtuw2ph {src{1to32}, dst {mask}|dst {mask}, src{1to32}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTUW2PHZrmbkz [HasFP16]
vcvtuw2ph {src{1to32}, dst {mask} {z}|dst {mask} {z}, src{1to32}}
|
Note
|
Properties: mayRaiseFPException |
VCVTUW2PHZrmk [HasFP16]
vcvtuw2ph {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTUW2PHZrmkz [HasFP16]
vcvtuw2ph {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTUW2PHZrr [HasFP16]
vcvtuw2ph {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTUW2PHZrrb [HasFP16]
vcvtuw2ph {rc, src, dst|dst, src, rc}
VCVTUW2PHZrrbk [HasFP16]
vcvtuw2ph {rc, src, dst {mask}|dst {mask}, src, rc}
|
Note
|
Constraints: src0 = dst |
VCVTUW2PHZrrbkz [HasFP16]
vcvtuw2ph {rc, src, dst {mask} {z}|dst {mask} {z}, src, rc}
VCVTUW2PHZrrk [HasFP16]
vcvtuw2ph {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTUW2PHZrrkz [HasFP16]
vcvtuw2ph {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTW2PHZrm [HasFP16]
vcvtw2ph {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTW2PHZrmb [HasFP16]
vcvtw2ph {src{1to32}, dst|dst, src{1to32}}
|
Note
|
Properties: mayRaiseFPException |
VCVTW2PHZrmbk [HasFP16]
vcvtw2ph {src{1to32}, dst {mask}|dst {mask}, src{1to32}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTW2PHZrmbkz [HasFP16]
vcvtw2ph {src{1to32}, dst {mask} {z}|dst {mask} {z}, src{1to32}}
|
Note
|
Properties: mayRaiseFPException |
VCVTW2PHZrmk [HasFP16]
vcvtw2ph {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTW2PHZrmkz [HasFP16]
vcvtw2ph {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTW2PHZrr [HasFP16]
vcvtw2ph {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTW2PHZrrb [HasFP16]
vcvtw2ph {rc, src, dst|dst, src, rc}
VCVTW2PHZrrbk [HasFP16]
vcvtw2ph {rc, src, dst {mask}|dst {mask}, src, rc}
|
Note
|
Constraints: src0 = dst |
VCVTW2PHZrrbkz [HasFP16]
vcvtw2ph {rc, src, dst {mask} {z}|dst {mask} {z}, src, rc}
VCVTW2PHZrrk [HasFP16]
vcvtw2ph {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTW2PHZrrkz [HasFP16]
vcvtw2ph {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VDIVPHZrm [HasFP16]
vdivph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VDIVPHZrmb [HasFP16]
vdivph {src2{1to32}, src1, dst|dst, src1, src2{1to32}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VDIVPHZrmbk [HasFP16]
vdivph {src2{1to32}, src1, dst {mask}|dst {mask}, src1, src2{1to32}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VDIVPHZrmbkz [HasFP16]
vdivph {src2{1to32}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to32}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VDIVPHZrmk [HasFP16]
vdivph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VDIVPHZrmkz [HasFP16]
vdivph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VDIVPHZrr [HasFP16]
vdivph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VDIVPHZrrb [HasFP16]
vdivph {rc, src2, src1, dst|dst, src1, src2, rc}
VDIVPHZrrbk [HasFP16]
vdivph {rc, src2, src1, dst {mask}|dst {mask}, src1, src2, rc}
|
Note
|
Constraints: src0 = dst |
VDIVPHZrrbkz [HasFP16]
vdivph {rc, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, rc}
VDIVPHZrrk [HasFP16]
vdivph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VDIVPHZrrkz [HasFP16]
vdivph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VDIVSHZrm_Int [HasFP16]
vdivsh {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VDIVSHZrmk_Int [HasFP16]
vdivsh {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VDIVSHZrmkz_Int [HasFP16]
vdivsh {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VDIVSHZrr_Int [HasFP16]
vdivsh {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VDIVSHZrrb_Int [HasFP16]
vdivsh {rc, src2, src1, dst|dst, src1, src2, rc}
VDIVSHZrrbk_Int [HasFP16]
vdivsh {rc, src2, src1, dst {mask}|dst {mask}, src1, src2, rc}
|
Note
|
Constraints: src0 = dst |
VDIVSHZrrbkz_Int [HasFP16]
vdivsh {rc, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, rc}
VDIVSHZrrk_Int [HasFP16]
vdivsh {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VDIVSHZrrkz_Int [HasFP16]
vdivsh {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VFCMADDCPHZm [HasFP16]
vfcmaddcph {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFCMADDCPHZmb [HasFP16]
vfcmaddcph {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFCMADDCPHZmbk [HasFP16]
vfcmaddcph {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFCMADDCPHZmbkz [HasFP16]
vfcmaddcph {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFCMADDCPHZmk [HasFP16]
vfcmaddcph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFCMADDCPHZmkz [HasFP16]
vfcmaddcph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFCMADDCPHZr [HasFP16]
vfcmaddcph {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFCMADDCPHZrb [HasFP16]
vfcmaddcph {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFCMADDCPHZrbk [HasFP16]
vfcmaddcph {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFCMADDCPHZrbkz [HasFP16]
vfcmaddcph {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFCMADDCPHZrk [HasFP16]
vfcmaddcph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFCMADDCPHZrkz [HasFP16]
vfcmaddcph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFCMADDCSHZm [HasFP16]
vfcmaddcsh {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFCMADDCSHZmk [HasFP16]
vfcmaddcsh {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFCMADDCSHZmkz [HasFP16]
vfcmaddcsh {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFCMADDCSHZr [HasFP16]
vfcmaddcsh {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFCMADDCSHZrb [HasFP16]
vfcmaddcsh {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFCMADDCSHZrbk [HasFP16]
vfcmaddcsh {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFCMADDCSHZrbkz [HasFP16]
vfcmaddcsh {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFCMADDCSHZrk [HasFP16]
vfcmaddcsh {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFCMADDCSHZrkz [HasFP16]
vfcmaddcsh {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFCMULCPHZrm [HasFP16]
vfcmulcph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst |
VFCMULCPHZrmb [HasFP16]
vfcmulcph {src2{1to16}, src1, dst|dst, src1, src2{1to16}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst |
VFCMULCPHZrmbk [HasFP16]
vfcmulcph {src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst, src0 = dst |
VFCMULCPHZrmbkz [HasFP16]
vfcmulcph {src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst |
VFCMULCPHZrmk [HasFP16]
vfcmulcph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst, src0 = dst |
VFCMULCPHZrmkz [HasFP16]
vfcmulcph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst |
VFCMULCPHZrr [HasFP16]
vfcmulcph {src2, src1, dst|dst, src1, src2}
|
Note
|
Constraints: @earlyclobber dst |
VFCMULCPHZrrb [HasFP16]
vfcmulcph {rc, src2, src1, dst|dst, src1, src2, rc}
|
Note
|
Constraints: @earlyclobber dst |
VFCMULCPHZrrbk [HasFP16]
vfcmulcph {rc, src2, src1, dst {mask}|dst {mask}, src1, src2, rc}
|
Note
|
Constraints: @earlyclobber dst, src0 = dst |
VFCMULCPHZrrbkz [HasFP16]
vfcmulcph {rc, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, rc}
|
Note
|
Constraints: @earlyclobber dst |
VFCMULCPHZrrk [HasFP16]
vfcmulcph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: @earlyclobber dst, src0 = dst |
VFCMULCPHZrrkz [HasFP16]
vfcmulcph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Constraints: @earlyclobber dst |
VFCMULCSHZrm [HasFP16]
vfcmulcsh {src2, src1, dst|dst, src1, src2}
|
Note
|
Constraints: @earlyclobber dst |
VFCMULCSHZrmk [HasFP16]
vfcmulcsh {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: @earlyclobber dst, src0 = dst |
VFCMULCSHZrmkz [HasFP16]
vfcmulcsh {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Constraints: @earlyclobber dst |
VFCMULCSHZrr [HasFP16]
vfcmulcsh {src2, src1, dst|dst, src1, src2}
|
Note
|
Constraints: @earlyclobber dst |
VFCMULCSHZrrb [HasFP16]
vfcmulcsh {rc, src2, src1, dst|dst, src1, src2, rc}
|
Note
|
Constraints: @earlyclobber dst |
VFCMULCSHZrrbk [HasFP16]
vfcmulcsh {rc, src2, src1, dst {mask}|dst {mask}, src1, src2, rc}
|
Note
|
Constraints: @earlyclobber dst, src0 = dst |
VFCMULCSHZrrbkz [HasFP16]
vfcmulcsh {rc, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, rc}
|
Note
|
Constraints: @earlyclobber dst |
VFCMULCSHZrrk [HasFP16]
vfcmulcsh {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: @earlyclobber dst, src0 = dst |
VFCMULCSHZrrkz [HasFP16]
vfcmulcsh {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Constraints: @earlyclobber dst |
VFMADD132PHZm [HasFP16]
vfmadd132ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PHZmb [HasFP16]
vfmadd132ph {src3{1to32}, src2, dst|dst, src2, src3{1to32}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PHZmbk [HasFP16]
vfmadd132ph {src3{1to32}, src2, dst {mask}|dst {mask}, src2, src3{1to32}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PHZmbkz [HasFP16]
vfmadd132ph {src3{1to32}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to32}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PHZmk [HasFP16]
vfmadd132ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PHZmkz [HasFP16]
vfmadd132ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PHZr [HasFP16]
vfmadd132ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PHZrb [HasFP16]
vfmadd132ph {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADD132PHZrbk [HasFP16]
vfmadd132ph {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADD132PHZrbkz [HasFP16]
vfmadd132ph {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADD132PHZrk [HasFP16]
vfmadd132ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PHZrkz [HasFP16]
vfmadd132ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132SHZm_Int [HasFP16]
vfmadd132sh {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132SHZmk_Int [HasFP16]
vfmadd132sh {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132SHZmkz_Int [HasFP16]
vfmadd132sh {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132SHZr_Int [HasFP16]
vfmadd132sh {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132SHZrb_Int [HasFP16]
vfmadd132sh {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADD132SHZrbk_Int [HasFP16]
vfmadd132sh {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADD132SHZrbkz_Int [HasFP16]
vfmadd132sh {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADD132SHZrk_Int [HasFP16]
vfmadd132sh {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132SHZrkz_Int [HasFP16]
vfmadd132sh {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PHZm [HasFP16]
vfmadd213ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PHZmb [HasFP16]
vfmadd213ph {src3{1to32}, src2, dst|dst, src2, src3{1to32}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PHZmbk [HasFP16]
vfmadd213ph {src3{1to32}, src2, dst {mask}|dst {mask}, src2, src3{1to32}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PHZmbkz [HasFP16]
vfmadd213ph {src3{1to32}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to32}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PHZmk [HasFP16]
vfmadd213ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PHZmkz [HasFP16]
vfmadd213ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PHZr [HasFP16]
vfmadd213ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PHZrb [HasFP16]
vfmadd213ph {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADD213PHZrbk [HasFP16]
vfmadd213ph {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADD213PHZrbkz [HasFP16]
vfmadd213ph {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADD213PHZrk [HasFP16]
vfmadd213ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PHZrkz [HasFP16]
vfmadd213ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213SHZm_Int [HasFP16]
vfmadd213sh {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213SHZmk_Int [HasFP16]
vfmadd213sh {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213SHZmkz_Int [HasFP16]
vfmadd213sh {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213SHZr_Int [HasFP16]
vfmadd213sh {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213SHZrb_Int [HasFP16]
vfmadd213sh {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADD213SHZrbk_Int [HasFP16]
vfmadd213sh {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADD213SHZrbkz_Int [HasFP16]
vfmadd213sh {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADD213SHZrk_Int [HasFP16]
vfmadd213sh {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213SHZrkz_Int [HasFP16]
vfmadd213sh {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PHZm [HasFP16]
vfmadd231ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PHZmb [HasFP16]
vfmadd231ph {src3{1to32}, src2, dst|dst, src2, src3{1to32}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PHZmbk [HasFP16]
vfmadd231ph {src3{1to32}, src2, dst {mask}|dst {mask}, src2, src3{1to32}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PHZmbkz [HasFP16]
vfmadd231ph {src3{1to32}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to32}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PHZmk [HasFP16]
vfmadd231ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PHZmkz [HasFP16]
vfmadd231ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PHZr [HasFP16]
vfmadd231ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PHZrb [HasFP16]
vfmadd231ph {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADD231PHZrbk [HasFP16]
vfmadd231ph {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADD231PHZrbkz [HasFP16]
vfmadd231ph {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADD231PHZrk [HasFP16]
vfmadd231ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PHZrkz [HasFP16]
vfmadd231ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231SHZm_Int [HasFP16]
vfmadd231sh {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231SHZmk_Int [HasFP16]
vfmadd231sh {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231SHZmkz_Int [HasFP16]
vfmadd231sh {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231SHZr_Int [HasFP16]
vfmadd231sh {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231SHZrb_Int [HasFP16]
vfmadd231sh {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADD231SHZrbk_Int [HasFP16]
vfmadd231sh {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADD231SHZrbkz_Int [HasFP16]
vfmadd231sh {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADD231SHZrk_Int [HasFP16]
vfmadd231sh {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231SHZrkz_Int [HasFP16]
vfmadd231sh {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDCPHZm [HasFP16]
vfmaddcph {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFMADDCPHZmb [HasFP16]
vfmaddcph {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFMADDCPHZmbk [HasFP16]
vfmaddcph {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFMADDCPHZmbkz [HasFP16]
vfmaddcph {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFMADDCPHZmk [HasFP16]
vfmaddcph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFMADDCPHZmkz [HasFP16]
vfmaddcph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFMADDCPHZr [HasFP16]
vfmaddcph {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFMADDCPHZrb [HasFP16]
vfmaddcph {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFMADDCPHZrbk [HasFP16]
vfmaddcph {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFMADDCPHZrbkz [HasFP16]
vfmaddcph {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFMADDCPHZrk [HasFP16]
vfmaddcph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFMADDCPHZrkz [HasFP16]
vfmaddcph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFMADDCSHZm [HasFP16]
vfmaddcsh {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFMADDCSHZmk [HasFP16]
vfmaddcsh {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFMADDCSHZmkz [HasFP16]
vfmaddcsh {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFMADDCSHZr [HasFP16]
vfmaddcsh {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFMADDCSHZrb [HasFP16]
vfmaddcsh {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFMADDCSHZrbk [HasFP16]
vfmaddcsh {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFMADDCSHZrbkz [HasFP16]
vfmaddcsh {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFMADDCSHZrk [HasFP16]
vfmaddcsh {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFMADDCSHZrkz [HasFP16]
vfmaddcsh {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: @earlyclobber dst, src1 = dst |
VFMADDSUB132PHZm [HasFP16]
vfmaddsub132ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PHZmb [HasFP16]
vfmaddsub132ph {src3{1to32}, src2, dst|dst, src2, src3{1to32}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PHZmbk [HasFP16]
vfmaddsub132ph {src3{1to32}, src2, dst {mask}|dst {mask}, src2, src3{1to32}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PHZmbkz [HasFP16]
vfmaddsub132ph {src3{1to32}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to32}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PHZmk [HasFP16]
vfmaddsub132ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PHZmkz [HasFP16]
vfmaddsub132ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PHZr [HasFP16]
vfmaddsub132ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PHZrb [HasFP16]
vfmaddsub132ph {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PHZrbk [HasFP16]
vfmaddsub132ph {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PHZrbkz [HasFP16]
vfmaddsub132ph {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PHZrk [HasFP16]
vfmaddsub132ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PHZrkz [HasFP16]
vfmaddsub132ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PHZm [HasFP16]
vfmaddsub213ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PHZmb [HasFP16]
vfmaddsub213ph {src3{1to32}, src2, dst|dst, src2, src3{1to32}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PHZmbk [HasFP16]
vfmaddsub213ph {src3{1to32}, src2, dst {mask}|dst {mask}, src2, src3{1to32}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PHZmbkz [HasFP16]
vfmaddsub213ph {src3{1to32}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to32}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PHZmk [HasFP16]
vfmaddsub213ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PHZmkz [HasFP16]
vfmaddsub213ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PHZr [HasFP16]
vfmaddsub213ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PHZrb [HasFP16]
vfmaddsub213ph {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PHZrbk [HasFP16]
vfmaddsub213ph {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PHZrbkz [HasFP16]
vfmaddsub213ph {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PHZrk [HasFP16]
vfmaddsub213ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PHZrkz [HasFP16]
vfmaddsub213ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PHZm [HasFP16]
vfmaddsub231ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PHZmb [HasFP16]
vfmaddsub231ph {src3{1to32}, src2, dst|dst, src2, src3{1to32}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PHZmbk [HasFP16]
vfmaddsub231ph {src3{1to32}, src2, dst {mask}|dst {mask}, src2, src3{1to32}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PHZmbkz [HasFP16]
vfmaddsub231ph {src3{1to32}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to32}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PHZmk [HasFP16]
vfmaddsub231ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PHZmkz [HasFP16]
vfmaddsub231ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PHZr [HasFP16]
vfmaddsub231ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PHZrb [HasFP16]
vfmaddsub231ph {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PHZrbk [HasFP16]
vfmaddsub231ph {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PHZrbkz [HasFP16]
vfmaddsub231ph {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PHZrk [HasFP16]
vfmaddsub231ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PHZrkz [HasFP16]
vfmaddsub231ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PHZm [HasFP16]
vfmsub132ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PHZmb [HasFP16]
vfmsub132ph {src3{1to32}, src2, dst|dst, src2, src3{1to32}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PHZmbk [HasFP16]
vfmsub132ph {src3{1to32}, src2, dst {mask}|dst {mask}, src2, src3{1to32}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PHZmbkz [HasFP16]
vfmsub132ph {src3{1to32}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to32}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PHZmk [HasFP16]
vfmsub132ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PHZmkz [HasFP16]
vfmsub132ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PHZr [HasFP16]
vfmsub132ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PHZrb [HasFP16]
vfmsub132ph {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUB132PHZrbk [HasFP16]
vfmsub132ph {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUB132PHZrbkz [HasFP16]
vfmsub132ph {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUB132PHZrk [HasFP16]
vfmsub132ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PHZrkz [HasFP16]
vfmsub132ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132SHZm_Int [HasFP16]
vfmsub132sh {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132SHZmk_Int [HasFP16]
vfmsub132sh {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132SHZmkz_Int [HasFP16]
vfmsub132sh {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132SHZr_Int [HasFP16]
vfmsub132sh {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132SHZrb_Int [HasFP16]
vfmsub132sh {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUB132SHZrbk_Int [HasFP16]
vfmsub132sh {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUB132SHZrbkz_Int [HasFP16]
vfmsub132sh {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUB132SHZrk_Int [HasFP16]
vfmsub132sh {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132SHZrkz_Int [HasFP16]
vfmsub132sh {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PHZm [HasFP16]
vfmsub213ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PHZmb [HasFP16]
vfmsub213ph {src3{1to32}, src2, dst|dst, src2, src3{1to32}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PHZmbk [HasFP16]
vfmsub213ph {src3{1to32}, src2, dst {mask}|dst {mask}, src2, src3{1to32}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PHZmbkz [HasFP16]
vfmsub213ph {src3{1to32}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to32}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PHZmk [HasFP16]
vfmsub213ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PHZmkz [HasFP16]
vfmsub213ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PHZr [HasFP16]
vfmsub213ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PHZrb [HasFP16]
vfmsub213ph {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUB213PHZrbk [HasFP16]
vfmsub213ph {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUB213PHZrbkz [HasFP16]
vfmsub213ph {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUB213PHZrk [HasFP16]
vfmsub213ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PHZrkz [HasFP16]
vfmsub213ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213SHZm_Int [HasFP16]
vfmsub213sh {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213SHZmk_Int [HasFP16]
vfmsub213sh {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213SHZmkz_Int [HasFP16]
vfmsub213sh {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213SHZr_Int [HasFP16]
vfmsub213sh {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213SHZrb_Int [HasFP16]
vfmsub213sh {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUB213SHZrbk_Int [HasFP16]
vfmsub213sh {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUB213SHZrbkz_Int [HasFP16]
vfmsub213sh {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUB213SHZrk_Int [HasFP16]
vfmsub213sh {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213SHZrkz_Int [HasFP16]
vfmsub213sh {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PHZm [HasFP16]
vfmsub231ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PHZmb [HasFP16]
vfmsub231ph {src3{1to32}, src2, dst|dst, src2, src3{1to32}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PHZmbk [HasFP16]
vfmsub231ph {src3{1to32}, src2, dst {mask}|dst {mask}, src2, src3{1to32}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PHZmbkz [HasFP16]
vfmsub231ph {src3{1to32}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to32}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PHZmk [HasFP16]
vfmsub231ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PHZmkz [HasFP16]
vfmsub231ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PHZr [HasFP16]
vfmsub231ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PHZrb [HasFP16]
vfmsub231ph {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUB231PHZrbk [HasFP16]
vfmsub231ph {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUB231PHZrbkz [HasFP16]
vfmsub231ph {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUB231PHZrk [HasFP16]
vfmsub231ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PHZrkz [HasFP16]
vfmsub231ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231SHZm_Int [HasFP16]
vfmsub231sh {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231SHZmk_Int [HasFP16]
vfmsub231sh {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231SHZmkz_Int [HasFP16]
vfmsub231sh {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231SHZr_Int [HasFP16]
vfmsub231sh {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231SHZrb_Int [HasFP16]
vfmsub231sh {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUB231SHZrbk_Int [HasFP16]
vfmsub231sh {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUB231SHZrbkz_Int [HasFP16]
vfmsub231sh {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUB231SHZrk_Int [HasFP16]
vfmsub231sh {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231SHZrkz_Int [HasFP16]
vfmsub231sh {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PHZm [HasFP16]
vfmsubadd132ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PHZmb [HasFP16]
vfmsubadd132ph {src3{1to32}, src2, dst|dst, src2, src3{1to32}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PHZmbk [HasFP16]
vfmsubadd132ph {src3{1to32}, src2, dst {mask}|dst {mask}, src2, src3{1to32}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PHZmbkz [HasFP16]
vfmsubadd132ph {src3{1to32}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to32}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PHZmk [HasFP16]
vfmsubadd132ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PHZmkz [HasFP16]
vfmsubadd132ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PHZr [HasFP16]
vfmsubadd132ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PHZrb [HasFP16]
vfmsubadd132ph {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PHZrbk [HasFP16]
vfmsubadd132ph {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PHZrbkz [HasFP16]
vfmsubadd132ph {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PHZrk [HasFP16]
vfmsubadd132ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PHZrkz [HasFP16]
vfmsubadd132ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PHZm [HasFP16]
vfmsubadd213ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PHZmb [HasFP16]
vfmsubadd213ph {src3{1to32}, src2, dst|dst, src2, src3{1to32}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PHZmbk [HasFP16]
vfmsubadd213ph {src3{1to32}, src2, dst {mask}|dst {mask}, src2, src3{1to32}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PHZmbkz [HasFP16]
vfmsubadd213ph {src3{1to32}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to32}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PHZmk [HasFP16]
vfmsubadd213ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PHZmkz [HasFP16]
vfmsubadd213ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PHZr [HasFP16]
vfmsubadd213ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PHZrb [HasFP16]
vfmsubadd213ph {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PHZrbk [HasFP16]
vfmsubadd213ph {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PHZrbkz [HasFP16]
vfmsubadd213ph {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PHZrk [HasFP16]
vfmsubadd213ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PHZrkz [HasFP16]
vfmsubadd213ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PHZm [HasFP16]
vfmsubadd231ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PHZmb [HasFP16]
vfmsubadd231ph {src3{1to32}, src2, dst|dst, src2, src3{1to32}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PHZmbk [HasFP16]
vfmsubadd231ph {src3{1to32}, src2, dst {mask}|dst {mask}, src2, src3{1to32}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PHZmbkz [HasFP16]
vfmsubadd231ph {src3{1to32}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to32}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PHZmk [HasFP16]
vfmsubadd231ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PHZmkz [HasFP16]
vfmsubadd231ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PHZr [HasFP16]
vfmsubadd231ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PHZrb [HasFP16]
vfmsubadd231ph {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PHZrbk [HasFP16]
vfmsubadd231ph {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PHZrbkz [HasFP16]
vfmsubadd231ph {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PHZrk [HasFP16]
vfmsubadd231ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PHZrkz [HasFP16]
vfmsubadd231ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMULCPHZrm [HasFP16]
vfmulcph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst |
VFMULCPHZrmb [HasFP16]
vfmulcph {src2{1to16}, src1, dst|dst, src1, src2{1to16}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst |
VFMULCPHZrmbk [HasFP16]
vfmulcph {src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst, src0 = dst |
VFMULCPHZrmbkz [HasFP16]
vfmulcph {src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst |
VFMULCPHZrmk [HasFP16]
vfmulcph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst, src0 = dst |
VFMULCPHZrmkz [HasFP16]
vfmulcph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst |
VFMULCPHZrr [HasFP16]
vfmulcph {src2, src1, dst|dst, src1, src2}
|
Note
|
Constraints: @earlyclobber dst |
VFMULCPHZrrb [HasFP16]
vfmulcph {rc, src2, src1, dst|dst, src1, src2, rc}
|
Note
|
Constraints: @earlyclobber dst |
VFMULCPHZrrbk [HasFP16]
vfmulcph {rc, src2, src1, dst {mask}|dst {mask}, src1, src2, rc}
|
Note
|
Constraints: @earlyclobber dst, src0 = dst |
VFMULCPHZrrbkz [HasFP16]
vfmulcph {rc, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, rc}
|
Note
|
Constraints: @earlyclobber dst |
VFMULCPHZrrk [HasFP16]
vfmulcph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: @earlyclobber dst, src0 = dst |
VFMULCPHZrrkz [HasFP16]
vfmulcph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Constraints: @earlyclobber dst |
VFMULCSHZrm [HasFP16]
vfmulcsh {src2, src1, dst|dst, src1, src2}
|
Note
|
Constraints: @earlyclobber dst |
VFMULCSHZrmk [HasFP16]
vfmulcsh {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: @earlyclobber dst, src0 = dst |
VFMULCSHZrmkz [HasFP16]
vfmulcsh {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Constraints: @earlyclobber dst |
VFMULCSHZrr [HasFP16]
vfmulcsh {src2, src1, dst|dst, src1, src2}
|
Note
|
Constraints: @earlyclobber dst |
VFMULCSHZrrb [HasFP16]
vfmulcsh {rc, src2, src1, dst|dst, src1, src2, rc}
|
Note
|
Constraints: @earlyclobber dst |
VFMULCSHZrrbk [HasFP16]
vfmulcsh {rc, src2, src1, dst {mask}|dst {mask}, src1, src2, rc}
|
Note
|
Constraints: @earlyclobber dst, src0 = dst |
VFMULCSHZrrbkz [HasFP16]
vfmulcsh {rc, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, rc}
|
Note
|
Constraints: @earlyclobber dst |
VFMULCSHZrrk [HasFP16]
vfmulcsh {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: @earlyclobber dst, src0 = dst |
VFMULCSHZrrkz [HasFP16]
vfmulcsh {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Constraints: @earlyclobber dst |
VFNMADD132PHZm [HasFP16]
vfnmadd132ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PHZmb [HasFP16]
vfnmadd132ph {src3{1to32}, src2, dst|dst, src2, src3{1to32}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PHZmbk [HasFP16]
vfnmadd132ph {src3{1to32}, src2, dst {mask}|dst {mask}, src2, src3{1to32}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PHZmbkz [HasFP16]
vfnmadd132ph {src3{1to32}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to32}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PHZmk [HasFP16]
vfnmadd132ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PHZmkz [HasFP16]
vfnmadd132ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PHZr [HasFP16]
vfnmadd132ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PHZrb [HasFP16]
vfnmadd132ph {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMADD132PHZrbk [HasFP16]
vfnmadd132ph {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMADD132PHZrbkz [HasFP16]
vfnmadd132ph {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMADD132PHZrk [HasFP16]
vfnmadd132ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PHZrkz [HasFP16]
vfnmadd132ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132SHZm_Int [HasFP16]
vfnmadd132sh {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132SHZmk_Int [HasFP16]
vfnmadd132sh {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132SHZmkz_Int [HasFP16]
vfnmadd132sh {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132SHZr_Int [HasFP16]
vfnmadd132sh {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132SHZrb_Int [HasFP16]
vfnmadd132sh {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMADD132SHZrbk_Int [HasFP16]
vfnmadd132sh {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMADD132SHZrbkz_Int [HasFP16]
vfnmadd132sh {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMADD132SHZrk_Int [HasFP16]
vfnmadd132sh {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132SHZrkz_Int [HasFP16]
vfnmadd132sh {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PHZm [HasFP16]
vfnmadd213ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PHZmb [HasFP16]
vfnmadd213ph {src3{1to32}, src2, dst|dst, src2, src3{1to32}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PHZmbk [HasFP16]
vfnmadd213ph {src3{1to32}, src2, dst {mask}|dst {mask}, src2, src3{1to32}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PHZmbkz [HasFP16]
vfnmadd213ph {src3{1to32}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to32}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PHZmk [HasFP16]
vfnmadd213ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PHZmkz [HasFP16]
vfnmadd213ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PHZr [HasFP16]
vfnmadd213ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PHZrb [HasFP16]
vfnmadd213ph {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMADD213PHZrbk [HasFP16]
vfnmadd213ph {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMADD213PHZrbkz [HasFP16]
vfnmadd213ph {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMADD213PHZrk [HasFP16]
vfnmadd213ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PHZrkz [HasFP16]
vfnmadd213ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213SHZm_Int [HasFP16]
vfnmadd213sh {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213SHZmk_Int [HasFP16]
vfnmadd213sh {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213SHZmkz_Int [HasFP16]
vfnmadd213sh {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213SHZr_Int [HasFP16]
vfnmadd213sh {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213SHZrb_Int [HasFP16]
vfnmadd213sh {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMADD213SHZrbk_Int [HasFP16]
vfnmadd213sh {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMADD213SHZrbkz_Int [HasFP16]
vfnmadd213sh {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMADD213SHZrk_Int [HasFP16]
vfnmadd213sh {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213SHZrkz_Int [HasFP16]
vfnmadd213sh {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PHZm [HasFP16]
vfnmadd231ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PHZmb [HasFP16]
vfnmadd231ph {src3{1to32}, src2, dst|dst, src2, src3{1to32}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PHZmbk [HasFP16]
vfnmadd231ph {src3{1to32}, src2, dst {mask}|dst {mask}, src2, src3{1to32}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PHZmbkz [HasFP16]
vfnmadd231ph {src3{1to32}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to32}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PHZmk [HasFP16]
vfnmadd231ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PHZmkz [HasFP16]
vfnmadd231ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PHZr [HasFP16]
vfnmadd231ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PHZrb [HasFP16]
vfnmadd231ph {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMADD231PHZrbk [HasFP16]
vfnmadd231ph {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMADD231PHZrbkz [HasFP16]
vfnmadd231ph {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMADD231PHZrk [HasFP16]
vfnmadd231ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PHZrkz [HasFP16]
vfnmadd231ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231SHZm_Int [HasFP16]
vfnmadd231sh {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231SHZmk_Int [HasFP16]
vfnmadd231sh {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231SHZmkz_Int [HasFP16]
vfnmadd231sh {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231SHZr_Int [HasFP16]
vfnmadd231sh {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231SHZrb_Int [HasFP16]
vfnmadd231sh {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMADD231SHZrbk_Int [HasFP16]
vfnmadd231sh {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMADD231SHZrbkz_Int [HasFP16]
vfnmadd231sh {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMADD231SHZrk_Int [HasFP16]
vfnmadd231sh {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231SHZrkz_Int [HasFP16]
vfnmadd231sh {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PHZm [HasFP16]
vfnmsub132ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PHZmb [HasFP16]
vfnmsub132ph {src3{1to32}, src2, dst|dst, src2, src3{1to32}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PHZmbk [HasFP16]
vfnmsub132ph {src3{1to32}, src2, dst {mask}|dst {mask}, src2, src3{1to32}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PHZmbkz [HasFP16]
vfnmsub132ph {src3{1to32}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to32}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PHZmk [HasFP16]
vfnmsub132ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PHZmkz [HasFP16]
vfnmsub132ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PHZr [HasFP16]
vfnmsub132ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PHZrb [HasFP16]
vfnmsub132ph {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PHZrbk [HasFP16]
vfnmsub132ph {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PHZrbkz [HasFP16]
vfnmsub132ph {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PHZrk [HasFP16]
vfnmsub132ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PHZrkz [HasFP16]
vfnmsub132ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132SHZm_Int [HasFP16]
vfnmsub132sh {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132SHZmk_Int [HasFP16]
vfnmsub132sh {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132SHZmkz_Int [HasFP16]
vfnmsub132sh {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132SHZr_Int [HasFP16]
vfnmsub132sh {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132SHZrb_Int [HasFP16]
vfnmsub132sh {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMSUB132SHZrbk_Int [HasFP16]
vfnmsub132sh {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMSUB132SHZrbkz_Int [HasFP16]
vfnmsub132sh {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMSUB132SHZrk_Int [HasFP16]
vfnmsub132sh {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132SHZrkz_Int [HasFP16]
vfnmsub132sh {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PHZm [HasFP16]
vfnmsub213ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PHZmb [HasFP16]
vfnmsub213ph {src3{1to32}, src2, dst|dst, src2, src3{1to32}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PHZmbk [HasFP16]
vfnmsub213ph {src3{1to32}, src2, dst {mask}|dst {mask}, src2, src3{1to32}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PHZmbkz [HasFP16]
vfnmsub213ph {src3{1to32}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to32}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PHZmk [HasFP16]
vfnmsub213ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PHZmkz [HasFP16]
vfnmsub213ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PHZr [HasFP16]
vfnmsub213ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PHZrb [HasFP16]
vfnmsub213ph {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PHZrbk [HasFP16]
vfnmsub213ph {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PHZrbkz [HasFP16]
vfnmsub213ph {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PHZrk [HasFP16]
vfnmsub213ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PHZrkz [HasFP16]
vfnmsub213ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213SHZm_Int [HasFP16]
vfnmsub213sh {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213SHZmk_Int [HasFP16]
vfnmsub213sh {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213SHZmkz_Int [HasFP16]
vfnmsub213sh {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213SHZr_Int [HasFP16]
vfnmsub213sh {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213SHZrb_Int [HasFP16]
vfnmsub213sh {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMSUB213SHZrbk_Int [HasFP16]
vfnmsub213sh {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMSUB213SHZrbkz_Int [HasFP16]
vfnmsub213sh {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMSUB213SHZrk_Int [HasFP16]
vfnmsub213sh {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213SHZrkz_Int [HasFP16]
vfnmsub213sh {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PHZm [HasFP16]
vfnmsub231ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PHZmb [HasFP16]
vfnmsub231ph {src3{1to32}, src2, dst|dst, src2, src3{1to32}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PHZmbk [HasFP16]
vfnmsub231ph {src3{1to32}, src2, dst {mask}|dst {mask}, src2, src3{1to32}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PHZmbkz [HasFP16]
vfnmsub231ph {src3{1to32}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to32}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PHZmk [HasFP16]
vfnmsub231ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PHZmkz [HasFP16]
vfnmsub231ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PHZr [HasFP16]
vfnmsub231ph {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PHZrb [HasFP16]
vfnmsub231ph {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PHZrbk [HasFP16]
vfnmsub231ph {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PHZrbkz [HasFP16]
vfnmsub231ph {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PHZrk [HasFP16]
vfnmsub231ph {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PHZrkz [HasFP16]
vfnmsub231ph {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231SHZm_Int [HasFP16]
vfnmsub231sh {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231SHZmk_Int [HasFP16]
vfnmsub231sh {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231SHZmkz_Int [HasFP16]
vfnmsub231sh {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231SHZr_Int [HasFP16]
vfnmsub231sh {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231SHZrb_Int [HasFP16]
vfnmsub231sh {rc, src3, src2, dst|dst, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMSUB231SHZrbk_Int [HasFP16]
vfnmsub231sh {rc, src3, src2, dst {mask}|dst {mask}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMSUB231SHZrbkz_Int [HasFP16]
vfnmsub231sh {rc, src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3, rc}
|
Note
|
Constraints: src1 = dst |
VFNMSUB231SHZrk_Int [HasFP16]
vfnmsub231sh {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231SHZrkz_Int [HasFP16]
vfnmsub231sh {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFPCLASSPHZmbi [HasFP16]
vfpclassph {src2, src1{1to32}, dst|dst, src1{1to32}, src2}
VFPCLASSPHZmbik [HasFP16]
vfpclassph {src2, src1{1to32}, dst {mask}|dst {mask}, src1{1to32}, src2}
VFPCLASSPHZmi [HasFP16]
vfpclassph{z} {src2, src1, dst|dst, src1, src2}
VFPCLASSPHZmik [HasFP16]
vfpclassph{z} {src2, src1, dst {mask}|dst {mask}, src1, src2}
VFPCLASSPHZri [HasFP16]
vfpclassph {src2, src1, dst|dst, src1, src2}
VFPCLASSPHZrik [HasFP16]
vfpclassph {src2, src1, dst {mask}|dst {mask}, src1, src2}
VFPCLASSSHZmi [HasFP16]
vfpclasssh {src2, src1, dst|dst, src1, src2}
VFPCLASSSHZmik [HasFP16]
vfpclasssh {src2, src1, dst {mask}|dst {mask}, src1, src2}
VFPCLASSSHZri [HasFP16]
vfpclasssh {src2, src1, dst|dst, src1, src2}
VFPCLASSSHZrik [HasFP16]
vfpclasssh {src2, src1, dst {mask}|dst {mask}, src1, src2}
VGETEXPPHZm [HasFP16]
vgetexpph {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VGETEXPPHZmb [HasFP16]
vgetexpph {src{1to32}, dst|dst, src{1to32}}
|
Note
|
Properties: mayRaiseFPException |
VGETEXPPHZmbk [HasFP16]
vgetexpph {src{1to32}, dst {mask}|dst {mask}, src{1to32}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VGETEXPPHZmbkz [HasFP16]
vgetexpph {src{1to32}, dst {mask} {z}|dst {mask} {z}, src{1to32}}
|
Note
|
Properties: mayRaiseFPException |
VGETEXPPHZmk [HasFP16]
vgetexpph {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VGETEXPPHZmkz [HasFP16]
vgetexpph {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VGETEXPPHZr [HasFP16]
vgetexpph {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VGETEXPPHZrb [HasFP16]
vgetexpph {{sae}, src, dst|dst, src, {sae}}
VGETEXPPHZrbk [HasFP16]
vgetexpph {{sae}, src, dst {mask}|dst {mask}, src, {sae}}
|
Note
|
Constraints: src0 = dst |
VGETEXPPHZrbkz [HasFP16]
vgetexpph {{sae}, src, dst {mask} {z}|dst {mask} {z}, src, {sae}}
VGETEXPPHZrk [HasFP16]
vgetexpph {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VGETEXPPHZrkz [HasFP16]
vgetexpph {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VGETEXPSHZm [HasFP16]
vgetexpsh {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VGETEXPSHZmk [HasFP16]
vgetexpsh {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VGETEXPSHZmkz [HasFP16]
vgetexpsh {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VGETEXPSHZr [HasFP16]
vgetexpsh {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VGETEXPSHZrb [HasFP16]
vgetexpsh {{sae}, src2, src1, dst|dst, src1, src2, {sae}}
VGETEXPSHZrbk [HasFP16]
vgetexpsh {{sae}, src2, src1, dst {mask}|dst {mask}, src1, src2, {sae}}
|
Note
|
Constraints: src0 = dst |
VGETEXPSHZrbkz [HasFP16]
vgetexpsh {{sae}, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, {sae}}
VGETEXPSHZrk [HasFP16]
vgetexpsh {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VGETEXPSHZrkz [HasFP16]
vgetexpsh {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VGETMANTPHZrmbi [HasFP16]
vgetmantph {src2, src1{1to32}, dst|dst, src1{1to32}, src2}
|
Note
|
Properties: mayRaiseFPException |
VGETMANTPHZrmbik [HasFP16]
vgetmantph {src2, src1{1to32}, dst {mask}|dst {mask}, src1{1to32}, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VGETMANTPHZrmbikz [HasFP16]
vgetmantph {src2, src1{1to32}, dst {mask} {z}|dst {mask} {z}, src1{1to32}, src2}
|
Note
|
Properties: mayRaiseFPException |
VGETMANTPHZrmi [HasFP16]
vgetmantph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VGETMANTPHZrmik [HasFP16]
vgetmantph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VGETMANTPHZrmikz [HasFP16]
vgetmantph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VGETMANTPHZrri [HasFP16]
vgetmantph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VGETMANTPHZrrib [HasFP16]
vgetmantph {src2, {sae}, src1, dst|dst, src1, {sae}, src2}
VGETMANTPHZrribk [HasFP16]
vgetmantph {src2, {sae}, src1, dst {mask}|dst {mask}, src1, {sae}, src2}
|
Note
|
Constraints: src0 = dst |
VGETMANTPHZrribkz [HasFP16]
vgetmantph {src2, {sae}, src1, dst {mask} {z}|dst {mask} {z}, src1, {sae}, src2}
VGETMANTPHZrrik [HasFP16]
vgetmantph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VGETMANTPHZrrikz [HasFP16]
vgetmantph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VGETMANTSHZrmi [HasFP16]
vgetmantsh {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VGETMANTSHZrmik [HasFP16]
vgetmantsh {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VGETMANTSHZrmikz [HasFP16]
vgetmantsh {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VGETMANTSHZrri [HasFP16]
vgetmantsh {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VGETMANTSHZrrib [HasFP16]
vgetmantsh {src3, {sae}, src2, src1, dst|dst, src1, src2, {sae}, src3}
VGETMANTSHZrribk [HasFP16]
vgetmantsh {src3, {sae}, src2, src1, dst {mask}|dst {mask}, src1, src2, {sae}, src3}
|
Note
|
Constraints: src0 = dst |
VGETMANTSHZrribkz [HasFP16]
vgetmantsh {src3, {sae}, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, {sae}, src3}
VGETMANTSHZrrik [HasFP16]
vgetmantsh {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VGETMANTSHZrrikz [HasFP16]
vgetmantsh {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VMAXPHZrm [HasFP16]
vmaxph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMAXPHZrmb [HasFP16]
vmaxph {src2{1to32}, src1, dst|dst, src1, src2{1to32}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMAXPHZrmbk [HasFP16]
vmaxph {src2{1to32}, src1, dst {mask}|dst {mask}, src1, src2{1to32}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMAXPHZrmbkz [HasFP16]
vmaxph {src2{1to32}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to32}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMAXPHZrmk [HasFP16]
vmaxph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMAXPHZrmkz [HasFP16]
vmaxph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMAXPHZrr [HasFP16]
vmaxph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMAXPHZrrb [HasFP16]
vmaxph {{sae}, src2, src1, dst|dst, src1, src2, {sae}}
VMAXPHZrrbk [HasFP16]
vmaxph {{sae}, src2, src1, dst {mask}|dst {mask}, src1, src2, {sae}}
|
Note
|
Constraints: src0 = dst |
VMAXPHZrrbkz [HasFP16]
vmaxph {{sae}, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, {sae}}
VMAXPHZrrk [HasFP16]
vmaxph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMAXPHZrrkz [HasFP16]
vmaxph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMAXSHZrm_Int [HasFP16]
vmaxsh {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMAXSHZrmk_Int [HasFP16]
vmaxsh {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMAXSHZrmkz_Int [HasFP16]
vmaxsh {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMAXSHZrr_Int [HasFP16]
vmaxsh {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMAXSHZrrb_Int [HasFP16]
vmaxsh {{sae}, src2, src1, dst|dst, src1, src2, {sae}}
VMAXSHZrrbk_Int [HasFP16]
vmaxsh {{sae}, src2, src1, dst {mask}|dst {mask}, src1, src2, {sae}}
|
Note
|
Constraints: src0 = dst |
VMAXSHZrrbkz_Int [HasFP16]
vmaxsh {{sae}, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, {sae}}
VMAXSHZrrk_Int [HasFP16]
vmaxsh {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMAXSHZrrkz_Int [HasFP16]
vmaxsh {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMINPHZrm [HasFP16]
vminph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMINPHZrmb [HasFP16]
vminph {src2{1to32}, src1, dst|dst, src1, src2{1to32}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMINPHZrmbk [HasFP16]
vminph {src2{1to32}, src1, dst {mask}|dst {mask}, src1, src2{1to32}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMINPHZrmbkz [HasFP16]
vminph {src2{1to32}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to32}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMINPHZrmk [HasFP16]
vminph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMINPHZrmkz [HasFP16]
vminph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMINPHZrr [HasFP16]
vminph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMINPHZrrb [HasFP16]
vminph {{sae}, src2, src1, dst|dst, src1, src2, {sae}}
VMINPHZrrbk [HasFP16]
vminph {{sae}, src2, src1, dst {mask}|dst {mask}, src1, src2, {sae}}
|
Note
|
Constraints: src0 = dst |
VMINPHZrrbkz [HasFP16]
vminph {{sae}, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, {sae}}
VMINPHZrrk [HasFP16]
vminph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMINPHZrrkz [HasFP16]
vminph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMINSHZrm_Int [HasFP16]
vminsh {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMINSHZrmk_Int [HasFP16]
vminsh {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMINSHZrmkz_Int [HasFP16]
vminsh {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMINSHZrr_Int [HasFP16]
vminsh {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMINSHZrrb_Int [HasFP16]
vminsh {{sae}, src2, src1, dst|dst, src1, src2, {sae}}
VMINSHZrrbk_Int [HasFP16]
vminsh {{sae}, src2, src1, dst {mask}|dst {mask}, src1, src2, {sae}}
|
Note
|
Constraints: src0 = dst |
VMINSHZrrbkz_Int [HasFP16]
vminsh {{sae}, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, {sae}}
VMINSHZrrk_Int [HasFP16]
vminsh {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMINSHZrrkz_Int [HasFP16]
vminsh {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMOVSH2Wrr [HasFP16]
vmovw {src, dst|dst, src}
VMOVSHZmr [HasFP16]
vmovsh {src, dst|dst, src}
VMOVSHZmrk [HasFP16]
vmovsh {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
VMOVSHZrm [HasFP16]
vmovsh {src, dst|dst, src}
VMOVSHZrmk [HasFP16]
vmovsh {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VMOVSHZrmkz [HasFP16]
vmovsh {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayLoad |
VMOVSHZrr [HasFP16]
vmovsh {src2, src1, dst|dst, src1, src2}
VMOVSHZrrk [HasFP16]
vmovsh {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VMOVSHZrrkz [HasFP16]
vmovsh {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VMOVSHtoW64rr [HasFP16]
vmovw {src, dst|dst, src}
VMOVW2SHrr [HasFP16]
vmovw {src, dst|dst, src}
VMOVW64toSHrr [HasFP16]
vmovw {src, dst|dst, src}
VMOVWmr [HasFP16]
vmovw {src, dst|dst, src}
VMOVWrm [HasFP16]
vmovw {src, dst|dst, src}
VMULPHZrm [HasFP16]
vmulph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMULPHZrmb [HasFP16]
vmulph {src2{1to32}, src1, dst|dst, src1, src2{1to32}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMULPHZrmbk [HasFP16]
vmulph {src2{1to32}, src1, dst {mask}|dst {mask}, src1, src2{1to32}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMULPHZrmbkz [HasFP16]
vmulph {src2{1to32}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to32}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMULPHZrmk [HasFP16]
vmulph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMULPHZrmkz [HasFP16]
vmulph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMULPHZrr [HasFP16]
vmulph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMULPHZrrb [HasFP16]
vmulph {rc, src2, src1, dst|dst, src1, src2, rc}
VMULPHZrrbk [HasFP16]
vmulph {rc, src2, src1, dst {mask}|dst {mask}, src1, src2, rc}
|
Note
|
Constraints: src0 = dst |
VMULPHZrrbkz [HasFP16]
vmulph {rc, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, rc}
VMULPHZrrk [HasFP16]
vmulph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMULPHZrrkz [HasFP16]
vmulph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMULSHZrm_Int [HasFP16]
vmulsh {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMULSHZrmk_Int [HasFP16]
vmulsh {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMULSHZrmkz_Int [HasFP16]
vmulsh {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMULSHZrr_Int [HasFP16]
vmulsh {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMULSHZrrb_Int [HasFP16]
vmulsh {rc, src2, src1, dst|dst, src1, src2, rc}
VMULSHZrrbk_Int [HasFP16]
vmulsh {rc, src2, src1, dst {mask}|dst {mask}, src1, src2, rc}
|
Note
|
Constraints: src0 = dst |
VMULSHZrrbkz_Int [HasFP16]
vmulsh {rc, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, rc}
VMULSHZrrk_Int [HasFP16]
vmulsh {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMULSHZrrkz_Int [HasFP16]
vmulsh {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VRCPPHZm [HasFP16]
vrcpph {src, dst|dst, src}
VRCPPHZmb [HasFP16]
vrcpph {src{1to32}, dst|dst, src{1to32}}
VRCPPHZmbk [HasFP16]
vrcpph {src{1to32}, dst {mask}|dst {mask}, src{1to32}}
|
Note
|
Constraints: src0 = dst |
VRCPPHZmbkz [HasFP16]
vrcpph {src{1to32}, dst {mask} {z}|dst {mask} {z}, src{1to32}}
VRCPPHZmk [HasFP16]
vrcpph {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VRCPPHZmkz [HasFP16]
vrcpph {src, dst {mask} {z}|dst {mask} {z}, src}
VRCPPHZr [HasFP16]
vrcpph {src, dst|dst, src}
VRCPPHZrk [HasFP16]
vrcpph {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VRCPPHZrkz [HasFP16]
vrcpph {src, dst {mask} {z}|dst {mask} {z}, src}
VRCPSHZrm [HasFP16]
vrcpsh {src2, src1, dst|dst, src1, src2}
VRCPSHZrmk [HasFP16]
vrcpsh {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VRCPSHZrmkz [HasFP16]
vrcpsh {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VRCPSHZrr [HasFP16]
vrcpsh {src2, src1, dst|dst, src1, src2}
VRCPSHZrrk [HasFP16]
vrcpsh {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VRCPSHZrrkz [HasFP16]
vrcpsh {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VREDUCEPHZrmbi [HasFP16]
vreduceph {src2, src1{1to32}, dst|dst, src1{1to32}, src2}
|
Note
|
Properties: mayRaiseFPException |
VREDUCEPHZrmbik [HasFP16]
vreduceph {src2, src1{1to32}, dst {mask}|dst {mask}, src1{1to32}, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VREDUCEPHZrmbikz [HasFP16]
vreduceph {src2, src1{1to32}, dst {mask} {z}|dst {mask} {z}, src1{1to32}, src2}
|
Note
|
Properties: mayRaiseFPException |
VREDUCEPHZrmi [HasFP16]
vreduceph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VREDUCEPHZrmik [HasFP16]
vreduceph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VREDUCEPHZrmikz [HasFP16]
vreduceph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VREDUCEPHZrri [HasFP16]
vreduceph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VREDUCEPHZrrib [HasFP16]
vreduceph {src2, {sae}, src1, dst|dst, src1, {sae}, src2}
VREDUCEPHZrribk [HasFP16]
vreduceph {src2, {sae}, src1, dst {mask}|dst {mask}, src1, {sae}, src2}
|
Note
|
Constraints: src0 = dst |
VREDUCEPHZrribkz [HasFP16]
vreduceph {src2, {sae}, src1, dst {mask} {z}|dst {mask} {z}, src1, {sae}, src2}
VREDUCEPHZrrik [HasFP16]
vreduceph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VREDUCEPHZrrikz [HasFP16]
vreduceph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VREDUCESHZrmi [HasFP16]
vreducesh {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VREDUCESHZrmik [HasFP16]
vreducesh {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VREDUCESHZrmikz [HasFP16]
vreducesh {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VREDUCESHZrri [HasFP16]
vreducesh {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VREDUCESHZrrib [HasFP16]
vreducesh {src3, {sae}, src2, src1, dst|dst, src1, src2, {sae}, src3}
VREDUCESHZrribk [HasFP16]
vreducesh {src3, {sae}, src2, src1, dst {mask}|dst {mask}, src1, src2, {sae}, src3}
|
Note
|
Constraints: src0 = dst |
VREDUCESHZrribkz [HasFP16]
vreducesh {src3, {sae}, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, {sae}, src3}
VREDUCESHZrrik [HasFP16]
vreducesh {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VREDUCESHZrrikz [HasFP16]
vreducesh {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VRNDSCALEPHZrmbi [HasFP16]
vrndscaleph {src2, src1{1to32}, dst|dst, src1{1to32}, src2}
|
Note
|
Properties: mayRaiseFPException |
VRNDSCALEPHZrmbik [HasFP16]
vrndscaleph {src2, src1{1to32}, dst {mask}|dst {mask}, src1{1to32}, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRNDSCALEPHZrmbikz [HasFP16]
vrndscaleph {src2, src1{1to32}, dst {mask} {z}|dst {mask} {z}, src1{1to32}, src2}
|
Note
|
Properties: mayRaiseFPException |
VRNDSCALEPHZrmi [HasFP16]
vrndscaleph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VRNDSCALEPHZrmik [HasFP16]
vrndscaleph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRNDSCALEPHZrmikz [HasFP16]
vrndscaleph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VRNDSCALEPHZrri [HasFP16]
vrndscaleph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VRNDSCALEPHZrrib [HasFP16]
vrndscaleph {src2, {sae}, src1, dst|dst, src1, {sae}, src2}
VRNDSCALEPHZrribk [HasFP16]
vrndscaleph {src2, {sae}, src1, dst {mask}|dst {mask}, src1, {sae}, src2}
|
Note
|
Constraints: src0 = dst |
VRNDSCALEPHZrribkz [HasFP16]
vrndscaleph {src2, {sae}, src1, dst {mask} {z}|dst {mask} {z}, src1, {sae}, src2}
VRNDSCALEPHZrrik [HasFP16]
vrndscaleph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRNDSCALEPHZrrikz [HasFP16]
vrndscaleph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VRNDSCALESHZrmi_Int [HasFP16]
vrndscalesh {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VRNDSCALESHZrmik_Int [HasFP16]
vrndscalesh {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRNDSCALESHZrmikz_Int [HasFP16]
vrndscalesh {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VRNDSCALESHZrri_Int [HasFP16]
vrndscalesh {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VRNDSCALESHZrrib_Int [HasFP16]
vrndscalesh {src3, {sae}, src2, src1, dst|dst, src1, src2, {sae}, src3}
VRNDSCALESHZrribk_Int [HasFP16]
vrndscalesh {src3, {sae}, src2, src1, dst {mask}|dst {mask}, src1, src2, {sae}, src3}
|
Note
|
Constraints: src0 = dst |
VRNDSCALESHZrribkz_Int [HasFP16]
vrndscalesh {src3, {sae}, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, {sae}, src3}
VRNDSCALESHZrrik_Int [HasFP16]
vrndscalesh {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRNDSCALESHZrrikz_Int [HasFP16]
vrndscalesh {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VRSQRTPHZm [HasFP16]
vrsqrtph {src, dst|dst, src}
VRSQRTPHZmb [HasFP16]
vrsqrtph {src{1to32}, dst|dst, src{1to32}}
VRSQRTPHZmbk [HasFP16]
vrsqrtph {src{1to32}, dst {mask}|dst {mask}, src{1to32}}
|
Note
|
Constraints: src0 = dst |
VRSQRTPHZmbkz [HasFP16]
vrsqrtph {src{1to32}, dst {mask} {z}|dst {mask} {z}, src{1to32}}
VRSQRTPHZmk [HasFP16]
vrsqrtph {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VRSQRTPHZmkz [HasFP16]
vrsqrtph {src, dst {mask} {z}|dst {mask} {z}, src}
VRSQRTPHZr [HasFP16]
vrsqrtph {src, dst|dst, src}
VRSQRTPHZrk [HasFP16]
vrsqrtph {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VRSQRTPHZrkz [HasFP16]
vrsqrtph {src, dst {mask} {z}|dst {mask} {z}, src}
VRSQRTSHZrm [HasFP16]
vrsqrtsh {src2, src1, dst|dst, src1, src2}
VRSQRTSHZrmk [HasFP16]
vrsqrtsh {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VRSQRTSHZrmkz [HasFP16]
vrsqrtsh {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VRSQRTSHZrr [HasFP16]
vrsqrtsh {src2, src1, dst|dst, src1, src2}
VRSQRTSHZrrk [HasFP16]
vrsqrtsh {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VRSQRTSHZrrkz [HasFP16]
vrsqrtsh {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VSCALEFPHZrm [HasFP16]
vscalefph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSCALEFPHZrmb [HasFP16]
vscalefph {src2{1to32}, src1, dst|dst, src1, src2{1to32}}
|
Note
|
Properties: mayRaiseFPException |
VSCALEFPHZrmbk [HasFP16]
vscalefph {src2{1to32}, src1, dst {mask}|dst {mask}, src1, src2{1to32}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSCALEFPHZrmbkz [HasFP16]
vscalefph {src2{1to32}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to32}}
|
Note
|
Properties: mayRaiseFPException |
VSCALEFPHZrmk [HasFP16]
vscalefph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSCALEFPHZrmkz [HasFP16]
vscalefph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSCALEFPHZrr [HasFP16]
vscalefph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSCALEFPHZrrb [HasFP16]
vscalefph {rc, src2, src1, dst|dst, src1, src2, rc}
VSCALEFPHZrrbk [HasFP16]
vscalefph {rc, src2, src1, dst {mask}|dst {mask}, src1, src2, rc}
|
Note
|
Constraints: src0 = dst |
VSCALEFPHZrrbkz [HasFP16]
vscalefph {rc, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, rc}
VSCALEFPHZrrk [HasFP16]
vscalefph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSCALEFPHZrrkz [HasFP16]
vscalefph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSCALEFSHZrm [HasFP16]
vscalefsh {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSCALEFSHZrmk [HasFP16]
vscalefsh {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSCALEFSHZrmkz [HasFP16]
vscalefsh {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSCALEFSHZrr [HasFP16]
vscalefsh {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSCALEFSHZrrb_Int [HasFP16]
vscalefsh {rc, src2, src1, dst|dst, src1, src2, rc}
VSCALEFSHZrrbk_Int [HasFP16]
vscalefsh {rc, src2, src1, dst {mask}|dst {mask}, src1, src2, rc}
|
Note
|
Constraints: src0 = dst |
VSCALEFSHZrrbkz_Int [HasFP16]
vscalefsh {rc, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, rc}
VSCALEFSHZrrk [HasFP16]
vscalefsh {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSCALEFSHZrrkz [HasFP16]
vscalefsh {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSQRTPHZm [HasFP16]
vsqrtph {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VSQRTPHZmb [HasFP16]
vsqrtph {src{1to32}, dst|dst, src{1to32}}
|
Note
|
Properties: mayRaiseFPException |
VSQRTPHZmbk [HasFP16]
vsqrtph {src{1to32}, dst {mask}|dst {mask}, src{1to32}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSQRTPHZmbkz [HasFP16]
vsqrtph {src{1to32}, dst {mask} {z}|dst {mask} {z}, src{1to32}}
|
Note
|
Properties: mayRaiseFPException |
VSQRTPHZmk [HasFP16]
vsqrtph {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSQRTPHZmkz [HasFP16]
vsqrtph {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VSQRTPHZr [HasFP16]
vsqrtph {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VSQRTPHZrb [HasFP16]
vsqrtph {rc, src, dst|dst, src, rc}
VSQRTPHZrbk [HasFP16]
vsqrtph {rc, src, dst {mask}|dst {mask}, src, rc}
|
Note
|
Constraints: src0 = dst |
VSQRTPHZrbkz [HasFP16]
vsqrtph {rc, src, dst {mask} {z}|dst {mask} {z}, src, rc}
VSQRTPHZrk [HasFP16]
vsqrtph {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSQRTPHZrkz [HasFP16]
vsqrtph {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VSQRTSHZm_Int [HasFP16]
vsqrtsh {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSQRTSHZmk_Int [HasFP16]
vsqrtsh {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSQRTSHZmkz_Int [HasFP16]
vsqrtsh {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSQRTSHZr_Int [HasFP16]
vsqrtsh {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSQRTSHZrb_Int [HasFP16]
vsqrtsh {rc, src2, src1, dst|dst, src1, src2, rc}
VSQRTSHZrbk_Int [HasFP16]
vsqrtsh {rc, src2, src1, dst {mask}|dst {mask}, src1, src2, rc}
|
Note
|
Constraints: src0 = dst |
VSQRTSHZrbkz_Int [HasFP16]
vsqrtsh {rc, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, rc}
VSQRTSHZrk_Int [HasFP16]
vsqrtsh {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSQRTSHZrkz_Int [HasFP16]
vsqrtsh {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSUBPHZrm [HasFP16]
vsubph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VSUBPHZrmb [HasFP16]
vsubph {src2{1to32}, src1, dst|dst, src1, src2{1to32}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VSUBPHZrmbk [HasFP16]
vsubph {src2{1to32}, src1, dst {mask}|dst {mask}, src1, src2{1to32}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSUBPHZrmbkz [HasFP16]
vsubph {src2{1to32}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to32}}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VSUBPHZrmk [HasFP16]
vsubph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSUBPHZrmkz [HasFP16]
vsubph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VSUBPHZrr [HasFP16]
vsubph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSUBPHZrrb [HasFP16]
vsubph {rc, src2, src1, dst|dst, src1, src2, rc}
VSUBPHZrrbk [HasFP16]
vsubph {rc, src2, src1, dst {mask}|dst {mask}, src1, src2, rc}
|
Note
|
Constraints: src0 = dst |
VSUBPHZrrbkz [HasFP16]
vsubph {rc, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, rc}
VSUBPHZrrk [HasFP16]
vsubph {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSUBPHZrrkz [HasFP16]
vsubph {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSUBSHZrm_Int [HasFP16]
vsubsh {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSUBSHZrmk_Int [HasFP16]
vsubsh {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSUBSHZrmkz_Int [HasFP16]
vsubsh {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSUBSHZrr_Int [HasFP16]
vsubsh {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSUBSHZrrb_Int [HasFP16]
vsubsh {rc, src2, src1, dst|dst, src1, src2, rc}
VSUBSHZrrbk_Int [HasFP16]
vsubsh {rc, src2, src1, dst {mask}|dst {mask}, src1, src2, rc}
|
Note
|
Constraints: src0 = dst |
VSUBSHZrrbkz_Int [HasFP16]
vsubsh {rc, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, rc}
VSUBSHZrrk_Int [HasFP16]
vsubsh {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VSUBSHZrrkz_Int [HasFP16]
vsubsh {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VUCOMISHZrm [HasFP16]
vucomish {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VUCOMISHZrr [HasFP16]
vucomish {src2, src1|src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VUCOMISHZrrb [HasFP16]
vucomish {{sae}, src2, src1|src1, src2, {sae}}
ADC16mi8_EVEX [In64BitMode]
adc{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ADC16mi_EVEX [In64BitMode]
adc{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ADC16mr_EVEX [In64BitMode]
adc{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ADC16ri8_EVEX [In64BitMode]
adc{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ADC16ri_EVEX [In64BitMode]
adc{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ADC16rm_EVEX [In64BitMode]
adc{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
ADC16rr_EVEX [In64BitMode]
adc{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ADC32mi8_EVEX [In64BitMode]
adc{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ADC32mi_EVEX [In64BitMode]
adc{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ADC32mr_EVEX [In64BitMode]
adc{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ADC32ri8_EVEX [In64BitMode]
adc{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ADC32ri_EVEX [In64BitMode]
adc{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ADC32rm_EVEX [In64BitMode]
adc{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
ADC32rr_EVEX [In64BitMode]
adc{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ADC64mi32 [In64BitMode]
adc{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ADC64mi32_EVEX [In64BitMode]
adc{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ADC64mi8 [In64BitMode]
adc{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ADC64mi8_EVEX [In64BitMode]
adc{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ADC64mr_EVEX [In64BitMode]
adc{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ADC64ri32_EVEX [In64BitMode]
adc{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ADC64ri8_EVEX [In64BitMode]
adc{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ADC64rm_EVEX [In64BitMode]
adc{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
ADC64rr_EVEX [In64BitMode]
adc{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ADC8mi_EVEX [In64BitMode]
adc{b} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ADC8mr_EVEX [In64BitMode]
adc{b} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ADC8ri_EVEX [In64BitMode]
adc{b} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ADC8rm_EVEX [In64BitMode]
adc{b} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
ADC8rr_EVEX [In64BitMode]
adc{b} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ADCX32rm_EVEX [In64BitMode]
adcx{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
ADCX32rm_ND [In64BitMode]
adcx{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
ADCX32rr_EVEX [In64BitMode]
adcx{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ADCX32rr_ND [In64BitMode]
adcx{l} {src2, src1, dst|dst, src1, src2}
ADCX64rm_EVEX [In64BitMode]
adcx{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
ADCX64rm_ND [In64BitMode]
adcx{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
ADCX64rr_EVEX [In64BitMode]
adcx{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ADCX64rr_ND [In64BitMode]
adcx{q} {src2, src1, dst|dst, src1, src2}
ADD16mi8_EVEX [In64BitMode]
add{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ADD16mi8_NF [In64BitMode]
add{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ADD16mi_EVEX [In64BitMode]
add{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ADD16mi_NF [In64BitMode]
add{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ADD16mr_EVEX [In64BitMode]
add{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ADD16mr_NF [In64BitMode]
add{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ADD16ri8_EVEX [In64BitMode]
add{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ADD16ri8_NF [In64BitMode]
add{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ADD16ri_EVEX [In64BitMode]
add{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ADD16ri_NF [In64BitMode]
add{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ADD16rm_EVEX [In64BitMode]
add{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
ADD16rm_NF [In64BitMode]
add{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
ADD16rr_EVEX [In64BitMode]
add{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ADD16rr_NF [In64BitMode]
add{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ADD32mi8_EVEX [In64BitMode]
add{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ADD32mi8_NF [In64BitMode]
add{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ADD32mi_EVEX [In64BitMode]
add{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ADD32mi_NF [In64BitMode]
add{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ADD32mr_EVEX [In64BitMode]
add{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ADD32mr_NF [In64BitMode]
add{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ADD32ri8_EVEX [In64BitMode]
add{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ADD32ri8_NF [In64BitMode]
add{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ADD32ri_EVEX [In64BitMode]
add{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ADD32ri_NF [In64BitMode]
add{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ADD32rm_EVEX [In64BitMode]
add{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
ADD32rm_NF [In64BitMode]
add{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
ADD32rr_EVEX [In64BitMode]
add{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ADD32rr_NF [In64BitMode]
add{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ADD64mi32 [In64BitMode]
add{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ADD64mi32_EVEX [In64BitMode]
add{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ADD64mi32_NF [In64BitMode]
add{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ADD64mi8 [In64BitMode]
add{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ADD64mi8_EVEX [In64BitMode]
add{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ADD64mi8_NF [In64BitMode]
add{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ADD64mr_EVEX [In64BitMode]
add{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ADD64mr_NF [In64BitMode]
add{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ADD64ri32_EVEX [In64BitMode]
add{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ADD64ri32_NF [In64BitMode]
add{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ADD64ri8_EVEX [In64BitMode]
add{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ADD64ri8_NF [In64BitMode]
add{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ADD64rm_EVEX [In64BitMode]
add{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
ADD64rm_NF [In64BitMode]
add{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
ADD64rr_EVEX [In64BitMode]
add{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ADD64rr_NF [In64BitMode]
add{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ADD8mi_EVEX [In64BitMode]
add{b} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ADD8mi_NF [In64BitMode]
add{b} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ADD8mr_EVEX [In64BitMode]
add{b} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ADD8mr_NF [In64BitMode]
add{b} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ADD8ri_EVEX [In64BitMode]
add{b} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ADD8ri_NF [In64BitMode]
add{b} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ADD8rm_EVEX [In64BitMode]
add{b} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
ADD8rm_NF [In64BitMode]
add{b} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
ADD8rr_EVEX [In64BitMode]
add{b} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ADD8rr_NF [In64BitMode]
add{b} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ADDR32_PREFIX [In64BitMode]
addr32
ADOX32rm_EVEX [In64BitMode]
adox{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
ADOX32rm_ND [In64BitMode]
adox{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
ADOX32rr_EVEX [In64BitMode]
adox{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ADOX32rr_ND [In64BitMode]
adox{l} {src2, src1, dst|dst, src1, src2}
ADOX64rm_EVEX [In64BitMode]
adox{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
ADOX64rm_ND [In64BitMode]
adox{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
ADOX64rr_EVEX [In64BitMode]
adox{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ADOX64rr_ND [In64BitMode]
adox{q} {src2, src1, dst|dst, src1, src2}
AND16mi8_EVEX [In64BitMode]
and{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
AND16mi8_NF [In64BitMode]
and{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
AND16mi_EVEX [In64BitMode]
and{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
AND16mi_NF [In64BitMode]
and{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
AND16mr_EVEX [In64BitMode]
and{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
AND16mr_NF [In64BitMode]
and{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
AND16ri8_EVEX [In64BitMode]
and{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
AND16ri8_NF [In64BitMode]
and{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
AND16ri_EVEX [In64BitMode]
and{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
AND16ri_NF [In64BitMode]
and{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
AND16rm_EVEX [In64BitMode]
and{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
AND16rm_NF [In64BitMode]
and{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
AND16rr_EVEX [In64BitMode]
and{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
AND16rr_NF [In64BitMode]
and{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
AND32mi8_EVEX [In64BitMode]
and{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
AND32mi8_NF [In64BitMode]
and{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
AND32mi_EVEX [In64BitMode]
and{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
AND32mi_NF [In64BitMode]
and{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
AND32mr_EVEX [In64BitMode]
and{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
AND32mr_NF [In64BitMode]
and{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
AND32ri8_EVEX [In64BitMode]
and{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
AND32ri8_NF [In64BitMode]
and{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
AND32ri_EVEX [In64BitMode]
and{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
AND32ri_NF [In64BitMode]
and{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
AND32rm_EVEX [In64BitMode]
and{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
AND32rm_NF [In64BitMode]
and{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
AND32rr_EVEX [In64BitMode]
and{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
AND32rr_NF [In64BitMode]
and{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
AND64mi32 [In64BitMode]
and{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
AND64mi32_EVEX [In64BitMode]
and{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
AND64mi32_NF [In64BitMode]
and{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
AND64mi8 [In64BitMode]
and{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
AND64mi8_EVEX [In64BitMode]
and{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
AND64mi8_NF [In64BitMode]
and{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
AND64mr_EVEX [In64BitMode]
and{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
AND64mr_NF [In64BitMode]
and{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
AND64ri32_EVEX [In64BitMode]
and{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
AND64ri32_NF [In64BitMode]
and{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
AND64ri8_EVEX [In64BitMode]
and{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
AND64ri8_NF [In64BitMode]
and{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
AND64rm_EVEX [In64BitMode]
and{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
AND64rm_NF [In64BitMode]
and{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
AND64rr_EVEX [In64BitMode]
and{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
AND64rr_NF [In64BitMode]
and{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
AND8mi_EVEX [In64BitMode]
and{b} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
AND8mi_NF [In64BitMode]
and{b} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
AND8mr_EVEX [In64BitMode]
and{b} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
AND8mr_NF [In64BitMode]
and{b} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
AND8ri_EVEX [In64BitMode]
and{b} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
AND8ri_NF [In64BitMode]
and{b} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
AND8rm_EVEX [In64BitMode]
and{b} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
AND8rm_NF [In64BitMode]
and{b} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
AND8rr_EVEX [In64BitMode]
and{b} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
AND8rr_NF [In64BitMode]
and{b} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ANDN32rm_NF [In64BitMode]
andn{l} {src2, src1, dst|dst, src1, src2}
ANDN32rr_NF [In64BitMode]
andn{l} {src2, src1, dst|dst, src1, src2}
ANDN64rm_NF [In64BitMode]
andn{q} {src2, src1, dst|dst, src1, src2}
ANDN64rr_NF [In64BitMode]
andn{q} {src2, src1, dst|dst, src1, src2}
BEXTR32rm_NF [In64BitMode]
bextr{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
BEXTR32rr_NF [In64BitMode]
bextr{l} {src2, src1, dst|dst, src1, src2}
BEXTR64rm_NF [In64BitMode]
bextr{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
BEXTR64rr_NF [In64BitMode]
bextr{q} {src2, src1, dst|dst, src1, src2}
BLSI32rm_EVEX [In64BitMode]
blsi{l} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
BLSI32rm_NF [In64BitMode]
blsi{l} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
BLSI32rr_EVEX [In64BitMode]
blsi{l} {src1, dst|dst, src1}
BLSI32rr_NF [In64BitMode]
blsi{l} {src1, dst|dst, src1}
BLSI64rm_EVEX [In64BitMode]
blsi{q} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
BLSI64rm_NF [In64BitMode]
blsi{q} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
BLSI64rr_EVEX [In64BitMode]
blsi{q} {src1, dst|dst, src1}
BLSI64rr_NF [In64BitMode]
blsi{q} {src1, dst|dst, src1}
BLSMSK32rm_EVEX [In64BitMode]
blsmsk{l} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
BLSMSK32rm_NF [In64BitMode]
blsmsk{l} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
BLSMSK32rr_EVEX [In64BitMode]
blsmsk{l} {src1, dst|dst, src1}
BLSMSK32rr_NF [In64BitMode]
blsmsk{l} {src1, dst|dst, src1}
BLSMSK64rm_EVEX [In64BitMode]
blsmsk{q} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
BLSMSK64rm_NF [In64BitMode]
blsmsk{q} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
BLSMSK64rr_EVEX [In64BitMode]
blsmsk{q} {src1, dst|dst, src1}
BLSMSK64rr_NF [In64BitMode]
blsmsk{q} {src1, dst|dst, src1}
BLSR32rm_EVEX [In64BitMode]
blsr{l} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
BLSR32rm_NF [In64BitMode]
blsr{l} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
BLSR32rr_EVEX [In64BitMode]
blsr{l} {src1, dst|dst, src1}
BLSR32rr_NF [In64BitMode]
blsr{l} {src1, dst|dst, src1}
BLSR64rm_EVEX [In64BitMode]
blsr{q} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
BLSR64rm_NF [In64BitMode]
blsr{q} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
BLSR64rr_EVEX [In64BitMode]
blsr{q} {src1, dst|dst, src1}
BLSR64rr_NF [In64BitMode]
blsr{q} {src1, dst|dst, src1}
BT64mi8 [In64BitMode]
bt{q} {src2, src1|src1, src2}
BTC64mi8 [In64BitMode]
btc{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
BTR64mi8 [In64BitMode]
btr{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
BTS64mi8 [In64BitMode]
bts{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
BZHI32rm_NF [In64BitMode]
bzhi{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
BZHI32rr_NF [In64BitMode]
bzhi{l} {src2, src1, dst|dst, src1, src2}
BZHI64rm_NF [In64BitMode]
bzhi{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
BZHI64rr_NF [In64BitMode]
bzhi{q} {src2, src1, dst|dst, src1, src2}
CALL64pcrel32 [In64BitMode]
call{q} dst
|
Note
|
Properties: isCall |
CDQE [In64BitMode]
{cltq|cdqe}
CMP64mi32 [In64BitMode]
cmp{q} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare, mayLoad |
CMP64mi8 [In64BitMode]
cmp{q} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare, mayLoad |
CMPSQ [In64BitMode]
cmpsq {dst, src|src, dst}
CQO [In64BitMode]
{cqto|cqo}
DEC16m_EVEX [In64BitMode]
dec{w} src1
|
Note
|
Properties: mayLoad, mayStore |
DEC16m_NF [In64BitMode]
dec{w} src1
|
Note
|
Properties: mayLoad, mayStore |
DEC16m_NF_ND [In64BitMode]
dec{w} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
DEC16r_EVEX [In64BitMode]
dec{w} src1
|
Note
|
Constraints: src1 = dst |
DEC16r_NF [In64BitMode]
dec{w} src1
|
Note
|
Constraints: src1 = dst |
DEC16r_NF_ND [In64BitMode]
dec{w} {src1, dst|dst, src1}
DEC32m_EVEX [In64BitMode]
dec{l} src1
|
Note
|
Properties: mayLoad, mayStore |
DEC32m_NF [In64BitMode]
dec{l} src1
|
Note
|
Properties: mayLoad, mayStore |
DEC32m_NF_ND [In64BitMode]
dec{l} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
DEC32r_EVEX [In64BitMode]
dec{l} src1
|
Note
|
Constraints: src1 = dst |
DEC32r_NF [In64BitMode]
dec{l} src1
|
Note
|
Constraints: src1 = dst |
DEC32r_NF_ND [In64BitMode]
dec{l} {src1, dst|dst, src1}
DEC64m_EVEX [In64BitMode]
dec{q} src1
|
Note
|
Properties: mayLoad, mayStore |
DEC64m_NF [In64BitMode]
dec{q} src1
|
Note
|
Properties: mayLoad, mayStore |
DEC64m_NF_ND [In64BitMode]
dec{q} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
DEC64r_EVEX [In64BitMode]
dec{q} src1
|
Note
|
Constraints: src1 = dst |
DEC64r_NF [In64BitMode]
dec{q} src1
|
Note
|
Constraints: src1 = dst |
DEC64r_NF_ND [In64BitMode]
dec{q} {src1, dst|dst, src1}
DEC8m_EVEX [In64BitMode]
dec{b} src1
|
Note
|
Properties: mayLoad, mayStore |
DEC8m_NF [In64BitMode]
dec{b} src1
|
Note
|
Properties: mayLoad, mayStore |
DEC8m_NF_ND [In64BitMode]
dec{b} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
DEC8r_EVEX [In64BitMode]
dec{b} src1
|
Note
|
Constraints: src1 = dst |
DEC8r_NF [In64BitMode]
dec{b} src1
|
Note
|
Constraints: src1 = dst |
DEC8r_NF_ND [In64BitMode]
dec{b} {src1, dst|dst, src1}
DIV16m_EVEX [In64BitMode]
div{w} src1
|
Note
|
Properties: hasSideEffects, mayLoad |
DIV16m_NF [In64BitMode]
div{w} src1
|
Note
|
Properties: hasSideEffects, mayLoad |
DIV16r_EVEX [In64BitMode]
div{w} src1
|
Note
|
Properties: hasSideEffects |
DIV16r_NF [In64BitMode]
div{w} src1
|
Note
|
Properties: hasSideEffects |
DIV32m_EVEX [In64BitMode]
div{l} src1
|
Note
|
Properties: hasSideEffects, mayLoad |
DIV32m_NF [In64BitMode]
div{l} src1
|
Note
|
Properties: hasSideEffects, mayLoad |
DIV32r_EVEX [In64BitMode]
div{l} src1
|
Note
|
Properties: hasSideEffects |
DIV32r_NF [In64BitMode]
div{l} src1
|
Note
|
Properties: hasSideEffects |
DIV64m [In64BitMode]
div{q} src1
|
Note
|
Properties: hasSideEffects, mayLoad |
DIV64m_EVEX [In64BitMode]
div{q} src1
|
Note
|
Properties: hasSideEffects, mayLoad |
DIV64m_NF [In64BitMode]
div{q} src1
|
Note
|
Properties: hasSideEffects, mayLoad |
DIV64r_EVEX [In64BitMode]
div{q} src1
|
Note
|
Properties: hasSideEffects |
DIV64r_NF [In64BitMode]
div{q} src1
|
Note
|
Properties: hasSideEffects |
DIV8m_EVEX [In64BitMode]
div{b} src1
|
Note
|
Properties: hasSideEffects, mayLoad |
DIV8m_NF [In64BitMode]
div{b} src1
|
Note
|
Properties: hasSideEffects, mayLoad |
DIV8r_EVEX [In64BitMode]
div{b} src1
|
Note
|
Properties: hasSideEffects |
DIV8r_NF [In64BitMode]
div{b} src1
|
Note
|
Properties: hasSideEffects |
ERETS [In64BitMode]
erets
|
Note
|
Properties: hasSideEffects |
ERETU [In64BitMode]
eretu
|
Note
|
Properties: hasSideEffects |
FARJMP64m [In64BitMode]
ljmp{q} {*}dst
|
Note
|
Properties: isBarrier, isBranch, isIndirectBranch, isTerminator, mayLoad |
IDIV16m_EVEX [In64BitMode]
idiv{w} src1
|
Note
|
Properties: hasSideEffects, mayLoad |
IDIV16m_NF [In64BitMode]
idiv{w} src1
|
Note
|
Properties: hasSideEffects, mayLoad |
IDIV16r_EVEX [In64BitMode]
idiv{w} src1
|
Note
|
Properties: hasSideEffects |
IDIV16r_NF [In64BitMode]
idiv{w} src1
|
Note
|
Properties: hasSideEffects |
IDIV32m_EVEX [In64BitMode]
idiv{l} src1
|
Note
|
Properties: hasSideEffects, mayLoad |
IDIV32m_NF [In64BitMode]
idiv{l} src1
|
Note
|
Properties: hasSideEffects, mayLoad |
IDIV32r_EVEX [In64BitMode]
idiv{l} src1
|
Note
|
Properties: hasSideEffects |
IDIV32r_NF [In64BitMode]
idiv{l} src1
|
Note
|
Properties: hasSideEffects |
IDIV64m [In64BitMode]
idiv{q} src1
|
Note
|
Properties: hasSideEffects, mayLoad |
IDIV64m_EVEX [In64BitMode]
idiv{q} src1
|
Note
|
Properties: hasSideEffects, mayLoad |
IDIV64m_NF [In64BitMode]
idiv{q} src1
|
Note
|
Properties: hasSideEffects, mayLoad |
IDIV64r_EVEX [In64BitMode]
idiv{q} src1
|
Note
|
Properties: hasSideEffects |
IDIV64r_NF [In64BitMode]
idiv{q} src1
|
Note
|
Properties: hasSideEffects |
IDIV8m_EVEX [In64BitMode]
idiv{b} src1
|
Note
|
Properties: hasSideEffects, mayLoad |
IDIV8m_NF [In64BitMode]
idiv{b} src1
|
Note
|
Properties: hasSideEffects, mayLoad |
IDIV8r_EVEX [In64BitMode]
idiv{b} src1
|
Note
|
Properties: hasSideEffects |
IDIV8r_NF [In64BitMode]
idiv{b} src1
|
Note
|
Properties: hasSideEffects |
IMUL16m_EVEX [In64BitMode]
imul{w} src1
|
Note
|
Properties: mayLoad |
IMUL16m_NF [In64BitMode]
imul{w} src1
|
Note
|
Properties: mayLoad |
IMUL16r_EVEX [In64BitMode]
imul{w} src1
IMUL16r_NF [In64BitMode]
imul{w} src1
IMUL16rm_EVEX [In64BitMode]
imul{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
IMUL16rm_NF [In64BitMode]
imul{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
IMUL16rm_NF_ND [In64BitMode]
imul{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
IMUL16rmi8_EVEX [In64BitMode]
imul{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
IMUL16rmi8_NF [In64BitMode]
imul{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
IMUL16rmi_EVEX [In64BitMode]
imul{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
IMUL16rmi_NF [In64BitMode]
imul{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
IMUL16rr_EVEX [In64BitMode]
imul{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
IMUL16rr_NF [In64BitMode]
imul{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
IMUL16rr_NF_ND [In64BitMode]
imul{w} {src2, src1, dst|dst, src1, src2}
IMUL16rri8_EVEX [In64BitMode]
imul{w} {src2, src1, dst|dst, src1, src2}
IMUL16rri8_NF [In64BitMode]
imul{w} {src2, src1, dst|dst, src1, src2}
IMUL16rri_EVEX [In64BitMode]
imul{w} {src2, src1, dst|dst, src1, src2}
IMUL16rri_NF [In64BitMode]
imul{w} {src2, src1, dst|dst, src1, src2}
IMUL32m_EVEX [In64BitMode]
imul{l} src1
|
Note
|
Properties: mayLoad |
IMUL32m_NF [In64BitMode]
imul{l} src1
|
Note
|
Properties: mayLoad |
IMUL32r_EVEX [In64BitMode]
imul{l} src1
IMUL32r_NF [In64BitMode]
imul{l} src1
IMUL32rm_EVEX [In64BitMode]
imul{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
IMUL32rm_NF [In64BitMode]
imul{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
IMUL32rm_NF_ND [In64BitMode]
imul{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
IMUL32rmi8_EVEX [In64BitMode]
imul{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
IMUL32rmi8_NF [In64BitMode]
imul{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
IMUL32rmi_EVEX [In64BitMode]
imul{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
IMUL32rmi_NF [In64BitMode]
imul{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
IMUL32rr_EVEX [In64BitMode]
imul{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
IMUL32rr_NF [In64BitMode]
imul{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
IMUL32rr_NF_ND [In64BitMode]
imul{l} {src2, src1, dst|dst, src1, src2}
IMUL32rri8_EVEX [In64BitMode]
imul{l} {src2, src1, dst|dst, src1, src2}
IMUL32rri8_NF [In64BitMode]
imul{l} {src2, src1, dst|dst, src1, src2}
IMUL32rri_EVEX [In64BitMode]
imul{l} {src2, src1, dst|dst, src1, src2}
IMUL32rri_NF [In64BitMode]
imul{l} {src2, src1, dst|dst, src1, src2}
IMUL64m [In64BitMode]
imul{q} src1
|
Note
|
Properties: mayLoad |
IMUL64m_EVEX [In64BitMode]
imul{q} src1
|
Note
|
Properties: mayLoad |
IMUL64m_NF [In64BitMode]
imul{q} src1
|
Note
|
Properties: mayLoad |
IMUL64r_EVEX [In64BitMode]
imul{q} src1
IMUL64r_NF [In64BitMode]
imul{q} src1
IMUL64rm_EVEX [In64BitMode]
imul{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
IMUL64rm_NF [In64BitMode]
imul{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
IMUL64rm_NF_ND [In64BitMode]
imul{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
IMUL64rmi32_EVEX [In64BitMode]
imul{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
IMUL64rmi32_NF [In64BitMode]
imul{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
IMUL64rmi8_EVEX [In64BitMode]
imul{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
IMUL64rmi8_NF [In64BitMode]
imul{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
IMUL64rr_EVEX [In64BitMode]
imul{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
IMUL64rr_NF [In64BitMode]
imul{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
IMUL64rr_NF_ND [In64BitMode]
imul{q} {src2, src1, dst|dst, src1, src2}
IMUL64rri32_EVEX [In64BitMode]
imul{q} {src2, src1, dst|dst, src1, src2}
IMUL64rri32_NF [In64BitMode]
imul{q} {src2, src1, dst|dst, src1, src2}
IMUL64rri8_EVEX [In64BitMode]
imul{q} {src2, src1, dst|dst, src1, src2}
IMUL64rri8_NF [In64BitMode]
imul{q} {src2, src1, dst|dst, src1, src2}
IMUL8m_EVEX [In64BitMode]
imul{b} src1
|
Note
|
Properties: mayLoad |
IMUL8m_NF [In64BitMode]
imul{b} src1
|
Note
|
Properties: mayLoad |
IMUL8r_EVEX [In64BitMode]
imul{b} src1
IMUL8r_NF [In64BitMode]
imul{b} src1
INC16m_EVEX [In64BitMode]
inc{w} src1
|
Note
|
Properties: mayLoad, mayStore |
INC16m_NF [In64BitMode]
inc{w} src1
|
Note
|
Properties: mayLoad, mayStore |
INC16m_NF_ND [In64BitMode]
inc{w} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
INC16r_EVEX [In64BitMode]
inc{w} src1
|
Note
|
Constraints: src1 = dst |
INC16r_NF [In64BitMode]
inc{w} src1
|
Note
|
Constraints: src1 = dst |
INC16r_NF_ND [In64BitMode]
inc{w} {src1, dst|dst, src1}
INC32m_EVEX [In64BitMode]
inc{l} src1
|
Note
|
Properties: mayLoad, mayStore |
INC32m_NF [In64BitMode]
inc{l} src1
|
Note
|
Properties: mayLoad, mayStore |
INC32m_NF_ND [In64BitMode]
inc{l} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
INC32r_EVEX [In64BitMode]
inc{l} src1
|
Note
|
Constraints: src1 = dst |
INC32r_NF [In64BitMode]
inc{l} src1
|
Note
|
Constraints: src1 = dst |
INC32r_NF_ND [In64BitMode]
inc{l} {src1, dst|dst, src1}
INC64m_EVEX [In64BitMode]
inc{q} src1
|
Note
|
Properties: mayLoad, mayStore |
INC64m_NF [In64BitMode]
inc{q} src1
|
Note
|
Properties: mayLoad, mayStore |
INC64m_NF_ND [In64BitMode]
inc{q} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
INC64r_EVEX [In64BitMode]
inc{q} src1
|
Note
|
Constraints: src1 = dst |
INC64r_NF [In64BitMode]
inc{q} src1
|
Note
|
Constraints: src1 = dst |
INC64r_NF_ND [In64BitMode]
inc{q} {src1, dst|dst, src1}
INC8m_EVEX [In64BitMode]
inc{b} src1
|
Note
|
Properties: mayLoad, mayStore |
INC8m_NF [In64BitMode]
inc{b} src1
|
Note
|
Properties: mayLoad, mayStore |
INC8m_NF_ND [In64BitMode]
inc{b} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
INC8r_EVEX [In64BitMode]
inc{b} src1
|
Note
|
Constraints: src1 = dst |
INC8r_NF [In64BitMode]
inc{b} src1
|
Note
|
Constraints: src1 = dst |
INC8r_NF_ND [In64BitMode]
inc{b} {src1, dst|dst, src1}
INVEPT64 [In64BitMode]
invept {src2, src1|src1, src2}
INVEPT64_EVEX [In64BitMode]
invept {src2, src1|src1, src2}
INVLPGA64 [In64BitMode]
invlpga
INVLPGB64 [In64BitMode]
invlpgb
INVPCID64 [In64BitMode]
invpcid {src2, src1|src1, src2}
INVPCID64_EVEX [In64BitMode]
invpcid {src2, src1|src1, src2}
INVVPID64 [In64BitMode]
invvpid {src2, src1|src1, src2}
INVVPID64_EVEX [In64BitMode]
invvpid {src2, src1|src1, src2}
IRET64 [In64BitMode]
iretq
|
Note
|
Properties: hasCtrlDep, isBarrier, isReturn, isTerminator |
JMP64m [In64BitMode]
jmp{q} {*}dst
|
Note
|
Properties: isBarrier, isBranch, isIndirectBranch, isTerminator |
JMP64r [In64BitMode]
jmp{q} {*}dst
|
Note
|
Properties: isBarrier, isBranch, isIndirectBranch, isTerminator |
JMPABS64i [In64BitMode]
jmpabs dst
JRCXZ [In64BitMode]
jrcxz dst
|
Note
|
Properties: isBranch, isTerminator |
LEA64_32r [In64BitMode]
lea{l} {src|dst}, {dst|src}
LEAVE64 [In64BitMode]
leave
|
Note
|
Properties: mayLoad |
LGDT64m [In64BitMode]
lgdt{q} src
LIDT64m [In64BitMode]
lidt{q} src
LKGS16m [In64BitMode]
lkgs src
|
Note
|
Properties: hasSideEffects, mayLoad |
LKGS16r [In64BitMode]
lkgs src
|
Note
|
Properties: hasSideEffects |
LODSQ [In64BitMode]
lodsq {src, %rax|rax, src}
LRET64 [In64BitMode]
{l}ret{|f}q
|
Note
|
Properties: hasCtrlDep, isBarrier, isReturn, isTerminator |
LRETI64 [In64BitMode]
{l}ret{|f}q amt
|
Note
|
Properties: hasCtrlDep, isBarrier, isReturn, isTerminator |
MOV64cr [In64BitMode]
mov{q} {src, dst|dst, src}
MOV64dr [In64BitMode]
mov{q} {src, dst|dst, src}
MOV64mi32 [In64BitMode]
mov{q} {src, dst|dst, src}
MOV64rc [In64BitMode]
mov{q} {src, dst|dst, src}
MOV64rd [In64BitMode]
mov{q} {src, dst|dst, src}
MOVSQ [In64BitMode]
movsq {src, dst|dst, src}
MOVSX64rm32 [In64BitMode]
movs{lq|xd} {src, dst|dst, src}
MOVSX64rr32 [In64BitMode]
movs{lq|xd} {src, dst|dst, src}
MUL16m_EVEX [In64BitMode]
mul{w} src1
|
Note
|
Properties: mayLoad |
MUL16m_NF [In64BitMode]
mul{w} src1
|
Note
|
Properties: mayLoad |
MUL16r_EVEX [In64BitMode]
mul{w} src1
MUL16r_NF [In64BitMode]
mul{w} src1
MUL32m_EVEX [In64BitMode]
mul{l} src1
|
Note
|
Properties: mayLoad |
MUL32m_NF [In64BitMode]
mul{l} src1
|
Note
|
Properties: mayLoad |
MUL32r_EVEX [In64BitMode]
mul{l} src1
MUL32r_NF [In64BitMode]
mul{l} src1
MUL64m [In64BitMode]
mul{q} src1
|
Note
|
Properties: mayLoad |
MUL64m_EVEX [In64BitMode]
mul{q} src1
|
Note
|
Properties: mayLoad |
MUL64m_NF [In64BitMode]
mul{q} src1
|
Note
|
Properties: mayLoad |
MUL64r_EVEX [In64BitMode]
mul{q} src1
MUL64r_NF [In64BitMode]
mul{q} src1
MUL8m_EVEX [In64BitMode]
mul{b} src1
|
Note
|
Properties: mayLoad |
MUL8m_NF [In64BitMode]
mul{b} src1
|
Note
|
Properties: mayLoad |
MUL8r_EVEX [In64BitMode]
mul{b} src1
MUL8r_NF [In64BitMode]
mul{b} src1
MULX32rm_EVEX [In64BitMode]
mulx{l} {src, dst2, dst1|dst1, dst2, src}
|
Note
|
Properties: mayLoad |
MULX32rr_EVEX [In64BitMode]
mulx{l} {src, dst2, dst1|dst1, dst2, src}
MULX64rm_EVEX [In64BitMode]
mulx{q} {src, dst2, dst1|dst1, dst2, src}
|
Note
|
Properties: mayLoad |
MULX64rr_EVEX [In64BitMode]
mulx{q} {src, dst2, dst1|dst1, dst2, src}
NEG16m_EVEX [In64BitMode]
neg{w} src1
|
Note
|
Properties: mayLoad, mayStore |
NEG16m_NF [In64BitMode]
neg{w} src1
|
Note
|
Properties: mayLoad, mayStore |
NEG16r_EVEX [In64BitMode]
neg{w} src1
|
Note
|
Constraints: src1 = dst |
NEG16r_NF [In64BitMode]
neg{w} src1
|
Note
|
Constraints: src1 = dst |
NEG32m_EVEX [In64BitMode]
neg{l} src1
|
Note
|
Properties: mayLoad, mayStore |
NEG32m_NF [In64BitMode]
neg{l} src1
|
Note
|
Properties: mayLoad, mayStore |
NEG32r_EVEX [In64BitMode]
neg{l} src1
|
Note
|
Constraints: src1 = dst |
NEG32r_NF [In64BitMode]
neg{l} src1
|
Note
|
Constraints: src1 = dst |
NEG64m [In64BitMode]
neg{q} src1
|
Note
|
Properties: mayLoad, mayStore |
NEG64m_EVEX [In64BitMode]
neg{q} src1
|
Note
|
Properties: mayLoad, mayStore |
NEG64m_NF [In64BitMode]
neg{q} src1
|
Note
|
Properties: mayLoad, mayStore |
NEG64r_EVEX [In64BitMode]
neg{q} src1
|
Note
|
Constraints: src1 = dst |
NEG64r_NF [In64BitMode]
neg{q} src1
|
Note
|
Constraints: src1 = dst |
NEG8m_EVEX [In64BitMode]
neg{b} src1
|
Note
|
Properties: mayLoad, mayStore |
NEG8m_NF [In64BitMode]
neg{b} src1
|
Note
|
Properties: mayLoad, mayStore |
NEG8r_EVEX [In64BitMode]
neg{b} src1
|
Note
|
Constraints: src1 = dst |
NEG8r_NF [In64BitMode]
neg{b} src1
|
Note
|
Constraints: src1 = dst |
NOOPQ [In64BitMode]
nop{q} zero
NOOPQr [In64BitMode]
nop{q} zero
NOT16m_EVEX [In64BitMode]
not{w} src1
|
Note
|
Properties: mayLoad, mayStore |
NOT16r_EVEX [In64BitMode]
not{w} src1
|
Note
|
Constraints: src1 = dst |
NOT32m_EVEX [In64BitMode]
not{l} src1
|
Note
|
Properties: mayLoad, mayStore |
NOT32r_EVEX [In64BitMode]
not{l} src1
|
Note
|
Constraints: src1 = dst |
NOT64m [In64BitMode]
not{q} src1
|
Note
|
Properties: mayLoad, mayStore |
NOT64m_EVEX [In64BitMode]
not{q} src1
|
Note
|
Properties: mayLoad, mayStore |
NOT64r_EVEX [In64BitMode]
not{q} src1
|
Note
|
Constraints: src1 = dst |
NOT8m_EVEX [In64BitMode]
not{b} src1
|
Note
|
Properties: mayLoad, mayStore |
NOT8r_EVEX [In64BitMode]
not{b} src1
|
Note
|
Constraints: src1 = dst |
OR16mi8_EVEX [In64BitMode]
or{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
OR16mi8_NF [In64BitMode]
or{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
OR16mi_EVEX [In64BitMode]
or{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
OR16mi_NF [In64BitMode]
or{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
OR16mr_EVEX [In64BitMode]
or{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
OR16mr_NF [In64BitMode]
or{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
OR16ri8_EVEX [In64BitMode]
or{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
OR16ri8_NF [In64BitMode]
or{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
OR16ri_EVEX [In64BitMode]
or{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
OR16ri_NF [In64BitMode]
or{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
OR16rm_EVEX [In64BitMode]
or{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
OR16rm_NF [In64BitMode]
or{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
OR16rr_EVEX [In64BitMode]
or{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
OR16rr_NF [In64BitMode]
or{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
OR32mi8_EVEX [In64BitMode]
or{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
OR32mi8_NF [In64BitMode]
or{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
OR32mi_EVEX [In64BitMode]
or{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
OR32mi_NF [In64BitMode]
or{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
OR32mr_EVEX [In64BitMode]
or{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
OR32mr_NF [In64BitMode]
or{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
OR32ri8_EVEX [In64BitMode]
or{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
OR32ri8_NF [In64BitMode]
or{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
OR32ri_EVEX [In64BitMode]
or{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
OR32ri_NF [In64BitMode]
or{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
OR32rm_EVEX [In64BitMode]
or{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
OR32rm_NF [In64BitMode]
or{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
OR32rr_EVEX [In64BitMode]
or{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
OR32rr_NF [In64BitMode]
or{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
OR64mi32 [In64BitMode]
or{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
OR64mi32_EVEX [In64BitMode]
or{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
OR64mi32_NF [In64BitMode]
or{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
OR64mi8 [In64BitMode]
or{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
OR64mi8_EVEX [In64BitMode]
or{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
OR64mi8_NF [In64BitMode]
or{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
OR64mr_EVEX [In64BitMode]
or{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
OR64mr_NF [In64BitMode]
or{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
OR64ri32_EVEX [In64BitMode]
or{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
OR64ri32_NF [In64BitMode]
or{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
OR64ri8_EVEX [In64BitMode]
or{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
OR64ri8_NF [In64BitMode]
or{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
OR64rm_EVEX [In64BitMode]
or{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
OR64rm_NF [In64BitMode]
or{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
OR64rr_EVEX [In64BitMode]
or{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
OR64rr_NF [In64BitMode]
or{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
OR8mi_EVEX [In64BitMode]
or{b} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
OR8mi_NF [In64BitMode]
or{b} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
OR8mr_EVEX [In64BitMode]
or{b} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
OR8mr_NF [In64BitMode]
or{b} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
OR8ri_EVEX [In64BitMode]
or{b} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
OR8ri_NF [In64BitMode]
or{b} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
OR8rm_EVEX [In64BitMode]
or{b} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
OR8rm_NF [In64BitMode]
or{b} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
OR8rr_EVEX [In64BitMode]
or{b} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
OR8rr_NF [In64BitMode]
or{b} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
PBNDKB [In64BitMode]
pbndkb
POP64r [In64BitMode]
pop{q} reg
|
Note
|
Properties: mayLoad |
POP64rmm [In64BitMode]
pop{q} dst
|
Note
|
Properties: mayLoad, mayStore |
POPF64 [In64BitMode]
popfq
|
Note
|
Properties: mayLoad |
POPFS64 [In64BitMode]
pop{q} {%fs|fs}
POPGS64 [In64BitMode]
pop{q} {%gs|gs}
POPP64r [In64BitMode]
popp reg
|
Note
|
Properties: mayLoad |
PSMASH [In64BitMode]
psmash
PUSH64i32 [In64BitMode]
push{q} imm
|
Note
|
Properties: mayStore |
PUSH64i8 [In64BitMode]
push{q} imm
|
Note
|
Properties: mayStore |
PUSH64r [In64BitMode]
push{q} reg
|
Note
|
Properties: mayStore |
PUSH64rmm [In64BitMode]
push{q} src
|
Note
|
Properties: mayLoad, mayStore |
PUSHF64 [In64BitMode]
pushfq
|
Note
|
Properties: mayStore |
PUSHFS64 [In64BitMode]
push{q} {%fs|fs}
PUSHGS64 [In64BitMode]
push{q} {%gs|gs}
PUSHP64r [In64BitMode]
pushp reg
|
Note
|
Properties: mayStore |
PVALIDATE64 [In64BitMode]
pvalidate
RCL16m1_EVEX [In64BitMode]
rcl{w} src1
|
Note
|
Properties: mayLoad, mayStore |
RCL16m1_ND [In64BitMode]
rcl{w} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
RCL16mCL_EVEX [In64BitMode]
rcl{w} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
RCL16mi_EVEX [In64BitMode]
rcl{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
RCL16r1_EVEX [In64BitMode]
rcl{w} src1
|
Note
|
Constraints: src1 = dst |
RCL16r1_ND [In64BitMode]
rcl{w} {src1, dst|dst, src1}
RCL16rCL_EVEX [In64BitMode]
rcl{w} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
RCL16ri_EVEX [In64BitMode]
rcl{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
RCL32m1_EVEX [In64BitMode]
rcl{l} src1
|
Note
|
Properties: mayLoad, mayStore |
RCL32m1_ND [In64BitMode]
rcl{l} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
RCL32mCL_EVEX [In64BitMode]
rcl{l} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
RCL32mi_EVEX [In64BitMode]
rcl{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
RCL32r1_EVEX [In64BitMode]
rcl{l} src1
|
Note
|
Constraints: src1 = dst |
RCL32r1_ND [In64BitMode]
rcl{l} {src1, dst|dst, src1}
RCL32rCL_EVEX [In64BitMode]
rcl{l} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
RCL32ri_EVEX [In64BitMode]
rcl{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
RCL64m1 [In64BitMode]
rcl{q} src1
|
Note
|
Properties: mayLoad, mayStore |
RCL64m1_EVEX [In64BitMode]
rcl{q} src1
|
Note
|
Properties: mayLoad, mayStore |
RCL64m1_ND [In64BitMode]
rcl{q} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
RCL64mCL [In64BitMode]
rcl{q} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
RCL64mCL_EVEX [In64BitMode]
rcl{q} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
RCL64mi [In64BitMode]
rcl{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
RCL64mi_EVEX [In64BitMode]
rcl{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
RCL64r1_EVEX [In64BitMode]
rcl{q} src1
|
Note
|
Constraints: src1 = dst |
RCL64r1_ND [In64BitMode]
rcl{q} {src1, dst|dst, src1}
RCL64rCL_EVEX [In64BitMode]
rcl{q} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
RCL64ri_EVEX [In64BitMode]
rcl{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
RCL8m1_EVEX [In64BitMode]
rcl{b} src1
|
Note
|
Properties: mayLoad, mayStore |
RCL8m1_ND [In64BitMode]
rcl{b} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
RCL8mCL_EVEX [In64BitMode]
rcl{b} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
RCL8mi_EVEX [In64BitMode]
rcl{b} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
RCL8r1_EVEX [In64BitMode]
rcl{b} src1
|
Note
|
Constraints: src1 = dst |
RCL8rCL_EVEX [In64BitMode]
rcl{b} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
RCL8ri_EVEX [In64BitMode]
rcl{b} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
RCR16m1_EVEX [In64BitMode]
rcr{w} src1
|
Note
|
Properties: mayLoad, mayStore |
RCR16m1_ND [In64BitMode]
rcr{w} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
RCR16mCL_EVEX [In64BitMode]
rcr{w} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
RCR16mi_EVEX [In64BitMode]
rcr{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
RCR16r1_EVEX [In64BitMode]
rcr{w} src1
|
Note
|
Constraints: src1 = dst |
RCR16r1_ND [In64BitMode]
rcr{w} {src1, dst|dst, src1}
RCR16rCL_EVEX [In64BitMode]
rcr{w} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
RCR16ri_EVEX [In64BitMode]
rcr{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
RCR32m1_EVEX [In64BitMode]
rcr{l} src1
|
Note
|
Properties: mayLoad, mayStore |
RCR32m1_ND [In64BitMode]
rcr{l} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
RCR32mCL_EVEX [In64BitMode]
rcr{l} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
RCR32mi_EVEX [In64BitMode]
rcr{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
RCR32r1_EVEX [In64BitMode]
rcr{l} src1
|
Note
|
Constraints: src1 = dst |
RCR32r1_ND [In64BitMode]
rcr{l} {src1, dst|dst, src1}
RCR32rCL_EVEX [In64BitMode]
rcr{l} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
RCR32ri_EVEX [In64BitMode]
rcr{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
RCR64m1 [In64BitMode]
rcr{q} src1
|
Note
|
Properties: mayLoad, mayStore |
RCR64m1_EVEX [In64BitMode]
rcr{q} src1
|
Note
|
Properties: mayLoad, mayStore |
RCR64m1_ND [In64BitMode]
rcr{q} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
RCR64mCL [In64BitMode]
rcr{q} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
RCR64mCL_EVEX [In64BitMode]
rcr{q} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
RCR64mi [In64BitMode]
rcr{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
RCR64mi_EVEX [In64BitMode]
rcr{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
RCR64r1_EVEX [In64BitMode]
rcr{q} src1
|
Note
|
Constraints: src1 = dst |
RCR64r1_ND [In64BitMode]
rcr{q} {src1, dst|dst, src1}
RCR64rCL_EVEX [In64BitMode]
rcr{q} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
RCR64ri_EVEX [In64BitMode]
rcr{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
RCR8m1_EVEX [In64BitMode]
rcr{b} src1
|
Note
|
Properties: mayLoad, mayStore |
RCR8m1_ND [In64BitMode]
rcr{b} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
RCR8mCL_EVEX [In64BitMode]
rcr{b} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
RCR8mi_EVEX [In64BitMode]
rcr{b} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
RCR8r1_EVEX [In64BitMode]
rcr{b} src1
|
Note
|
Constraints: src1 = dst |
RCR8rCL_EVEX [In64BitMode]
rcr{b} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
RCR8ri_EVEX [In64BitMode]
rcr{b} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
RDMSRLIST [In64BitMode]
rdmsrlist
RET64 [In64BitMode]
ret{q}
|
Note
|
Properties: hasCtrlDep, isBarrier, isReturn, isTerminator |
RETI64 [In64BitMode]
ret{q} amt
|
Note
|
Properties: hasCtrlDep, isBarrier, isReturn, isTerminator |
REX64_PREFIX [In64BitMode]
rex64
RMPADJUST [In64BitMode]
rmpadjust
RMPQUERY [In64BitMode]
rmpquery
RMPUPDATE [In64BitMode]
rmpupdate
ROL16m1_EVEX [In64BitMode]
rol{w} src1
|
Note
|
Properties: mayLoad, mayStore |
ROL16m1_ND [In64BitMode]
rol{w} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
ROL16m1_NF [In64BitMode]
rol{w} src1
|
Note
|
Properties: mayLoad, mayStore |
ROL16m1_NF_ND [In64BitMode]
rol{w} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
ROL16mCL_EVEX [In64BitMode]
rol{w} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
ROL16mCL_NF [In64BitMode]
rol{w} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
ROL16mCL_NF_ND [In64BitMode]
rol{w} {%cl, src1, dst|dst, src1, cl}
|
Note
|
Properties: mayLoad |
ROL16mi_EVEX [In64BitMode]
rol{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ROL16mi_NF [In64BitMode]
rol{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ROL16mi_NF_ND [In64BitMode]
rol{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
ROL16r1_EVEX [In64BitMode]
rol{w} src1
|
Note
|
Constraints: src1 = dst |
ROL16r1_ND [In64BitMode]
rol{w} {src1, dst|dst, src1}
ROL16r1_NF [In64BitMode]
rol{w} src1
|
Note
|
Constraints: src1 = dst |
ROL16r1_NF_ND [In64BitMode]
rol{w} {src1, dst|dst, src1}
ROL16rCL_EVEX [In64BitMode]
rol{w} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
ROL16rCL_NF [In64BitMode]
rol{w} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
ROL16rCL_NF_ND [In64BitMode]
rol{w} {%cl, src1, dst|dst, src1, cl}
ROL16ri_EVEX [In64BitMode]
rol{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ROL16ri_NF [In64BitMode]
rol{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ROL16ri_NF_ND [In64BitMode]
rol{w} {src2, src1, dst|dst, src1, src2}
ROL32m1_EVEX [In64BitMode]
rol{l} src1
|
Note
|
Properties: mayLoad, mayStore |
ROL32m1_ND [In64BitMode]
rol{l} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
ROL32m1_NF [In64BitMode]
rol{l} src1
|
Note
|
Properties: mayLoad, mayStore |
ROL32m1_NF_ND [In64BitMode]
rol{l} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
ROL32mCL_EVEX [In64BitMode]
rol{l} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
ROL32mCL_NF [In64BitMode]
rol{l} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
ROL32mCL_NF_ND [In64BitMode]
rol{l} {%cl, src1, dst|dst, src1, cl}
|
Note
|
Properties: mayLoad |
ROL32mi_EVEX [In64BitMode]
rol{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ROL32mi_NF [In64BitMode]
rol{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ROL32mi_NF_ND [In64BitMode]
rol{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
ROL32r1_EVEX [In64BitMode]
rol{l} src1
|
Note
|
Constraints: src1 = dst |
ROL32r1_ND [In64BitMode]
rol{l} {src1, dst|dst, src1}
ROL32r1_NF [In64BitMode]
rol{l} src1
|
Note
|
Constraints: src1 = dst |
ROL32r1_NF_ND [In64BitMode]
rol{l} {src1, dst|dst, src1}
ROL32rCL_EVEX [In64BitMode]
rol{l} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
ROL32rCL_NF [In64BitMode]
rol{l} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
ROL32rCL_NF_ND [In64BitMode]
rol{l} {%cl, src1, dst|dst, src1, cl}
ROL32ri_EVEX [In64BitMode]
rol{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ROL32ri_NF [In64BitMode]
rol{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ROL32ri_NF_ND [In64BitMode]
rol{l} {src2, src1, dst|dst, src1, src2}
ROL64m1 [In64BitMode]
rol{q} src1
|
Note
|
Properties: mayLoad, mayStore |
ROL64m1_EVEX [In64BitMode]
rol{q} src1
|
Note
|
Properties: mayLoad, mayStore |
ROL64m1_ND [In64BitMode]
rol{q} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
ROL64m1_NF [In64BitMode]
rol{q} src1
|
Note
|
Properties: mayLoad, mayStore |
ROL64m1_NF_ND [In64BitMode]
rol{q} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
ROL64mCL [In64BitMode]
rol{q} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
ROL64mCL_EVEX [In64BitMode]
rol{q} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
ROL64mCL_NF [In64BitMode]
rol{q} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
ROL64mCL_NF_ND [In64BitMode]
rol{q} {%cl, src1, dst|dst, src1, cl}
|
Note
|
Properties: mayLoad |
ROL64mi [In64BitMode]
rol{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ROL64mi_EVEX [In64BitMode]
rol{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ROL64mi_NF [In64BitMode]
rol{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ROL64mi_NF_ND [In64BitMode]
rol{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
ROL64r1_EVEX [In64BitMode]
rol{q} src1
|
Note
|
Constraints: src1 = dst |
ROL64r1_ND [In64BitMode]
rol{q} {src1, dst|dst, src1}
ROL64r1_NF [In64BitMode]
rol{q} src1
|
Note
|
Constraints: src1 = dst |
ROL64r1_NF_ND [In64BitMode]
rol{q} {src1, dst|dst, src1}
ROL64rCL_EVEX [In64BitMode]
rol{q} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
ROL64rCL_NF [In64BitMode]
rol{q} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
ROL64rCL_NF_ND [In64BitMode]
rol{q} {%cl, src1, dst|dst, src1, cl}
ROL64ri_EVEX [In64BitMode]
rol{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ROL64ri_NF [In64BitMode]
rol{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ROL64ri_NF_ND [In64BitMode]
rol{q} {src2, src1, dst|dst, src1, src2}
ROL8m1_EVEX [In64BitMode]
rol{b} src1
|
Note
|
Properties: mayLoad, mayStore |
ROL8m1_ND [In64BitMode]
rol{b} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
ROL8m1_NF [In64BitMode]
rol{b} src1
|
Note
|
Properties: mayLoad, mayStore |
ROL8m1_NF_ND [In64BitMode]
rol{b} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
ROL8mCL_EVEX [In64BitMode]
rol{b} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
ROL8mCL_NF [In64BitMode]
rol{b} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
ROL8mCL_NF_ND [In64BitMode]
rol{b} {%cl, src1, dst|dst, src1, cl}
|
Note
|
Properties: mayLoad |
ROL8mi_EVEX [In64BitMode]
rol{b} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ROL8mi_NF [In64BitMode]
rol{b} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ROL8mi_NF_ND [In64BitMode]
rol{b} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
ROL8r1_EVEX [In64BitMode]
rol{b} src1
|
Note
|
Constraints: src1 = dst |
ROL8r1_NF [In64BitMode]
rol{b} src1
|
Note
|
Constraints: src1 = dst |
ROL8rCL_EVEX [In64BitMode]
rol{b} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
ROL8rCL_NF [In64BitMode]
rol{b} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
ROL8rCL_NF_ND [In64BitMode]
rol{b} {%cl, src1, dst|dst, src1, cl}
ROL8ri_EVEX [In64BitMode]
rol{b} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ROL8ri_NF [In64BitMode]
rol{b} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ROL8ri_NF_ND [In64BitMode]
rol{b} {src2, src1, dst|dst, src1, src2}
ROR16m1_EVEX [In64BitMode]
ror{w} src1
|
Note
|
Properties: mayLoad, mayStore |
ROR16m1_ND [In64BitMode]
ror{w} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
ROR16m1_NF [In64BitMode]
ror{w} src1
|
Note
|
Properties: mayLoad, mayStore |
ROR16m1_NF_ND [In64BitMode]
ror{w} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
ROR16mCL_EVEX [In64BitMode]
ror{w} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
ROR16mCL_NF [In64BitMode]
ror{w} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
ROR16mCL_NF_ND [In64BitMode]
ror{w} {%cl, src1, dst|dst, src1, cl}
|
Note
|
Properties: mayLoad |
ROR16mi_EVEX [In64BitMode]
ror{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ROR16mi_NF [In64BitMode]
ror{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ROR16mi_NF_ND [In64BitMode]
ror{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
ROR16r1_EVEX [In64BitMode]
ror{w} src1
|
Note
|
Constraints: src1 = dst |
ROR16r1_ND [In64BitMode]
ror{w} {src1, dst|dst, src1}
ROR16r1_NF [In64BitMode]
ror{w} src1
|
Note
|
Constraints: src1 = dst |
ROR16r1_NF_ND [In64BitMode]
ror{w} {src1, dst|dst, src1}
ROR16rCL_EVEX [In64BitMode]
ror{w} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
ROR16rCL_NF [In64BitMode]
ror{w} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
ROR16rCL_NF_ND [In64BitMode]
ror{w} {%cl, src1, dst|dst, src1, cl}
ROR16ri_EVEX [In64BitMode]
ror{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ROR16ri_NF [In64BitMode]
ror{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ROR16ri_NF_ND [In64BitMode]
ror{w} {src2, src1, dst|dst, src1, src2}
ROR32m1_EVEX [In64BitMode]
ror{l} src1
|
Note
|
Properties: mayLoad, mayStore |
ROR32m1_ND [In64BitMode]
ror{l} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
ROR32m1_NF [In64BitMode]
ror{l} src1
|
Note
|
Properties: mayLoad, mayStore |
ROR32m1_NF_ND [In64BitMode]
ror{l} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
ROR32mCL_EVEX [In64BitMode]
ror{l} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
ROR32mCL_NF [In64BitMode]
ror{l} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
ROR32mCL_NF_ND [In64BitMode]
ror{l} {%cl, src1, dst|dst, src1, cl}
|
Note
|
Properties: mayLoad |
ROR32mi_EVEX [In64BitMode]
ror{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ROR32mi_NF [In64BitMode]
ror{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ROR32mi_NF_ND [In64BitMode]
ror{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
ROR32r1_EVEX [In64BitMode]
ror{l} src1
|
Note
|
Constraints: src1 = dst |
ROR32r1_ND [In64BitMode]
ror{l} {src1, dst|dst, src1}
ROR32r1_NF [In64BitMode]
ror{l} src1
|
Note
|
Constraints: src1 = dst |
ROR32r1_NF_ND [In64BitMode]
ror{l} {src1, dst|dst, src1}
ROR32rCL_EVEX [In64BitMode]
ror{l} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
ROR32rCL_NF [In64BitMode]
ror{l} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
ROR32rCL_NF_ND [In64BitMode]
ror{l} {%cl, src1, dst|dst, src1, cl}
ROR32ri_EVEX [In64BitMode]
ror{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ROR32ri_NF [In64BitMode]
ror{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ROR32ri_NF_ND [In64BitMode]
ror{l} {src2, src1, dst|dst, src1, src2}
ROR64m1 [In64BitMode]
ror{q} src1
|
Note
|
Properties: mayLoad, mayStore |
ROR64m1_EVEX [In64BitMode]
ror{q} src1
|
Note
|
Properties: mayLoad, mayStore |
ROR64m1_ND [In64BitMode]
ror{q} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
ROR64m1_NF [In64BitMode]
ror{q} src1
|
Note
|
Properties: mayLoad, mayStore |
ROR64m1_NF_ND [In64BitMode]
ror{q} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
ROR64mCL [In64BitMode]
ror{q} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
ROR64mCL_EVEX [In64BitMode]
ror{q} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
ROR64mCL_NF [In64BitMode]
ror{q} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
ROR64mCL_NF_ND [In64BitMode]
ror{q} {%cl, src1, dst|dst, src1, cl}
|
Note
|
Properties: mayLoad |
ROR64mi [In64BitMode]
ror{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ROR64mi_EVEX [In64BitMode]
ror{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ROR64mi_NF [In64BitMode]
ror{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ROR64mi_NF_ND [In64BitMode]
ror{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
ROR64r1_EVEX [In64BitMode]
ror{q} src1
|
Note
|
Constraints: src1 = dst |
ROR64r1_ND [In64BitMode]
ror{q} {src1, dst|dst, src1}
ROR64r1_NF [In64BitMode]
ror{q} src1
|
Note
|
Constraints: src1 = dst |
ROR64r1_NF_ND [In64BitMode]
ror{q} {src1, dst|dst, src1}
ROR64rCL_EVEX [In64BitMode]
ror{q} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
ROR64rCL_NF [In64BitMode]
ror{q} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
ROR64rCL_NF_ND [In64BitMode]
ror{q} {%cl, src1, dst|dst, src1, cl}
ROR64ri_EVEX [In64BitMode]
ror{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ROR64ri_NF [In64BitMode]
ror{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ROR64ri_NF_ND [In64BitMode]
ror{q} {src2, src1, dst|dst, src1, src2}
ROR8m1_EVEX [In64BitMode]
ror{b} src1
|
Note
|
Properties: mayLoad, mayStore |
ROR8m1_ND [In64BitMode]
ror{b} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
ROR8m1_NF [In64BitMode]
ror{b} src1
|
Note
|
Properties: mayLoad, mayStore |
ROR8m1_NF_ND [In64BitMode]
ror{b} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
ROR8mCL_EVEX [In64BitMode]
ror{b} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
ROR8mCL_NF [In64BitMode]
ror{b} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
ROR8mCL_NF_ND [In64BitMode]
ror{b} {%cl, src1, dst|dst, src1, cl}
|
Note
|
Properties: mayLoad |
ROR8mi_EVEX [In64BitMode]
ror{b} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ROR8mi_NF [In64BitMode]
ror{b} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
ROR8mi_NF_ND [In64BitMode]
ror{b} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
ROR8r1_EVEX [In64BitMode]
ror{b} src1
|
Note
|
Constraints: src1 = dst |
ROR8r1_NF [In64BitMode]
ror{b} src1
|
Note
|
Constraints: src1 = dst |
ROR8rCL_EVEX [In64BitMode]
ror{b} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
ROR8rCL_NF [In64BitMode]
ror{b} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
ROR8rCL_NF_ND [In64BitMode]
ror{b} {%cl, src1, dst|dst, src1, cl}
ROR8ri_EVEX [In64BitMode]
ror{b} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ROR8ri_NF [In64BitMode]
ror{b} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ROR8ri_NF_ND [In64BitMode]
ror{b} {src2, src1, dst|dst, src1, src2}
SAR16m1_EVEX [In64BitMode]
sar{w} src1
|
Note
|
Properties: mayLoad, mayStore |
SAR16m1_ND [In64BitMode]
sar{w} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
SAR16m1_NF [In64BitMode]
sar{w} src1
|
Note
|
Properties: mayLoad, mayStore |
SAR16m1_NF_ND [In64BitMode]
sar{w} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
SAR16mCL_EVEX [In64BitMode]
sar{w} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
SAR16mCL_NF [In64BitMode]
sar{w} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
SAR16mCL_NF_ND [In64BitMode]
sar{w} {%cl, src1, dst|dst, src1, cl}
|
Note
|
Properties: mayLoad |
SAR16mi_EVEX [In64BitMode]
sar{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
SAR16mi_NF [In64BitMode]
sar{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
SAR16mi_NF_ND [In64BitMode]
sar{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
SAR16r1_EVEX [In64BitMode]
sar{w} src1
|
Note
|
Constraints: src1 = dst |
SAR16r1_ND [In64BitMode]
sar{w} {src1, dst|dst, src1}
SAR16r1_NF [In64BitMode]
sar{w} src1
|
Note
|
Constraints: src1 = dst |
SAR16r1_NF_ND [In64BitMode]
sar{w} {src1, dst|dst, src1}
SAR16rCL_EVEX [In64BitMode]
sar{w} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
SAR16rCL_NF [In64BitMode]
sar{w} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
SAR16rCL_NF_ND [In64BitMode]
sar{w} {%cl, src1, dst|dst, src1, cl}
SAR16ri_EVEX [In64BitMode]
sar{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
SAR16ri_NF [In64BitMode]
sar{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
SAR16ri_NF_ND [In64BitMode]
sar{w} {src2, src1, dst|dst, src1, src2}
SAR32m1_EVEX [In64BitMode]
sar{l} src1
|
Note
|
Properties: mayLoad, mayStore |
SAR32m1_ND [In64BitMode]
sar{l} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
SAR32m1_NF [In64BitMode]
sar{l} src1
|
Note
|
Properties: mayLoad, mayStore |
SAR32m1_NF_ND [In64BitMode]
sar{l} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
SAR32mCL_EVEX [In64BitMode]
sar{l} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
SAR32mCL_NF [In64BitMode]
sar{l} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
SAR32mCL_NF_ND [In64BitMode]
sar{l} {%cl, src1, dst|dst, src1, cl}
|
Note
|
Properties: mayLoad |
SAR32mi_EVEX [In64BitMode]
sar{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
SAR32mi_NF [In64BitMode]
sar{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
SAR32mi_NF_ND [In64BitMode]
sar{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
SAR32r1_EVEX [In64BitMode]
sar{l} src1
|
Note
|
Constraints: src1 = dst |
SAR32r1_ND [In64BitMode]
sar{l} {src1, dst|dst, src1}
SAR32r1_NF [In64BitMode]
sar{l} src1
|
Note
|
Constraints: src1 = dst |
SAR32r1_NF_ND [In64BitMode]
sar{l} {src1, dst|dst, src1}
SAR32rCL_EVEX [In64BitMode]
sar{l} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
SAR32rCL_NF [In64BitMode]
sar{l} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
SAR32rCL_NF_ND [In64BitMode]
sar{l} {%cl, src1, dst|dst, src1, cl}
SAR32ri_EVEX [In64BitMode]
sar{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
SAR32ri_NF [In64BitMode]
sar{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
SAR32ri_NF_ND [In64BitMode]
sar{l} {src2, src1, dst|dst, src1, src2}
SAR64m1 [In64BitMode]
sar{q} src1
|
Note
|
Properties: mayLoad, mayStore |
SAR64m1_EVEX [In64BitMode]
sar{q} src1
|
Note
|
Properties: mayLoad, mayStore |
SAR64m1_ND [In64BitMode]
sar{q} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
SAR64m1_NF [In64BitMode]
sar{q} src1
|
Note
|
Properties: mayLoad, mayStore |
SAR64m1_NF_ND [In64BitMode]
sar{q} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
SAR64mCL [In64BitMode]
sar{q} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
SAR64mCL_EVEX [In64BitMode]
sar{q} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
SAR64mCL_NF [In64BitMode]
sar{q} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
SAR64mCL_NF_ND [In64BitMode]
sar{q} {%cl, src1, dst|dst, src1, cl}
|
Note
|
Properties: mayLoad |
SAR64mi [In64BitMode]
sar{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
SAR64mi_EVEX [In64BitMode]
sar{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
SAR64mi_NF [In64BitMode]
sar{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
SAR64mi_NF_ND [In64BitMode]
sar{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
SAR64r1_EVEX [In64BitMode]
sar{q} src1
|
Note
|
Constraints: src1 = dst |
SAR64r1_ND [In64BitMode]
sar{q} {src1, dst|dst, src1}
SAR64r1_NF [In64BitMode]
sar{q} src1
|
Note
|
Constraints: src1 = dst |
SAR64r1_NF_ND [In64BitMode]
sar{q} {src1, dst|dst, src1}
SAR64rCL_EVEX [In64BitMode]
sar{q} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
SAR64rCL_NF [In64BitMode]
sar{q} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
SAR64rCL_NF_ND [In64BitMode]
sar{q} {%cl, src1, dst|dst, src1, cl}
SAR64ri_EVEX [In64BitMode]
sar{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
SAR64ri_NF [In64BitMode]
sar{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
SAR64ri_NF_ND [In64BitMode]
sar{q} {src2, src1, dst|dst, src1, src2}
SAR8m1_EVEX [In64BitMode]
sar{b} src1
|
Note
|
Properties: mayLoad, mayStore |
SAR8m1_ND [In64BitMode]
sar{b} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
SAR8m1_NF [In64BitMode]
sar{b} src1
|
Note
|
Properties: mayLoad, mayStore |
SAR8m1_NF_ND [In64BitMode]
sar{b} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
SAR8mCL_EVEX [In64BitMode]
sar{b} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
SAR8mCL_NF [In64BitMode]
sar{b} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
SAR8mCL_NF_ND [In64BitMode]
sar{b} {%cl, src1, dst|dst, src1, cl}
|
Note
|
Properties: mayLoad |
SAR8mi_EVEX [In64BitMode]
sar{b} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
SAR8mi_NF [In64BitMode]
sar{b} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
SAR8mi_NF_ND [In64BitMode]
sar{b} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
SAR8r1_EVEX [In64BitMode]
sar{b} src1
|
Note
|
Constraints: src1 = dst |
SAR8r1_NF [In64BitMode]
sar{b} src1
|
Note
|
Constraints: src1 = dst |
SAR8rCL_EVEX [In64BitMode]
sar{b} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
SAR8rCL_NF [In64BitMode]
sar{b} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
SAR8rCL_NF_ND [In64BitMode]
sar{b} {%cl, src1, dst|dst, src1, cl}
SAR8ri_EVEX [In64BitMode]
sar{b} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
SAR8ri_NF [In64BitMode]
sar{b} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
SAR8ri_NF_ND [In64BitMode]
sar{b} {src2, src1, dst|dst, src1, src2}
SBB16mi8_EVEX [In64BitMode]
sbb{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
SBB16mi_EVEX [In64BitMode]
sbb{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
SBB16mr_EVEX [In64BitMode]
sbb{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
SBB16ri8_EVEX [In64BitMode]
sbb{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
SBB16ri_EVEX [In64BitMode]
sbb{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
SBB16rm_EVEX [In64BitMode]
sbb{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
SBB16rr_EVEX [In64BitMode]
sbb{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
SBB32mi8_EVEX [In64BitMode]
sbb{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
SBB32mi_EVEX [In64BitMode]
sbb{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
SBB32mr_EVEX [In64BitMode]
sbb{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
SBB32ri8_EVEX [In64BitMode]
sbb{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
SBB32ri_EVEX [In64BitMode]
sbb{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
SBB32rm_EVEX [In64BitMode]
sbb{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
SBB32rr_EVEX [In64BitMode]
sbb{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
SBB64mi32 [In64BitMode]
sbb{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
SBB64mi32_EVEX [In64BitMode]
sbb{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
SBB64mi8 [In64BitMode]
sbb{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
SBB64mi8_EVEX [In64BitMode]
sbb{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
SBB64mr_EVEX [In64BitMode]
sbb{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
SBB64ri32_EVEX [In64BitMode]
sbb{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
SBB64ri8_EVEX [In64BitMode]
sbb{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
SBB64rm_EVEX [In64BitMode]
sbb{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
SBB64rr_EVEX [In64BitMode]
sbb{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
SBB8mi_EVEX [In64BitMode]
sbb{b} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
SBB8mr_EVEX [In64BitMode]
sbb{b} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
SBB8ri_EVEX [In64BitMode]
sbb{b} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
SBB8rm_EVEX [In64BitMode]
sbb{b} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
SBB8rr_EVEX [In64BitMode]
sbb{b} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
SCASQ [In64BitMode]
scasq {dst, %rax|rax, dst}
SEAMCALL [In64BitMode]
seamcall
SEAMOPS [In64BitMode]
seamops
SEAMRET [In64BitMode]
seamret
SGDT64m [In64BitMode]
sgdt{q} dst
SHL16m1_EVEX [In64BitMode]
shl{w} src1
|
Note
|
Properties: mayLoad, mayStore |
SHL16m1_ND [In64BitMode]
shl{w} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
SHL16m1_NF [In64BitMode]
shl{w} src1
|
Note
|
Properties: mayLoad, mayStore |
SHL16m1_NF_ND [In64BitMode]
shl{w} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
SHL16mCL_EVEX [In64BitMode]
shl{w} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
SHL16mCL_NF [In64BitMode]
shl{w} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
SHL16mCL_NF_ND [In64BitMode]
shl{w} {%cl, src1, dst|dst, src1, cl}
|
Note
|
Properties: mayLoad |
SHL16mi_EVEX [In64BitMode]
shl{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
SHL16mi_NF [In64BitMode]
shl{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
SHL16mi_NF_ND [In64BitMode]
shl{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
SHL16r1_EVEX [In64BitMode]
shl{w} src1
|
Note
|
Constraints: src1 = dst |
SHL16r1_ND [In64BitMode]
shl{w} {src1, dst|dst, src1}
SHL16r1_NF [In64BitMode]
shl{w} src1
|
Note
|
Constraints: src1 = dst |
SHL16r1_NF_ND [In64BitMode]
shl{w} {src1, dst|dst, src1}
SHL16rCL_EVEX [In64BitMode]
shl{w} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
SHL16rCL_NF [In64BitMode]
shl{w} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
SHL16rCL_NF_ND [In64BitMode]
shl{w} {%cl, src1, dst|dst, src1, cl}
SHL16ri_EVEX [In64BitMode]
shl{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
SHL16ri_NF [In64BitMode]
shl{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
SHL16ri_NF_ND [In64BitMode]
shl{w} {src2, src1, dst|dst, src1, src2}
SHL32m1_EVEX [In64BitMode]
shl{l} src1
|
Note
|
Properties: mayLoad, mayStore |
SHL32m1_ND [In64BitMode]
shl{l} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
SHL32m1_NF [In64BitMode]
shl{l} src1
|
Note
|
Properties: mayLoad, mayStore |
SHL32m1_NF_ND [In64BitMode]
shl{l} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
SHL32mCL_EVEX [In64BitMode]
shl{l} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
SHL32mCL_NF [In64BitMode]
shl{l} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
SHL32mCL_NF_ND [In64BitMode]
shl{l} {%cl, src1, dst|dst, src1, cl}
|
Note
|
Properties: mayLoad |
SHL32mi_EVEX [In64BitMode]
shl{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
SHL32mi_NF [In64BitMode]
shl{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
SHL32mi_NF_ND [In64BitMode]
shl{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
SHL32r1_EVEX [In64BitMode]
shl{l} src1
|
Note
|
Constraints: src1 = dst |
SHL32r1_ND [In64BitMode]
shl{l} {src1, dst|dst, src1}
SHL32r1_NF [In64BitMode]
shl{l} src1
|
Note
|
Constraints: src1 = dst |
SHL32r1_NF_ND [In64BitMode]
shl{l} {src1, dst|dst, src1}
SHL32rCL_EVEX [In64BitMode]
shl{l} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
SHL32rCL_NF [In64BitMode]
shl{l} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
SHL32rCL_NF_ND [In64BitMode]
shl{l} {%cl, src1, dst|dst, src1, cl}
SHL32ri_EVEX [In64BitMode]
shl{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
SHL32ri_NF [In64BitMode]
shl{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
SHL32ri_NF_ND [In64BitMode]
shl{l} {src2, src1, dst|dst, src1, src2}
SHL64m1 [In64BitMode]
shl{q} src1
|
Note
|
Properties: mayLoad, mayStore |
SHL64m1_EVEX [In64BitMode]
shl{q} src1
|
Note
|
Properties: mayLoad, mayStore |
SHL64m1_ND [In64BitMode]
shl{q} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
SHL64m1_NF [In64BitMode]
shl{q} src1
|
Note
|
Properties: mayLoad, mayStore |
SHL64m1_NF_ND [In64BitMode]
shl{q} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
SHL64mCL [In64BitMode]
shl{q} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
SHL64mCL_EVEX [In64BitMode]
shl{q} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
SHL64mCL_NF [In64BitMode]
shl{q} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
SHL64mCL_NF_ND [In64BitMode]
shl{q} {%cl, src1, dst|dst, src1, cl}
|
Note
|
Properties: mayLoad |
SHL64mi [In64BitMode]
shl{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
SHL64mi_EVEX [In64BitMode]
shl{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
SHL64mi_NF [In64BitMode]
shl{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
SHL64mi_NF_ND [In64BitMode]
shl{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
SHL64r1_EVEX [In64BitMode]
shl{q} src1
|
Note
|
Constraints: src1 = dst |
SHL64r1_ND [In64BitMode]
shl{q} {src1, dst|dst, src1}
SHL64r1_NF [In64BitMode]
shl{q} src1
|
Note
|
Constraints: src1 = dst |
SHL64r1_NF_ND [In64BitMode]
shl{q} {src1, dst|dst, src1}
SHL64rCL_EVEX [In64BitMode]
shl{q} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
SHL64rCL_NF [In64BitMode]
shl{q} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
SHL64rCL_NF_ND [In64BitMode]
shl{q} {%cl, src1, dst|dst, src1, cl}
SHL64ri_EVEX [In64BitMode]
shl{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
SHL64ri_NF [In64BitMode]
shl{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
SHL64ri_NF_ND [In64BitMode]
shl{q} {src2, src1, dst|dst, src1, src2}
SHL8m1_EVEX [In64BitMode]
shl{b} src1
|
Note
|
Properties: mayLoad, mayStore |
SHL8m1_ND [In64BitMode]
shl{b} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
SHL8m1_NF [In64BitMode]
shl{b} src1
|
Note
|
Properties: mayLoad, mayStore |
SHL8m1_NF_ND [In64BitMode]
shl{b} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
SHL8mCL_EVEX [In64BitMode]
shl{b} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
SHL8mCL_NF [In64BitMode]
shl{b} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
SHL8mCL_NF_ND [In64BitMode]
shl{b} {%cl, src1, dst|dst, src1, cl}
|
Note
|
Properties: mayLoad |
SHL8mi_EVEX [In64BitMode]
shl{b} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
SHL8mi_NF [In64BitMode]
shl{b} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
SHL8mi_NF_ND [In64BitMode]
shl{b} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
SHL8r1_EVEX [In64BitMode]
shl{b} src1
|
Note
|
Constraints: src1 = dst |
SHL8r1_NF [In64BitMode]
shl{b} src1
|
Note
|
Constraints: src1 = dst |
SHL8rCL_EVEX [In64BitMode]
shl{b} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
SHL8rCL_NF [In64BitMode]
shl{b} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
SHL8rCL_NF_ND [In64BitMode]
shl{b} {%cl, src1, dst|dst, src1, cl}
SHL8ri_EVEX [In64BitMode]
shl{b} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
SHL8ri_NF [In64BitMode]
shl{b} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
SHL8ri_NF_ND [In64BitMode]
shl{b} {src2, src1, dst|dst, src1, src2}
SHLD16mrCL_EVEX [In64BitMode]
shld{w} {%cl, src2, src1|src1, src2, cl}
|
Note
|
Properties: mayLoad, mayStore |
SHLD16mrCL_NF [In64BitMode]
shld{w} {%cl, src2, src1|src1, src2, cl}
|
Note
|
Properties: mayLoad, mayStore |
SHLD16mrCL_NF_ND [In64BitMode]
shld{w} {%cl, src2, src1, dst|dst, src1, src2, cl}
|
Note
|
Properties: mayLoad |
SHLD16mri8_EVEX [In64BitMode]
shld{w} {src3, src2, src1|src1, src2, src3}
|
Note
|
Properties: mayLoad, mayStore |
SHLD16mri8_NF [In64BitMode]
shld{w} {src3, src2, src1|src1, src2, src3}
|
Note
|
Properties: mayLoad, mayStore |
SHLD16mri8_NF_ND [In64BitMode]
shld{w} {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayLoad |
SHLD16rrCL_EVEX [In64BitMode]
shld{w} {%cl, src2, src1|src1, src2, cl}
|
Note
|
Constraints: src1 = dst |
SHLD16rrCL_NF [In64BitMode]
shld{w} {%cl, src2, src1|src1, src2, cl}
|
Note
|
Constraints: src1 = dst |
SHLD16rrCL_NF_ND [In64BitMode]
shld{w} {%cl, src2, src1, dst|dst, src1, src2, cl}
SHLD16rri8_EVEX [In64BitMode]
shld{w} {src3, src2, src1|src1, src2, src3}
|
Note
|
Constraints: src1 = dst |
SHLD16rri8_NF [In64BitMode]
shld{w} {src3, src2, src1|src1, src2, src3}
|
Note
|
Constraints: src1 = dst |
SHLD16rri8_NF_ND [In64BitMode]
shld{w} {src3, src2, src1, dst|dst, src1, src2, src3}
SHLD32mrCL_EVEX [In64BitMode]
shld{l} {%cl, src2, src1|src1, src2, cl}
|
Note
|
Properties: mayLoad, mayStore |
SHLD32mrCL_NF [In64BitMode]
shld{l} {%cl, src2, src1|src1, src2, cl}
|
Note
|
Properties: mayLoad, mayStore |
SHLD32mrCL_NF_ND [In64BitMode]
shld{l} {%cl, src2, src1, dst|dst, src1, src2, cl}
|
Note
|
Properties: mayLoad |
SHLD32mri8_EVEX [In64BitMode]
shld{l} {src3, src2, src1|src1, src2, src3}
|
Note
|
Properties: mayLoad, mayStore |
SHLD32mri8_NF [In64BitMode]
shld{l} {src3, src2, src1|src1, src2, src3}
|
Note
|
Properties: mayLoad, mayStore |
SHLD32mri8_NF_ND [In64BitMode]
shld{l} {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayLoad |
SHLD32rrCL_EVEX [In64BitMode]
shld{l} {%cl, src2, src1|src1, src2, cl}
|
Note
|
Constraints: src1 = dst |
SHLD32rrCL_NF [In64BitMode]
shld{l} {%cl, src2, src1|src1, src2, cl}
|
Note
|
Constraints: src1 = dst |
SHLD32rrCL_NF_ND [In64BitMode]
shld{l} {%cl, src2, src1, dst|dst, src1, src2, cl}
SHLD32rri8_EVEX [In64BitMode]
shld{l} {src3, src2, src1|src1, src2, src3}
|
Note
|
Constraints: src1 = dst |
SHLD32rri8_NF [In64BitMode]
shld{l} {src3, src2, src1|src1, src2, src3}
|
Note
|
Constraints: src1 = dst |
SHLD32rri8_NF_ND [In64BitMode]
shld{l} {src3, src2, src1, dst|dst, src1, src2, src3}
SHLD64mrCL_EVEX [In64BitMode]
shld{q} {%cl, src2, src1|src1, src2, cl}
|
Note
|
Properties: mayLoad, mayStore |
SHLD64mrCL_NF [In64BitMode]
shld{q} {%cl, src2, src1|src1, src2, cl}
|
Note
|
Properties: mayLoad, mayStore |
SHLD64mrCL_NF_ND [In64BitMode]
shld{q} {%cl, src2, src1, dst|dst, src1, src2, cl}
|
Note
|
Properties: mayLoad |
SHLD64mri8_EVEX [In64BitMode]
shld{q} {src3, src2, src1|src1, src2, src3}
|
Note
|
Properties: mayLoad, mayStore |
SHLD64mri8_NF [In64BitMode]
shld{q} {src3, src2, src1|src1, src2, src3}
|
Note
|
Properties: mayLoad, mayStore |
SHLD64mri8_NF_ND [In64BitMode]
shld{q} {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayLoad |
SHLD64rrCL_EVEX [In64BitMode]
shld{q} {%cl, src2, src1|src1, src2, cl}
|
Note
|
Constraints: src1 = dst |
SHLD64rrCL_NF [In64BitMode]
shld{q} {%cl, src2, src1|src1, src2, cl}
|
Note
|
Constraints: src1 = dst |
SHLD64rrCL_NF_ND [In64BitMode]
shld{q} {%cl, src2, src1, dst|dst, src1, src2, cl}
SHLD64rri8_EVEX [In64BitMode]
shld{q} {src3, src2, src1|src1, src2, src3}
|
Note
|
Constraints: src1 = dst |
SHLD64rri8_NF [In64BitMode]
shld{q} {src3, src2, src1|src1, src2, src3}
|
Note
|
Constraints: src1 = dst |
SHLD64rri8_NF_ND [In64BitMode]
shld{q} {src3, src2, src1, dst|dst, src1, src2, src3}
SHR16m1_EVEX [In64BitMode]
shr{w} src1
|
Note
|
Properties: mayLoad, mayStore |
SHR16m1_ND [In64BitMode]
shr{w} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
SHR16m1_NF [In64BitMode]
shr{w} src1
|
Note
|
Properties: mayLoad, mayStore |
SHR16m1_NF_ND [In64BitMode]
shr{w} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
SHR16mCL_EVEX [In64BitMode]
shr{w} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
SHR16mCL_NF [In64BitMode]
shr{w} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
SHR16mCL_NF_ND [In64BitMode]
shr{w} {%cl, src1, dst|dst, src1, cl}
|
Note
|
Properties: mayLoad |
SHR16mi_EVEX [In64BitMode]
shr{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
SHR16mi_NF [In64BitMode]
shr{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
SHR16mi_NF_ND [In64BitMode]
shr{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
SHR16r1_EVEX [In64BitMode]
shr{w} src1
|
Note
|
Constraints: src1 = dst |
SHR16r1_ND [In64BitMode]
shr{w} {src1, dst|dst, src1}
SHR16r1_NF [In64BitMode]
shr{w} src1
|
Note
|
Constraints: src1 = dst |
SHR16r1_NF_ND [In64BitMode]
shr{w} {src1, dst|dst, src1}
SHR16rCL_EVEX [In64BitMode]
shr{w} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
SHR16rCL_NF [In64BitMode]
shr{w} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
SHR16rCL_NF_ND [In64BitMode]
shr{w} {%cl, src1, dst|dst, src1, cl}
SHR16ri_EVEX [In64BitMode]
shr{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
SHR16ri_NF [In64BitMode]
shr{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
SHR16ri_NF_ND [In64BitMode]
shr{w} {src2, src1, dst|dst, src1, src2}
SHR32m1_EVEX [In64BitMode]
shr{l} src1
|
Note
|
Properties: mayLoad, mayStore |
SHR32m1_ND [In64BitMode]
shr{l} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
SHR32m1_NF [In64BitMode]
shr{l} src1
|
Note
|
Properties: mayLoad, mayStore |
SHR32m1_NF_ND [In64BitMode]
shr{l} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
SHR32mCL_EVEX [In64BitMode]
shr{l} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
SHR32mCL_NF [In64BitMode]
shr{l} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
SHR32mCL_NF_ND [In64BitMode]
shr{l} {%cl, src1, dst|dst, src1, cl}
|
Note
|
Properties: mayLoad |
SHR32mi_EVEX [In64BitMode]
shr{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
SHR32mi_NF [In64BitMode]
shr{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
SHR32mi_NF_ND [In64BitMode]
shr{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
SHR32r1_EVEX [In64BitMode]
shr{l} src1
|
Note
|
Constraints: src1 = dst |
SHR32r1_ND [In64BitMode]
shr{l} {src1, dst|dst, src1}
SHR32r1_NF [In64BitMode]
shr{l} src1
|
Note
|
Constraints: src1 = dst |
SHR32r1_NF_ND [In64BitMode]
shr{l} {src1, dst|dst, src1}
SHR32rCL_EVEX [In64BitMode]
shr{l} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
SHR32rCL_NF [In64BitMode]
shr{l} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
SHR32rCL_NF_ND [In64BitMode]
shr{l} {%cl, src1, dst|dst, src1, cl}
SHR32ri_EVEX [In64BitMode]
shr{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
SHR32ri_NF [In64BitMode]
shr{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
SHR32ri_NF_ND [In64BitMode]
shr{l} {src2, src1, dst|dst, src1, src2}
SHR64m1 [In64BitMode]
shr{q} src1
|
Note
|
Properties: mayLoad, mayStore |
SHR64m1_EVEX [In64BitMode]
shr{q} src1
|
Note
|
Properties: mayLoad, mayStore |
SHR64m1_ND [In64BitMode]
shr{q} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
SHR64m1_NF [In64BitMode]
shr{q} src1
|
Note
|
Properties: mayLoad, mayStore |
SHR64m1_NF_ND [In64BitMode]
shr{q} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
SHR64mCL [In64BitMode]
shr{q} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
SHR64mCL_EVEX [In64BitMode]
shr{q} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
SHR64mCL_NF [In64BitMode]
shr{q} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
SHR64mCL_NF_ND [In64BitMode]
shr{q} {%cl, src1, dst|dst, src1, cl}
|
Note
|
Properties: mayLoad |
SHR64mi [In64BitMode]
shr{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
SHR64mi_EVEX [In64BitMode]
shr{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
SHR64mi_NF [In64BitMode]
shr{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
SHR64mi_NF_ND [In64BitMode]
shr{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
SHR64r1_EVEX [In64BitMode]
shr{q} src1
|
Note
|
Constraints: src1 = dst |
SHR64r1_ND [In64BitMode]
shr{q} {src1, dst|dst, src1}
SHR64r1_NF [In64BitMode]
shr{q} src1
|
Note
|
Constraints: src1 = dst |
SHR64r1_NF_ND [In64BitMode]
shr{q} {src1, dst|dst, src1}
SHR64rCL_EVEX [In64BitMode]
shr{q} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
SHR64rCL_NF [In64BitMode]
shr{q} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
SHR64rCL_NF_ND [In64BitMode]
shr{q} {%cl, src1, dst|dst, src1, cl}
SHR64ri_EVEX [In64BitMode]
shr{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
SHR64ri_NF [In64BitMode]
shr{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
SHR64ri_NF_ND [In64BitMode]
shr{q} {src2, src1, dst|dst, src1, src2}
SHR8m1_EVEX [In64BitMode]
shr{b} src1
|
Note
|
Properties: mayLoad, mayStore |
SHR8m1_ND [In64BitMode]
shr{b} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
SHR8m1_NF [In64BitMode]
shr{b} src1
|
Note
|
Properties: mayLoad, mayStore |
SHR8m1_NF_ND [In64BitMode]
shr{b} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
SHR8mCL_EVEX [In64BitMode]
shr{b} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
SHR8mCL_NF [In64BitMode]
shr{b} {%cl, src1|src1, cl}
|
Note
|
Properties: mayLoad, mayStore |
SHR8mCL_NF_ND [In64BitMode]
shr{b} {%cl, src1, dst|dst, src1, cl}
|
Note
|
Properties: mayLoad |
SHR8mi_EVEX [In64BitMode]
shr{b} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
SHR8mi_NF [In64BitMode]
shr{b} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
SHR8mi_NF_ND [In64BitMode]
shr{b} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
SHR8r1_EVEX [In64BitMode]
shr{b} src1
|
Note
|
Constraints: src1 = dst |
SHR8r1_NF [In64BitMode]
shr{b} src1
|
Note
|
Constraints: src1 = dst |
SHR8rCL_EVEX [In64BitMode]
shr{b} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
SHR8rCL_NF [In64BitMode]
shr{b} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
SHR8rCL_NF_ND [In64BitMode]
shr{b} {%cl, src1, dst|dst, src1, cl}
SHR8ri_EVEX [In64BitMode]
shr{b} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
SHR8ri_NF [In64BitMode]
shr{b} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
SHR8ri_NF_ND [In64BitMode]
shr{b} {src2, src1, dst|dst, src1, src2}
SHRD16mrCL_EVEX [In64BitMode]
shrd{w} {%cl, src2, src1|src1, src2, cl}
|
Note
|
Properties: mayLoad, mayStore |
SHRD16mrCL_NF [In64BitMode]
shrd{w} {%cl, src2, src1|src1, src2, cl}
|
Note
|
Properties: mayLoad, mayStore |
SHRD16mrCL_NF_ND [In64BitMode]
shrd{w} {%cl, src2, src1, dst|dst, src1, src2, cl}
|
Note
|
Properties: mayLoad |
SHRD16mri8_EVEX [In64BitMode]
shrd{w} {src3, src2, src1|src1, src2, src3}
|
Note
|
Properties: mayLoad, mayStore |
SHRD16mri8_NF [In64BitMode]
shrd{w} {src3, src2, src1|src1, src2, src3}
|
Note
|
Properties: mayLoad, mayStore |
SHRD16mri8_NF_ND [In64BitMode]
shrd{w} {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayLoad |
SHRD16rrCL_EVEX [In64BitMode]
shrd{w} {%cl, src2, src1|src1, src2, cl}
|
Note
|
Constraints: src1 = dst |
SHRD16rrCL_NF [In64BitMode]
shrd{w} {%cl, src2, src1|src1, src2, cl}
|
Note
|
Constraints: src1 = dst |
SHRD16rrCL_NF_ND [In64BitMode]
shrd{w} {%cl, src2, src1, dst|dst, src1, src2, cl}
SHRD16rri8_EVEX [In64BitMode]
shrd{w} {src3, src2, src1|src1, src2, src3}
|
Note
|
Constraints: src1 = dst |
SHRD16rri8_NF [In64BitMode]
shrd{w} {src3, src2, src1|src1, src2, src3}
|
Note
|
Constraints: src1 = dst |
SHRD16rri8_NF_ND [In64BitMode]
shrd{w} {src3, src2, src1, dst|dst, src1, src2, src3}
SHRD32mrCL_EVEX [In64BitMode]
shrd{l} {%cl, src2, src1|src1, src2, cl}
|
Note
|
Properties: mayLoad, mayStore |
SHRD32mrCL_NF [In64BitMode]
shrd{l} {%cl, src2, src1|src1, src2, cl}
|
Note
|
Properties: mayLoad, mayStore |
SHRD32mrCL_NF_ND [In64BitMode]
shrd{l} {%cl, src2, src1, dst|dst, src1, src2, cl}
|
Note
|
Properties: mayLoad |
SHRD32mri8_EVEX [In64BitMode]
shrd{l} {src3, src2, src1|src1, src2, src3}
|
Note
|
Properties: mayLoad, mayStore |
SHRD32mri8_NF [In64BitMode]
shrd{l} {src3, src2, src1|src1, src2, src3}
|
Note
|
Properties: mayLoad, mayStore |
SHRD32mri8_NF_ND [In64BitMode]
shrd{l} {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayLoad |
SHRD32rrCL_EVEX [In64BitMode]
shrd{l} {%cl, src2, src1|src1, src2, cl}
|
Note
|
Constraints: src1 = dst |
SHRD32rrCL_NF [In64BitMode]
shrd{l} {%cl, src2, src1|src1, src2, cl}
|
Note
|
Constraints: src1 = dst |
SHRD32rrCL_NF_ND [In64BitMode]
shrd{l} {%cl, src2, src1, dst|dst, src1, src2, cl}
SHRD32rri8_EVEX [In64BitMode]
shrd{l} {src3, src2, src1|src1, src2, src3}
|
Note
|
Constraints: src1 = dst |
SHRD32rri8_NF [In64BitMode]
shrd{l} {src3, src2, src1|src1, src2, src3}
|
Note
|
Constraints: src1 = dst |
SHRD32rri8_NF_ND [In64BitMode]
shrd{l} {src3, src2, src1, dst|dst, src1, src2, src3}
SHRD64mrCL_EVEX [In64BitMode]
shrd{q} {%cl, src2, src1|src1, src2, cl}
|
Note
|
Properties: mayLoad, mayStore |
SHRD64mrCL_NF [In64BitMode]
shrd{q} {%cl, src2, src1|src1, src2, cl}
|
Note
|
Properties: mayLoad, mayStore |
SHRD64mrCL_NF_ND [In64BitMode]
shrd{q} {%cl, src2, src1, dst|dst, src1, src2, cl}
|
Note
|
Properties: mayLoad |
SHRD64mri8_EVEX [In64BitMode]
shrd{q} {src3, src2, src1|src1, src2, src3}
|
Note
|
Properties: mayLoad, mayStore |
SHRD64mri8_NF [In64BitMode]
shrd{q} {src3, src2, src1|src1, src2, src3}
|
Note
|
Properties: mayLoad, mayStore |
SHRD64mri8_NF_ND [In64BitMode]
shrd{q} {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayLoad |
SHRD64rrCL_EVEX [In64BitMode]
shrd{q} {%cl, src2, src1|src1, src2, cl}
|
Note
|
Constraints: src1 = dst |
SHRD64rrCL_NF [In64BitMode]
shrd{q} {%cl, src2, src1|src1, src2, cl}
|
Note
|
Constraints: src1 = dst |
SHRD64rrCL_NF_ND [In64BitMode]
shrd{q} {%cl, src2, src1, dst|dst, src1, src2, cl}
SHRD64rri8_EVEX [In64BitMode]
shrd{q} {src3, src2, src1|src1, src2, src3}
|
Note
|
Constraints: src1 = dst |
SHRD64rri8_NF [In64BitMode]
shrd{q} {src3, src2, src1|src1, src2, src3}
|
Note
|
Constraints: src1 = dst |
SHRD64rri8_NF_ND [In64BitMode]
shrd{q} {src3, src2, src1, dst|dst, src1, src2, src3}
SIDT64m [In64BitMode]
sidt{q} dst
SLDT64r [In64BitMode]
sldt{q} dst
STOSQ [In64BitMode]
stosq {%rax, dst|dst, rax}
SUB16mi8_EVEX [In64BitMode]
sub{w} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare, mayLoad, mayStore |
SUB16mi8_NF [In64BitMode]
sub{w} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare, mayLoad, mayStore |
SUB16mi_EVEX [In64BitMode]
sub{w} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare, mayLoad, mayStore |
SUB16mi_NF [In64BitMode]
sub{w} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare, mayLoad, mayStore |
SUB16mr_EVEX [In64BitMode]
sub{w} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare, mayLoad, mayStore |
SUB16mr_NF [In64BitMode]
sub{w} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare, mayLoad, mayStore |
SUB16ri8_EVEX [In64BitMode]
sub{w} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare |
|
Note
|
Constraints: src1 = dst |
SUB16ri8_NF [In64BitMode]
sub{w} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare |
|
Note
|
Constraints: src1 = dst |
SUB16ri_EVEX [In64BitMode]
sub{w} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare |
|
Note
|
Constraints: src1 = dst |
SUB16ri_NF [In64BitMode]
sub{w} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare |
|
Note
|
Constraints: src1 = dst |
SUB16rm_EVEX [In64BitMode]
sub{w} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare, mayLoad |
|
Note
|
Constraints: src1 = dst |
SUB16rm_NF [In64BitMode]
sub{w} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare, mayLoad |
|
Note
|
Constraints: src1 = dst |
SUB16rr_EVEX [In64BitMode]
sub{w} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare |
|
Note
|
Constraints: src1 = dst |
SUB16rr_NF [In64BitMode]
sub{w} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare |
|
Note
|
Constraints: src1 = dst |
SUB32mi8_EVEX [In64BitMode]
sub{l} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare, mayLoad, mayStore |
SUB32mi8_NF [In64BitMode]
sub{l} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare, mayLoad, mayStore |
SUB32mi_EVEX [In64BitMode]
sub{l} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare, mayLoad, mayStore |
SUB32mi_NF [In64BitMode]
sub{l} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare, mayLoad, mayStore |
SUB32mr_EVEX [In64BitMode]
sub{l} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare, mayLoad, mayStore |
SUB32mr_NF [In64BitMode]
sub{l} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare, mayLoad, mayStore |
SUB32ri8_EVEX [In64BitMode]
sub{l} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare |
|
Note
|
Constraints: src1 = dst |
SUB32ri8_NF [In64BitMode]
sub{l} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare |
|
Note
|
Constraints: src1 = dst |
SUB32ri_EVEX [In64BitMode]
sub{l} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare |
|
Note
|
Constraints: src1 = dst |
SUB32ri_NF [In64BitMode]
sub{l} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare |
|
Note
|
Constraints: src1 = dst |
SUB32rm_EVEX [In64BitMode]
sub{l} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare, mayLoad |
|
Note
|
Constraints: src1 = dst |
SUB32rm_NF [In64BitMode]
sub{l} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare, mayLoad |
|
Note
|
Constraints: src1 = dst |
SUB32rr_EVEX [In64BitMode]
sub{l} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare |
|
Note
|
Constraints: src1 = dst |
SUB32rr_NF [In64BitMode]
sub{l} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare |
|
Note
|
Constraints: src1 = dst |
SUB64mi32 [In64BitMode]
sub{q} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare, mayLoad, mayStore |
SUB64mi32_EVEX [In64BitMode]
sub{q} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare, mayLoad, mayStore |
SUB64mi32_NF [In64BitMode]
sub{q} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare, mayLoad, mayStore |
SUB64mi8 [In64BitMode]
sub{q} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare, mayLoad, mayStore |
SUB64mi8_EVEX [In64BitMode]
sub{q} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare, mayLoad, mayStore |
SUB64mi8_NF [In64BitMode]
sub{q} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare, mayLoad, mayStore |
SUB64mr_EVEX [In64BitMode]
sub{q} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare, mayLoad, mayStore |
SUB64mr_NF [In64BitMode]
sub{q} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare, mayLoad, mayStore |
SUB64ri32_EVEX [In64BitMode]
sub{q} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare |
|
Note
|
Constraints: src1 = dst |
SUB64ri32_NF [In64BitMode]
sub{q} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare |
|
Note
|
Constraints: src1 = dst |
SUB64ri8_EVEX [In64BitMode]
sub{q} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare |
|
Note
|
Constraints: src1 = dst |
SUB64ri8_NF [In64BitMode]
sub{q} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare |
|
Note
|
Constraints: src1 = dst |
SUB64rm_EVEX [In64BitMode]
sub{q} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare, mayLoad |
|
Note
|
Constraints: src1 = dst |
SUB64rm_NF [In64BitMode]
sub{q} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare, mayLoad |
|
Note
|
Constraints: src1 = dst |
SUB64rr_EVEX [In64BitMode]
sub{q} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare |
|
Note
|
Constraints: src1 = dst |
SUB64rr_NF [In64BitMode]
sub{q} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare |
|
Note
|
Constraints: src1 = dst |
SUB8mi_EVEX [In64BitMode]
sub{b} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare, mayLoad, mayStore |
SUB8mi_NF [In64BitMode]
sub{b} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare, mayLoad, mayStore |
SUB8mr_EVEX [In64BitMode]
sub{b} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare, mayLoad, mayStore |
SUB8mr_NF [In64BitMode]
sub{b} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare, mayLoad, mayStore |
SUB8ri_EVEX [In64BitMode]
sub{b} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare |
|
Note
|
Constraints: src1 = dst |
SUB8ri_NF [In64BitMode]
sub{b} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare |
|
Note
|
Constraints: src1 = dst |
SUB8rm_EVEX [In64BitMode]
sub{b} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare, mayLoad |
|
Note
|
Constraints: src1 = dst |
SUB8rm_NF [In64BitMode]
sub{b} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare, mayLoad |
|
Note
|
Constraints: src1 = dst |
SUB8rr_EVEX [In64BitMode]
sub{b} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare |
|
Note
|
Constraints: src1 = dst |
SUB8rr_NF [In64BitMode]
sub{b} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare |
|
Note
|
Constraints: src1 = dst |
SYSEXIT64 [In64BitMode]
sysexitq
SYSRET64 [In64BitMode]
sysretq
TEST64mi32 [In64BitMode]
test{q} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare, mayLoad |
VMLOAD64 [In64BitMode]
vmload
VMREAD64mr [In64BitMode]
vmread{q} {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VMREAD64rr [In64BitMode]
vmread{q} {src, dst|dst, src}
VMRUN64 [In64BitMode]
vmrun
VMSAVE64 [In64BitMode]
vmsave
VMWRITE64rm [In64BitMode]
vmwrite{q} {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
VMWRITE64rr [In64BitMode]
vmwrite{q} {src, dst|dst, src}
WRMSRLIST [In64BitMode]
wrmsrlist
XOR16mi8_EVEX [In64BitMode]
xor{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
XOR16mi8_NF [In64BitMode]
xor{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
XOR16mi_EVEX [In64BitMode]
xor{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
XOR16mi_NF [In64BitMode]
xor{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
XOR16mr_EVEX [In64BitMode]
xor{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
XOR16mr_NF [In64BitMode]
xor{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
XOR16ri8_EVEX [In64BitMode]
xor{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
XOR16ri8_NF [In64BitMode]
xor{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
XOR16ri_EVEX [In64BitMode]
xor{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
XOR16ri_NF [In64BitMode]
xor{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
XOR16rm_EVEX [In64BitMode]
xor{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
XOR16rm_NF [In64BitMode]
xor{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
XOR16rr_EVEX [In64BitMode]
xor{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
XOR16rr_NF [In64BitMode]
xor{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
XOR32mi8_EVEX [In64BitMode]
xor{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
XOR32mi8_NF [In64BitMode]
xor{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
XOR32mi_EVEX [In64BitMode]
xor{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
XOR32mi_NF [In64BitMode]
xor{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
XOR32mr_EVEX [In64BitMode]
xor{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
XOR32mr_NF [In64BitMode]
xor{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
XOR32ri8_EVEX [In64BitMode]
xor{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
XOR32ri8_NF [In64BitMode]
xor{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
XOR32ri_EVEX [In64BitMode]
xor{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
XOR32ri_NF [In64BitMode]
xor{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
XOR32rm_EVEX [In64BitMode]
xor{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
XOR32rm_NF [In64BitMode]
xor{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
XOR32rr_EVEX [In64BitMode]
xor{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
XOR32rr_NF [In64BitMode]
xor{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
XOR64mi32 [In64BitMode]
xor{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
XOR64mi32_EVEX [In64BitMode]
xor{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
XOR64mi32_NF [In64BitMode]
xor{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
XOR64mi8 [In64BitMode]
xor{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
XOR64mi8_EVEX [In64BitMode]
xor{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
XOR64mi8_NF [In64BitMode]
xor{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
XOR64mr_EVEX [In64BitMode]
xor{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
XOR64mr_NF [In64BitMode]
xor{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
XOR64ri32_EVEX [In64BitMode]
xor{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
XOR64ri32_NF [In64BitMode]
xor{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
XOR64ri8_EVEX [In64BitMode]
xor{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
XOR64ri8_NF [In64BitMode]
xor{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
XOR64rm_EVEX [In64BitMode]
xor{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
XOR64rm_NF [In64BitMode]
xor{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
XOR64rr_EVEX [In64BitMode]
xor{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
XOR64rr_NF [In64BitMode]
xor{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
XOR8mi_EVEX [In64BitMode]
xor{b} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
XOR8mi_NF [In64BitMode]
xor{b} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
XOR8mr_EVEX [In64BitMode]
xor{b} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
XOR8mr_NF [In64BitMode]
xor{b} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
XOR8ri_EVEX [In64BitMode]
xor{b} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
XOR8ri_NF [In64BitMode]
xor{b} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
XOR8rm_EVEX [In64BitMode]
xor{b} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
XOR8rm_NF [In64BitMode]
xor{b} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
XOR8rr_EVEX [In64BitMode]
xor{b} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
XOR8rr_NF [In64BitMode]
xor{b} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
VMOVRSBZ128m [In64BitMode, HasAVX10_2, HasMOVRS]
vmovrsb {src, dst|dst, src}
VMOVRSBZ128mk [In64BitMode, HasAVX10_2, HasMOVRS]
vmovrsb {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VMOVRSBZ128mkz [In64BitMode, HasAVX10_2, HasMOVRS]
vmovrsb {src, dst {mask} {z}|dst {mask} {z}, src}
VMOVRSBZ256m [In64BitMode, HasAVX10_2, HasMOVRS]
vmovrsb {src, dst|dst, src}
VMOVRSBZ256mk [In64BitMode, HasAVX10_2, HasMOVRS]
vmovrsb {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VMOVRSBZ256mkz [In64BitMode, HasAVX10_2, HasMOVRS]
vmovrsb {src, dst {mask} {z}|dst {mask} {z}, src}
VMOVRSDZ128m [In64BitMode, HasAVX10_2, HasMOVRS]
vmovrsd {src, dst|dst, src}
VMOVRSDZ128mk [In64BitMode, HasAVX10_2, HasMOVRS]
vmovrsd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VMOVRSDZ128mkz [In64BitMode, HasAVX10_2, HasMOVRS]
vmovrsd {src, dst {mask} {z}|dst {mask} {z}, src}
VMOVRSDZ256m [In64BitMode, HasAVX10_2, HasMOVRS]
vmovrsd {src, dst|dst, src}
VMOVRSDZ256mk [In64BitMode, HasAVX10_2, HasMOVRS]
vmovrsd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VMOVRSDZ256mkz [In64BitMode, HasAVX10_2, HasMOVRS]
vmovrsd {src, dst {mask} {z}|dst {mask} {z}, src}
VMOVRSQZ128m [In64BitMode, HasAVX10_2, HasMOVRS]
vmovrsq {src, dst|dst, src}
VMOVRSQZ128mk [In64BitMode, HasAVX10_2, HasMOVRS]
vmovrsq {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VMOVRSQZ128mkz [In64BitMode, HasAVX10_2, HasMOVRS]
vmovrsq {src, dst {mask} {z}|dst {mask} {z}, src}
VMOVRSQZ256m [In64BitMode, HasAVX10_2, HasMOVRS]
vmovrsq {src, dst|dst, src}
VMOVRSQZ256mk [In64BitMode, HasAVX10_2, HasMOVRS]
vmovrsq {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VMOVRSQZ256mkz [In64BitMode, HasAVX10_2, HasMOVRS]
vmovrsq {src, dst {mask} {z}|dst {mask} {z}, src}
VMOVRSWZ128m [In64BitMode, HasAVX10_2, HasMOVRS]
vmovrsw {src, dst|dst, src}
VMOVRSWZ128mk [In64BitMode, HasAVX10_2, HasMOVRS]
vmovrsw {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VMOVRSWZ128mkz [In64BitMode, HasAVX10_2, HasMOVRS]
vmovrsw {src, dst {mask} {z}|dst {mask} {z}, src}
VMOVRSWZ256m [In64BitMode, HasAVX10_2, HasMOVRS]
vmovrsw {src, dst|dst, src}
VMOVRSWZ256mk [In64BitMode, HasAVX10_2, HasMOVRS]
vmovrsw {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VMOVRSWZ256mkz [In64BitMode, HasAVX10_2, HasMOVRS]
vmovrsw {src, dst {mask} {z}|dst {mask} {z}, src}
KMOVDkk_EVEX [In64BitMode, HasBWI, HasEGPR]
kmovd {src, dst|dst, src}
|
Note
|
Properties: isMoveReg |
KMOVDkm_EVEX [In64BitMode, HasBWI, HasEGPR]
kmovd {src, dst|dst, src}
KMOVDkr_EVEX [In64BitMode, HasBWI, HasEGPR]
kmovd {src, dst|dst, src}
KMOVDmk_EVEX [In64BitMode, HasBWI, HasEGPR]
kmovd {src, dst|dst, src}
KMOVDrk_EVEX [In64BitMode, HasBWI, HasEGPR]
kmovd {src, dst|dst, src}
KMOVQkk_EVEX [In64BitMode, HasBWI, HasEGPR]
kmovq {src, dst|dst, src}
|
Note
|
Properties: isMoveReg |
KMOVQkm_EVEX [In64BitMode, HasBWI, HasEGPR]
kmovq {src, dst|dst, src}
KMOVQkr_EVEX [In64BitMode, HasBWI, HasEGPR]
kmovq {src, dst|dst, src}
KMOVQmk_EVEX [In64BitMode, HasBWI, HasEGPR]
kmovq {src, dst|dst, src}
KMOVQrk_EVEX [In64BitMode, HasBWI, HasEGPR]
kmovq {src, dst|dst, src}
KMOVBkk_EVEX [In64BitMode, HasDQI, HasEGPR]
kmovb {src, dst|dst, src}
|
Note
|
Properties: isMoveReg |
KMOVBkm_EVEX [In64BitMode, HasDQI, HasEGPR]
kmovb {src, dst|dst, src}
KMOVBkr_EVEX [In64BitMode, HasDQI, HasEGPR]
kmovb {src, dst|dst, src}
KMOVBmk_EVEX [In64BitMode, HasDQI, HasEGPR]
kmovb {src, dst|dst, src}
KMOVBrk_EVEX [In64BitMode, HasDQI, HasEGPR]
kmovb {src, dst|dst, src}
VMOVRSBZm [In64BitMode, HasAVX10_2_512, HasMOVRS]
vmovrsb {src, dst|dst, src}
VMOVRSBZmk [In64BitMode, HasAVX10_2_512, HasMOVRS]
vmovrsb {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VMOVRSBZmkz [In64BitMode, HasAVX10_2_512, HasMOVRS]
vmovrsb {src, dst {mask} {z}|dst {mask} {z}, src}
VMOVRSDZm [In64BitMode, HasAVX10_2_512, HasMOVRS]
vmovrsd {src, dst|dst, src}
VMOVRSDZmk [In64BitMode, HasAVX10_2_512, HasMOVRS]
vmovrsd {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VMOVRSDZmkz [In64BitMode, HasAVX10_2_512, HasMOVRS]
vmovrsd {src, dst {mask} {z}|dst {mask} {z}, src}
VMOVRSQZm [In64BitMode, HasAVX10_2_512, HasMOVRS]
vmovrsq {src, dst|dst, src}
VMOVRSQZmk [In64BitMode, HasAVX10_2_512, HasMOVRS]
vmovrsq {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VMOVRSQZmkz [In64BitMode, HasAVX10_2_512, HasMOVRS]
vmovrsq {src, dst {mask} {z}|dst {mask} {z}, src}
VMOVRSWZm [In64BitMode, HasAVX10_2_512, HasMOVRS]
vmovrsw {src, dst|dst, src}
VMOVRSWZmk [In64BitMode, HasAVX10_2_512, HasMOVRS]
vmovrsw {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VMOVRSWZmkz [In64BitMode, HasAVX10_2_512, HasMOVRS]
vmovrsw {src, dst {mask} {z}|dst {mask} {z}, src}
TCVTROWD2PSrre [In64BitMode, HasAVX10_2_512, HasAMXAVX512]
tcvtrowd2ps {src2, src1, dst|dst, src1, src2}
TCVTROWD2PSrri [In64BitMode, HasAVX10_2_512, HasAMXAVX512]
tcvtrowd2ps {src2, src1, dst|dst, src1, src2}
TCVTROWPS2BF16Hrre [In64BitMode, HasAVX10_2_512, HasAMXAVX512]
tcvtrowps2bf16h {src2, src1, dst|dst, src1, src2}
TCVTROWPS2BF16Hrri [In64BitMode, HasAVX10_2_512, HasAMXAVX512]
tcvtrowps2bf16h {src2, src1, dst|dst, src1, src2}
TCVTROWPS2BF16Lrre [In64BitMode, HasAVX10_2_512, HasAMXAVX512]
tcvtrowps2bf16l {src2, src1, dst|dst, src1, src2}
TCVTROWPS2BF16Lrri [In64BitMode, HasAVX10_2_512, HasAMXAVX512]
tcvtrowps2bf16l {src2, src1, dst|dst, src1, src2}
TCVTROWPS2PHHrre [In64BitMode, HasAVX10_2_512, HasAMXAVX512]
tcvtrowps2phh {src2, src1, dst|dst, src1, src2}
TCVTROWPS2PHHrri [In64BitMode, HasAVX10_2_512, HasAMXAVX512]
tcvtrowps2phh {src2, src1, dst|dst, src1, src2}
TCVTROWPS2PHLrre [In64BitMode, HasAVX10_2_512, HasAMXAVX512]
tcvtrowps2phl {src2, src1, dst|dst, src1, src2}
TCVTROWPS2PHLrri [In64BitMode, HasAVX10_2_512, HasAMXAVX512]
tcvtrowps2phl {src2, src1, dst|dst, src1, src2}
TILEMOVROWrre [In64BitMode, HasAVX10_2_512, HasAMXAVX512]
tilemovrow {src2, src1, dst|dst, src1, src2}
TILEMOVROWrri [In64BitMode, HasAVX10_2_512, HasAMXAVX512]
tilemovrow {src2, src1, dst|dst, src1, src2}
VMASKMOVDQU64 [In64BitMode, HasAVX]
vmaskmovdqu {mask, src|src, mask}
ADC16mi8_ND [In64BitMode, HasNDD]
adc{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
ADC16mi_ND [In64BitMode, HasNDD]
adc{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
ADC16mr_ND [In64BitMode, HasNDD]
adc{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
ADC16ri8_ND [In64BitMode, HasNDD]
adc{w} {src2, src1, dst|dst, src1, src2}
ADC16ri_ND [In64BitMode, HasNDD]
adc{w} {src2, src1, dst|dst, src1, src2}
ADC16rm_ND [In64BitMode, HasNDD]
adc{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
ADC16rr_ND [In64BitMode, HasNDD]
adc{w} {src2, src1, dst|dst, src1, src2}
ADC32mi8_ND [In64BitMode, HasNDD]
adc{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
ADC32mi_ND [In64BitMode, HasNDD]
adc{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
ADC32mr_ND [In64BitMode, HasNDD]
adc{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
ADC32ri8_ND [In64BitMode, HasNDD]
adc{l} {src2, src1, dst|dst, src1, src2}
ADC32ri_ND [In64BitMode, HasNDD]
adc{l} {src2, src1, dst|dst, src1, src2}
ADC32rm_ND [In64BitMode, HasNDD]
adc{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
ADC32rr_ND [In64BitMode, HasNDD]
adc{l} {src2, src1, dst|dst, src1, src2}
ADC64mi32_ND [In64BitMode, HasNDD]
adc{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
ADC64mi8_ND [In64BitMode, HasNDD]
adc{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
ADC64mr_ND [In64BitMode, HasNDD]
adc{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
ADC64ri32_ND [In64BitMode, HasNDD]
adc{q} {src2, src1, dst|dst, src1, src2}
ADC64ri8_ND [In64BitMode, HasNDD]
adc{q} {src2, src1, dst|dst, src1, src2}
ADC64rm_ND [In64BitMode, HasNDD]
adc{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
ADC64rr_ND [In64BitMode, HasNDD]
adc{q} {src2, src1, dst|dst, src1, src2}
ADC8mi_ND [In64BitMode, HasNDD]
adc{b} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
ADC8mr_ND [In64BitMode, HasNDD]
adc{b} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
ADC8ri_ND [In64BitMode, HasNDD]
adc{b} {src2, src1, dst|dst, src1, src2}
ADC8rm_ND [In64BitMode, HasNDD]
adc{b} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
ADC8rr_ND [In64BitMode, HasNDD]
adc{b} {src2, src1, dst|dst, src1, src2}
ADD16mi8_ND [In64BitMode, HasNDD]
add{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
ADD16mi8_NF_ND [In64BitMode, HasNDD]
add{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
ADD16mi_ND [In64BitMode, HasNDD]
add{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
ADD16mi_NF_ND [In64BitMode, HasNDD]
add{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
ADD16mr_ND [In64BitMode, HasNDD]
add{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
ADD16mr_NF_ND [In64BitMode, HasNDD]
add{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
ADD16ri8_ND [In64BitMode, HasNDD]
add{w} {src2, src1, dst|dst, src1, src2}
ADD16ri8_NF_ND [In64BitMode, HasNDD]
add{w} {src2, src1, dst|dst, src1, src2}
ADD16ri_ND [In64BitMode, HasNDD]
add{w} {src2, src1, dst|dst, src1, src2}
ADD16ri_NF_ND [In64BitMode, HasNDD]
add{w} {src2, src1, dst|dst, src1, src2}
ADD16rm_ND [In64BitMode, HasNDD]
add{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
ADD16rm_NF_ND [In64BitMode, HasNDD]
add{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
ADD16rr_ND [In64BitMode, HasNDD]
add{w} {src2, src1, dst|dst, src1, src2}
ADD16rr_NF_ND [In64BitMode, HasNDD]
add{w} {src2, src1, dst|dst, src1, src2}
ADD32mi8_ND [In64BitMode, HasNDD]
add{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
ADD32mi8_NF_ND [In64BitMode, HasNDD]
add{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
ADD32mi_ND [In64BitMode, HasNDD]
add{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
ADD32mi_NF_ND [In64BitMode, HasNDD]
add{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
ADD32mr_ND [In64BitMode, HasNDD]
add{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
ADD32mr_NF_ND [In64BitMode, HasNDD]
add{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
ADD32ri8_ND [In64BitMode, HasNDD]
add{l} {src2, src1, dst|dst, src1, src2}
ADD32ri8_NF_ND [In64BitMode, HasNDD]
add{l} {src2, src1, dst|dst, src1, src2}
ADD32ri_ND [In64BitMode, HasNDD]
add{l} {src2, src1, dst|dst, src1, src2}
ADD32ri_NF_ND [In64BitMode, HasNDD]
add{l} {src2, src1, dst|dst, src1, src2}
ADD32rm_ND [In64BitMode, HasNDD]
add{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
ADD32rm_NF_ND [In64BitMode, HasNDD]
add{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
ADD32rr_ND [In64BitMode, HasNDD]
add{l} {src2, src1, dst|dst, src1, src2}
ADD32rr_NF_ND [In64BitMode, HasNDD]
add{l} {src2, src1, dst|dst, src1, src2}
ADD64mi32_ND [In64BitMode, HasNDD]
add{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
ADD64mi32_NF_ND [In64BitMode, HasNDD]
add{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
ADD64mi8_ND [In64BitMode, HasNDD]
add{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
ADD64mi8_NF_ND [In64BitMode, HasNDD]
add{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
ADD64mr_ND [In64BitMode, HasNDD]
add{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
ADD64mr_NF_ND [In64BitMode, HasNDD]
add{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
ADD64ri32_ND [In64BitMode, HasNDD]
add{q} {src2, src1, dst|dst, src1, src2}
ADD64ri32_NF_ND [In64BitMode, HasNDD]
add{q} {src2, src1, dst|dst, src1, src2}
ADD64ri8_ND [In64BitMode, HasNDD]
add{q} {src2, src1, dst|dst, src1, src2}
ADD64ri8_NF_ND [In64BitMode, HasNDD]
add{q} {src2, src1, dst|dst, src1, src2}
ADD64rm_ND [In64BitMode, HasNDD]
add{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
ADD64rm_NF_ND [In64BitMode, HasNDD]
add{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
ADD64rr_ND [In64BitMode, HasNDD]
add{q} {src2, src1, dst|dst, src1, src2}
ADD64rr_NF_ND [In64BitMode, HasNDD]
add{q} {src2, src1, dst|dst, src1, src2}
ADD8mi_ND [In64BitMode, HasNDD]
add{b} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
ADD8mi_NF_ND [In64BitMode, HasNDD]
add{b} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
ADD8mr_ND [In64BitMode, HasNDD]
add{b} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
ADD8mr_NF_ND [In64BitMode, HasNDD]
add{b} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
ADD8ri_ND [In64BitMode, HasNDD]
add{b} {src2, src1, dst|dst, src1, src2}
ADD8ri_NF_ND [In64BitMode, HasNDD]
add{b} {src2, src1, dst|dst, src1, src2}
ADD8rm_ND [In64BitMode, HasNDD]
add{b} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
ADD8rm_NF_ND [In64BitMode, HasNDD]
add{b} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
ADD8rr_ND [In64BitMode, HasNDD]
add{b} {src2, src1, dst|dst, src1, src2}
ADD8rr_NF_ND [In64BitMode, HasNDD]
add{b} {src2, src1, dst|dst, src1, src2}
AND16mi8_ND [In64BitMode, HasNDD]
and{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
AND16mi8_NF_ND [In64BitMode, HasNDD]
and{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
AND16mi_ND [In64BitMode, HasNDD]
and{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
AND16mi_NF_ND [In64BitMode, HasNDD]
and{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
AND16mr_ND [In64BitMode, HasNDD]
and{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
AND16mr_NF_ND [In64BitMode, HasNDD]
and{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
AND16ri8_ND [In64BitMode, HasNDD]
and{w} {src2, src1, dst|dst, src1, src2}
AND16ri8_NF_ND [In64BitMode, HasNDD]
and{w} {src2, src1, dst|dst, src1, src2}
AND16ri_ND [In64BitMode, HasNDD]
and{w} {src2, src1, dst|dst, src1, src2}
AND16ri_NF_ND [In64BitMode, HasNDD]
and{w} {src2, src1, dst|dst, src1, src2}
AND16rm_ND [In64BitMode, HasNDD]
and{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
AND16rm_NF_ND [In64BitMode, HasNDD]
and{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
AND16rr_ND [In64BitMode, HasNDD]
and{w} {src2, src1, dst|dst, src1, src2}
AND16rr_NF_ND [In64BitMode, HasNDD]
and{w} {src2, src1, dst|dst, src1, src2}
AND32mi8_ND [In64BitMode, HasNDD]
and{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
AND32mi8_NF_ND [In64BitMode, HasNDD]
and{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
AND32mi_ND [In64BitMode, HasNDD]
and{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
AND32mi_NF_ND [In64BitMode, HasNDD]
and{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
AND32mr_ND [In64BitMode, HasNDD]
and{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
AND32mr_NF_ND [In64BitMode, HasNDD]
and{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
AND32ri8_ND [In64BitMode, HasNDD]
and{l} {src2, src1, dst|dst, src1, src2}
AND32ri8_NF_ND [In64BitMode, HasNDD]
and{l} {src2, src1, dst|dst, src1, src2}
AND32ri_ND [In64BitMode, HasNDD]
and{l} {src2, src1, dst|dst, src1, src2}
AND32ri_NF_ND [In64BitMode, HasNDD]
and{l} {src2, src1, dst|dst, src1, src2}
AND32rm_ND [In64BitMode, HasNDD]
and{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
AND32rm_NF_ND [In64BitMode, HasNDD]
and{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
AND32rr_ND [In64BitMode, HasNDD]
and{l} {src2, src1, dst|dst, src1, src2}
AND32rr_NF_ND [In64BitMode, HasNDD]
and{l} {src2, src1, dst|dst, src1, src2}
AND64mi32_ND [In64BitMode, HasNDD]
and{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
AND64mi32_NF_ND [In64BitMode, HasNDD]
and{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
AND64mi8_ND [In64BitMode, HasNDD]
and{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
AND64mi8_NF_ND [In64BitMode, HasNDD]
and{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
AND64mr_ND [In64BitMode, HasNDD]
and{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
AND64mr_NF_ND [In64BitMode, HasNDD]
and{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
AND64ri32_ND [In64BitMode, HasNDD]
and{q} {src2, src1, dst|dst, src1, src2}
AND64ri32_NF_ND [In64BitMode, HasNDD]
and{q} {src2, src1, dst|dst, src1, src2}
AND64ri8_ND [In64BitMode, HasNDD]
and{q} {src2, src1, dst|dst, src1, src2}
AND64ri8_NF_ND [In64BitMode, HasNDD]
and{q} {src2, src1, dst|dst, src1, src2}
AND64rm_ND [In64BitMode, HasNDD]
and{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
AND64rm_NF_ND [In64BitMode, HasNDD]
and{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
AND64rr_ND [In64BitMode, HasNDD]
and{q} {src2, src1, dst|dst, src1, src2}
AND64rr_NF_ND [In64BitMode, HasNDD]
and{q} {src2, src1, dst|dst, src1, src2}
AND8mi_ND [In64BitMode, HasNDD]
and{b} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
AND8mi_NF_ND [In64BitMode, HasNDD]
and{b} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
AND8mr_ND [In64BitMode, HasNDD]
and{b} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
AND8mr_NF_ND [In64BitMode, HasNDD]
and{b} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
AND8ri_ND [In64BitMode, HasNDD]
and{b} {src2, src1, dst|dst, src1, src2}
AND8ri_NF_ND [In64BitMode, HasNDD]
and{b} {src2, src1, dst|dst, src1, src2}
AND8rm_ND [In64BitMode, HasNDD]
and{b} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
AND8rm_NF_ND [In64BitMode, HasNDD]
and{b} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
AND8rr_ND [In64BitMode, HasNDD]
and{b} {src2, src1, dst|dst, src1, src2}
AND8rr_NF_ND [In64BitMode, HasNDD]
and{b} {src2, src1, dst|dst, src1, src2}
DEC16r_ND [In64BitMode, HasNDD]
dec{w} {src1, dst|dst, src1}
DEC32r_ND [In64BitMode, HasNDD]
dec{l} {src1, dst|dst, src1}
DEC64r_ND [In64BitMode, HasNDD]
dec{q} {src1, dst|dst, src1}
DEC8r_ND [In64BitMode, HasNDD]
dec{b} {src1, dst|dst, src1}
IMUL16rm_ND [In64BitMode, HasNDD]
imul{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
IMUL16rr_ND [In64BitMode, HasNDD]
imul{w} {src2, src1, dst|dst, src1, src2}
IMUL32rm_ND [In64BitMode, HasNDD]
imul{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
IMUL32rr_ND [In64BitMode, HasNDD]
imul{l} {src2, src1, dst|dst, src1, src2}
IMUL64rm_ND [In64BitMode, HasNDD]
imul{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
IMUL64rr_ND [In64BitMode, HasNDD]
imul{q} {src2, src1, dst|dst, src1, src2}
INC16r_ND [In64BitMode, HasNDD]
inc{w} {src1, dst|dst, src1}
INC32r_ND [In64BitMode, HasNDD]
inc{l} {src1, dst|dst, src1}
INC64r_ND [In64BitMode, HasNDD]
inc{q} {src1, dst|dst, src1}
INC8r_ND [In64BitMode, HasNDD]
inc{b} {src1, dst|dst, src1}
NEG16m_ND [In64BitMode, HasNDD]
neg{w} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
NEG16m_NF_ND [In64BitMode, HasNDD]
neg{w} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
NEG16r_ND [In64BitMode, HasNDD]
neg{w} {src1, dst|dst, src1}
NEG16r_NF_ND [In64BitMode, HasNDD]
neg{w} {src1, dst|dst, src1}
NEG32m_ND [In64BitMode, HasNDD]
neg{l} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
NEG32m_NF_ND [In64BitMode, HasNDD]
neg{l} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
NEG32r_ND [In64BitMode, HasNDD]
neg{l} {src1, dst|dst, src1}
NEG32r_NF_ND [In64BitMode, HasNDD]
neg{l} {src1, dst|dst, src1}
NEG64m_ND [In64BitMode, HasNDD]
neg{q} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
NEG64m_NF_ND [In64BitMode, HasNDD]
neg{q} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
NEG64r_ND [In64BitMode, HasNDD]
neg{q} {src1, dst|dst, src1}
NEG64r_NF_ND [In64BitMode, HasNDD]
neg{q} {src1, dst|dst, src1}
NEG8m_ND [In64BitMode, HasNDD]
neg{b} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
NEG8m_NF_ND [In64BitMode, HasNDD]
neg{b} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
NEG8r_ND [In64BitMode, HasNDD]
neg{b} {src1, dst|dst, src1}
NEG8r_NF_ND [In64BitMode, HasNDD]
neg{b} {src1, dst|dst, src1}
NOT16m_ND [In64BitMode, HasNDD]
not{w} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
NOT16r_ND [In64BitMode, HasNDD]
not{w} {src1, dst|dst, src1}
NOT32m_ND [In64BitMode, HasNDD]
not{l} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
NOT32r_ND [In64BitMode, HasNDD]
not{l} {src1, dst|dst, src1}
NOT64m_ND [In64BitMode, HasNDD]
not{q} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
NOT64r_ND [In64BitMode, HasNDD]
not{q} {src1, dst|dst, src1}
NOT8m_ND [In64BitMode, HasNDD]
not{b} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
NOT8r_ND [In64BitMode, HasNDD]
not{b} {src1, dst|dst, src1}
OR16mi8_ND [In64BitMode, HasNDD]
or{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
OR16mi8_NF_ND [In64BitMode, HasNDD]
or{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
OR16mi_ND [In64BitMode, HasNDD]
or{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
OR16mi_NF_ND [In64BitMode, HasNDD]
or{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
OR16mr_ND [In64BitMode, HasNDD]
or{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
OR16mr_NF_ND [In64BitMode, HasNDD]
or{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
OR16ri8_ND [In64BitMode, HasNDD]
or{w} {src2, src1, dst|dst, src1, src2}
OR16ri8_NF_ND [In64BitMode, HasNDD]
or{w} {src2, src1, dst|dst, src1, src2}
OR16ri_ND [In64BitMode, HasNDD]
or{w} {src2, src1, dst|dst, src1, src2}
OR16ri_NF_ND [In64BitMode, HasNDD]
or{w} {src2, src1, dst|dst, src1, src2}
OR16rm_ND [In64BitMode, HasNDD]
or{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
OR16rm_NF_ND [In64BitMode, HasNDD]
or{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
OR16rr_ND [In64BitMode, HasNDD]
or{w} {src2, src1, dst|dst, src1, src2}
OR16rr_NF_ND [In64BitMode, HasNDD]
or{w} {src2, src1, dst|dst, src1, src2}
OR32mi8_ND [In64BitMode, HasNDD]
or{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
OR32mi8_NF_ND [In64BitMode, HasNDD]
or{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
OR32mi_ND [In64BitMode, HasNDD]
or{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
OR32mi_NF_ND [In64BitMode, HasNDD]
or{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
OR32mr_ND [In64BitMode, HasNDD]
or{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
OR32mr_NF_ND [In64BitMode, HasNDD]
or{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
OR32ri8_ND [In64BitMode, HasNDD]
or{l} {src2, src1, dst|dst, src1, src2}
OR32ri8_NF_ND [In64BitMode, HasNDD]
or{l} {src2, src1, dst|dst, src1, src2}
OR32ri_ND [In64BitMode, HasNDD]
or{l} {src2, src1, dst|dst, src1, src2}
OR32ri_NF_ND [In64BitMode, HasNDD]
or{l} {src2, src1, dst|dst, src1, src2}
OR32rm_ND [In64BitMode, HasNDD]
or{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
OR32rm_NF_ND [In64BitMode, HasNDD]
or{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
OR32rr_ND [In64BitMode, HasNDD]
or{l} {src2, src1, dst|dst, src1, src2}
OR32rr_NF_ND [In64BitMode, HasNDD]
or{l} {src2, src1, dst|dst, src1, src2}
OR64mi32_ND [In64BitMode, HasNDD]
or{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
OR64mi32_NF_ND [In64BitMode, HasNDD]
or{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
OR64mi8_ND [In64BitMode, HasNDD]
or{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
OR64mi8_NF_ND [In64BitMode, HasNDD]
or{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
OR64mr_ND [In64BitMode, HasNDD]
or{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
OR64mr_NF_ND [In64BitMode, HasNDD]
or{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
OR64ri32_ND [In64BitMode, HasNDD]
or{q} {src2, src1, dst|dst, src1, src2}
OR64ri32_NF_ND [In64BitMode, HasNDD]
or{q} {src2, src1, dst|dst, src1, src2}
OR64ri8_ND [In64BitMode, HasNDD]
or{q} {src2, src1, dst|dst, src1, src2}
OR64ri8_NF_ND [In64BitMode, HasNDD]
or{q} {src2, src1, dst|dst, src1, src2}
OR64rm_ND [In64BitMode, HasNDD]
or{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
OR64rm_NF_ND [In64BitMode, HasNDD]
or{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
OR64rr_ND [In64BitMode, HasNDD]
or{q} {src2, src1, dst|dst, src1, src2}
OR64rr_NF_ND [In64BitMode, HasNDD]
or{q} {src2, src1, dst|dst, src1, src2}
OR8mi_ND [In64BitMode, HasNDD]
or{b} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
OR8mi_NF_ND [In64BitMode, HasNDD]
or{b} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
OR8mr_ND [In64BitMode, HasNDD]
or{b} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
OR8mr_NF_ND [In64BitMode, HasNDD]
or{b} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
OR8ri_ND [In64BitMode, HasNDD]
or{b} {src2, src1, dst|dst, src1, src2}
OR8ri_NF_ND [In64BitMode, HasNDD]
or{b} {src2, src1, dst|dst, src1, src2}
OR8rm_ND [In64BitMode, HasNDD]
or{b} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
OR8rm_NF_ND [In64BitMode, HasNDD]
or{b} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
OR8rr_ND [In64BitMode, HasNDD]
or{b} {src2, src1, dst|dst, src1, src2}
OR8rr_NF_ND [In64BitMode, HasNDD]
or{b} {src2, src1, dst|dst, src1, src2}
RCL16mCL_ND [In64BitMode, HasNDD]
rcl{w} {%cl, src1, dst|dst, src1, cl}
|
Note
|
Properties: mayLoad |
RCL16mi_ND [In64BitMode, HasNDD]
rcl{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
RCL16rCL_ND [In64BitMode, HasNDD]
rcl{w} {%cl, src1, dst|dst, src1, cl}
RCL16ri_ND [In64BitMode, HasNDD]
rcl{w} {src2, src1, dst|dst, src1, src2}
RCL32mCL_ND [In64BitMode, HasNDD]
rcl{l} {%cl, src1, dst|dst, src1, cl}
|
Note
|
Properties: mayLoad |
RCL32mi_ND [In64BitMode, HasNDD]
rcl{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
RCL32rCL_ND [In64BitMode, HasNDD]
rcl{l} {%cl, src1, dst|dst, src1, cl}
RCL32ri_ND [In64BitMode, HasNDD]
rcl{l} {src2, src1, dst|dst, src1, src2}
RCL64mCL_ND [In64BitMode, HasNDD]
rcl{q} {%cl, src1, dst|dst, src1, cl}
|
Note
|
Properties: mayLoad |
RCL64mi_ND [In64BitMode, HasNDD]
rcl{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
RCL64rCL_ND [In64BitMode, HasNDD]
rcl{q} {%cl, src1, dst|dst, src1, cl}
RCL64ri_ND [In64BitMode, HasNDD]
rcl{q} {src2, src1, dst|dst, src1, src2}
RCL8mCL_ND [In64BitMode, HasNDD]
rcl{b} {%cl, src1, dst|dst, src1, cl}
|
Note
|
Properties: mayLoad |
RCL8mi_ND [In64BitMode, HasNDD]
rcl{b} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
RCL8rCL_ND [In64BitMode, HasNDD]
rcl{b} {%cl, src1, dst|dst, src1, cl}
RCL8ri_ND [In64BitMode, HasNDD]
rcl{b} {src2, src1, dst|dst, src1, src2}
RCR16mCL_ND [In64BitMode, HasNDD]
rcr{w} {%cl, src1, dst|dst, src1, cl}
|
Note
|
Properties: mayLoad |
RCR16mi_ND [In64BitMode, HasNDD]
rcr{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
RCR16rCL_ND [In64BitMode, HasNDD]
rcr{w} {%cl, src1, dst|dst, src1, cl}
RCR16ri_ND [In64BitMode, HasNDD]
rcr{w} {src2, src1, dst|dst, src1, src2}
RCR32mCL_ND [In64BitMode, HasNDD]
rcr{l} {%cl, src1, dst|dst, src1, cl}
|
Note
|
Properties: mayLoad |
RCR32mi_ND [In64BitMode, HasNDD]
rcr{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
RCR32rCL_ND [In64BitMode, HasNDD]
rcr{l} {%cl, src1, dst|dst, src1, cl}
RCR32ri_ND [In64BitMode, HasNDD]
rcr{l} {src2, src1, dst|dst, src1, src2}
RCR64mCL_ND [In64BitMode, HasNDD]
rcr{q} {%cl, src1, dst|dst, src1, cl}
|
Note
|
Properties: mayLoad |
RCR64mi_ND [In64BitMode, HasNDD]
rcr{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
RCR64rCL_ND [In64BitMode, HasNDD]
rcr{q} {%cl, src1, dst|dst, src1, cl}
RCR64ri_ND [In64BitMode, HasNDD]
rcr{q} {src2, src1, dst|dst, src1, src2}
RCR8mCL_ND [In64BitMode, HasNDD]
rcr{b} {%cl, src1, dst|dst, src1, cl}
|
Note
|
Properties: mayLoad |
RCR8mi_ND [In64BitMode, HasNDD]
rcr{b} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
RCR8rCL_ND [In64BitMode, HasNDD]
rcr{b} {%cl, src1, dst|dst, src1, cl}
RCR8ri_ND [In64BitMode, HasNDD]
rcr{b} {src2, src1, dst|dst, src1, src2}
ROL16mCL_ND [In64BitMode, HasNDD]
rol{w} {%cl, src1, dst|dst, src1, cl}
|
Note
|
Properties: mayLoad |
ROL16mi_ND [In64BitMode, HasNDD]
rol{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
ROL16rCL_ND [In64BitMode, HasNDD]
rol{w} {%cl, src1, dst|dst, src1, cl}
ROL16ri_ND [In64BitMode, HasNDD]
rol{w} {src2, src1, dst|dst, src1, src2}
ROL32mCL_ND [In64BitMode, HasNDD]
rol{l} {%cl, src1, dst|dst, src1, cl}
|
Note
|
Properties: mayLoad |
ROL32mi_ND [In64BitMode, HasNDD]
rol{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
ROL32rCL_ND [In64BitMode, HasNDD]
rol{l} {%cl, src1, dst|dst, src1, cl}
ROL32ri_ND [In64BitMode, HasNDD]
rol{l} {src2, src1, dst|dst, src1, src2}
ROL64mCL_ND [In64BitMode, HasNDD]
rol{q} {%cl, src1, dst|dst, src1, cl}
|
Note
|
Properties: mayLoad |
ROL64mi_ND [In64BitMode, HasNDD]
rol{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
ROL64rCL_ND [In64BitMode, HasNDD]
rol{q} {%cl, src1, dst|dst, src1, cl}
ROL64ri_ND [In64BitMode, HasNDD]
rol{q} {src2, src1, dst|dst, src1, src2}
ROL8mCL_ND [In64BitMode, HasNDD]
rol{b} {%cl, src1, dst|dst, src1, cl}
|
Note
|
Properties: mayLoad |
ROL8mi_ND [In64BitMode, HasNDD]
rol{b} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
ROL8rCL_ND [In64BitMode, HasNDD]
rol{b} {%cl, src1, dst|dst, src1, cl}
ROL8ri_ND [In64BitMode, HasNDD]
rol{b} {src2, src1, dst|dst, src1, src2}
ROR16mCL_ND [In64BitMode, HasNDD]
ror{w} {%cl, src1, dst|dst, src1, cl}
|
Note
|
Properties: mayLoad |
ROR16mi_ND [In64BitMode, HasNDD]
ror{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
ROR16rCL_ND [In64BitMode, HasNDD]
ror{w} {%cl, src1, dst|dst, src1, cl}
ROR16ri_ND [In64BitMode, HasNDD]
ror{w} {src2, src1, dst|dst, src1, src2}
ROR32mCL_ND [In64BitMode, HasNDD]
ror{l} {%cl, src1, dst|dst, src1, cl}
|
Note
|
Properties: mayLoad |
ROR32mi_ND [In64BitMode, HasNDD]
ror{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
ROR32rCL_ND [In64BitMode, HasNDD]
ror{l} {%cl, src1, dst|dst, src1, cl}
ROR32ri_ND [In64BitMode, HasNDD]
ror{l} {src2, src1, dst|dst, src1, src2}
ROR64mCL_ND [In64BitMode, HasNDD]
ror{q} {%cl, src1, dst|dst, src1, cl}
|
Note
|
Properties: mayLoad |
ROR64mi_ND [In64BitMode, HasNDD]
ror{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
ROR64rCL_ND [In64BitMode, HasNDD]
ror{q} {%cl, src1, dst|dst, src1, cl}
ROR64ri_ND [In64BitMode, HasNDD]
ror{q} {src2, src1, dst|dst, src1, src2}
ROR8mCL_ND [In64BitMode, HasNDD]
ror{b} {%cl, src1, dst|dst, src1, cl}
|
Note
|
Properties: mayLoad |
ROR8mi_ND [In64BitMode, HasNDD]
ror{b} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
ROR8rCL_ND [In64BitMode, HasNDD]
ror{b} {%cl, src1, dst|dst, src1, cl}
ROR8ri_ND [In64BitMode, HasNDD]
ror{b} {src2, src1, dst|dst, src1, src2}
SAR16mCL_ND [In64BitMode, HasNDD]
sar{w} {%cl, src1, dst|dst, src1, cl}
|
Note
|
Properties: mayLoad |
SAR16mi_ND [In64BitMode, HasNDD]
sar{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
SAR16rCL_ND [In64BitMode, HasNDD]
sar{w} {%cl, src1, dst|dst, src1, cl}
SAR16ri_ND [In64BitMode, HasNDD]
sar{w} {src2, src1, dst|dst, src1, src2}
SAR32mCL_ND [In64BitMode, HasNDD]
sar{l} {%cl, src1, dst|dst, src1, cl}
|
Note
|
Properties: mayLoad |
SAR32mi_ND [In64BitMode, HasNDD]
sar{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
SAR32rCL_ND [In64BitMode, HasNDD]
sar{l} {%cl, src1, dst|dst, src1, cl}
SAR32ri_ND [In64BitMode, HasNDD]
sar{l} {src2, src1, dst|dst, src1, src2}
SAR64mCL_ND [In64BitMode, HasNDD]
sar{q} {%cl, src1, dst|dst, src1, cl}
|
Note
|
Properties: mayLoad |
SAR64mi_ND [In64BitMode, HasNDD]
sar{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
SAR64rCL_ND [In64BitMode, HasNDD]
sar{q} {%cl, src1, dst|dst, src1, cl}
SAR64ri_ND [In64BitMode, HasNDD]
sar{q} {src2, src1, dst|dst, src1, src2}
SAR8mCL_ND [In64BitMode, HasNDD]
sar{b} {%cl, src1, dst|dst, src1, cl}
|
Note
|
Properties: mayLoad |
SAR8mi_ND [In64BitMode, HasNDD]
sar{b} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
SAR8rCL_ND [In64BitMode, HasNDD]
sar{b} {%cl, src1, dst|dst, src1, cl}
SAR8ri_ND [In64BitMode, HasNDD]
sar{b} {src2, src1, dst|dst, src1, src2}
SBB16mi8_ND [In64BitMode, HasNDD]
sbb{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
SBB16mi_ND [In64BitMode, HasNDD]
sbb{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
SBB16mr_ND [In64BitMode, HasNDD]
sbb{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
SBB16ri8_ND [In64BitMode, HasNDD]
sbb{w} {src2, src1, dst|dst, src1, src2}
SBB16ri_ND [In64BitMode, HasNDD]
sbb{w} {src2, src1, dst|dst, src1, src2}
SBB16rm_ND [In64BitMode, HasNDD]
sbb{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
SBB16rr_ND [In64BitMode, HasNDD]
sbb{w} {src2, src1, dst|dst, src1, src2}
SBB32mi8_ND [In64BitMode, HasNDD]
sbb{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
SBB32mi_ND [In64BitMode, HasNDD]
sbb{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
SBB32mr_ND [In64BitMode, HasNDD]
sbb{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
SBB32ri8_ND [In64BitMode, HasNDD]
sbb{l} {src2, src1, dst|dst, src1, src2}
SBB32ri_ND [In64BitMode, HasNDD]
sbb{l} {src2, src1, dst|dst, src1, src2}
SBB32rm_ND [In64BitMode, HasNDD]
sbb{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
SBB32rr_ND [In64BitMode, HasNDD]
sbb{l} {src2, src1, dst|dst, src1, src2}
SBB64mi32_ND [In64BitMode, HasNDD]
sbb{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
SBB64mi8_ND [In64BitMode, HasNDD]
sbb{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
SBB64mr_ND [In64BitMode, HasNDD]
sbb{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
SBB64ri32_ND [In64BitMode, HasNDD]
sbb{q} {src2, src1, dst|dst, src1, src2}
SBB64ri8_ND [In64BitMode, HasNDD]
sbb{q} {src2, src1, dst|dst, src1, src2}
SBB64rm_ND [In64BitMode, HasNDD]
sbb{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
SBB64rr_ND [In64BitMode, HasNDD]
sbb{q} {src2, src1, dst|dst, src1, src2}
SBB8mi_ND [In64BitMode, HasNDD]
sbb{b} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
SBB8mr_ND [In64BitMode, HasNDD]
sbb{b} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
SBB8ri_ND [In64BitMode, HasNDD]
sbb{b} {src2, src1, dst|dst, src1, src2}
SBB8rm_ND [In64BitMode, HasNDD]
sbb{b} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
SBB8rr_ND [In64BitMode, HasNDD]
sbb{b} {src2, src1, dst|dst, src1, src2}
SHL16mCL_ND [In64BitMode, HasNDD]
shl{w} {%cl, src1, dst|dst, src1, cl}
|
Note
|
Properties: mayLoad |
SHL16mi_ND [In64BitMode, HasNDD]
shl{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
SHL16rCL_ND [In64BitMode, HasNDD]
shl{w} {%cl, src1, dst|dst, src1, cl}
SHL16ri_ND [In64BitMode, HasNDD]
shl{w} {src2, src1, dst|dst, src1, src2}
SHL32mCL_ND [In64BitMode, HasNDD]
shl{l} {%cl, src1, dst|dst, src1, cl}
|
Note
|
Properties: mayLoad |
SHL32mi_ND [In64BitMode, HasNDD]
shl{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
SHL32rCL_ND [In64BitMode, HasNDD]
shl{l} {%cl, src1, dst|dst, src1, cl}
SHL32ri_ND [In64BitMode, HasNDD]
shl{l} {src2, src1, dst|dst, src1, src2}
SHL64mCL_ND [In64BitMode, HasNDD]
shl{q} {%cl, src1, dst|dst, src1, cl}
|
Note
|
Properties: mayLoad |
SHL64mi_ND [In64BitMode, HasNDD]
shl{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
SHL64rCL_ND [In64BitMode, HasNDD]
shl{q} {%cl, src1, dst|dst, src1, cl}
SHL64ri_ND [In64BitMode, HasNDD]
shl{q} {src2, src1, dst|dst, src1, src2}
SHL8mCL_ND [In64BitMode, HasNDD]
shl{b} {%cl, src1, dst|dst, src1, cl}
|
Note
|
Properties: mayLoad |
SHL8mi_ND [In64BitMode, HasNDD]
shl{b} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
SHL8rCL_ND [In64BitMode, HasNDD]
shl{b} {%cl, src1, dst|dst, src1, cl}
SHL8ri_ND [In64BitMode, HasNDD]
shl{b} {src2, src1, dst|dst, src1, src2}
SHLD16mrCL_ND [In64BitMode, HasNDD]
shld{w} {%cl, src2, src1, dst|dst, src1, src2, cl}
|
Note
|
Properties: mayLoad |
SHLD16mri8_ND [In64BitMode, HasNDD]
shld{w} {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayLoad |
SHLD16rrCL_ND [In64BitMode, HasNDD]
shld{w} {%cl, src2, src1, dst|dst, src1, src2, cl}
SHLD16rri8_ND [In64BitMode, HasNDD]
shld{w} {src3, src2, src1, dst|dst, src1, src2, src3}
SHLD32mrCL_ND [In64BitMode, HasNDD]
shld{l} {%cl, src2, src1, dst|dst, src1, src2, cl}
|
Note
|
Properties: mayLoad |
SHLD32mri8_ND [In64BitMode, HasNDD]
shld{l} {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayLoad |
SHLD32rrCL_ND [In64BitMode, HasNDD]
shld{l} {%cl, src2, src1, dst|dst, src1, src2, cl}
SHLD32rri8_ND [In64BitMode, HasNDD]
shld{l} {src3, src2, src1, dst|dst, src1, src2, src3}
SHLD64mrCL_ND [In64BitMode, HasNDD]
shld{q} {%cl, src2, src1, dst|dst, src1, src2, cl}
|
Note
|
Properties: mayLoad |
SHLD64mri8_ND [In64BitMode, HasNDD]
shld{q} {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayLoad |
SHLD64rrCL_ND [In64BitMode, HasNDD]
shld{q} {%cl, src2, src1, dst|dst, src1, src2, cl}
SHLD64rri8_ND [In64BitMode, HasNDD]
shld{q} {src3, src2, src1, dst|dst, src1, src2, src3}
SHR16mCL_ND [In64BitMode, HasNDD]
shr{w} {%cl, src1, dst|dst, src1, cl}
|
Note
|
Properties: mayLoad |
SHR16mi_ND [In64BitMode, HasNDD]
shr{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
SHR16rCL_ND [In64BitMode, HasNDD]
shr{w} {%cl, src1, dst|dst, src1, cl}
SHR16ri_ND [In64BitMode, HasNDD]
shr{w} {src2, src1, dst|dst, src1, src2}
SHR32mCL_ND [In64BitMode, HasNDD]
shr{l} {%cl, src1, dst|dst, src1, cl}
|
Note
|
Properties: mayLoad |
SHR32mi_ND [In64BitMode, HasNDD]
shr{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
SHR32rCL_ND [In64BitMode, HasNDD]
shr{l} {%cl, src1, dst|dst, src1, cl}
SHR32ri_ND [In64BitMode, HasNDD]
shr{l} {src2, src1, dst|dst, src1, src2}
SHR64mCL_ND [In64BitMode, HasNDD]
shr{q} {%cl, src1, dst|dst, src1, cl}
|
Note
|
Properties: mayLoad |
SHR64mi_ND [In64BitMode, HasNDD]
shr{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
SHR64rCL_ND [In64BitMode, HasNDD]
shr{q} {%cl, src1, dst|dst, src1, cl}
SHR64ri_ND [In64BitMode, HasNDD]
shr{q} {src2, src1, dst|dst, src1, src2}
SHR8mCL_ND [In64BitMode, HasNDD]
shr{b} {%cl, src1, dst|dst, src1, cl}
|
Note
|
Properties: mayLoad |
SHR8mi_ND [In64BitMode, HasNDD]
shr{b} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
SHR8rCL_ND [In64BitMode, HasNDD]
shr{b} {%cl, src1, dst|dst, src1, cl}
SHR8ri_ND [In64BitMode, HasNDD]
shr{b} {src2, src1, dst|dst, src1, src2}
SHRD16mrCL_ND [In64BitMode, HasNDD]
shrd{w} {%cl, src2, src1, dst|dst, src1, src2, cl}
|
Note
|
Properties: mayLoad |
SHRD16mri8_ND [In64BitMode, HasNDD]
shrd{w} {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayLoad |
SHRD16rrCL_ND [In64BitMode, HasNDD]
shrd{w} {%cl, src2, src1, dst|dst, src1, src2, cl}
SHRD16rri8_ND [In64BitMode, HasNDD]
shrd{w} {src3, src2, src1, dst|dst, src1, src2, src3}
SHRD32mrCL_ND [In64BitMode, HasNDD]
shrd{l} {%cl, src2, src1, dst|dst, src1, src2, cl}
|
Note
|
Properties: mayLoad |
SHRD32mri8_ND [In64BitMode, HasNDD]
shrd{l} {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayLoad |
SHRD32rrCL_ND [In64BitMode, HasNDD]
shrd{l} {%cl, src2, src1, dst|dst, src1, src2, cl}
SHRD32rri8_ND [In64BitMode, HasNDD]
shrd{l} {src3, src2, src1, dst|dst, src1, src2, src3}
SHRD64mrCL_ND [In64BitMode, HasNDD]
shrd{q} {%cl, src2, src1, dst|dst, src1, src2, cl}
|
Note
|
Properties: mayLoad |
SHRD64mri8_ND [In64BitMode, HasNDD]
shrd{q} {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayLoad |
SHRD64rrCL_ND [In64BitMode, HasNDD]
shrd{q} {%cl, src2, src1, dst|dst, src1, src2, cl}
SHRD64rri8_ND [In64BitMode, HasNDD]
shrd{q} {src3, src2, src1, dst|dst, src1, src2, src3}
SUB16mi8_ND [In64BitMode, HasNDD]
sub{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: isCompare, mayLoad |
SUB16mi8_NF_ND [In64BitMode, HasNDD]
sub{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: isCompare, mayLoad |
SUB16mi_ND [In64BitMode, HasNDD]
sub{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: isCompare, mayLoad |
SUB16mi_NF_ND [In64BitMode, HasNDD]
sub{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: isCompare, mayLoad |
SUB16mr_ND [In64BitMode, HasNDD]
sub{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: isCompare, mayLoad |
SUB16mr_NF_ND [In64BitMode, HasNDD]
sub{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: isCompare, mayLoad |
SUB16ri8_ND [In64BitMode, HasNDD]
sub{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: isCompare |
SUB16ri8_NF_ND [In64BitMode, HasNDD]
sub{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: isCompare |
SUB16ri_ND [In64BitMode, HasNDD]
sub{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: isCompare |
SUB16ri_NF_ND [In64BitMode, HasNDD]
sub{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: isCompare |
SUB16rm_ND [In64BitMode, HasNDD]
sub{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: isCompare, mayLoad |
SUB16rm_NF_ND [In64BitMode, HasNDD]
sub{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: isCompare, mayLoad |
SUB16rr_ND [In64BitMode, HasNDD]
sub{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: isCompare |
SUB16rr_NF_ND [In64BitMode, HasNDD]
sub{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: isCompare |
SUB32mi8_ND [In64BitMode, HasNDD]
sub{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: isCompare, mayLoad |
SUB32mi8_NF_ND [In64BitMode, HasNDD]
sub{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: isCompare, mayLoad |
SUB32mi_ND [In64BitMode, HasNDD]
sub{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: isCompare, mayLoad |
SUB32mi_NF_ND [In64BitMode, HasNDD]
sub{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: isCompare, mayLoad |
SUB32mr_ND [In64BitMode, HasNDD]
sub{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: isCompare, mayLoad |
SUB32mr_NF_ND [In64BitMode, HasNDD]
sub{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: isCompare, mayLoad |
SUB32ri8_ND [In64BitMode, HasNDD]
sub{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: isCompare |
SUB32ri8_NF_ND [In64BitMode, HasNDD]
sub{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: isCompare |
SUB32ri_ND [In64BitMode, HasNDD]
sub{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: isCompare |
SUB32ri_NF_ND [In64BitMode, HasNDD]
sub{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: isCompare |
SUB32rm_ND [In64BitMode, HasNDD]
sub{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: isCompare, mayLoad |
SUB32rm_NF_ND [In64BitMode, HasNDD]
sub{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: isCompare, mayLoad |
SUB32rr_ND [In64BitMode, HasNDD]
sub{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: isCompare |
SUB32rr_NF_ND [In64BitMode, HasNDD]
sub{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: isCompare |
SUB64mi32_ND [In64BitMode, HasNDD]
sub{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: isCompare, mayLoad |
SUB64mi32_NF_ND [In64BitMode, HasNDD]
sub{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: isCompare, mayLoad |
SUB64mi8_ND [In64BitMode, HasNDD]
sub{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: isCompare, mayLoad |
SUB64mi8_NF_ND [In64BitMode, HasNDD]
sub{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: isCompare, mayLoad |
SUB64mr_ND [In64BitMode, HasNDD]
sub{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: isCompare, mayLoad |
SUB64mr_NF_ND [In64BitMode, HasNDD]
sub{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: isCompare, mayLoad |
SUB64ri32_ND [In64BitMode, HasNDD]
sub{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: isCompare |
SUB64ri32_NF_ND [In64BitMode, HasNDD]
sub{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: isCompare |
SUB64ri8_ND [In64BitMode, HasNDD]
sub{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: isCompare |
SUB64ri8_NF_ND [In64BitMode, HasNDD]
sub{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: isCompare |
SUB64rm_ND [In64BitMode, HasNDD]
sub{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: isCompare, mayLoad |
SUB64rm_NF_ND [In64BitMode, HasNDD]
sub{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: isCompare, mayLoad |
SUB64rr_ND [In64BitMode, HasNDD]
sub{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: isCompare |
SUB64rr_NF_ND [In64BitMode, HasNDD]
sub{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: isCompare |
SUB8mi_ND [In64BitMode, HasNDD]
sub{b} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: isCompare, mayLoad |
SUB8mi_NF_ND [In64BitMode, HasNDD]
sub{b} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: isCompare, mayLoad |
SUB8mr_ND [In64BitMode, HasNDD]
sub{b} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: isCompare, mayLoad |
SUB8mr_NF_ND [In64BitMode, HasNDD]
sub{b} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: isCompare, mayLoad |
SUB8ri_ND [In64BitMode, HasNDD]
sub{b} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: isCompare |
SUB8ri_NF_ND [In64BitMode, HasNDD]
sub{b} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: isCompare |
SUB8rm_ND [In64BitMode, HasNDD]
sub{b} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: isCompare, mayLoad |
SUB8rm_NF_ND [In64BitMode, HasNDD]
sub{b} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: isCompare, mayLoad |
SUB8rr_ND [In64BitMode, HasNDD]
sub{b} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: isCompare |
SUB8rr_NF_ND [In64BitMode, HasNDD]
sub{b} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: isCompare |
XOR16mi8_ND [In64BitMode, HasNDD]
xor{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
XOR16mi8_NF_ND [In64BitMode, HasNDD]
xor{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
XOR16mi_ND [In64BitMode, HasNDD]
xor{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
XOR16mi_NF_ND [In64BitMode, HasNDD]
xor{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
XOR16mr_ND [In64BitMode, HasNDD]
xor{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
XOR16mr_NF_ND [In64BitMode, HasNDD]
xor{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
XOR16ri8_ND [In64BitMode, HasNDD]
xor{w} {src2, src1, dst|dst, src1, src2}
XOR16ri8_NF_ND [In64BitMode, HasNDD]
xor{w} {src2, src1, dst|dst, src1, src2}
XOR16ri_ND [In64BitMode, HasNDD]
xor{w} {src2, src1, dst|dst, src1, src2}
XOR16ri_NF_ND [In64BitMode, HasNDD]
xor{w} {src2, src1, dst|dst, src1, src2}
XOR16rm_ND [In64BitMode, HasNDD]
xor{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
XOR16rm_NF_ND [In64BitMode, HasNDD]
xor{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
XOR16rr_ND [In64BitMode, HasNDD]
xor{w} {src2, src1, dst|dst, src1, src2}
XOR16rr_NF_ND [In64BitMode, HasNDD]
xor{w} {src2, src1, dst|dst, src1, src2}
XOR32mi8_ND [In64BitMode, HasNDD]
xor{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
XOR32mi8_NF_ND [In64BitMode, HasNDD]
xor{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
XOR32mi_ND [In64BitMode, HasNDD]
xor{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
XOR32mi_NF_ND [In64BitMode, HasNDD]
xor{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
XOR32mr_ND [In64BitMode, HasNDD]
xor{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
XOR32mr_NF_ND [In64BitMode, HasNDD]
xor{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
XOR32ri8_ND [In64BitMode, HasNDD]
xor{l} {src2, src1, dst|dst, src1, src2}
XOR32ri8_NF_ND [In64BitMode, HasNDD]
xor{l} {src2, src1, dst|dst, src1, src2}
XOR32ri_ND [In64BitMode, HasNDD]
xor{l} {src2, src1, dst|dst, src1, src2}
XOR32ri_NF_ND [In64BitMode, HasNDD]
xor{l} {src2, src1, dst|dst, src1, src2}
XOR32rm_ND [In64BitMode, HasNDD]
xor{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
XOR32rm_NF_ND [In64BitMode, HasNDD]
xor{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
XOR32rr_ND [In64BitMode, HasNDD]
xor{l} {src2, src1, dst|dst, src1, src2}
XOR32rr_NF_ND [In64BitMode, HasNDD]
xor{l} {src2, src1, dst|dst, src1, src2}
XOR64mi32_ND [In64BitMode, HasNDD]
xor{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
XOR64mi32_NF_ND [In64BitMode, HasNDD]
xor{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
XOR64mi8_ND [In64BitMode, HasNDD]
xor{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
XOR64mi8_NF_ND [In64BitMode, HasNDD]
xor{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
XOR64mr_ND [In64BitMode, HasNDD]
xor{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
XOR64mr_NF_ND [In64BitMode, HasNDD]
xor{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
XOR64ri32_ND [In64BitMode, HasNDD]
xor{q} {src2, src1, dst|dst, src1, src2}
XOR64ri32_NF_ND [In64BitMode, HasNDD]
xor{q} {src2, src1, dst|dst, src1, src2}
XOR64ri8_ND [In64BitMode, HasNDD]
xor{q} {src2, src1, dst|dst, src1, src2}
XOR64ri8_NF_ND [In64BitMode, HasNDD]
xor{q} {src2, src1, dst|dst, src1, src2}
XOR64rm_ND [In64BitMode, HasNDD]
xor{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
XOR64rm_NF_ND [In64BitMode, HasNDD]
xor{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
XOR64rr_ND [In64BitMode, HasNDD]
xor{q} {src2, src1, dst|dst, src1, src2}
XOR64rr_NF_ND [In64BitMode, HasNDD]
xor{q} {src2, src1, dst|dst, src1, src2}
XOR8mi_ND [In64BitMode, HasNDD]
xor{b} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
XOR8mi_NF_ND [In64BitMode, HasNDD]
xor{b} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
XOR8mr_ND [In64BitMode, HasNDD]
xor{b} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
XOR8mr_NF_ND [In64BitMode, HasNDD]
xor{b} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
XOR8ri_ND [In64BitMode, HasNDD]
xor{b} {src2, src1, dst|dst, src1, src2}
XOR8ri_NF_ND [In64BitMode, HasNDD]
xor{b} {src2, src1, dst|dst, src1, src2}
XOR8rm_ND [In64BitMode, HasNDD]
xor{b} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
XOR8rm_NF_ND [In64BitMode, HasNDD]
xor{b} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
XOR8rr_ND [In64BitMode, HasNDD]
xor{b} {src2, src1, dst|dst, src1, src2}
XOR8rr_NF_ND [In64BitMode, HasNDD]
xor{b} {src2, src1, dst|dst, src1, src2}
DEC16m_ND [In64BitMode, HasNDD, UseIncDec]
dec{w} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
DEC32m_ND [In64BitMode, HasNDD, UseIncDec]
dec{l} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
DEC64m_ND [In64BitMode, HasNDD, UseIncDec]
dec{q} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
DEC8m_ND [In64BitMode, HasNDD, UseIncDec]
dec{b} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
INC16m_ND [In64BitMode, HasNDD, UseIncDec]
inc{w} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
INC32m_ND [In64BitMode, HasNDD, UseIncDec]
inc{l} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
INC64m_ND [In64BitMode, HasNDD, UseIncDec]
inc{q} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
INC8m_ND [In64BitMode, HasNDD, UseIncDec]
inc{b} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
MOVBE16rr [In64BitMode, HasNDD, HasMOVBE]
movbe{w} {src1, dst|dst, src1}
MOVBE32rr [In64BitMode, HasNDD, HasMOVBE]
movbe{l} {src1, dst|dst, src1}
MOVBE64rr [In64BitMode, HasNDD, HasMOVBE]
movbe{q} {src1, dst|dst, src1}
MASKMOVDQU64 [In64BitMode, UseSSE2]
maskmovdqu {mask, src|src, mask}
MMX_MOVD64from64rr [In64BitMode, HasMMX]
movq {src, dst|dst, src}
|
Note
|
Properties: isBitcast |
MMX_MOVD64to64rr [In64BitMode, HasMMX]
movq {src, dst|dst, src}
|
Note
|
Properties: isBitcast |
MMX_MASKMOVQ64 [In64BitMode, HasMMX, HasSSE1]
maskmovq {mask, src|src, mask}
IMULZU16rmi [In64BitMode, HasEGPR]
imulzu{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
IMULZU16rmi8 [In64BitMode, HasEGPR]
imulzu{w} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
IMULZU16rri [In64BitMode, HasEGPR]
imulzu{w} {src2, src1, dst|dst, src1, src2}
IMULZU16rri8 [In64BitMode, HasEGPR]
imulzu{w} {src2, src1, dst|dst, src1, src2}
IMULZU32rmi [In64BitMode, HasEGPR]
imulzu{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
IMULZU32rmi8 [In64BitMode, HasEGPR]
imulzu{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
IMULZU32rri [In64BitMode, HasEGPR]
imulzu{l} {src2, src1, dst|dst, src1, src2}
IMULZU32rri8 [In64BitMode, HasEGPR]
imulzu{l} {src2, src1, dst|dst, src1, src2}
IMULZU64rmi32 [In64BitMode, HasEGPR]
imulzu{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
IMULZU64rmi8 [In64BitMode, HasEGPR]
imulzu{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
IMULZU64rri32 [In64BitMode, HasEGPR]
imulzu{q} {src2, src1, dst|dst, src1, src2}
IMULZU64rri8 [In64BitMode, HasEGPR]
imulzu{q} {src2, src1, dst|dst, src1, src2}
WRSSD_EVEX [In64BitMode, HasEGPR]
wrssd {src, dst|dst, src}
WRSSQ_EVEX [In64BitMode, HasEGPR]
wrssq {src, dst|dst, src}
WRUSSD_EVEX [In64BitMode, HasEGPR]
wrussd {src, dst|dst, src}
WRUSSQ_EVEX [In64BitMode, HasEGPR]
wrussq {src, dst|dst, src}
BZHI32rm_EVEX [In64BitMode, HasEGPR, HasBMI2]
bzhi{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
BZHI32rr_EVEX [In64BitMode, HasEGPR, HasBMI2]
bzhi{l} {src2, src1, dst|dst, src1, src2}
BZHI64rm_EVEX [In64BitMode, HasEGPR, HasBMI2]
bzhi{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
BZHI64rr_EVEX [In64BitMode, HasEGPR, HasBMI2]
bzhi{q} {src2, src1, dst|dst, src1, src2}
RORX32mi_EVEX [In64BitMode, HasEGPR, HasBMI2]
rorx{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
RORX32ri_EVEX [In64BitMode, HasEGPR, HasBMI2]
rorx{l} {src2, src1, dst|dst, src1, src2}
RORX64mi_EVEX [In64BitMode, HasEGPR, HasBMI2]
rorx{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
RORX64ri_EVEX [In64BitMode, HasEGPR, HasBMI2]
rorx{q} {src2, src1, dst|dst, src1, src2}
SARX32rm_EVEX [In64BitMode, HasEGPR, HasBMI2]
sarx{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
SARX32rr_EVEX [In64BitMode, HasEGPR, HasBMI2]
sarx{l} {src2, src1, dst|dst, src1, src2}
SARX64rm_EVEX [In64BitMode, HasEGPR, HasBMI2]
sarx{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
SARX64rr_EVEX [In64BitMode, HasEGPR, HasBMI2]
sarx{q} {src2, src1, dst|dst, src1, src2}
SHLX32rm_EVEX [In64BitMode, HasEGPR, HasBMI2]
shlx{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
SHLX32rr_EVEX [In64BitMode, HasEGPR, HasBMI2]
shlx{l} {src2, src1, dst|dst, src1, src2}
SHLX64rm_EVEX [In64BitMode, HasEGPR, HasBMI2]
shlx{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
SHLX64rr_EVEX [In64BitMode, HasEGPR, HasBMI2]
shlx{q} {src2, src1, dst|dst, src1, src2}
SHRX32rm_EVEX [In64BitMode, HasEGPR, HasBMI2]
shrx{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
SHRX32rr_EVEX [In64BitMode, HasEGPR, HasBMI2]
shrx{l} {src2, src1, dst|dst, src1, src2}
SHRX64rm_EVEX [In64BitMode, HasEGPR, HasBMI2]
shrx{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
SHRX64rr_EVEX [In64BitMode, HasEGPR, HasBMI2]
shrx{q} {src2, src1, dst|dst, src1, src2}
MOVRS16rm_EVEX [In64BitMode, HasEGPR, HasMOVRS]
movrs{w} {src, dst|dst, src}
MOVRS32rm_EVEX [In64BitMode, HasEGPR, HasMOVRS]
movrs{l} {src, dst|dst, src}
MOVRS64rm_EVEX [In64BitMode, HasEGPR, HasMOVRS]
movrs{q} {src, dst|dst, src}
MOVRS8rm_EVEX [In64BitMode, HasEGPR, HasMOVRS]
movrs{b} {src, dst|dst, src}
ANDN32rm_EVEX [In64BitMode, HasEGPR, HasBMI]
andn{l} {src2, src1, dst|dst, src1, src2}
ANDN32rr_EVEX [In64BitMode, HasEGPR, HasBMI]
andn{l} {src2, src1, dst|dst, src1, src2}
ANDN64rm_EVEX [In64BitMode, HasEGPR, HasBMI]
andn{q} {src2, src1, dst|dst, src1, src2}
ANDN64rr_EVEX [In64BitMode, HasEGPR, HasBMI]
andn{q} {src2, src1, dst|dst, src1, src2}
BEXTR32rm_EVEX [In64BitMode, HasEGPR, HasBMI]
bextr{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
BEXTR32rr_EVEX [In64BitMode, HasEGPR, HasBMI]
bextr{l} {src2, src1, dst|dst, src1, src2}
BEXTR64rm_EVEX [In64BitMode, HasEGPR, HasBMI]
bextr{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
BEXTR64rr_EVEX [In64BitMode, HasEGPR, HasBMI]
bextr{q} {src2, src1, dst|dst, src1, src2}
T2RPNTLVWZ0T1_EVEX [In64BitMode, HasEGPR, HasAMXTRANSPOSE]
t2rpntlvwz0t1 {src, dst|dst, src}
T2RPNTLVWZ0_EVEX [In64BitMode, HasEGPR, HasAMXTRANSPOSE]
t2rpntlvwz0 {src, dst|dst, src}
T2RPNTLVWZ1T1_EVEX [In64BitMode, HasEGPR, HasAMXTRANSPOSE]
t2rpntlvwz1t1 {src, dst|dst, src}
T2RPNTLVWZ1_EVEX [In64BitMode, HasEGPR, HasAMXTRANSPOSE]
t2rpntlvwz1 {src, dst|dst, src}
T2RPNTLVWZ0RST1_EVEX [In64BitMode, HasEGPR, HasAMXTRANSPOSE, HasAMXMOVRS]
t2rpntlvwz0rst1 {src, dst|dst, src}
T2RPNTLVWZ0RS_EVEX [In64BitMode, HasEGPR, HasAMXTRANSPOSE, HasAMXMOVRS]
t2rpntlvwz0rs {src, dst|dst, src}
T2RPNTLVWZ1RST1_EVEX [In64BitMode, HasEGPR, HasAMXTRANSPOSE, HasAMXMOVRS]
t2rpntlvwz1rst1 {src, dst|dst, src}
T2RPNTLVWZ1RS_EVEX [In64BitMode, HasEGPR, HasAMXTRANSPOSE, HasAMXMOVRS]
t2rpntlvwz1rs {src, dst|dst, src}
CRC32r32m16_EVEX [In64BitMode, HasEGPR, HasCRC32]
crc32{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
CRC32r32m32_EVEX [In64BitMode, HasEGPR, HasCRC32]
crc32{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
CRC32r32m8_EVEX [In64BitMode, HasEGPR, HasCRC32]
crc32{b} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
CRC32r32r16_EVEX [In64BitMode, HasEGPR, HasCRC32]
crc32{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
CRC32r32r32_EVEX [In64BitMode, HasEGPR, HasCRC32]
crc32{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
CRC32r32r8_EVEX [In64BitMode, HasEGPR, HasCRC32]
crc32{b} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
CRC32r64m64_EVEX [In64BitMode, HasEGPR, HasCRC32]
crc32{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
CRC32r64m8_EVEX [In64BitMode, HasEGPR, HasCRC32]
crc32{b} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
CRC32r64r64_EVEX [In64BitMode, HasEGPR, HasCRC32]
crc32{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
CRC32r64r8_EVEX [In64BitMode, HasEGPR, HasCRC32]
crc32{b} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
AADD32mr_EVEX [In64BitMode, HasEGPR, HasRAOINT]
aadd{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
AADD64mr_EVEX [In64BitMode, HasEGPR, HasRAOINT]
aadd{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
AAND32mr_EVEX [In64BitMode, HasEGPR, HasRAOINT]
aand{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
AAND64mr_EVEX [In64BitMode, HasEGPR, HasRAOINT]
aand{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
AOR32mr_EVEX [In64BitMode, HasEGPR, HasRAOINT]
aor{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
AOR64mr_EVEX [In64BitMode, HasEGPR, HasRAOINT]
aor{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
AXOR32mr_EVEX [In64BitMode, HasEGPR, HasRAOINT]
axor{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
AXOR64mr_EVEX [In64BitMode, HasEGPR, HasRAOINT]
axor{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
MOVBE16mr_EVEX [In64BitMode, HasEGPR, HasMOVBE]
movbe{w} {src1, dst|dst, src1}
MOVBE16rm_EVEX [In64BitMode, HasEGPR, HasMOVBE]
movbe{w} {src1, dst|dst, src1}
MOVBE32mr_EVEX [In64BitMode, HasEGPR, HasMOVBE]
movbe{l} {src1, dst|dst, src1}
MOVBE32rm_EVEX [In64BitMode, HasEGPR, HasMOVBE]
movbe{l} {src1, dst|dst, src1}
MOVBE64mr_EVEX [In64BitMode, HasEGPR, HasMOVBE]
movbe{q} {src1, dst|dst, src1}
MOVBE64rm_EVEX [In64BitMode, HasEGPR, HasMOVBE]
movbe{q} {src1, dst|dst, src1}
LDTILECFG_EVEX [In64BitMode, HasEGPR, HasAMXTILE]
ldtilecfg src
|
Note
|
Properties: hasSideEffects |
RDMSRri_EVEX [In64BitMode, HasEGPR, HasUSERMSR]
rdmsr {imm, dst|dst, imm}
|
Note
|
Properties: mayLoad |
STTILECFG_EVEX [In64BitMode, HasEGPR, HasAMXTILE]
sttilecfg src
|
Note
|
Properties: hasSideEffects |
TILELOADDRST1_EVEX [In64BitMode, HasEGPR, HasAMXMOVRS]
tileloaddrst1 {src1, dst|dst, src1}
TILELOADDRS_EVEX [In64BitMode, HasEGPR, HasAMXMOVRS]
tileloaddrs {src1, dst|dst, src1}
TILELOADDT1_EVEX [In64BitMode, HasEGPR, HasAMXTILE]
tileloaddt1 {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
TILELOADD_EVEX [In64BitMode, HasEGPR, HasAMXTILE]
tileloadd {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
TILESTORED_EVEX [In64BitMode, HasEGPR, HasAMXTILE]
tilestored {src, dst|dst, src}
|
Note
|
Properties: mayStore |
URDMSRri_EVEX [In64BitMode, HasEGPR, HasUSERMSR]
urdmsr {imm, dst|dst, imm}
|
Note
|
Properties: mayLoad |
URDMSRrr_EVEX [In64BitMode, HasEGPR, HasUSERMSR]
urdmsr {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
UWRMSRir_EVEX [In64BitMode, HasEGPR, HasUSERMSR]
uwrmsr {src, imm|imm, src}
|
Note
|
Properties: mayStore |
UWRMSRrr_EVEX [In64BitMode, HasEGPR, HasUSERMSR]
uwrmsr {src2, src1|src1, src2}
|
Note
|
Properties: mayStore |
WRMSRNSir_EVEX [In64BitMode, HasEGPR, HasUSERMSR]
wrmsrns {src, imm|imm, src}
|
Note
|
Properties: mayStore |
ENQCMD32_EVEX [In64BitMode, HasEGPR, HasENQCMD]
enqcmd {src, dst|dst, src}
ENQCMD64_EVEX [In64BitMode, HasEGPR, HasENQCMD]
enqcmd {src, dst|dst, src}
ENQCMDS32_EVEX [In64BitMode, HasEGPR, HasENQCMD]
enqcmds {src, dst|dst, src}
ENQCMDS64_EVEX [In64BitMode, HasEGPR, HasENQCMD]
enqcmds {src, dst|dst, src}
MOVDIR64B32_EVEX [In64BitMode, HasEGPR, HasMOVDIR64B]
movdir64b {src, dst|dst, src}
MOVDIR64B64_EVEX [In64BitMode, HasEGPR, HasMOVDIR64B]
movdir64b {src, dst|dst, src}
MOVDIRI32_EVEX [In64BitMode, HasEGPR, HasMOVDIRI]
movdiri {src, dst|dst, src}
MOVDIRI64_EVEX [In64BitMode, HasEGPR, HasMOVDIRI]
movdiri {src, dst|dst, src}
MOVRS16rm [In64BitMode, NoEGPR, HasMOVRS]
movrs{w} {src, dst|dst, src}
MOVRS32rm [In64BitMode, NoEGPR, HasMOVRS]
movrs{l} {src, dst|dst, src}
MOVRS64rm [In64BitMode, NoEGPR, HasMOVRS]
movrs{q} {src, dst|dst, src}
MOVRS8rm [In64BitMode, NoEGPR, HasMOVRS]
movrs{b} {src, dst|dst, src}
LDTILECFG [In64BitMode, NoEGPR, HasAMXTILE]
ldtilecfg src
|
Note
|
Properties: hasSideEffects |
STTILECFG [In64BitMode, NoEGPR, HasAMXTILE]
sttilecfg src
|
Note
|
Properties: hasSideEffects |
TILELOADD [In64BitMode, NoEGPR, HasAMXTILE]
tileloadd {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
TILELOADDT1 [In64BitMode, NoEGPR, HasAMXTILE]
tileloaddt1 {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
TILESTORED [In64BitMode, NoEGPR, HasAMXTILE]
tilestored {src, dst|dst, src}
|
Note
|
Properties: mayStore |
MOVDIR64B64 [In64BitMode, NoEGPR, HasMOVDIR64B]
movdir64b {src, dst|dst, src}
MOVDIRI64 [In64BitMode, NoEGPR, HasMOVDIRI]
movdiri {src, dst|dst, src}
T2RPNTLVWZ0 [In64BitMode, HasAMXTRANSPOSE]
t2rpntlvwz0 {src, dst|dst, src}
T2RPNTLVWZ0T1 [In64BitMode, HasAMXTRANSPOSE]
t2rpntlvwz0t1 {src, dst|dst, src}
T2RPNTLVWZ1 [In64BitMode, HasAMXTRANSPOSE]
t2rpntlvwz1 {src, dst|dst, src}
T2RPNTLVWZ1T1 [In64BitMode, HasAMXTRANSPOSE]
t2rpntlvwz1t1 {src, dst|dst, src}
TTRANSPOSED [In64BitMode, HasAMXTRANSPOSE]
ttransposed {src, dst|dst, src}
T2RPNTLVWZ0RS [In64BitMode, HasAMXTRANSPOSE, HasAMXMOVRS]
t2rpntlvwz0rs {src, dst|dst, src}
T2RPNTLVWZ0RST1 [In64BitMode, HasAMXTRANSPOSE, HasAMXMOVRS]
t2rpntlvwz0rst1 {src, dst|dst, src}
T2RPNTLVWZ1RS [In64BitMode, HasAMXTRANSPOSE, HasAMXMOVRS]
t2rpntlvwz1rs {src, dst|dst, src}
T2RPNTLVWZ1RST1 [In64BitMode, HasAMXTRANSPOSE, HasAMXMOVRS]
t2rpntlvwz1rst1 {src, dst|dst, src}
TCONJTCMMIMFP16PS [In64BitMode, HasAMXTRANSPOSE, HasAMXCOMPLEX]
tconjtcmmimfp16ps {src3, src2, src1|src1, src2, src3}
|
Note
|
Constraints: src1 = dst |
TCONJTFP16 [In64BitMode, HasAMXTRANSPOSE, HasAMXCOMPLEX]
tconjtfp16 {src, dst|dst, src}
TTCMMIMFP16PS [In64BitMode, HasAMXTRANSPOSE, HasAMXCOMPLEX]
ttcmmimfp16ps {src3, src2, src1|src1, src2, src3}
|
Note
|
Constraints: src1 = dst |
TTCMMRLFP16PS [In64BitMode, HasAMXTRANSPOSE, HasAMXCOMPLEX]
ttcmmrlfp16ps {src3, src2, src1|src1, src2, src3}
|
Note
|
Constraints: src1 = dst |
TTDPBF16PS [In64BitMode, HasAMXTRANSPOSE, HasAMXBF16]
ttdpbf16ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
TTDPFP16PS [In64BitMode, HasAMXTRANSPOSE, HasAMXFP16]
ttdpfp16ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
TTMMULTF32PS [In64BitMode, HasAMXTRANSPOSE, HasAMXTF32]
ttmmultf32ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
DEC64m [In64BitMode, UseIncDec]
dec{q} src1
|
Note
|
Properties: mayLoad, mayStore |
INC64m [In64BitMode, UseIncDec]
inc{q} src1
|
Note
|
Properties: mayLoad, mayStore |
TILELOADDRS [In64BitMode, HasAMXMOVRS]
tileloaddrs {src1, dst|dst, src1}
TILELOADDRST1 [In64BitMode, HasAMXMOVRS]
tileloaddrst1 {src1, dst|dst, src1}
TILERELEASE [In64BitMode, HasAMXTILE]
tilerelease
TILEZERO [In64BitMode, HasAMXTILE]
tilezero dst
RDFSBASE [In64BitMode, HasFSGSBase]
rdfsbase{l} dst
RDFSBASE64 [In64BitMode, HasFSGSBase]
rdfsbase{q} dst
RDGSBASE [In64BitMode, HasFSGSBase]
rdgsbase{l} dst
RDGSBASE64 [In64BitMode, HasFSGSBase]
rdgsbase{q} dst
WRFSBASE [In64BitMode, HasFSGSBase]
wrfsbase{l} src
WRFSBASE64 [In64BitMode, HasFSGSBase]
wrfsbase{q} src
WRGSBASE [In64BitMode, HasFSGSBase]
wrgsbase{l} src
WRGSBASE64 [In64BitMode, HasFSGSBase]
wrgsbase{q} src
TCMMIMFP16PS [In64BitMode, HasAMXCOMPLEX]
tcmmimfp16ps {src3, src2, src1|src1, src2, src3}
|
Note
|
Constraints: src1 = dst |
TCMMRLFP16PS [In64BitMode, HasAMXCOMPLEX]
tcmmrlfp16ps {src3, src2, src1|src1, src2, src3}
|
Note
|
Constraints: src1 = dst |
CLUI [In64BitMode, HasUINTR]
clui
SENDUIPI [In64BitMode, HasUINTR]
senduipi arg
STUI [In64BitMode, HasUINTR]
stui
TESTUI [In64BitMode, HasUINTR]
testui
UIRET [In64BitMode, HasUINTR]
uiret
UMONITOR64 [In64BitMode, HasWAITPKG]
umonitor src
XRSTOR64 [In64BitMode, HasXSAVE]
xrstor64 dst
XSAVE64 [In64BitMode, HasXSAVE]
xsave64 dst
XSAVES64 [In64BitMode, HasXSAVE]
xsaves64 dst
FXRSTOR64 [In64BitMode, HasFXSR]
fxrstor64 src
FXSAVE64 [In64BitMode, HasFXSR]
fxsave64 dst
PTWRITE64m [In64BitMode, HasPTWRITE]
ptwrite{q} dst
PTWRITE64r [In64BitMode, HasPTWRITE]
ptwrite{q} dst
TDPBF8PS [In64BitMode, HasAMXFP8]
tdpbf8ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
TDPBHF8PS [In64BitMode, HasAMXFP8]
tdpbhf8ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
TDPBSSD [In64BitMode, HasAMXINT8]
tdpbssd {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
TDPBSUD [In64BitMode, HasAMXINT8]
tdpbsud {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
TDPBUSD [In64BitMode, HasAMXINT8]
tdpbusd {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
TDPBUUD [In64BitMode, HasAMXINT8]
tdpbuud {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
TDPHBF8PS [In64BitMode, HasAMXFP8]
tdphbf8ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
TDPHF8PS [In64BitMode, HasAMXFP8]
tdphf8ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
CALL64m [In64BitMode, NotUseIndirectThunkCalls, FavorMemIndirectCall]
call{q} {*}dst
|
Note
|
Properties: isCall |
CALL64r [In64BitMode, NotUseIndirectThunkCalls, ImportCallOptimizationDisabled]
call{q} {*}dst
|
Note
|
Properties: isCall |
MONITOR64rrr [In64BitMode, HasSSE3]
monitor
MONITORX64rrr [In64BitMode, HasMWAITX]
monitorx
XRSTORS64 [In64BitMode, HasXSAVES]
xrstors64 dst
CLZERO64r [In64BitMode, HasCLZERO]
clzero
PREFETCHIT0 [In64BitMode, HasPREFETCHI]
prefetchit0 src
PREFETCHIT1 [In64BitMode, HasPREFETCHI]
prefetchit1 src
RDPID64 [In64BitMode, HasRDPID]
rdpid dst
TDPBF16PS [In64BitMode, HasAMXBF16]
tdpbf16ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
TDPFP16PS [In64BitMode, HasAMXFP16]
tdpfp16ps {src3, src2, src1|src1, src2, src3}
|
Note
|
Constraints: src1 = dst |
TMMULTF32PS [In64BitMode, HasAMXTF32]
tmmultf32ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
XSAVEC64 [In64BitMode, HasXSAVEC]
xsavec64 dst
XSAVEOPT64 [In64BitMode, HasXSAVEOPT]
xsaveopt64 dst
CMPXCHG16B [In64BitMode, HasCX16]
cmpxchg16b dst
|
Note
|
Properties: mayLoad, mayStore |
VADDBF16Z128rm [HasAVX10_2]
vaddbf16 {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VADDBF16Z128rmb [HasAVX10_2]
vaddbf16 {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
VADDBF16Z128rmbk [HasAVX10_2]
vaddbf16 {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VADDBF16Z128rmbkz [HasAVX10_2]
vaddbf16 {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
VADDBF16Z128rmk [HasAVX10_2]
vaddbf16 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VADDBF16Z128rmkz [HasAVX10_2]
vaddbf16 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VADDBF16Z128rr [HasAVX10_2]
vaddbf16 {src2, src1, dst|dst, src1, src2}
VADDBF16Z128rrk [HasAVX10_2]
vaddbf16 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VADDBF16Z128rrkz [HasAVX10_2]
vaddbf16 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VADDBF16Z256rm [HasAVX10_2]
vaddbf16 {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VADDBF16Z256rmb [HasAVX10_2]
vaddbf16 {src2{1to16}, src1, dst|dst, src1, src2{1to16}}
|
Note
|
Properties: mayLoad |
VADDBF16Z256rmbk [HasAVX10_2]
vaddbf16 {src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VADDBF16Z256rmbkz [HasAVX10_2]
vaddbf16 {src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}}
|
Note
|
Properties: mayLoad |
VADDBF16Z256rmk [HasAVX10_2]
vaddbf16 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VADDBF16Z256rmkz [HasAVX10_2]
vaddbf16 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VADDBF16Z256rr [HasAVX10_2]
vaddbf16 {src2, src1, dst|dst, src1, src2}
VADDBF16Z256rrk [HasAVX10_2]
vaddbf16 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VADDBF16Z256rrkz [HasAVX10_2]
vaddbf16 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VCMPBF16Z128rmbi [HasAVX10_2]
vcmpbf16 {cc, src2{1to8}, src1, dst|dst, src1, src2{1to8}, cc}
VCMPBF16Z128rmbik [HasAVX10_2]
vcmpbf16 {cc, src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}, cc}
VCMPBF16Z128rmi [HasAVX10_2]
vcmpbf16 {cc, src2, src1, dst|dst, src1, src2, cc}
VCMPBF16Z128rmik [HasAVX10_2]
vcmpbf16 {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
VCMPBF16Z128rri [HasAVX10_2]
vcmpbf16 {cc, src2, src1, dst|dst, src1, src2, cc}
VCMPBF16Z128rrik [HasAVX10_2]
vcmpbf16 {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
VCMPBF16Z256rmbi [HasAVX10_2]
vcmpbf16 {cc, src2{1to16}, src1, dst|dst, src1, src2{1to16}, cc}
VCMPBF16Z256rmbik [HasAVX10_2]
vcmpbf16 {cc, src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}, cc}
VCMPBF16Z256rmi [HasAVX10_2]
vcmpbf16 {cc, src2, src1, dst|dst, src1, src2, cc}
VCMPBF16Z256rmik [HasAVX10_2]
vcmpbf16 {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
VCMPBF16Z256rri [HasAVX10_2]
vcmpbf16 {cc, src2, src1, dst|dst, src1, src2, cc}
VCMPBF16Z256rrik [HasAVX10_2]
vcmpbf16 {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
VCOMISBF16Zrm [HasAVX10_2]
vcomisbf16 {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
VCOMISBF16Zrr [HasAVX10_2]
vcomisbf16 {src2, src1|src1, src2}
VCOMXSDZrm_Int [HasAVX10_2]
vcomxsd {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VCOMXSDZrr_Int [HasAVX10_2]
vcomxsd {src2, src1|src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VCOMXSDZrrb_Int [HasAVX10_2]
vcomxsd {{sae}, src2, src1|src1, src2, {sae}}
|
Note
|
Properties: mayRaiseFPException |
VCOMXSHZrm_Int [HasAVX10_2]
vcomxsh {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VCOMXSHZrr_Int [HasAVX10_2]
vcomxsh {src2, src1|src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VCOMXSHZrrb_Int [HasAVX10_2]
vcomxsh {{sae}, src2, src1|src1, src2, {sae}}
|
Note
|
Properties: mayRaiseFPException |
VCOMXSSZrm_Int [HasAVX10_2]
vcomxss {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VCOMXSSZrr_Int [HasAVX10_2]
vcomxss {src2, src1|src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VCOMXSSZrrb_Int [HasAVX10_2]
vcomxss {{sae}, src2, src1|src1, src2, {sae}}
|
Note
|
Properties: mayRaiseFPException |
VCVT2PH2BF8SZ128rm [HasAVX10_2]
vcvt2ph2bf8s {src2, src1, dst|dst, src1, src2}
VCVT2PH2BF8SZ128rmb [HasAVX10_2]
vcvt2ph2bf8s {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
VCVT2PH2BF8SZ128rmbk [HasAVX10_2]
vcvt2ph2bf8s {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Constraints: src0 = dst |
VCVT2PH2BF8SZ128rmbkz [HasAVX10_2]
vcvt2ph2bf8s {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
VCVT2PH2BF8SZ128rmk [HasAVX10_2]
vcvt2ph2bf8s {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VCVT2PH2BF8SZ128rmkz [HasAVX10_2]
vcvt2ph2bf8s {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VCVT2PH2BF8SZ128rr [HasAVX10_2]
vcvt2ph2bf8s {src2, src1, dst|dst, src1, src2}
VCVT2PH2BF8SZ128rrk [HasAVX10_2]
vcvt2ph2bf8s {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VCVT2PH2BF8SZ128rrkz [HasAVX10_2]
vcvt2ph2bf8s {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VCVT2PH2BF8SZ256rm [HasAVX10_2]
vcvt2ph2bf8s {src2, src1, dst|dst, src1, src2}
VCVT2PH2BF8SZ256rmb [HasAVX10_2]
vcvt2ph2bf8s {src2{1to16}, src1, dst|dst, src1, src2{1to16}}
VCVT2PH2BF8SZ256rmbk [HasAVX10_2]
vcvt2ph2bf8s {src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}}
|
Note
|
Constraints: src0 = dst |
VCVT2PH2BF8SZ256rmbkz [HasAVX10_2]
vcvt2ph2bf8s {src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}}
VCVT2PH2BF8SZ256rmk [HasAVX10_2]
vcvt2ph2bf8s {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VCVT2PH2BF8SZ256rmkz [HasAVX10_2]
vcvt2ph2bf8s {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VCVT2PH2BF8SZ256rr [HasAVX10_2]
vcvt2ph2bf8s {src2, src1, dst|dst, src1, src2}
VCVT2PH2BF8SZ256rrk [HasAVX10_2]
vcvt2ph2bf8s {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VCVT2PH2BF8SZ256rrkz [HasAVX10_2]
vcvt2ph2bf8s {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VCVT2PH2BF8Z128rm [HasAVX10_2]
vcvt2ph2bf8 {src2, src1, dst|dst, src1, src2}
VCVT2PH2BF8Z128rmb [HasAVX10_2]
vcvt2ph2bf8 {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
VCVT2PH2BF8Z128rmbk [HasAVX10_2]
vcvt2ph2bf8 {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Constraints: src0 = dst |
VCVT2PH2BF8Z128rmbkz [HasAVX10_2]
vcvt2ph2bf8 {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
VCVT2PH2BF8Z128rmk [HasAVX10_2]
vcvt2ph2bf8 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VCVT2PH2BF8Z128rmkz [HasAVX10_2]
vcvt2ph2bf8 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VCVT2PH2BF8Z128rr [HasAVX10_2]
vcvt2ph2bf8 {src2, src1, dst|dst, src1, src2}
VCVT2PH2BF8Z128rrk [HasAVX10_2]
vcvt2ph2bf8 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VCVT2PH2BF8Z128rrkz [HasAVX10_2]
vcvt2ph2bf8 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VCVT2PH2BF8Z256rm [HasAVX10_2]
vcvt2ph2bf8 {src2, src1, dst|dst, src1, src2}
VCVT2PH2BF8Z256rmb [HasAVX10_2]
vcvt2ph2bf8 {src2{1to16}, src1, dst|dst, src1, src2{1to16}}
VCVT2PH2BF8Z256rmbk [HasAVX10_2]
vcvt2ph2bf8 {src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}}
|
Note
|
Constraints: src0 = dst |
VCVT2PH2BF8Z256rmbkz [HasAVX10_2]
vcvt2ph2bf8 {src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}}
VCVT2PH2BF8Z256rmk [HasAVX10_2]
vcvt2ph2bf8 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VCVT2PH2BF8Z256rmkz [HasAVX10_2]
vcvt2ph2bf8 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VCVT2PH2BF8Z256rr [HasAVX10_2]
vcvt2ph2bf8 {src2, src1, dst|dst, src1, src2}
VCVT2PH2BF8Z256rrk [HasAVX10_2]
vcvt2ph2bf8 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VCVT2PH2BF8Z256rrkz [HasAVX10_2]
vcvt2ph2bf8 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VCVT2PH2HF8SZ128rm [HasAVX10_2]
vcvt2ph2hf8s {src2, src1, dst|dst, src1, src2}
VCVT2PH2HF8SZ128rmb [HasAVX10_2]
vcvt2ph2hf8s {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
VCVT2PH2HF8SZ128rmbk [HasAVX10_2]
vcvt2ph2hf8s {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Constraints: src0 = dst |
VCVT2PH2HF8SZ128rmbkz [HasAVX10_2]
vcvt2ph2hf8s {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
VCVT2PH2HF8SZ128rmk [HasAVX10_2]
vcvt2ph2hf8s {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VCVT2PH2HF8SZ128rmkz [HasAVX10_2]
vcvt2ph2hf8s {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VCVT2PH2HF8SZ128rr [HasAVX10_2]
vcvt2ph2hf8s {src2, src1, dst|dst, src1, src2}
VCVT2PH2HF8SZ128rrk [HasAVX10_2]
vcvt2ph2hf8s {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VCVT2PH2HF8SZ128rrkz [HasAVX10_2]
vcvt2ph2hf8s {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VCVT2PH2HF8SZ256rm [HasAVX10_2]
vcvt2ph2hf8s {src2, src1, dst|dst, src1, src2}
VCVT2PH2HF8SZ256rmb [HasAVX10_2]
vcvt2ph2hf8s {src2{1to16}, src1, dst|dst, src1, src2{1to16}}
VCVT2PH2HF8SZ256rmbk [HasAVX10_2]
vcvt2ph2hf8s {src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}}
|
Note
|
Constraints: src0 = dst |
VCVT2PH2HF8SZ256rmbkz [HasAVX10_2]
vcvt2ph2hf8s {src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}}
VCVT2PH2HF8SZ256rmk [HasAVX10_2]
vcvt2ph2hf8s {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VCVT2PH2HF8SZ256rmkz [HasAVX10_2]
vcvt2ph2hf8s {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VCVT2PH2HF8SZ256rr [HasAVX10_2]
vcvt2ph2hf8s {src2, src1, dst|dst, src1, src2}
VCVT2PH2HF8SZ256rrk [HasAVX10_2]
vcvt2ph2hf8s {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VCVT2PH2HF8SZ256rrkz [HasAVX10_2]
vcvt2ph2hf8s {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VCVT2PH2HF8Z128rm [HasAVX10_2]
vcvt2ph2hf8 {src2, src1, dst|dst, src1, src2}
VCVT2PH2HF8Z128rmb [HasAVX10_2]
vcvt2ph2hf8 {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
VCVT2PH2HF8Z128rmbk [HasAVX10_2]
vcvt2ph2hf8 {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Constraints: src0 = dst |
VCVT2PH2HF8Z128rmbkz [HasAVX10_2]
vcvt2ph2hf8 {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
VCVT2PH2HF8Z128rmk [HasAVX10_2]
vcvt2ph2hf8 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VCVT2PH2HF8Z128rmkz [HasAVX10_2]
vcvt2ph2hf8 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VCVT2PH2HF8Z128rr [HasAVX10_2]
vcvt2ph2hf8 {src2, src1, dst|dst, src1, src2}
VCVT2PH2HF8Z128rrk [HasAVX10_2]
vcvt2ph2hf8 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VCVT2PH2HF8Z128rrkz [HasAVX10_2]
vcvt2ph2hf8 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VCVT2PH2HF8Z256rm [HasAVX10_2]
vcvt2ph2hf8 {src2, src1, dst|dst, src1, src2}
VCVT2PH2HF8Z256rmb [HasAVX10_2]
vcvt2ph2hf8 {src2{1to16}, src1, dst|dst, src1, src2{1to16}}
VCVT2PH2HF8Z256rmbk [HasAVX10_2]
vcvt2ph2hf8 {src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}}
|
Note
|
Constraints: src0 = dst |
VCVT2PH2HF8Z256rmbkz [HasAVX10_2]
vcvt2ph2hf8 {src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}}
VCVT2PH2HF8Z256rmk [HasAVX10_2]
vcvt2ph2hf8 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VCVT2PH2HF8Z256rmkz [HasAVX10_2]
vcvt2ph2hf8 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VCVT2PH2HF8Z256rr [HasAVX10_2]
vcvt2ph2hf8 {src2, src1, dst|dst, src1, src2}
VCVT2PH2HF8Z256rrk [HasAVX10_2]
vcvt2ph2hf8 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VCVT2PH2HF8Z256rrkz [HasAVX10_2]
vcvt2ph2hf8 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VCVT2PS2PHXZ128rm [HasAVX10_2]
vcvt2ps2phx {src2, src1, dst|dst, src1, src2}
VCVT2PS2PHXZ128rmb [HasAVX10_2]
vcvt2ps2phx {src2{1to4}, src1, dst|dst, src1, src2{1to4}}
VCVT2PS2PHXZ128rmbk [HasAVX10_2]
vcvt2ps2phx {src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}}
|
Note
|
Constraints: src0 = dst |
VCVT2PS2PHXZ128rmbkz [HasAVX10_2]
vcvt2ps2phx {src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}}
VCVT2PS2PHXZ128rmk [HasAVX10_2]
vcvt2ps2phx {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VCVT2PS2PHXZ128rmkz [HasAVX10_2]
vcvt2ps2phx {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VCVT2PS2PHXZ128rr [HasAVX10_2]
vcvt2ps2phx {src2, src1, dst|dst, src1, src2}
VCVT2PS2PHXZ128rrk [HasAVX10_2]
vcvt2ps2phx {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VCVT2PS2PHXZ128rrkz [HasAVX10_2]
vcvt2ps2phx {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VCVT2PS2PHXZ256rm [HasAVX10_2]
vcvt2ps2phx {src2, src1, dst|dst, src1, src2}
VCVT2PS2PHXZ256rmb [HasAVX10_2]
vcvt2ps2phx {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
VCVT2PS2PHXZ256rmbk [HasAVX10_2]
vcvt2ps2phx {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Constraints: src0 = dst |
VCVT2PS2PHXZ256rmbkz [HasAVX10_2]
vcvt2ps2phx {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
VCVT2PS2PHXZ256rmk [HasAVX10_2]
vcvt2ps2phx {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VCVT2PS2PHXZ256rmkz [HasAVX10_2]
vcvt2ps2phx {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VCVT2PS2PHXZ256rr [HasAVX10_2]
vcvt2ps2phx {src2, src1, dst|dst, src1, src2}
VCVT2PS2PHXZ256rrk [HasAVX10_2]
vcvt2ps2phx {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VCVT2PS2PHXZ256rrkz [HasAVX10_2]
vcvt2ps2phx {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VCVTBF162IBSZ128rm [HasAVX10_2]
vcvtbf162ibs {src, dst|dst, src}
VCVTBF162IBSZ128rmb [HasAVX10_2]
vcvtbf162ibs {src{1to8}, dst|dst, src{1to8}}
VCVTBF162IBSZ128rmbk [HasAVX10_2]
vcvtbf162ibs {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Constraints: src0 = dst |
VCVTBF162IBSZ128rmbkz [HasAVX10_2]
vcvtbf162ibs {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
VCVTBF162IBSZ128rmk [HasAVX10_2]
vcvtbf162ibs {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTBF162IBSZ128rmkz [HasAVX10_2]
vcvtbf162ibs {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTBF162IBSZ128rr [HasAVX10_2]
vcvtbf162ibs {src, dst|dst, src}
VCVTBF162IBSZ128rrk [HasAVX10_2]
vcvtbf162ibs {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTBF162IBSZ128rrkz [HasAVX10_2]
vcvtbf162ibs {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTBF162IBSZ256rm [HasAVX10_2]
vcvtbf162ibs {src, dst|dst, src}
VCVTBF162IBSZ256rmb [HasAVX10_2]
vcvtbf162ibs {src{1to16}, dst|dst, src{1to16}}
VCVTBF162IBSZ256rmbk [HasAVX10_2]
vcvtbf162ibs {src{1to16}, dst {mask}|dst {mask}, src{1to16}}
|
Note
|
Constraints: src0 = dst |
VCVTBF162IBSZ256rmbkz [HasAVX10_2]
vcvtbf162ibs {src{1to16}, dst {mask} {z}|dst {mask} {z}, src{1to16}}
VCVTBF162IBSZ256rmk [HasAVX10_2]
vcvtbf162ibs {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTBF162IBSZ256rmkz [HasAVX10_2]
vcvtbf162ibs {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTBF162IBSZ256rr [HasAVX10_2]
vcvtbf162ibs {src, dst|dst, src}
VCVTBF162IBSZ256rrk [HasAVX10_2]
vcvtbf162ibs {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTBF162IBSZ256rrkz [HasAVX10_2]
vcvtbf162ibs {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTBF162IUBSZ128rm [HasAVX10_2]
vcvtbf162iubs {src, dst|dst, src}
VCVTBF162IUBSZ128rmb [HasAVX10_2]
vcvtbf162iubs {src{1to8}, dst|dst, src{1to8}}
VCVTBF162IUBSZ128rmbk [HasAVX10_2]
vcvtbf162iubs {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Constraints: src0 = dst |
VCVTBF162IUBSZ128rmbkz [HasAVX10_2]
vcvtbf162iubs {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
VCVTBF162IUBSZ128rmk [HasAVX10_2]
vcvtbf162iubs {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTBF162IUBSZ128rmkz [HasAVX10_2]
vcvtbf162iubs {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTBF162IUBSZ128rr [HasAVX10_2]
vcvtbf162iubs {src, dst|dst, src}
VCVTBF162IUBSZ128rrk [HasAVX10_2]
vcvtbf162iubs {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTBF162IUBSZ128rrkz [HasAVX10_2]
vcvtbf162iubs {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTBF162IUBSZ256rm [HasAVX10_2]
vcvtbf162iubs {src, dst|dst, src}
VCVTBF162IUBSZ256rmb [HasAVX10_2]
vcvtbf162iubs {src{1to16}, dst|dst, src{1to16}}
VCVTBF162IUBSZ256rmbk [HasAVX10_2]
vcvtbf162iubs {src{1to16}, dst {mask}|dst {mask}, src{1to16}}
|
Note
|
Constraints: src0 = dst |
VCVTBF162IUBSZ256rmbkz [HasAVX10_2]
vcvtbf162iubs {src{1to16}, dst {mask} {z}|dst {mask} {z}, src{1to16}}
VCVTBF162IUBSZ256rmk [HasAVX10_2]
vcvtbf162iubs {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTBF162IUBSZ256rmkz [HasAVX10_2]
vcvtbf162iubs {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTBF162IUBSZ256rr [HasAVX10_2]
vcvtbf162iubs {src, dst|dst, src}
VCVTBF162IUBSZ256rrk [HasAVX10_2]
vcvtbf162iubs {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTBF162IUBSZ256rrkz [HasAVX10_2]
vcvtbf162iubs {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTBIASPH2BF8SZ128rm [HasAVX10_2]
vcvtbiasph2bf8s {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VCVTBIASPH2BF8SZ128rmb [HasAVX10_2]
vcvtbiasph2bf8s {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
VCVTBIASPH2BF8SZ128rmbk [HasAVX10_2]
vcvtbiasph2bf8s {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VCVTBIASPH2BF8SZ128rmbkz [HasAVX10_2]
vcvtbiasph2bf8s {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
VCVTBIASPH2BF8SZ128rmk [HasAVX10_2]
vcvtbiasph2bf8s {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VCVTBIASPH2BF8SZ128rmkz [HasAVX10_2]
vcvtbiasph2bf8s {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VCVTBIASPH2BF8SZ128rr [HasAVX10_2]
vcvtbiasph2bf8s {src2, src1, dst|dst, src1, src2}
VCVTBIASPH2BF8SZ128rrk [HasAVX10_2]
vcvtbiasph2bf8s {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VCVTBIASPH2BF8SZ128rrkz [HasAVX10_2]
vcvtbiasph2bf8s {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VCVTBIASPH2BF8SZ256rm [HasAVX10_2]
vcvtbiasph2bf8s {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VCVTBIASPH2BF8SZ256rmb [HasAVX10_2]
vcvtbiasph2bf8s {src2{1to16}, src1, dst|dst, src1, src2{1to16}}
|
Note
|
Properties: mayLoad |
VCVTBIASPH2BF8SZ256rmbk [HasAVX10_2]
vcvtbiasph2bf8s {src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VCVTBIASPH2BF8SZ256rmbkz [HasAVX10_2]
vcvtbiasph2bf8s {src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}}
|
Note
|
Properties: mayLoad |
VCVTBIASPH2BF8SZ256rmk [HasAVX10_2]
vcvtbiasph2bf8s {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VCVTBIASPH2BF8SZ256rmkz [HasAVX10_2]
vcvtbiasph2bf8s {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VCVTBIASPH2BF8SZ256rr [HasAVX10_2]
vcvtbiasph2bf8s {src2, src1, dst|dst, src1, src2}
VCVTBIASPH2BF8SZ256rrk [HasAVX10_2]
vcvtbiasph2bf8s {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VCVTBIASPH2BF8SZ256rrkz [HasAVX10_2]
vcvtbiasph2bf8s {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VCVTBIASPH2BF8Z128rm [HasAVX10_2]
vcvtbiasph2bf8 {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VCVTBIASPH2BF8Z128rmb [HasAVX10_2]
vcvtbiasph2bf8 {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
VCVTBIASPH2BF8Z128rmbk [HasAVX10_2]
vcvtbiasph2bf8 {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VCVTBIASPH2BF8Z128rmbkz [HasAVX10_2]
vcvtbiasph2bf8 {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
VCVTBIASPH2BF8Z128rmk [HasAVX10_2]
vcvtbiasph2bf8 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VCVTBIASPH2BF8Z128rmkz [HasAVX10_2]
vcvtbiasph2bf8 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VCVTBIASPH2BF8Z128rr [HasAVX10_2]
vcvtbiasph2bf8 {src2, src1, dst|dst, src1, src2}
VCVTBIASPH2BF8Z128rrk [HasAVX10_2]
vcvtbiasph2bf8 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VCVTBIASPH2BF8Z128rrkz [HasAVX10_2]
vcvtbiasph2bf8 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VCVTBIASPH2BF8Z256rm [HasAVX10_2]
vcvtbiasph2bf8 {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VCVTBIASPH2BF8Z256rmb [HasAVX10_2]
vcvtbiasph2bf8 {src2{1to16}, src1, dst|dst, src1, src2{1to16}}
|
Note
|
Properties: mayLoad |
VCVTBIASPH2BF8Z256rmbk [HasAVX10_2]
vcvtbiasph2bf8 {src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VCVTBIASPH2BF8Z256rmbkz [HasAVX10_2]
vcvtbiasph2bf8 {src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}}
|
Note
|
Properties: mayLoad |
VCVTBIASPH2BF8Z256rmk [HasAVX10_2]
vcvtbiasph2bf8 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VCVTBIASPH2BF8Z256rmkz [HasAVX10_2]
vcvtbiasph2bf8 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VCVTBIASPH2BF8Z256rr [HasAVX10_2]
vcvtbiasph2bf8 {src2, src1, dst|dst, src1, src2}
VCVTBIASPH2BF8Z256rrk [HasAVX10_2]
vcvtbiasph2bf8 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VCVTBIASPH2BF8Z256rrkz [HasAVX10_2]
vcvtbiasph2bf8 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VCVTBIASPH2HF8SZ128rm [HasAVX10_2]
vcvtbiasph2hf8s {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VCVTBIASPH2HF8SZ128rmb [HasAVX10_2]
vcvtbiasph2hf8s {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
VCVTBIASPH2HF8SZ128rmbk [HasAVX10_2]
vcvtbiasph2hf8s {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VCVTBIASPH2HF8SZ128rmbkz [HasAVX10_2]
vcvtbiasph2hf8s {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
VCVTBIASPH2HF8SZ128rmk [HasAVX10_2]
vcvtbiasph2hf8s {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VCVTBIASPH2HF8SZ128rmkz [HasAVX10_2]
vcvtbiasph2hf8s {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VCVTBIASPH2HF8SZ128rr [HasAVX10_2]
vcvtbiasph2hf8s {src2, src1, dst|dst, src1, src2}
VCVTBIASPH2HF8SZ128rrk [HasAVX10_2]
vcvtbiasph2hf8s {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VCVTBIASPH2HF8SZ128rrkz [HasAVX10_2]
vcvtbiasph2hf8s {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VCVTBIASPH2HF8SZ256rm [HasAVX10_2]
vcvtbiasph2hf8s {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VCVTBIASPH2HF8SZ256rmb [HasAVX10_2]
vcvtbiasph2hf8s {src2{1to16}, src1, dst|dst, src1, src2{1to16}}
|
Note
|
Properties: mayLoad |
VCVTBIASPH2HF8SZ256rmbk [HasAVX10_2]
vcvtbiasph2hf8s {src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VCVTBIASPH2HF8SZ256rmbkz [HasAVX10_2]
vcvtbiasph2hf8s {src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}}
|
Note
|
Properties: mayLoad |
VCVTBIASPH2HF8SZ256rmk [HasAVX10_2]
vcvtbiasph2hf8s {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VCVTBIASPH2HF8SZ256rmkz [HasAVX10_2]
vcvtbiasph2hf8s {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VCVTBIASPH2HF8SZ256rr [HasAVX10_2]
vcvtbiasph2hf8s {src2, src1, dst|dst, src1, src2}
VCVTBIASPH2HF8SZ256rrk [HasAVX10_2]
vcvtbiasph2hf8s {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VCVTBIASPH2HF8SZ256rrkz [HasAVX10_2]
vcvtbiasph2hf8s {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VCVTBIASPH2HF8Z128rm [HasAVX10_2]
vcvtbiasph2hf8 {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VCVTBIASPH2HF8Z128rmb [HasAVX10_2]
vcvtbiasph2hf8 {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
VCVTBIASPH2HF8Z128rmbk [HasAVX10_2]
vcvtbiasph2hf8 {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VCVTBIASPH2HF8Z128rmbkz [HasAVX10_2]
vcvtbiasph2hf8 {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
VCVTBIASPH2HF8Z128rmk [HasAVX10_2]
vcvtbiasph2hf8 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VCVTBIASPH2HF8Z128rmkz [HasAVX10_2]
vcvtbiasph2hf8 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VCVTBIASPH2HF8Z128rr [HasAVX10_2]
vcvtbiasph2hf8 {src2, src1, dst|dst, src1, src2}
VCVTBIASPH2HF8Z128rrk [HasAVX10_2]
vcvtbiasph2hf8 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VCVTBIASPH2HF8Z128rrkz [HasAVX10_2]
vcvtbiasph2hf8 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VCVTBIASPH2HF8Z256rm [HasAVX10_2]
vcvtbiasph2hf8 {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VCVTBIASPH2HF8Z256rmb [HasAVX10_2]
vcvtbiasph2hf8 {src2{1to16}, src1, dst|dst, src1, src2{1to16}}
|
Note
|
Properties: mayLoad |
VCVTBIASPH2HF8Z256rmbk [HasAVX10_2]
vcvtbiasph2hf8 {src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VCVTBIASPH2HF8Z256rmbkz [HasAVX10_2]
vcvtbiasph2hf8 {src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}}
|
Note
|
Properties: mayLoad |
VCVTBIASPH2HF8Z256rmk [HasAVX10_2]
vcvtbiasph2hf8 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VCVTBIASPH2HF8Z256rmkz [HasAVX10_2]
vcvtbiasph2hf8 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VCVTBIASPH2HF8Z256rr [HasAVX10_2]
vcvtbiasph2hf8 {src2, src1, dst|dst, src1, src2}
VCVTBIASPH2HF8Z256rrk [HasAVX10_2]
vcvtbiasph2hf8 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VCVTBIASPH2HF8Z256rrkz [HasAVX10_2]
vcvtbiasph2hf8 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VCVTHF82PHZ128rm [HasAVX10_2]
vcvthf82ph {src, dst|dst, src}
VCVTHF82PHZ128rmk [HasAVX10_2]
vcvthf82ph {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTHF82PHZ128rmkz [HasAVX10_2]
vcvthf82ph {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTHF82PHZ128rr [HasAVX10_2]
vcvthf82ph {src, dst|dst, src}
VCVTHF82PHZ128rrk [HasAVX10_2]
vcvthf82ph {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTHF82PHZ128rrkz [HasAVX10_2]
vcvthf82ph {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTHF82PHZ256rm [HasAVX10_2]
vcvthf82ph {src, dst|dst, src}
VCVTHF82PHZ256rmk [HasAVX10_2]
vcvthf82ph {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTHF82PHZ256rmkz [HasAVX10_2]
vcvthf82ph {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTHF82PHZ256rr [HasAVX10_2]
vcvthf82ph {src, dst|dst, src}
VCVTHF82PHZ256rrk [HasAVX10_2]
vcvthf82ph {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTHF82PHZ256rrkz [HasAVX10_2]
vcvthf82ph {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTPH2BF8SZ128rm [HasAVX10_2]
vcvtph2bf8s{x} {src, dst|dst, src}
VCVTPH2BF8SZ128rmb [HasAVX10_2]
vcvtph2bf8s {src{1to8}, dst|dst, src{1to8}}
VCVTPH2BF8SZ128rmbk [HasAVX10_2]
vcvtph2bf8s {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Constraints: src0 = dst |
VCVTPH2BF8SZ128rmbkz [HasAVX10_2]
vcvtph2bf8s {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
VCVTPH2BF8SZ128rmk [HasAVX10_2]
vcvtph2bf8s{x} {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTPH2BF8SZ128rmkz [HasAVX10_2]
vcvtph2bf8s{x} {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTPH2BF8SZ128rr [HasAVX10_2]
vcvtph2bf8s {src, dst|dst, src}
VCVTPH2BF8SZ128rrk [HasAVX10_2]
vcvtph2bf8s {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTPH2BF8SZ128rrkz [HasAVX10_2]
vcvtph2bf8s {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTPH2BF8SZ256rm [HasAVX10_2]
vcvtph2bf8s{y} {src, dst|dst, src}
VCVTPH2BF8SZ256rmb [HasAVX10_2]
vcvtph2bf8s {src{1to16}, dst|dst, src{1to16}}
VCVTPH2BF8SZ256rmbk [HasAVX10_2]
vcvtph2bf8s {src{1to16}, dst {mask}|dst {mask}, src{1to16}}
|
Note
|
Constraints: src0 = dst |
VCVTPH2BF8SZ256rmbkz [HasAVX10_2]
vcvtph2bf8s {src{1to16}, dst {mask} {z}|dst {mask} {z}, src{1to16}}
VCVTPH2BF8SZ256rmk [HasAVX10_2]
vcvtph2bf8s{y} {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTPH2BF8SZ256rmkz [HasAVX10_2]
vcvtph2bf8s{y} {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTPH2BF8SZ256rr [HasAVX10_2]
vcvtph2bf8s {src, dst|dst, src}
VCVTPH2BF8SZ256rrk [HasAVX10_2]
vcvtph2bf8s {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTPH2BF8SZ256rrkz [HasAVX10_2]
vcvtph2bf8s {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTPH2BF8Z128rm [HasAVX10_2]
vcvtph2bf8{x} {src, dst|dst, src}
VCVTPH2BF8Z128rmb [HasAVX10_2]
vcvtph2bf8 {src{1to8}, dst|dst, src{1to8}}
VCVTPH2BF8Z128rmbk [HasAVX10_2]
vcvtph2bf8 {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Constraints: src0 = dst |
VCVTPH2BF8Z128rmbkz [HasAVX10_2]
vcvtph2bf8 {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
VCVTPH2BF8Z128rmk [HasAVX10_2]
vcvtph2bf8{x} {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTPH2BF8Z128rmkz [HasAVX10_2]
vcvtph2bf8{x} {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTPH2BF8Z128rr [HasAVX10_2]
vcvtph2bf8 {src, dst|dst, src}
VCVTPH2BF8Z128rrk [HasAVX10_2]
vcvtph2bf8 {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTPH2BF8Z128rrkz [HasAVX10_2]
vcvtph2bf8 {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTPH2BF8Z256rm [HasAVX10_2]
vcvtph2bf8{y} {src, dst|dst, src}
VCVTPH2BF8Z256rmb [HasAVX10_2]
vcvtph2bf8 {src{1to16}, dst|dst, src{1to16}}
VCVTPH2BF8Z256rmbk [HasAVX10_2]
vcvtph2bf8 {src{1to16}, dst {mask}|dst {mask}, src{1to16}}
|
Note
|
Constraints: src0 = dst |
VCVTPH2BF8Z256rmbkz [HasAVX10_2]
vcvtph2bf8 {src{1to16}, dst {mask} {z}|dst {mask} {z}, src{1to16}}
VCVTPH2BF8Z256rmk [HasAVX10_2]
vcvtph2bf8{y} {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTPH2BF8Z256rmkz [HasAVX10_2]
vcvtph2bf8{y} {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTPH2BF8Z256rr [HasAVX10_2]
vcvtph2bf8 {src, dst|dst, src}
VCVTPH2BF8Z256rrk [HasAVX10_2]
vcvtph2bf8 {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTPH2BF8Z256rrkz [HasAVX10_2]
vcvtph2bf8 {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTPH2HF8SZ128rm [HasAVX10_2]
vcvtph2hf8s{x} {src, dst|dst, src}
VCVTPH2HF8SZ128rmb [HasAVX10_2]
vcvtph2hf8s {src{1to8}, dst|dst, src{1to8}}
VCVTPH2HF8SZ128rmbk [HasAVX10_2]
vcvtph2hf8s {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Constraints: src0 = dst |
VCVTPH2HF8SZ128rmbkz [HasAVX10_2]
vcvtph2hf8s {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
VCVTPH2HF8SZ128rmk [HasAVX10_2]
vcvtph2hf8s{x} {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTPH2HF8SZ128rmkz [HasAVX10_2]
vcvtph2hf8s{x} {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTPH2HF8SZ128rr [HasAVX10_2]
vcvtph2hf8s {src, dst|dst, src}
VCVTPH2HF8SZ128rrk [HasAVX10_2]
vcvtph2hf8s {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTPH2HF8SZ128rrkz [HasAVX10_2]
vcvtph2hf8s {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTPH2HF8SZ256rm [HasAVX10_2]
vcvtph2hf8s{y} {src, dst|dst, src}
VCVTPH2HF8SZ256rmb [HasAVX10_2]
vcvtph2hf8s {src{1to16}, dst|dst, src{1to16}}
VCVTPH2HF8SZ256rmbk [HasAVX10_2]
vcvtph2hf8s {src{1to16}, dst {mask}|dst {mask}, src{1to16}}
|
Note
|
Constraints: src0 = dst |
VCVTPH2HF8SZ256rmbkz [HasAVX10_2]
vcvtph2hf8s {src{1to16}, dst {mask} {z}|dst {mask} {z}, src{1to16}}
VCVTPH2HF8SZ256rmk [HasAVX10_2]
vcvtph2hf8s{y} {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTPH2HF8SZ256rmkz [HasAVX10_2]
vcvtph2hf8s{y} {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTPH2HF8SZ256rr [HasAVX10_2]
vcvtph2hf8s {src, dst|dst, src}
VCVTPH2HF8SZ256rrk [HasAVX10_2]
vcvtph2hf8s {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTPH2HF8SZ256rrkz [HasAVX10_2]
vcvtph2hf8s {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTPH2HF8Z128rm [HasAVX10_2]
vcvtph2hf8{x} {src, dst|dst, src}
VCVTPH2HF8Z128rmb [HasAVX10_2]
vcvtph2hf8 {src{1to8}, dst|dst, src{1to8}}
VCVTPH2HF8Z128rmbk [HasAVX10_2]
vcvtph2hf8 {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Constraints: src0 = dst |
VCVTPH2HF8Z128rmbkz [HasAVX10_2]
vcvtph2hf8 {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
VCVTPH2HF8Z128rmk [HasAVX10_2]
vcvtph2hf8{x} {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTPH2HF8Z128rmkz [HasAVX10_2]
vcvtph2hf8{x} {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTPH2HF8Z128rr [HasAVX10_2]
vcvtph2hf8 {src, dst|dst, src}
VCVTPH2HF8Z128rrk [HasAVX10_2]
vcvtph2hf8 {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTPH2HF8Z128rrkz [HasAVX10_2]
vcvtph2hf8 {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTPH2HF8Z256rm [HasAVX10_2]
vcvtph2hf8{y} {src, dst|dst, src}
VCVTPH2HF8Z256rmb [HasAVX10_2]
vcvtph2hf8 {src{1to16}, dst|dst, src{1to16}}
VCVTPH2HF8Z256rmbk [HasAVX10_2]
vcvtph2hf8 {src{1to16}, dst {mask}|dst {mask}, src{1to16}}
|
Note
|
Constraints: src0 = dst |
VCVTPH2HF8Z256rmbkz [HasAVX10_2]
vcvtph2hf8 {src{1to16}, dst {mask} {z}|dst {mask} {z}, src{1to16}}
VCVTPH2HF8Z256rmk [HasAVX10_2]
vcvtph2hf8{y} {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTPH2HF8Z256rmkz [HasAVX10_2]
vcvtph2hf8{y} {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTPH2HF8Z256rr [HasAVX10_2]
vcvtph2hf8 {src, dst|dst, src}
VCVTPH2HF8Z256rrk [HasAVX10_2]
vcvtph2hf8 {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTPH2HF8Z256rrkz [HasAVX10_2]
vcvtph2hf8 {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTPH2IBSZ128rm [HasAVX10_2]
vcvtph2ibs {src, dst|dst, src}
VCVTPH2IBSZ128rmb [HasAVX10_2]
vcvtph2ibs {src{1to8}, dst|dst, src{1to8}}
VCVTPH2IBSZ128rmbk [HasAVX10_2]
vcvtph2ibs {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Constraints: src0 = dst |
VCVTPH2IBSZ128rmbkz [HasAVX10_2]
vcvtph2ibs {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
VCVTPH2IBSZ128rmk [HasAVX10_2]
vcvtph2ibs {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTPH2IBSZ128rmkz [HasAVX10_2]
vcvtph2ibs {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTPH2IBSZ128rr [HasAVX10_2]
vcvtph2ibs {src, dst|dst, src}
VCVTPH2IBSZ128rrk [HasAVX10_2]
vcvtph2ibs {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTPH2IBSZ128rrkz [HasAVX10_2]
vcvtph2ibs {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTPH2IBSZ256rm [HasAVX10_2]
vcvtph2ibs {src, dst|dst, src}
VCVTPH2IBSZ256rmb [HasAVX10_2]
vcvtph2ibs {src{1to16}, dst|dst, src{1to16}}
VCVTPH2IBSZ256rmbk [HasAVX10_2]
vcvtph2ibs {src{1to16}, dst {mask}|dst {mask}, src{1to16}}
|
Note
|
Constraints: src0 = dst |
VCVTPH2IBSZ256rmbkz [HasAVX10_2]
vcvtph2ibs {src{1to16}, dst {mask} {z}|dst {mask} {z}, src{1to16}}
VCVTPH2IBSZ256rmk [HasAVX10_2]
vcvtph2ibs {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTPH2IBSZ256rmkz [HasAVX10_2]
vcvtph2ibs {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTPH2IBSZ256rr [HasAVX10_2]
vcvtph2ibs {src, dst|dst, src}
VCVTPH2IBSZ256rrk [HasAVX10_2]
vcvtph2ibs {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTPH2IBSZ256rrkz [HasAVX10_2]
vcvtph2ibs {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTPH2IUBSZ128rm [HasAVX10_2]
vcvtph2iubs {src, dst|dst, src}
VCVTPH2IUBSZ128rmb [HasAVX10_2]
vcvtph2iubs {src{1to8}, dst|dst, src{1to8}}
VCVTPH2IUBSZ128rmbk [HasAVX10_2]
vcvtph2iubs {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Constraints: src0 = dst |
VCVTPH2IUBSZ128rmbkz [HasAVX10_2]
vcvtph2iubs {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
VCVTPH2IUBSZ128rmk [HasAVX10_2]
vcvtph2iubs {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTPH2IUBSZ128rmkz [HasAVX10_2]
vcvtph2iubs {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTPH2IUBSZ128rr [HasAVX10_2]
vcvtph2iubs {src, dst|dst, src}
VCVTPH2IUBSZ128rrk [HasAVX10_2]
vcvtph2iubs {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTPH2IUBSZ128rrkz [HasAVX10_2]
vcvtph2iubs {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTPH2IUBSZ256rm [HasAVX10_2]
vcvtph2iubs {src, dst|dst, src}
VCVTPH2IUBSZ256rmb [HasAVX10_2]
vcvtph2iubs {src{1to16}, dst|dst, src{1to16}}
VCVTPH2IUBSZ256rmbk [HasAVX10_2]
vcvtph2iubs {src{1to16}, dst {mask}|dst {mask}, src{1to16}}
|
Note
|
Constraints: src0 = dst |
VCVTPH2IUBSZ256rmbkz [HasAVX10_2]
vcvtph2iubs {src{1to16}, dst {mask} {z}|dst {mask} {z}, src{1to16}}
VCVTPH2IUBSZ256rmk [HasAVX10_2]
vcvtph2iubs {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTPH2IUBSZ256rmkz [HasAVX10_2]
vcvtph2iubs {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTPH2IUBSZ256rr [HasAVX10_2]
vcvtph2iubs {src, dst|dst, src}
VCVTPH2IUBSZ256rrk [HasAVX10_2]
vcvtph2iubs {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTPH2IUBSZ256rrkz [HasAVX10_2]
vcvtph2iubs {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTPS2IBSZ128rm [HasAVX10_2]
vcvtps2ibs {src, dst|dst, src}
VCVTPS2IBSZ128rmb [HasAVX10_2]
vcvtps2ibs {src{1to4}, dst|dst, src{1to4}}
VCVTPS2IBSZ128rmbk [HasAVX10_2]
vcvtps2ibs {src{1to4}, dst {mask}|dst {mask}, src{1to4}}
|
Note
|
Constraints: src0 = dst |
VCVTPS2IBSZ128rmbkz [HasAVX10_2]
vcvtps2ibs {src{1to4}, dst {mask} {z}|dst {mask} {z}, src{1to4}}
VCVTPS2IBSZ128rmk [HasAVX10_2]
vcvtps2ibs {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTPS2IBSZ128rmkz [HasAVX10_2]
vcvtps2ibs {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTPS2IBSZ128rr [HasAVX10_2]
vcvtps2ibs {src, dst|dst, src}
VCVTPS2IBSZ128rrk [HasAVX10_2]
vcvtps2ibs {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTPS2IBSZ128rrkz [HasAVX10_2]
vcvtps2ibs {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTPS2IBSZ256rm [HasAVX10_2]
vcvtps2ibs {src, dst|dst, src}
VCVTPS2IBSZ256rmb [HasAVX10_2]
vcvtps2ibs {src{1to8}, dst|dst, src{1to8}}
VCVTPS2IBSZ256rmbk [HasAVX10_2]
vcvtps2ibs {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Constraints: src0 = dst |
VCVTPS2IBSZ256rmbkz [HasAVX10_2]
vcvtps2ibs {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
VCVTPS2IBSZ256rmk [HasAVX10_2]
vcvtps2ibs {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTPS2IBSZ256rmkz [HasAVX10_2]
vcvtps2ibs {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTPS2IBSZ256rr [HasAVX10_2]
vcvtps2ibs {src, dst|dst, src}
VCVTPS2IBSZ256rrk [HasAVX10_2]
vcvtps2ibs {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTPS2IBSZ256rrkz [HasAVX10_2]
vcvtps2ibs {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTPS2IUBSZ128rm [HasAVX10_2]
vcvtps2iubs {src, dst|dst, src}
VCVTPS2IUBSZ128rmb [HasAVX10_2]
vcvtps2iubs {src{1to4}, dst|dst, src{1to4}}
VCVTPS2IUBSZ128rmbk [HasAVX10_2]
vcvtps2iubs {src{1to4}, dst {mask}|dst {mask}, src{1to4}}
|
Note
|
Constraints: src0 = dst |
VCVTPS2IUBSZ128rmbkz [HasAVX10_2]
vcvtps2iubs {src{1to4}, dst {mask} {z}|dst {mask} {z}, src{1to4}}
VCVTPS2IUBSZ128rmk [HasAVX10_2]
vcvtps2iubs {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTPS2IUBSZ128rmkz [HasAVX10_2]
vcvtps2iubs {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTPS2IUBSZ128rr [HasAVX10_2]
vcvtps2iubs {src, dst|dst, src}
VCVTPS2IUBSZ128rrk [HasAVX10_2]
vcvtps2iubs {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTPS2IUBSZ128rrkz [HasAVX10_2]
vcvtps2iubs {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTPS2IUBSZ256rm [HasAVX10_2]
vcvtps2iubs {src, dst|dst, src}
VCVTPS2IUBSZ256rmb [HasAVX10_2]
vcvtps2iubs {src{1to8}, dst|dst, src{1to8}}
VCVTPS2IUBSZ256rmbk [HasAVX10_2]
vcvtps2iubs {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Constraints: src0 = dst |
VCVTPS2IUBSZ256rmbkz [HasAVX10_2]
vcvtps2iubs {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
VCVTPS2IUBSZ256rmk [HasAVX10_2]
vcvtps2iubs {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTPS2IUBSZ256rmkz [HasAVX10_2]
vcvtps2iubs {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTPS2IUBSZ256rr [HasAVX10_2]
vcvtps2iubs {src, dst|dst, src}
VCVTPS2IUBSZ256rrk [HasAVX10_2]
vcvtps2iubs {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTPS2IUBSZ256rrkz [HasAVX10_2]
vcvtps2iubs {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTTBF162IBSZ128rm [HasAVX10_2]
vcvttbf162ibs {src, dst|dst, src}
VCVTTBF162IBSZ128rmb [HasAVX10_2]
vcvttbf162ibs {src{1to8}, dst|dst, src{1to8}}
VCVTTBF162IBSZ128rmbk [HasAVX10_2]
vcvttbf162ibs {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Constraints: src0 = dst |
VCVTTBF162IBSZ128rmbkz [HasAVX10_2]
vcvttbf162ibs {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
VCVTTBF162IBSZ128rmk [HasAVX10_2]
vcvttbf162ibs {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTTBF162IBSZ128rmkz [HasAVX10_2]
vcvttbf162ibs {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTTBF162IBSZ128rr [HasAVX10_2]
vcvttbf162ibs {src, dst|dst, src}
VCVTTBF162IBSZ128rrk [HasAVX10_2]
vcvttbf162ibs {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTTBF162IBSZ128rrkz [HasAVX10_2]
vcvttbf162ibs {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTTBF162IBSZ256rm [HasAVX10_2]
vcvttbf162ibs {src, dst|dst, src}
VCVTTBF162IBSZ256rmb [HasAVX10_2]
vcvttbf162ibs {src{1to16}, dst|dst, src{1to16}}
VCVTTBF162IBSZ256rmbk [HasAVX10_2]
vcvttbf162ibs {src{1to16}, dst {mask}|dst {mask}, src{1to16}}
|
Note
|
Constraints: src0 = dst |
VCVTTBF162IBSZ256rmbkz [HasAVX10_2]
vcvttbf162ibs {src{1to16}, dst {mask} {z}|dst {mask} {z}, src{1to16}}
VCVTTBF162IBSZ256rmk [HasAVX10_2]
vcvttbf162ibs {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTTBF162IBSZ256rmkz [HasAVX10_2]
vcvttbf162ibs {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTTBF162IBSZ256rr [HasAVX10_2]
vcvttbf162ibs {src, dst|dst, src}
VCVTTBF162IBSZ256rrk [HasAVX10_2]
vcvttbf162ibs {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTTBF162IBSZ256rrkz [HasAVX10_2]
vcvttbf162ibs {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTTBF162IUBSZ128rm [HasAVX10_2]
vcvttbf162iubs {src, dst|dst, src}
VCVTTBF162IUBSZ128rmb [HasAVX10_2]
vcvttbf162iubs {src{1to8}, dst|dst, src{1to8}}
VCVTTBF162IUBSZ128rmbk [HasAVX10_2]
vcvttbf162iubs {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Constraints: src0 = dst |
VCVTTBF162IUBSZ128rmbkz [HasAVX10_2]
vcvttbf162iubs {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
VCVTTBF162IUBSZ128rmk [HasAVX10_2]
vcvttbf162iubs {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTTBF162IUBSZ128rmkz [HasAVX10_2]
vcvttbf162iubs {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTTBF162IUBSZ128rr [HasAVX10_2]
vcvttbf162iubs {src, dst|dst, src}
VCVTTBF162IUBSZ128rrk [HasAVX10_2]
vcvttbf162iubs {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTTBF162IUBSZ128rrkz [HasAVX10_2]
vcvttbf162iubs {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTTBF162IUBSZ256rm [HasAVX10_2]
vcvttbf162iubs {src, dst|dst, src}
VCVTTBF162IUBSZ256rmb [HasAVX10_2]
vcvttbf162iubs {src{1to16}, dst|dst, src{1to16}}
VCVTTBF162IUBSZ256rmbk [HasAVX10_2]
vcvttbf162iubs {src{1to16}, dst {mask}|dst {mask}, src{1to16}}
|
Note
|
Constraints: src0 = dst |
VCVTTBF162IUBSZ256rmbkz [HasAVX10_2]
vcvttbf162iubs {src{1to16}, dst {mask} {z}|dst {mask} {z}, src{1to16}}
VCVTTBF162IUBSZ256rmk [HasAVX10_2]
vcvttbf162iubs {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTTBF162IUBSZ256rmkz [HasAVX10_2]
vcvttbf162iubs {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTTBF162IUBSZ256rr [HasAVX10_2]
vcvttbf162iubs {src, dst|dst, src}
VCVTTBF162IUBSZ256rrk [HasAVX10_2]
vcvttbf162iubs {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTTBF162IUBSZ256rrkz [HasAVX10_2]
vcvttbf162iubs {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTTPD2DQSZ128rm [HasAVX10_2]
vcvttpd2dqs{x} {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2DQSZ128rmb [HasAVX10_2]
vcvttpd2dqs {src{1to2}, dst|dst, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2DQSZ128rmbk [HasAVX10_2]
vcvttpd2dqs {src{1to2}, dst {mask}|dst {mask}, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPD2DQSZ128rmbkz [HasAVX10_2]
vcvttpd2dqs {src{1to2}, dst {mask} {z}|dst {mask} {z}, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2DQSZ128rmk [HasAVX10_2]
vcvttpd2dqs{x} {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPD2DQSZ128rmkz [HasAVX10_2]
vcvttpd2dqs{x} {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2DQSZ128rr [HasAVX10_2]
vcvttpd2dqs {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2DQSZ128rrk [HasAVX10_2]
vcvttpd2dqs {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPD2DQSZ128rrkz [HasAVX10_2]
vcvttpd2dqs {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2DQSZ256rm [HasAVX10_2]
vcvttpd2dqs{y} {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2DQSZ256rmb [HasAVX10_2]
vcvttpd2dqs {src{1to4}, dst|dst, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2DQSZ256rmbk [HasAVX10_2]
vcvttpd2dqs {src{1to4}, dst {mask}|dst {mask}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPD2DQSZ256rmbkz [HasAVX10_2]
vcvttpd2dqs {src{1to4}, dst {mask} {z}|dst {mask} {z}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2DQSZ256rmk [HasAVX10_2]
vcvttpd2dqs{y} {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPD2DQSZ256rmkz [HasAVX10_2]
vcvttpd2dqs{y} {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2DQSZ256rr [HasAVX10_2]
vcvttpd2dqs {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2DQSZ256rrb [HasAVX10_2]
vcvttpd2dqs {{sae}, src, dst|dst, src, {sae}}
VCVTTPD2DQSZ256rrbk [HasAVX10_2]
vcvttpd2dqs {{sae}, src, dst {mask}|dst {mask}, src, {sae}}
|
Note
|
Constraints: src0 = dst |
VCVTTPD2DQSZ256rrbkz [HasAVX10_2]
vcvttpd2dqs {{sae}, src, dst {mask} {z}|dst {mask} {z}, src, {sae}}
VCVTTPD2DQSZ256rrk [HasAVX10_2]
vcvttpd2dqs {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPD2DQSZ256rrkz [HasAVX10_2]
vcvttpd2dqs {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2QQSZ128rm [HasAVX10_2]
vcvttpd2qqs {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2QQSZ128rmb [HasAVX10_2]
vcvttpd2qqs {src{1to2}, dst|dst, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2QQSZ128rmbk [HasAVX10_2]
vcvttpd2qqs {src{1to2}, dst {mask}|dst {mask}, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPD2QQSZ128rmbkz [HasAVX10_2]
vcvttpd2qqs {src{1to2}, dst {mask} {z}|dst {mask} {z}, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2QQSZ128rmk [HasAVX10_2]
vcvttpd2qqs {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPD2QQSZ128rmkz [HasAVX10_2]
vcvttpd2qqs {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2QQSZ128rr [HasAVX10_2]
vcvttpd2qqs {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2QQSZ128rrk [HasAVX10_2]
vcvttpd2qqs {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPD2QQSZ128rrkz [HasAVX10_2]
vcvttpd2qqs {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2QQSZ256rm [HasAVX10_2]
vcvttpd2qqs {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2QQSZ256rmb [HasAVX10_2]
vcvttpd2qqs {src{1to4}, dst|dst, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2QQSZ256rmbk [HasAVX10_2]
vcvttpd2qqs {src{1to4}, dst {mask}|dst {mask}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPD2QQSZ256rmbkz [HasAVX10_2]
vcvttpd2qqs {src{1to4}, dst {mask} {z}|dst {mask} {z}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2QQSZ256rmk [HasAVX10_2]
vcvttpd2qqs {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPD2QQSZ256rmkz [HasAVX10_2]
vcvttpd2qqs {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2QQSZ256rr [HasAVX10_2]
vcvttpd2qqs {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2QQSZ256rrb [HasAVX10_2]
vcvttpd2qqs {{sae}, src, dst|dst, src, {sae}}
VCVTTPD2QQSZ256rrbk [HasAVX10_2]
vcvttpd2qqs {{sae}, src, dst {mask}|dst {mask}, src, {sae}}
|
Note
|
Constraints: src0 = dst |
VCVTTPD2QQSZ256rrbkz [HasAVX10_2]
vcvttpd2qqs {{sae}, src, dst {mask} {z}|dst {mask} {z}, src, {sae}}
VCVTTPD2QQSZ256rrk [HasAVX10_2]
vcvttpd2qqs {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPD2QQSZ256rrkz [HasAVX10_2]
vcvttpd2qqs {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2UDQSZ128rm [HasAVX10_2]
vcvttpd2udqs{x} {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2UDQSZ128rmb [HasAVX10_2]
vcvttpd2udqs {src{1to2}, dst|dst, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2UDQSZ128rmbk [HasAVX10_2]
vcvttpd2udqs {src{1to2}, dst {mask}|dst {mask}, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPD2UDQSZ128rmbkz [HasAVX10_2]
vcvttpd2udqs {src{1to2}, dst {mask} {z}|dst {mask} {z}, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2UDQSZ128rmk [HasAVX10_2]
vcvttpd2udqs{x} {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPD2UDQSZ128rmkz [HasAVX10_2]
vcvttpd2udqs{x} {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2UDQSZ128rr [HasAVX10_2]
vcvttpd2udqs {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2UDQSZ128rrk [HasAVX10_2]
vcvttpd2udqs {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPD2UDQSZ128rrkz [HasAVX10_2]
vcvttpd2udqs {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2UDQSZ256rm [HasAVX10_2]
vcvttpd2udqs{y} {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2UDQSZ256rmb [HasAVX10_2]
vcvttpd2udqs {src{1to4}, dst|dst, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2UDQSZ256rmbk [HasAVX10_2]
vcvttpd2udqs {src{1to4}, dst {mask}|dst {mask}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPD2UDQSZ256rmbkz [HasAVX10_2]
vcvttpd2udqs {src{1to4}, dst {mask} {z}|dst {mask} {z}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2UDQSZ256rmk [HasAVX10_2]
vcvttpd2udqs{y} {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPD2UDQSZ256rmkz [HasAVX10_2]
vcvttpd2udqs{y} {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2UDQSZ256rr [HasAVX10_2]
vcvttpd2udqs {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2UDQSZ256rrb [HasAVX10_2]
vcvttpd2udqs {{sae}, src, dst|dst, src, {sae}}
VCVTTPD2UDQSZ256rrbk [HasAVX10_2]
vcvttpd2udqs {{sae}, src, dst {mask}|dst {mask}, src, {sae}}
|
Note
|
Constraints: src0 = dst |
VCVTTPD2UDQSZ256rrbkz [HasAVX10_2]
vcvttpd2udqs {{sae}, src, dst {mask} {z}|dst {mask} {z}, src, {sae}}
VCVTTPD2UDQSZ256rrk [HasAVX10_2]
vcvttpd2udqs {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPD2UDQSZ256rrkz [HasAVX10_2]
vcvttpd2udqs {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2UQQSZ128rm [HasAVX10_2]
vcvttpd2uqqs {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2UQQSZ128rmb [HasAVX10_2]
vcvttpd2uqqs {src{1to2}, dst|dst, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2UQQSZ128rmbk [HasAVX10_2]
vcvttpd2uqqs {src{1to2}, dst {mask}|dst {mask}, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPD2UQQSZ128rmbkz [HasAVX10_2]
vcvttpd2uqqs {src{1to2}, dst {mask} {z}|dst {mask} {z}, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2UQQSZ128rmk [HasAVX10_2]
vcvttpd2uqqs {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPD2UQQSZ128rmkz [HasAVX10_2]
vcvttpd2uqqs {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2UQQSZ128rr [HasAVX10_2]
vcvttpd2uqqs {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2UQQSZ128rrk [HasAVX10_2]
vcvttpd2uqqs {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPD2UQQSZ128rrkz [HasAVX10_2]
vcvttpd2uqqs {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2UQQSZ256rm [HasAVX10_2]
vcvttpd2uqqs {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2UQQSZ256rmb [HasAVX10_2]
vcvttpd2uqqs {src{1to4}, dst|dst, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2UQQSZ256rmbk [HasAVX10_2]
vcvttpd2uqqs {src{1to4}, dst {mask}|dst {mask}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPD2UQQSZ256rmbkz [HasAVX10_2]
vcvttpd2uqqs {src{1to4}, dst {mask} {z}|dst {mask} {z}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2UQQSZ256rmk [HasAVX10_2]
vcvttpd2uqqs {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPD2UQQSZ256rmkz [HasAVX10_2]
vcvttpd2uqqs {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2UQQSZ256rr [HasAVX10_2]
vcvttpd2uqqs {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2UQQSZ256rrb [HasAVX10_2]
vcvttpd2uqqs {{sae}, src, dst|dst, src, {sae}}
VCVTTPD2UQQSZ256rrbk [HasAVX10_2]
vcvttpd2uqqs {{sae}, src, dst {mask}|dst {mask}, src, {sae}}
|
Note
|
Constraints: src0 = dst |
VCVTTPD2UQQSZ256rrbkz [HasAVX10_2]
vcvttpd2uqqs {{sae}, src, dst {mask} {z}|dst {mask} {z}, src, {sae}}
VCVTTPD2UQQSZ256rrk [HasAVX10_2]
vcvttpd2uqqs {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPD2UQQSZ256rrkz [HasAVX10_2]
vcvttpd2uqqs {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2IBSZ128rm [HasAVX10_2]
vcvttph2ibs {src, dst|dst, src}
VCVTTPH2IBSZ128rmb [HasAVX10_2]
vcvttph2ibs {src{1to8}, dst|dst, src{1to8}}
VCVTTPH2IBSZ128rmbk [HasAVX10_2]
vcvttph2ibs {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Constraints: src0 = dst |
VCVTTPH2IBSZ128rmbkz [HasAVX10_2]
vcvttph2ibs {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
VCVTTPH2IBSZ128rmk [HasAVX10_2]
vcvttph2ibs {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTTPH2IBSZ128rmkz [HasAVX10_2]
vcvttph2ibs {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTTPH2IBSZ128rr [HasAVX10_2]
vcvttph2ibs {src, dst|dst, src}
VCVTTPH2IBSZ128rrk [HasAVX10_2]
vcvttph2ibs {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTTPH2IBSZ128rrkz [HasAVX10_2]
vcvttph2ibs {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTTPH2IBSZ256rm [HasAVX10_2]
vcvttph2ibs {src, dst|dst, src}
VCVTTPH2IBSZ256rmb [HasAVX10_2]
vcvttph2ibs {src{1to16}, dst|dst, src{1to16}}
VCVTTPH2IBSZ256rmbk [HasAVX10_2]
vcvttph2ibs {src{1to16}, dst {mask}|dst {mask}, src{1to16}}
|
Note
|
Constraints: src0 = dst |
VCVTTPH2IBSZ256rmbkz [HasAVX10_2]
vcvttph2ibs {src{1to16}, dst {mask} {z}|dst {mask} {z}, src{1to16}}
VCVTTPH2IBSZ256rmk [HasAVX10_2]
vcvttph2ibs {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTTPH2IBSZ256rmkz [HasAVX10_2]
vcvttph2ibs {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTTPH2IBSZ256rr [HasAVX10_2]
vcvttph2ibs {src, dst|dst, src}
VCVTTPH2IBSZ256rrk [HasAVX10_2]
vcvttph2ibs {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTTPH2IBSZ256rrkz [HasAVX10_2]
vcvttph2ibs {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTTPH2IUBSZ128rm [HasAVX10_2]
vcvttph2iubs {src, dst|dst, src}
VCVTTPH2IUBSZ128rmb [HasAVX10_2]
vcvttph2iubs {src{1to8}, dst|dst, src{1to8}}
VCVTTPH2IUBSZ128rmbk [HasAVX10_2]
vcvttph2iubs {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Constraints: src0 = dst |
VCVTTPH2IUBSZ128rmbkz [HasAVX10_2]
vcvttph2iubs {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
VCVTTPH2IUBSZ128rmk [HasAVX10_2]
vcvttph2iubs {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTTPH2IUBSZ128rmkz [HasAVX10_2]
vcvttph2iubs {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTTPH2IUBSZ128rr [HasAVX10_2]
vcvttph2iubs {src, dst|dst, src}
VCVTTPH2IUBSZ128rrk [HasAVX10_2]
vcvttph2iubs {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTTPH2IUBSZ128rrkz [HasAVX10_2]
vcvttph2iubs {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTTPH2IUBSZ256rm [HasAVX10_2]
vcvttph2iubs {src, dst|dst, src}
VCVTTPH2IUBSZ256rmb [HasAVX10_2]
vcvttph2iubs {src{1to16}, dst|dst, src{1to16}}
VCVTTPH2IUBSZ256rmbk [HasAVX10_2]
vcvttph2iubs {src{1to16}, dst {mask}|dst {mask}, src{1to16}}
|
Note
|
Constraints: src0 = dst |
VCVTTPH2IUBSZ256rmbkz [HasAVX10_2]
vcvttph2iubs {src{1to16}, dst {mask} {z}|dst {mask} {z}, src{1to16}}
VCVTTPH2IUBSZ256rmk [HasAVX10_2]
vcvttph2iubs {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTTPH2IUBSZ256rmkz [HasAVX10_2]
vcvttph2iubs {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTTPH2IUBSZ256rr [HasAVX10_2]
vcvttph2iubs {src, dst|dst, src}
VCVTTPH2IUBSZ256rrk [HasAVX10_2]
vcvttph2iubs {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTTPH2IUBSZ256rrkz [HasAVX10_2]
vcvttph2iubs {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTTPS2DQSZ128rm [HasAVX10_2]
vcvttps2dqs {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2DQSZ128rmb [HasAVX10_2]
vcvttps2dqs {src{1to4}, dst|dst, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2DQSZ128rmbk [HasAVX10_2]
vcvttps2dqs {src{1to4}, dst {mask}|dst {mask}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPS2DQSZ128rmbkz [HasAVX10_2]
vcvttps2dqs {src{1to4}, dst {mask} {z}|dst {mask} {z}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2DQSZ128rmk [HasAVX10_2]
vcvttps2dqs {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPS2DQSZ128rmkz [HasAVX10_2]
vcvttps2dqs {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2DQSZ128rr [HasAVX10_2]
vcvttps2dqs {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2DQSZ128rrk [HasAVX10_2]
vcvttps2dqs {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPS2DQSZ128rrkz [HasAVX10_2]
vcvttps2dqs {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2DQSZ256rm [HasAVX10_2]
vcvttps2dqs {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2DQSZ256rmb [HasAVX10_2]
vcvttps2dqs {src{1to8}, dst|dst, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2DQSZ256rmbk [HasAVX10_2]
vcvttps2dqs {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPS2DQSZ256rmbkz [HasAVX10_2]
vcvttps2dqs {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2DQSZ256rmk [HasAVX10_2]
vcvttps2dqs {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPS2DQSZ256rmkz [HasAVX10_2]
vcvttps2dqs {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2DQSZ256rr [HasAVX10_2]
vcvttps2dqs {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2DQSZ256rrk [HasAVX10_2]
vcvttps2dqs {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPS2DQSZ256rrkz [HasAVX10_2]
vcvttps2dqs {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2IBSZ128rm [HasAVX10_2]
vcvttps2ibs {src, dst|dst, src}
VCVTTPS2IBSZ128rmb [HasAVX10_2]
vcvttps2ibs {src{1to4}, dst|dst, src{1to4}}
VCVTTPS2IBSZ128rmbk [HasAVX10_2]
vcvttps2ibs {src{1to4}, dst {mask}|dst {mask}, src{1to4}}
|
Note
|
Constraints: src0 = dst |
VCVTTPS2IBSZ128rmbkz [HasAVX10_2]
vcvttps2ibs {src{1to4}, dst {mask} {z}|dst {mask} {z}, src{1to4}}
VCVTTPS2IBSZ128rmk [HasAVX10_2]
vcvttps2ibs {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTTPS2IBSZ128rmkz [HasAVX10_2]
vcvttps2ibs {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTTPS2IBSZ128rr [HasAVX10_2]
vcvttps2ibs {src, dst|dst, src}
VCVTTPS2IBSZ128rrk [HasAVX10_2]
vcvttps2ibs {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTTPS2IBSZ128rrkz [HasAVX10_2]
vcvttps2ibs {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTTPS2IBSZ256rm [HasAVX10_2]
vcvttps2ibs {src, dst|dst, src}
VCVTTPS2IBSZ256rmb [HasAVX10_2]
vcvttps2ibs {src{1to8}, dst|dst, src{1to8}}
VCVTTPS2IBSZ256rmbk [HasAVX10_2]
vcvttps2ibs {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Constraints: src0 = dst |
VCVTTPS2IBSZ256rmbkz [HasAVX10_2]
vcvttps2ibs {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
VCVTTPS2IBSZ256rmk [HasAVX10_2]
vcvttps2ibs {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTTPS2IBSZ256rmkz [HasAVX10_2]
vcvttps2ibs {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTTPS2IBSZ256rr [HasAVX10_2]
vcvttps2ibs {src, dst|dst, src}
VCVTTPS2IBSZ256rrk [HasAVX10_2]
vcvttps2ibs {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTTPS2IBSZ256rrkz [HasAVX10_2]
vcvttps2ibs {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTTPS2IUBSZ128rm [HasAVX10_2]
vcvttps2iubs {src, dst|dst, src}
VCVTTPS2IUBSZ128rmb [HasAVX10_2]
vcvttps2iubs {src{1to4}, dst|dst, src{1to4}}
VCVTTPS2IUBSZ128rmbk [HasAVX10_2]
vcvttps2iubs {src{1to4}, dst {mask}|dst {mask}, src{1to4}}
|
Note
|
Constraints: src0 = dst |
VCVTTPS2IUBSZ128rmbkz [HasAVX10_2]
vcvttps2iubs {src{1to4}, dst {mask} {z}|dst {mask} {z}, src{1to4}}
VCVTTPS2IUBSZ128rmk [HasAVX10_2]
vcvttps2iubs {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTTPS2IUBSZ128rmkz [HasAVX10_2]
vcvttps2iubs {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTTPS2IUBSZ128rr [HasAVX10_2]
vcvttps2iubs {src, dst|dst, src}
VCVTTPS2IUBSZ128rrk [HasAVX10_2]
vcvttps2iubs {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTTPS2IUBSZ128rrkz [HasAVX10_2]
vcvttps2iubs {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTTPS2IUBSZ256rm [HasAVX10_2]
vcvttps2iubs {src, dst|dst, src}
VCVTTPS2IUBSZ256rmb [HasAVX10_2]
vcvttps2iubs {src{1to8}, dst|dst, src{1to8}}
VCVTTPS2IUBSZ256rmbk [HasAVX10_2]
vcvttps2iubs {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Constraints: src0 = dst |
VCVTTPS2IUBSZ256rmbkz [HasAVX10_2]
vcvttps2iubs {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
VCVTTPS2IUBSZ256rmk [HasAVX10_2]
vcvttps2iubs {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTTPS2IUBSZ256rmkz [HasAVX10_2]
vcvttps2iubs {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTTPS2IUBSZ256rr [HasAVX10_2]
vcvttps2iubs {src, dst|dst, src}
VCVTTPS2IUBSZ256rrk [HasAVX10_2]
vcvttps2iubs {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTTPS2IUBSZ256rrkz [HasAVX10_2]
vcvttps2iubs {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTTPS2QQSZ128rm [HasAVX10_2]
vcvttps2qqs {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2QQSZ128rmb [HasAVX10_2]
vcvttps2qqs {src{1to2}, dst|dst, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2QQSZ128rmbk [HasAVX10_2]
vcvttps2qqs {src{1to2}, dst {mask}|dst {mask}, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPS2QQSZ128rmbkz [HasAVX10_2]
vcvttps2qqs {src{1to2}, dst {mask} {z}|dst {mask} {z}, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2QQSZ128rmk [HasAVX10_2]
vcvttps2qqs {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPS2QQSZ128rmkz [HasAVX10_2]
vcvttps2qqs {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2QQSZ128rr [HasAVX10_2]
vcvttps2qqs {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2QQSZ128rrk [HasAVX10_2]
vcvttps2qqs {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPS2QQSZ128rrkz [HasAVX10_2]
vcvttps2qqs {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2QQSZ256rm [HasAVX10_2]
vcvttps2qqs {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2QQSZ256rmb [HasAVX10_2]
vcvttps2qqs {src{1to4}, dst|dst, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2QQSZ256rmbk [HasAVX10_2]
vcvttps2qqs {src{1to4}, dst {mask}|dst {mask}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPS2QQSZ256rmbkz [HasAVX10_2]
vcvttps2qqs {src{1to4}, dst {mask} {z}|dst {mask} {z}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2QQSZ256rmk [HasAVX10_2]
vcvttps2qqs {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPS2QQSZ256rmkz [HasAVX10_2]
vcvttps2qqs {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2QQSZ256rr [HasAVX10_2]
vcvttps2qqs {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2QQSZ256rrb [HasAVX10_2]
vcvttps2qqs {{sae}, src, dst|dst, src, {sae}}
VCVTTPS2QQSZ256rrbk [HasAVX10_2]
vcvttps2qqs {{sae}, src, dst {mask}|dst {mask}, src, {sae}}
|
Note
|
Constraints: src0 = dst |
VCVTTPS2QQSZ256rrbkz [HasAVX10_2]
vcvttps2qqs {{sae}, src, dst {mask} {z}|dst {mask} {z}, src, {sae}}
VCVTTPS2QQSZ256rrk [HasAVX10_2]
vcvttps2qqs {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPS2QQSZ256rrkz [HasAVX10_2]
vcvttps2qqs {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2UDQSZ128rm [HasAVX10_2]
vcvttps2udqs {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2UDQSZ128rmb [HasAVX10_2]
vcvttps2udqs {src{1to4}, dst|dst, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2UDQSZ128rmbk [HasAVX10_2]
vcvttps2udqs {src{1to4}, dst {mask}|dst {mask}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPS2UDQSZ128rmbkz [HasAVX10_2]
vcvttps2udqs {src{1to4}, dst {mask} {z}|dst {mask} {z}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2UDQSZ128rmk [HasAVX10_2]
vcvttps2udqs {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPS2UDQSZ128rmkz [HasAVX10_2]
vcvttps2udqs {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2UDQSZ128rr [HasAVX10_2]
vcvttps2udqs {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2UDQSZ128rrk [HasAVX10_2]
vcvttps2udqs {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPS2UDQSZ128rrkz [HasAVX10_2]
vcvttps2udqs {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2UDQSZ256rm [HasAVX10_2]
vcvttps2udqs {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2UDQSZ256rmb [HasAVX10_2]
vcvttps2udqs {src{1to8}, dst|dst, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2UDQSZ256rmbk [HasAVX10_2]
vcvttps2udqs {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPS2UDQSZ256rmbkz [HasAVX10_2]
vcvttps2udqs {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2UDQSZ256rmk [HasAVX10_2]
vcvttps2udqs {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPS2UDQSZ256rmkz [HasAVX10_2]
vcvttps2udqs {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2UDQSZ256rr [HasAVX10_2]
vcvttps2udqs {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2UDQSZ256rrk [HasAVX10_2]
vcvttps2udqs {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPS2UDQSZ256rrkz [HasAVX10_2]
vcvttps2udqs {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2UQQSZ128rm [HasAVX10_2]
vcvttps2uqqs {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2UQQSZ128rmb [HasAVX10_2]
vcvttps2uqqs {src{1to2}, dst|dst, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2UQQSZ128rmbk [HasAVX10_2]
vcvttps2uqqs {src{1to2}, dst {mask}|dst {mask}, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPS2UQQSZ128rmbkz [HasAVX10_2]
vcvttps2uqqs {src{1to2}, dst {mask} {z}|dst {mask} {z}, src{1to2}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2UQQSZ128rmk [HasAVX10_2]
vcvttps2uqqs {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPS2UQQSZ128rmkz [HasAVX10_2]
vcvttps2uqqs {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2UQQSZ128rr [HasAVX10_2]
vcvttps2uqqs {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2UQQSZ128rrk [HasAVX10_2]
vcvttps2uqqs {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPS2UQQSZ128rrkz [HasAVX10_2]
vcvttps2uqqs {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2UQQSZ256rm [HasAVX10_2]
vcvttps2uqqs {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2UQQSZ256rmb [HasAVX10_2]
vcvttps2uqqs {src{1to4}, dst|dst, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2UQQSZ256rmbk [HasAVX10_2]
vcvttps2uqqs {src{1to4}, dst {mask}|dst {mask}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPS2UQQSZ256rmbkz [HasAVX10_2]
vcvttps2uqqs {src{1to4}, dst {mask} {z}|dst {mask} {z}, src{1to4}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2UQQSZ256rmk [HasAVX10_2]
vcvttps2uqqs {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPS2UQQSZ256rmkz [HasAVX10_2]
vcvttps2uqqs {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2UQQSZ256rr [HasAVX10_2]
vcvttps2uqqs {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2UQQSZ256rrb [HasAVX10_2]
vcvttps2uqqs {{sae}, src, dst|dst, src, {sae}}
VCVTTPS2UQQSZ256rrbk [HasAVX10_2]
vcvttps2uqqs {{sae}, src, dst {mask}|dst {mask}, src, {sae}}
|
Note
|
Constraints: src0 = dst |
VCVTTPS2UQQSZ256rrbkz [HasAVX10_2]
vcvttps2uqqs {{sae}, src, dst {mask} {z}|dst {mask} {z}, src, {sae}}
VCVTTPS2UQQSZ256rrk [HasAVX10_2]
vcvttps2uqqs {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPS2UQQSZ256rrkz [HasAVX10_2]
vcvttps2uqqs {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTSD2SI64Srm_Int [HasAVX10_2]
vcvttsd2sis {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTSD2SI64Srr_Int [HasAVX10_2]
vcvttsd2sis {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTSD2SI64Srrb_Int [HasAVX10_2]
vcvttsd2sis {{sae}, src, dst|dst, src, {sae}}
VCVTTSD2SISrm_Int [HasAVX10_2]
vcvttsd2sis {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTSD2SISrr_Int [HasAVX10_2]
vcvttsd2sis {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTSD2SISrrb_Int [HasAVX10_2]
vcvttsd2sis {{sae}, src, dst|dst, src, {sae}}
VCVTTSD2USI64Srm_Int [HasAVX10_2]
vcvttsd2usis {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTSD2USI64Srr_Int [HasAVX10_2]
vcvttsd2usis {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTSD2USI64Srrb_Int [HasAVX10_2]
vcvttsd2usis {{sae}, src, dst|dst, src, {sae}}
VCVTTSD2USISrm_Int [HasAVX10_2]
vcvttsd2usis {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTSD2USISrr_Int [HasAVX10_2]
vcvttsd2usis {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTSD2USISrrb_Int [HasAVX10_2]
vcvttsd2usis {{sae}, src, dst|dst, src, {sae}}
VCVTTSS2SI64Srm_Int [HasAVX10_2]
vcvttss2sis {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTSS2SI64Srr_Int [HasAVX10_2]
vcvttss2sis {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTSS2SI64Srrb_Int [HasAVX10_2]
vcvttss2sis {{sae}, src, dst|dst, src, {sae}}
VCVTTSS2SISrm_Int [HasAVX10_2]
vcvttss2sis {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTSS2SISrr_Int [HasAVX10_2]
vcvttss2sis {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTSS2SISrrb_Int [HasAVX10_2]
vcvttss2sis {{sae}, src, dst|dst, src, {sae}}
VCVTTSS2USI64Srm_Int [HasAVX10_2]
vcvttss2usis {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTSS2USI64Srr_Int [HasAVX10_2]
vcvttss2usis {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTSS2USI64Srrb_Int [HasAVX10_2]
vcvttss2usis {{sae}, src, dst|dst, src, {sae}}
VCVTTSS2USISrm_Int [HasAVX10_2]
vcvttss2usis {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTSS2USISrr_Int [HasAVX10_2]
vcvttss2usis {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTSS2USISrrb_Int [HasAVX10_2]
vcvttss2usis {{sae}, src, dst|dst, src, {sae}}
VDIVBF16Z128rm [HasAVX10_2]
vdivbf16 {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VDIVBF16Z128rmb [HasAVX10_2]
vdivbf16 {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
VDIVBF16Z128rmbk [HasAVX10_2]
vdivbf16 {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VDIVBF16Z128rmbkz [HasAVX10_2]
vdivbf16 {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
VDIVBF16Z128rmk [HasAVX10_2]
vdivbf16 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VDIVBF16Z128rmkz [HasAVX10_2]
vdivbf16 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VDIVBF16Z128rr [HasAVX10_2]
vdivbf16 {src2, src1, dst|dst, src1, src2}
VDIVBF16Z128rrk [HasAVX10_2]
vdivbf16 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VDIVBF16Z128rrkz [HasAVX10_2]
vdivbf16 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VDIVBF16Z256rm [HasAVX10_2]
vdivbf16 {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VDIVBF16Z256rmb [HasAVX10_2]
vdivbf16 {src2{1to16}, src1, dst|dst, src1, src2{1to16}}
|
Note
|
Properties: mayLoad |
VDIVBF16Z256rmbk [HasAVX10_2]
vdivbf16 {src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VDIVBF16Z256rmbkz [HasAVX10_2]
vdivbf16 {src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}}
|
Note
|
Properties: mayLoad |
VDIVBF16Z256rmk [HasAVX10_2]
vdivbf16 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VDIVBF16Z256rmkz [HasAVX10_2]
vdivbf16 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VDIVBF16Z256rr [HasAVX10_2]
vdivbf16 {src2, src1, dst|dst, src1, src2}
VDIVBF16Z256rrk [HasAVX10_2]
vdivbf16 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VDIVBF16Z256rrkz [HasAVX10_2]
vdivbf16 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VDPPHPSZ128m [HasAVX10_2]
vdpphps {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VDPPHPSZ128mb [HasAVX10_2]
vdpphps {src3{1to4}, src2, dst|dst, src2, src3{1to4}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VDPPHPSZ128mbk [HasAVX10_2]
vdpphps {src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VDPPHPSZ128mbkz [HasAVX10_2]
vdpphps {src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VDPPHPSZ128mk [HasAVX10_2]
vdpphps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VDPPHPSZ128mkz [HasAVX10_2]
vdpphps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VDPPHPSZ128r [HasAVX10_2]
vdpphps {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VDPPHPSZ128rk [HasAVX10_2]
vdpphps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VDPPHPSZ128rkz [HasAVX10_2]
vdpphps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VDPPHPSZ256m [HasAVX10_2]
vdpphps {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VDPPHPSZ256mb [HasAVX10_2]
vdpphps {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VDPPHPSZ256mbk [HasAVX10_2]
vdpphps {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VDPPHPSZ256mbkz [HasAVX10_2]
vdpphps {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VDPPHPSZ256mk [HasAVX10_2]
vdpphps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VDPPHPSZ256mkz [HasAVX10_2]
vdpphps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VDPPHPSZ256r [HasAVX10_2]
vdpphps {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VDPPHPSZ256rk [HasAVX10_2]
vdpphps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VDPPHPSZ256rkz [HasAVX10_2]
vdpphps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMADD132BF16Z128m [HasAVX10_2]
vfmadd132bf16 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMADD132BF16Z128mb [HasAVX10_2]
vfmadd132bf16 {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VFMADD132BF16Z128mbk [HasAVX10_2]
vfmadd132bf16 {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VFMADD132BF16Z128mbkz [HasAVX10_2]
vfmadd132bf16 {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VFMADD132BF16Z128mk [HasAVX10_2]
vfmadd132bf16 {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMADD132BF16Z128mkz [HasAVX10_2]
vfmadd132bf16 {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMADD132BF16Z128r [HasAVX10_2]
vfmadd132bf16 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMADD132BF16Z128rk [HasAVX10_2]
vfmadd132bf16 {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMADD132BF16Z128rkz [HasAVX10_2]
vfmadd132bf16 {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMADD132BF16Z256m [HasAVX10_2]
vfmadd132bf16 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMADD132BF16Z256mb [HasAVX10_2]
vfmadd132bf16 {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VFMADD132BF16Z256mbk [HasAVX10_2]
vfmadd132bf16 {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VFMADD132BF16Z256mbkz [HasAVX10_2]
vfmadd132bf16 {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VFMADD132BF16Z256mk [HasAVX10_2]
vfmadd132bf16 {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMADD132BF16Z256mkz [HasAVX10_2]
vfmadd132bf16 {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMADD132BF16Z256r [HasAVX10_2]
vfmadd132bf16 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMADD132BF16Z256rk [HasAVX10_2]
vfmadd132bf16 {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMADD132BF16Z256rkz [HasAVX10_2]
vfmadd132bf16 {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMADD213BF16Z128m [HasAVX10_2]
vfmadd213bf16 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMADD213BF16Z128mb [HasAVX10_2]
vfmadd213bf16 {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VFMADD213BF16Z128mbk [HasAVX10_2]
vfmadd213bf16 {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VFMADD213BF16Z128mbkz [HasAVX10_2]
vfmadd213bf16 {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VFMADD213BF16Z128mk [HasAVX10_2]
vfmadd213bf16 {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMADD213BF16Z128mkz [HasAVX10_2]
vfmadd213bf16 {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMADD213BF16Z128r [HasAVX10_2]
vfmadd213bf16 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMADD213BF16Z128rk [HasAVX10_2]
vfmadd213bf16 {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMADD213BF16Z128rkz [HasAVX10_2]
vfmadd213bf16 {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMADD213BF16Z256m [HasAVX10_2]
vfmadd213bf16 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMADD213BF16Z256mb [HasAVX10_2]
vfmadd213bf16 {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VFMADD213BF16Z256mbk [HasAVX10_2]
vfmadd213bf16 {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VFMADD213BF16Z256mbkz [HasAVX10_2]
vfmadd213bf16 {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VFMADD213BF16Z256mk [HasAVX10_2]
vfmadd213bf16 {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMADD213BF16Z256mkz [HasAVX10_2]
vfmadd213bf16 {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMADD213BF16Z256r [HasAVX10_2]
vfmadd213bf16 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMADD213BF16Z256rk [HasAVX10_2]
vfmadd213bf16 {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMADD213BF16Z256rkz [HasAVX10_2]
vfmadd213bf16 {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMADD231BF16Z128m [HasAVX10_2]
vfmadd231bf16 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMADD231BF16Z128mb [HasAVX10_2]
vfmadd231bf16 {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VFMADD231BF16Z128mbk [HasAVX10_2]
vfmadd231bf16 {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VFMADD231BF16Z128mbkz [HasAVX10_2]
vfmadd231bf16 {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VFMADD231BF16Z128mk [HasAVX10_2]
vfmadd231bf16 {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMADD231BF16Z128mkz [HasAVX10_2]
vfmadd231bf16 {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMADD231BF16Z128r [HasAVX10_2]
vfmadd231bf16 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMADD231BF16Z128rk [HasAVX10_2]
vfmadd231bf16 {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMADD231BF16Z128rkz [HasAVX10_2]
vfmadd231bf16 {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMADD231BF16Z256m [HasAVX10_2]
vfmadd231bf16 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMADD231BF16Z256mb [HasAVX10_2]
vfmadd231bf16 {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VFMADD231BF16Z256mbk [HasAVX10_2]
vfmadd231bf16 {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VFMADD231BF16Z256mbkz [HasAVX10_2]
vfmadd231bf16 {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VFMADD231BF16Z256mk [HasAVX10_2]
vfmadd231bf16 {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMADD231BF16Z256mkz [HasAVX10_2]
vfmadd231bf16 {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMADD231BF16Z256r [HasAVX10_2]
vfmadd231bf16 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMADD231BF16Z256rk [HasAVX10_2]
vfmadd231bf16 {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMADD231BF16Z256rkz [HasAVX10_2]
vfmadd231bf16 {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMSUB132BF16Z128m [HasAVX10_2]
vfmsub132bf16 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMSUB132BF16Z128mb [HasAVX10_2]
vfmsub132bf16 {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VFMSUB132BF16Z128mbk [HasAVX10_2]
vfmsub132bf16 {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VFMSUB132BF16Z128mbkz [HasAVX10_2]
vfmsub132bf16 {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VFMSUB132BF16Z128mk [HasAVX10_2]
vfmsub132bf16 {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMSUB132BF16Z128mkz [HasAVX10_2]
vfmsub132bf16 {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMSUB132BF16Z128r [HasAVX10_2]
vfmsub132bf16 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMSUB132BF16Z128rk [HasAVX10_2]
vfmsub132bf16 {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMSUB132BF16Z128rkz [HasAVX10_2]
vfmsub132bf16 {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMSUB132BF16Z256m [HasAVX10_2]
vfmsub132bf16 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMSUB132BF16Z256mb [HasAVX10_2]
vfmsub132bf16 {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VFMSUB132BF16Z256mbk [HasAVX10_2]
vfmsub132bf16 {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VFMSUB132BF16Z256mbkz [HasAVX10_2]
vfmsub132bf16 {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VFMSUB132BF16Z256mk [HasAVX10_2]
vfmsub132bf16 {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMSUB132BF16Z256mkz [HasAVX10_2]
vfmsub132bf16 {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMSUB132BF16Z256r [HasAVX10_2]
vfmsub132bf16 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMSUB132BF16Z256rk [HasAVX10_2]
vfmsub132bf16 {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMSUB132BF16Z256rkz [HasAVX10_2]
vfmsub132bf16 {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMSUB213BF16Z128m [HasAVX10_2]
vfmsub213bf16 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMSUB213BF16Z128mb [HasAVX10_2]
vfmsub213bf16 {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VFMSUB213BF16Z128mbk [HasAVX10_2]
vfmsub213bf16 {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VFMSUB213BF16Z128mbkz [HasAVX10_2]
vfmsub213bf16 {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VFMSUB213BF16Z128mk [HasAVX10_2]
vfmsub213bf16 {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMSUB213BF16Z128mkz [HasAVX10_2]
vfmsub213bf16 {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMSUB213BF16Z128r [HasAVX10_2]
vfmsub213bf16 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMSUB213BF16Z128rk [HasAVX10_2]
vfmsub213bf16 {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMSUB213BF16Z128rkz [HasAVX10_2]
vfmsub213bf16 {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMSUB213BF16Z256m [HasAVX10_2]
vfmsub213bf16 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMSUB213BF16Z256mb [HasAVX10_2]
vfmsub213bf16 {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VFMSUB213BF16Z256mbk [HasAVX10_2]
vfmsub213bf16 {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VFMSUB213BF16Z256mbkz [HasAVX10_2]
vfmsub213bf16 {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VFMSUB213BF16Z256mk [HasAVX10_2]
vfmsub213bf16 {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMSUB213BF16Z256mkz [HasAVX10_2]
vfmsub213bf16 {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMSUB213BF16Z256r [HasAVX10_2]
vfmsub213bf16 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMSUB213BF16Z256rk [HasAVX10_2]
vfmsub213bf16 {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMSUB213BF16Z256rkz [HasAVX10_2]
vfmsub213bf16 {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMSUB231BF16Z128m [HasAVX10_2]
vfmsub231bf16 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMSUB231BF16Z128mb [HasAVX10_2]
vfmsub231bf16 {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VFMSUB231BF16Z128mbk [HasAVX10_2]
vfmsub231bf16 {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VFMSUB231BF16Z128mbkz [HasAVX10_2]
vfmsub231bf16 {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VFMSUB231BF16Z128mk [HasAVX10_2]
vfmsub231bf16 {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMSUB231BF16Z128mkz [HasAVX10_2]
vfmsub231bf16 {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMSUB231BF16Z128r [HasAVX10_2]
vfmsub231bf16 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMSUB231BF16Z128rk [HasAVX10_2]
vfmsub231bf16 {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMSUB231BF16Z128rkz [HasAVX10_2]
vfmsub231bf16 {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMSUB231BF16Z256m [HasAVX10_2]
vfmsub231bf16 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMSUB231BF16Z256mb [HasAVX10_2]
vfmsub231bf16 {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VFMSUB231BF16Z256mbk [HasAVX10_2]
vfmsub231bf16 {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VFMSUB231BF16Z256mbkz [HasAVX10_2]
vfmsub231bf16 {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VFMSUB231BF16Z256mk [HasAVX10_2]
vfmsub231bf16 {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMSUB231BF16Z256mkz [HasAVX10_2]
vfmsub231bf16 {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMSUB231BF16Z256r [HasAVX10_2]
vfmsub231bf16 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMSUB231BF16Z256rk [HasAVX10_2]
vfmsub231bf16 {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMSUB231BF16Z256rkz [HasAVX10_2]
vfmsub231bf16 {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMADD132BF16Z128m [HasAVX10_2]
vfnmadd132bf16 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMADD132BF16Z128mb [HasAVX10_2]
vfnmadd132bf16 {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VFNMADD132BF16Z128mbk [HasAVX10_2]
vfnmadd132bf16 {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VFNMADD132BF16Z128mbkz [HasAVX10_2]
vfnmadd132bf16 {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VFNMADD132BF16Z128mk [HasAVX10_2]
vfnmadd132bf16 {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMADD132BF16Z128mkz [HasAVX10_2]
vfnmadd132bf16 {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMADD132BF16Z128r [HasAVX10_2]
vfnmadd132bf16 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMADD132BF16Z128rk [HasAVX10_2]
vfnmadd132bf16 {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMADD132BF16Z128rkz [HasAVX10_2]
vfnmadd132bf16 {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMADD132BF16Z256m [HasAVX10_2]
vfnmadd132bf16 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMADD132BF16Z256mb [HasAVX10_2]
vfnmadd132bf16 {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VFNMADD132BF16Z256mbk [HasAVX10_2]
vfnmadd132bf16 {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VFNMADD132BF16Z256mbkz [HasAVX10_2]
vfnmadd132bf16 {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VFNMADD132BF16Z256mk [HasAVX10_2]
vfnmadd132bf16 {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMADD132BF16Z256mkz [HasAVX10_2]
vfnmadd132bf16 {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMADD132BF16Z256r [HasAVX10_2]
vfnmadd132bf16 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMADD132BF16Z256rk [HasAVX10_2]
vfnmadd132bf16 {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMADD132BF16Z256rkz [HasAVX10_2]
vfnmadd132bf16 {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMADD213BF16Z128m [HasAVX10_2]
vfnmadd213bf16 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMADD213BF16Z128mb [HasAVX10_2]
vfnmadd213bf16 {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VFNMADD213BF16Z128mbk [HasAVX10_2]
vfnmadd213bf16 {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VFNMADD213BF16Z128mbkz [HasAVX10_2]
vfnmadd213bf16 {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VFNMADD213BF16Z128mk [HasAVX10_2]
vfnmadd213bf16 {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMADD213BF16Z128mkz [HasAVX10_2]
vfnmadd213bf16 {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMADD213BF16Z128r [HasAVX10_2]
vfnmadd213bf16 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMADD213BF16Z128rk [HasAVX10_2]
vfnmadd213bf16 {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMADD213BF16Z128rkz [HasAVX10_2]
vfnmadd213bf16 {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMADD213BF16Z256m [HasAVX10_2]
vfnmadd213bf16 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMADD213BF16Z256mb [HasAVX10_2]
vfnmadd213bf16 {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VFNMADD213BF16Z256mbk [HasAVX10_2]
vfnmadd213bf16 {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VFNMADD213BF16Z256mbkz [HasAVX10_2]
vfnmadd213bf16 {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VFNMADD213BF16Z256mk [HasAVX10_2]
vfnmadd213bf16 {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMADD213BF16Z256mkz [HasAVX10_2]
vfnmadd213bf16 {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMADD213BF16Z256r [HasAVX10_2]
vfnmadd213bf16 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMADD213BF16Z256rk [HasAVX10_2]
vfnmadd213bf16 {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMADD213BF16Z256rkz [HasAVX10_2]
vfnmadd213bf16 {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMADD231BF16Z128m [HasAVX10_2]
vfnmadd231bf16 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMADD231BF16Z128mb [HasAVX10_2]
vfnmadd231bf16 {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VFNMADD231BF16Z128mbk [HasAVX10_2]
vfnmadd231bf16 {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VFNMADD231BF16Z128mbkz [HasAVX10_2]
vfnmadd231bf16 {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VFNMADD231BF16Z128mk [HasAVX10_2]
vfnmadd231bf16 {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMADD231BF16Z128mkz [HasAVX10_2]
vfnmadd231bf16 {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMADD231BF16Z128r [HasAVX10_2]
vfnmadd231bf16 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMADD231BF16Z128rk [HasAVX10_2]
vfnmadd231bf16 {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMADD231BF16Z128rkz [HasAVX10_2]
vfnmadd231bf16 {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMADD231BF16Z256m [HasAVX10_2]
vfnmadd231bf16 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMADD231BF16Z256mb [HasAVX10_2]
vfnmadd231bf16 {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VFNMADD231BF16Z256mbk [HasAVX10_2]
vfnmadd231bf16 {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VFNMADD231BF16Z256mbkz [HasAVX10_2]
vfnmadd231bf16 {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VFNMADD231BF16Z256mk [HasAVX10_2]
vfnmadd231bf16 {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMADD231BF16Z256mkz [HasAVX10_2]
vfnmadd231bf16 {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMADD231BF16Z256r [HasAVX10_2]
vfnmadd231bf16 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMADD231BF16Z256rk [HasAVX10_2]
vfnmadd231bf16 {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMADD231BF16Z256rkz [HasAVX10_2]
vfnmadd231bf16 {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMSUB132BF16Z128m [HasAVX10_2]
vfnmsub132bf16 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMSUB132BF16Z128mb [HasAVX10_2]
vfnmsub132bf16 {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VFNMSUB132BF16Z128mbk [HasAVX10_2]
vfnmsub132bf16 {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VFNMSUB132BF16Z128mbkz [HasAVX10_2]
vfnmsub132bf16 {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VFNMSUB132BF16Z128mk [HasAVX10_2]
vfnmsub132bf16 {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMSUB132BF16Z128mkz [HasAVX10_2]
vfnmsub132bf16 {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMSUB132BF16Z128r [HasAVX10_2]
vfnmsub132bf16 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMSUB132BF16Z128rk [HasAVX10_2]
vfnmsub132bf16 {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMSUB132BF16Z128rkz [HasAVX10_2]
vfnmsub132bf16 {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMSUB132BF16Z256m [HasAVX10_2]
vfnmsub132bf16 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMSUB132BF16Z256mb [HasAVX10_2]
vfnmsub132bf16 {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VFNMSUB132BF16Z256mbk [HasAVX10_2]
vfnmsub132bf16 {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VFNMSUB132BF16Z256mbkz [HasAVX10_2]
vfnmsub132bf16 {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VFNMSUB132BF16Z256mk [HasAVX10_2]
vfnmsub132bf16 {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMSUB132BF16Z256mkz [HasAVX10_2]
vfnmsub132bf16 {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMSUB132BF16Z256r [HasAVX10_2]
vfnmsub132bf16 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMSUB132BF16Z256rk [HasAVX10_2]
vfnmsub132bf16 {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMSUB132BF16Z256rkz [HasAVX10_2]
vfnmsub132bf16 {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMSUB213BF16Z128m [HasAVX10_2]
vfnmsub213bf16 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMSUB213BF16Z128mb [HasAVX10_2]
vfnmsub213bf16 {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VFNMSUB213BF16Z128mbk [HasAVX10_2]
vfnmsub213bf16 {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VFNMSUB213BF16Z128mbkz [HasAVX10_2]
vfnmsub213bf16 {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VFNMSUB213BF16Z128mk [HasAVX10_2]
vfnmsub213bf16 {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMSUB213BF16Z128mkz [HasAVX10_2]
vfnmsub213bf16 {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMSUB213BF16Z128r [HasAVX10_2]
vfnmsub213bf16 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMSUB213BF16Z128rk [HasAVX10_2]
vfnmsub213bf16 {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMSUB213BF16Z128rkz [HasAVX10_2]
vfnmsub213bf16 {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMSUB213BF16Z256m [HasAVX10_2]
vfnmsub213bf16 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMSUB213BF16Z256mb [HasAVX10_2]
vfnmsub213bf16 {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VFNMSUB213BF16Z256mbk [HasAVX10_2]
vfnmsub213bf16 {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VFNMSUB213BF16Z256mbkz [HasAVX10_2]
vfnmsub213bf16 {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VFNMSUB213BF16Z256mk [HasAVX10_2]
vfnmsub213bf16 {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMSUB213BF16Z256mkz [HasAVX10_2]
vfnmsub213bf16 {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMSUB213BF16Z256r [HasAVX10_2]
vfnmsub213bf16 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMSUB213BF16Z256rk [HasAVX10_2]
vfnmsub213bf16 {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMSUB213BF16Z256rkz [HasAVX10_2]
vfnmsub213bf16 {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMSUB231BF16Z128m [HasAVX10_2]
vfnmsub231bf16 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMSUB231BF16Z128mb [HasAVX10_2]
vfnmsub231bf16 {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VFNMSUB231BF16Z128mbk [HasAVX10_2]
vfnmsub231bf16 {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VFNMSUB231BF16Z128mbkz [HasAVX10_2]
vfnmsub231bf16 {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VFNMSUB231BF16Z128mk [HasAVX10_2]
vfnmsub231bf16 {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMSUB231BF16Z128mkz [HasAVX10_2]
vfnmsub231bf16 {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMSUB231BF16Z128r [HasAVX10_2]
vfnmsub231bf16 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMSUB231BF16Z128rk [HasAVX10_2]
vfnmsub231bf16 {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMSUB231BF16Z128rkz [HasAVX10_2]
vfnmsub231bf16 {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMSUB231BF16Z256m [HasAVX10_2]
vfnmsub231bf16 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMSUB231BF16Z256mb [HasAVX10_2]
vfnmsub231bf16 {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VFNMSUB231BF16Z256mbk [HasAVX10_2]
vfnmsub231bf16 {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VFNMSUB231BF16Z256mbkz [HasAVX10_2]
vfnmsub231bf16 {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VFNMSUB231BF16Z256mk [HasAVX10_2]
vfnmsub231bf16 {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMSUB231BF16Z256mkz [HasAVX10_2]
vfnmsub231bf16 {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMSUB231BF16Z256r [HasAVX10_2]
vfnmsub231bf16 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMSUB231BF16Z256rk [HasAVX10_2]
vfnmsub231bf16 {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMSUB231BF16Z256rkz [HasAVX10_2]
vfnmsub231bf16 {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFPCLASSBF16Z128mbi [HasAVX10_2]
vfpclassbf16 {src2, src1{1to8}, dst|dst, src1{1to8}, src2}
VFPCLASSBF16Z128mbik [HasAVX10_2]
vfpclassbf16 {src2, src1{1to8}, dst {mask}|dst {mask}, src1{1to8}, src2}
VFPCLASSBF16Z128mi [HasAVX10_2]
vfpclassbf16{x} {src2, src1, dst|dst, src1, src2}
VFPCLASSBF16Z128mik [HasAVX10_2]
vfpclassbf16{x} {src2, src1, dst {mask}|dst {mask}, src1, src2}
VFPCLASSBF16Z128ri [HasAVX10_2]
vfpclassbf16 {src2, src1, dst|dst, src1, src2}
VFPCLASSBF16Z128rik [HasAVX10_2]
vfpclassbf16 {src2, src1, dst {mask}|dst {mask}, src1, src2}
VFPCLASSBF16Z256mbi [HasAVX10_2]
vfpclassbf16 {src2, src1{1to16}, dst|dst, src1{1to16}, src2}
VFPCLASSBF16Z256mbik [HasAVX10_2]
vfpclassbf16 {src2, src1{1to16}, dst {mask}|dst {mask}, src1{1to16}, src2}
VFPCLASSBF16Z256mi [HasAVX10_2]
vfpclassbf16{y} {src2, src1, dst|dst, src1, src2}
VFPCLASSBF16Z256mik [HasAVX10_2]
vfpclassbf16{y} {src2, src1, dst {mask}|dst {mask}, src1, src2}
VFPCLASSBF16Z256ri [HasAVX10_2]
vfpclassbf16 {src2, src1, dst|dst, src1, src2}
VFPCLASSBF16Z256rik [HasAVX10_2]
vfpclassbf16 {src2, src1, dst {mask}|dst {mask}, src1, src2}
VGETEXPBF16Z128m [HasAVX10_2]
vgetexpbf16 {src, dst|dst, src}
VGETEXPBF16Z128mb [HasAVX10_2]
vgetexpbf16 {src{1to8}, dst|dst, src{1to8}}
VGETEXPBF16Z128mbk [HasAVX10_2]
vgetexpbf16 {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Constraints: src0 = dst |
VGETEXPBF16Z128mbkz [HasAVX10_2]
vgetexpbf16 {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
VGETEXPBF16Z128mk [HasAVX10_2]
vgetexpbf16 {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VGETEXPBF16Z128mkz [HasAVX10_2]
vgetexpbf16 {src, dst {mask} {z}|dst {mask} {z}, src}
VGETEXPBF16Z128r [HasAVX10_2]
vgetexpbf16 {src, dst|dst, src}
VGETEXPBF16Z128rk [HasAVX10_2]
vgetexpbf16 {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VGETEXPBF16Z128rkz [HasAVX10_2]
vgetexpbf16 {src, dst {mask} {z}|dst {mask} {z}, src}
VGETEXPBF16Z256m [HasAVX10_2]
vgetexpbf16 {src, dst|dst, src}
VGETEXPBF16Z256mb [HasAVX10_2]
vgetexpbf16 {src{1to16}, dst|dst, src{1to16}}
VGETEXPBF16Z256mbk [HasAVX10_2]
vgetexpbf16 {src{1to16}, dst {mask}|dst {mask}, src{1to16}}
|
Note
|
Constraints: src0 = dst |
VGETEXPBF16Z256mbkz [HasAVX10_2]
vgetexpbf16 {src{1to16}, dst {mask} {z}|dst {mask} {z}, src{1to16}}
VGETEXPBF16Z256mk [HasAVX10_2]
vgetexpbf16 {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VGETEXPBF16Z256mkz [HasAVX10_2]
vgetexpbf16 {src, dst {mask} {z}|dst {mask} {z}, src}
VGETEXPBF16Z256r [HasAVX10_2]
vgetexpbf16 {src, dst|dst, src}
VGETEXPBF16Z256rk [HasAVX10_2]
vgetexpbf16 {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VGETEXPBF16Z256rkz [HasAVX10_2]
vgetexpbf16 {src, dst {mask} {z}|dst {mask} {z}, src}
VGETMANTBF16Z128rmbi [HasAVX10_2]
vgetmantbf16 {src2, src1{1to8}, dst|dst, src1{1to8}, src2}
VGETMANTBF16Z128rmbik [HasAVX10_2]
vgetmantbf16 {src2, src1{1to8}, dst {mask}|dst {mask}, src1{1to8}, src2}
|
Note
|
Constraints: src0 = dst |
VGETMANTBF16Z128rmbikz [HasAVX10_2]
vgetmantbf16 {src2, src1{1to8}, dst {mask} {z}|dst {mask} {z}, src1{1to8}, src2}
VGETMANTBF16Z128rmi [HasAVX10_2]
vgetmantbf16 {src2, src1, dst|dst, src1, src2}
VGETMANTBF16Z128rmik [HasAVX10_2]
vgetmantbf16 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VGETMANTBF16Z128rmikz [HasAVX10_2]
vgetmantbf16 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VGETMANTBF16Z128rri [HasAVX10_2]
vgetmantbf16 {src2, src1, dst|dst, src1, src2}
VGETMANTBF16Z128rrik [HasAVX10_2]
vgetmantbf16 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VGETMANTBF16Z128rrikz [HasAVX10_2]
vgetmantbf16 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VGETMANTBF16Z256rmbi [HasAVX10_2]
vgetmantbf16 {src2, src1{1to16}, dst|dst, src1{1to16}, src2}
VGETMANTBF16Z256rmbik [HasAVX10_2]
vgetmantbf16 {src2, src1{1to16}, dst {mask}|dst {mask}, src1{1to16}, src2}
|
Note
|
Constraints: src0 = dst |
VGETMANTBF16Z256rmbikz [HasAVX10_2]
vgetmantbf16 {src2, src1{1to16}, dst {mask} {z}|dst {mask} {z}, src1{1to16}, src2}
VGETMANTBF16Z256rmi [HasAVX10_2]
vgetmantbf16 {src2, src1, dst|dst, src1, src2}
VGETMANTBF16Z256rmik [HasAVX10_2]
vgetmantbf16 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VGETMANTBF16Z256rmikz [HasAVX10_2]
vgetmantbf16 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VGETMANTBF16Z256rri [HasAVX10_2]
vgetmantbf16 {src2, src1, dst|dst, src1, src2}
VGETMANTBF16Z256rrik [HasAVX10_2]
vgetmantbf16 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VGETMANTBF16Z256rrikz [HasAVX10_2]
vgetmantbf16 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VMAXBF16Z128rm [HasAVX10_2]
vmaxbf16 {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VMAXBF16Z128rmb [HasAVX10_2]
vmaxbf16 {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
VMAXBF16Z128rmbk [HasAVX10_2]
vmaxbf16 {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VMAXBF16Z128rmbkz [HasAVX10_2]
vmaxbf16 {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
VMAXBF16Z128rmk [HasAVX10_2]
vmaxbf16 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VMAXBF16Z128rmkz [HasAVX10_2]
vmaxbf16 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VMAXBF16Z128rr [HasAVX10_2]
vmaxbf16 {src2, src1, dst|dst, src1, src2}
VMAXBF16Z128rrk [HasAVX10_2]
vmaxbf16 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VMAXBF16Z128rrkz [HasAVX10_2]
vmaxbf16 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VMAXBF16Z256rm [HasAVX10_2]
vmaxbf16 {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VMAXBF16Z256rmb [HasAVX10_2]
vmaxbf16 {src2{1to16}, src1, dst|dst, src1, src2{1to16}}
|
Note
|
Properties: mayLoad |
VMAXBF16Z256rmbk [HasAVX10_2]
vmaxbf16 {src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VMAXBF16Z256rmbkz [HasAVX10_2]
vmaxbf16 {src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}}
|
Note
|
Properties: mayLoad |
VMAXBF16Z256rmk [HasAVX10_2]
vmaxbf16 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VMAXBF16Z256rmkz [HasAVX10_2]
vmaxbf16 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VMAXBF16Z256rr [HasAVX10_2]
vmaxbf16 {src2, src1, dst|dst, src1, src2}
VMAXBF16Z256rrk [HasAVX10_2]
vmaxbf16 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VMAXBF16Z256rrkz [HasAVX10_2]
vmaxbf16 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VMINBF16Z128rm [HasAVX10_2]
vminbf16 {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VMINBF16Z128rmb [HasAVX10_2]
vminbf16 {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
VMINBF16Z128rmbk [HasAVX10_2]
vminbf16 {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VMINBF16Z128rmbkz [HasAVX10_2]
vminbf16 {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
VMINBF16Z128rmk [HasAVX10_2]
vminbf16 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VMINBF16Z128rmkz [HasAVX10_2]
vminbf16 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VMINBF16Z128rr [HasAVX10_2]
vminbf16 {src2, src1, dst|dst, src1, src2}
VMINBF16Z128rrk [HasAVX10_2]
vminbf16 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VMINBF16Z128rrkz [HasAVX10_2]
vminbf16 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VMINBF16Z256rm [HasAVX10_2]
vminbf16 {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VMINBF16Z256rmb [HasAVX10_2]
vminbf16 {src2{1to16}, src1, dst|dst, src1, src2{1to16}}
|
Note
|
Properties: mayLoad |
VMINBF16Z256rmbk [HasAVX10_2]
vminbf16 {src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VMINBF16Z256rmbkz [HasAVX10_2]
vminbf16 {src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}}
|
Note
|
Properties: mayLoad |
VMINBF16Z256rmk [HasAVX10_2]
vminbf16 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VMINBF16Z256rmkz [HasAVX10_2]
vminbf16 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VMINBF16Z256rr [HasAVX10_2]
vminbf16 {src2, src1, dst|dst, src1, src2}
VMINBF16Z256rrk [HasAVX10_2]
vminbf16 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VMINBF16Z256rrkz [HasAVX10_2]
vminbf16 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VMINMAXBF16Z128rmbi [HasAVX10_2]
vminmaxbf16 {src3, src2{1to8}, src1, dst|dst, src1, src2{1to8}, src3}
VMINMAXBF16Z128rmbik [HasAVX10_2]
vminmaxbf16 {src3, src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}, src3}
|
Note
|
Constraints: src0 = dst |
VMINMAXBF16Z128rmbikz [HasAVX10_2]
vminmaxbf16 {src3, src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}, src3}
VMINMAXBF16Z128rmi [HasAVX10_2]
vminmaxbf16 {src3, src2, src1, dst|dst, src1, src2, src3}
VMINMAXBF16Z128rmik [HasAVX10_2]
vminmaxbf16 {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VMINMAXBF16Z128rmikz [HasAVX10_2]
vminmaxbf16 {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VMINMAXBF16Z128rri [HasAVX10_2]
vminmaxbf16 {src3, src2, src1, dst|dst, src1, src2, src3}
VMINMAXBF16Z128rrik [HasAVX10_2]
vminmaxbf16 {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VMINMAXBF16Z128rrikz [HasAVX10_2]
vminmaxbf16 {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VMINMAXBF16Z256rmbi [HasAVX10_2]
vminmaxbf16 {src3, src2{1to16}, src1, dst|dst, src1, src2{1to16}, src3}
VMINMAXBF16Z256rmbik [HasAVX10_2]
vminmaxbf16 {src3, src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}, src3}
|
Note
|
Constraints: src0 = dst |
VMINMAXBF16Z256rmbikz [HasAVX10_2]
vminmaxbf16 {src3, src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}, src3}
VMINMAXBF16Z256rmi [HasAVX10_2]
vminmaxbf16 {src3, src2, src1, dst|dst, src1, src2, src3}
VMINMAXBF16Z256rmik [HasAVX10_2]
vminmaxbf16 {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VMINMAXBF16Z256rmikz [HasAVX10_2]
vminmaxbf16 {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VMINMAXBF16Z256rri [HasAVX10_2]
vminmaxbf16 {src3, src2, src1, dst|dst, src1, src2, src3}
VMINMAXBF16Z256rrik [HasAVX10_2]
vminmaxbf16 {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VMINMAXBF16Z256rrikz [HasAVX10_2]
vminmaxbf16 {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VMINMAXPDZ128rmbi [HasAVX10_2]
vminmaxpd {src3, src2{1to2}, src1, dst|dst, src1, src2{1to2}, src3}
|
Note
|
Properties: mayRaiseFPException |
VMINMAXPDZ128rmbik [HasAVX10_2]
vminmaxpd {src3, src2{1to2}, src1, dst {mask}|dst {mask}, src1, src2{1to2}, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMINMAXPDZ128rmbikz [HasAVX10_2]
vminmaxpd {src3, src2{1to2}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to2}, src3}
|
Note
|
Properties: mayRaiseFPException |
VMINMAXPDZ128rmi [HasAVX10_2]
vminmaxpd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VMINMAXPDZ128rmik [HasAVX10_2]
vminmaxpd {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMINMAXPDZ128rmikz [HasAVX10_2]
vminmaxpd {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VMINMAXPDZ128rri [HasAVX10_2]
vminmaxpd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VMINMAXPDZ128rrik [HasAVX10_2]
vminmaxpd {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMINMAXPDZ128rrikz [HasAVX10_2]
vminmaxpd {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VMINMAXPDZ256rmbi [HasAVX10_2]
vminmaxpd {src3, src2{1to4}, src1, dst|dst, src1, src2{1to4}, src3}
|
Note
|
Properties: mayRaiseFPException |
VMINMAXPDZ256rmbik [HasAVX10_2]
vminmaxpd {src3, src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMINMAXPDZ256rmbikz [HasAVX10_2]
vminmaxpd {src3, src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}, src3}
|
Note
|
Properties: mayRaiseFPException |
VMINMAXPDZ256rmi [HasAVX10_2]
vminmaxpd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VMINMAXPDZ256rmik [HasAVX10_2]
vminmaxpd {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMINMAXPDZ256rmikz [HasAVX10_2]
vminmaxpd {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VMINMAXPDZ256rri [HasAVX10_2]
vminmaxpd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VMINMAXPDZ256rrik [HasAVX10_2]
vminmaxpd {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMINMAXPDZ256rrikz [HasAVX10_2]
vminmaxpd {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VMINMAXPHZ128rmbi [HasAVX10_2]
vminmaxph {src3, src2{1to8}, src1, dst|dst, src1, src2{1to8}, src3}
|
Note
|
Properties: mayRaiseFPException |
VMINMAXPHZ128rmbik [HasAVX10_2]
vminmaxph {src3, src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMINMAXPHZ128rmbikz [HasAVX10_2]
vminmaxph {src3, src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}, src3}
|
Note
|
Properties: mayRaiseFPException |
VMINMAXPHZ128rmi [HasAVX10_2]
vminmaxph {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VMINMAXPHZ128rmik [HasAVX10_2]
vminmaxph {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMINMAXPHZ128rmikz [HasAVX10_2]
vminmaxph {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VMINMAXPHZ128rri [HasAVX10_2]
vminmaxph {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VMINMAXPHZ128rrik [HasAVX10_2]
vminmaxph {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMINMAXPHZ128rrikz [HasAVX10_2]
vminmaxph {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VMINMAXPHZ256rmbi [HasAVX10_2]
vminmaxph {src3, src2{1to16}, src1, dst|dst, src1, src2{1to16}, src3}
|
Note
|
Properties: mayRaiseFPException |
VMINMAXPHZ256rmbik [HasAVX10_2]
vminmaxph {src3, src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMINMAXPHZ256rmbikz [HasAVX10_2]
vminmaxph {src3, src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}, src3}
|
Note
|
Properties: mayRaiseFPException |
VMINMAXPHZ256rmi [HasAVX10_2]
vminmaxph {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VMINMAXPHZ256rmik [HasAVX10_2]
vminmaxph {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMINMAXPHZ256rmikz [HasAVX10_2]
vminmaxph {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VMINMAXPHZ256rri [HasAVX10_2]
vminmaxph {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VMINMAXPHZ256rrik [HasAVX10_2]
vminmaxph {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMINMAXPHZ256rrikz [HasAVX10_2]
vminmaxph {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VMINMAXPSZ128rmbi [HasAVX10_2]
vminmaxps {src3, src2{1to4}, src1, dst|dst, src1, src2{1to4}, src3}
|
Note
|
Properties: mayRaiseFPException |
VMINMAXPSZ128rmbik [HasAVX10_2]
vminmaxps {src3, src2{1to4}, src1, dst {mask}|dst {mask}, src1, src2{1to4}, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMINMAXPSZ128rmbikz [HasAVX10_2]
vminmaxps {src3, src2{1to4}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to4}, src3}
|
Note
|
Properties: mayRaiseFPException |
VMINMAXPSZ128rmi [HasAVX10_2]
vminmaxps {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VMINMAXPSZ128rmik [HasAVX10_2]
vminmaxps {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMINMAXPSZ128rmikz [HasAVX10_2]
vminmaxps {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VMINMAXPSZ128rri [HasAVX10_2]
vminmaxps {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VMINMAXPSZ128rrik [HasAVX10_2]
vminmaxps {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMINMAXPSZ128rrikz [HasAVX10_2]
vminmaxps {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VMINMAXPSZ256rmbi [HasAVX10_2]
vminmaxps {src3, src2{1to8}, src1, dst|dst, src1, src2{1to8}, src3}
|
Note
|
Properties: mayRaiseFPException |
VMINMAXPSZ256rmbik [HasAVX10_2]
vminmaxps {src3, src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMINMAXPSZ256rmbikz [HasAVX10_2]
vminmaxps {src3, src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}, src3}
|
Note
|
Properties: mayRaiseFPException |
VMINMAXPSZ256rmi [HasAVX10_2]
vminmaxps {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VMINMAXPSZ256rmik [HasAVX10_2]
vminmaxps {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMINMAXPSZ256rmikz [HasAVX10_2]
vminmaxps {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VMINMAXPSZ256rri [HasAVX10_2]
vminmaxps {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VMINMAXPSZ256rrik [HasAVX10_2]
vminmaxps {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMINMAXPSZ256rrikz [HasAVX10_2]
vminmaxps {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VMINMAXSDrmi_Int [HasAVX10_2]
vminmaxsd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VMINMAXSDrmik_Int [HasAVX10_2]
vminmaxsd {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMINMAXSDrmikz_Int [HasAVX10_2]
vminmaxsd {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VMINMAXSDrri_Int [HasAVX10_2]
vminmaxsd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VMINMAXSDrrib_Int [HasAVX10_2]
vminmaxsd {src3, {sae}, src2, src1, dst|dst, src1, src2, {sae}, src3}
VMINMAXSDrribk_Int [HasAVX10_2]
vminmaxsd {src3, {sae}, src2, src1, dst {mask}|dst {mask}, src1, src2, {sae}, src3}
|
Note
|
Constraints: src0 = dst |
VMINMAXSDrribkz_Int [HasAVX10_2]
vminmaxsd {src3, {sae}, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, {sae}, src3}
VMINMAXSDrrik_Int [HasAVX10_2]
vminmaxsd {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMINMAXSDrrikz_Int [HasAVX10_2]
vminmaxsd {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VMINMAXSHrmi_Int [HasAVX10_2]
vminmaxsh {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VMINMAXSHrmik_Int [HasAVX10_2]
vminmaxsh {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMINMAXSHrmikz_Int [HasAVX10_2]
vminmaxsh {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VMINMAXSHrri_Int [HasAVX10_2]
vminmaxsh {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VMINMAXSHrrib_Int [HasAVX10_2]
vminmaxsh {src3, {sae}, src2, src1, dst|dst, src1, src2, {sae}, src3}
VMINMAXSHrribk_Int [HasAVX10_2]
vminmaxsh {src3, {sae}, src2, src1, dst {mask}|dst {mask}, src1, src2, {sae}, src3}
|
Note
|
Constraints: src0 = dst |
VMINMAXSHrribkz_Int [HasAVX10_2]
vminmaxsh {src3, {sae}, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, {sae}, src3}
VMINMAXSHrrik_Int [HasAVX10_2]
vminmaxsh {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMINMAXSHrrikz_Int [HasAVX10_2]
vminmaxsh {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VMINMAXSSrmi_Int [HasAVX10_2]
vminmaxss {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VMINMAXSSrmik_Int [HasAVX10_2]
vminmaxss {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMINMAXSSrmikz_Int [HasAVX10_2]
vminmaxss {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VMINMAXSSrri_Int [HasAVX10_2]
vminmaxss {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VMINMAXSSrrib_Int [HasAVX10_2]
vminmaxss {src3, {sae}, src2, src1, dst|dst, src1, src2, {sae}, src3}
VMINMAXSSrribk_Int [HasAVX10_2]
vminmaxss {src3, {sae}, src2, src1, dst {mask}|dst {mask}, src1, src2, {sae}, src3}
|
Note
|
Constraints: src0 = dst |
VMINMAXSSrribkz_Int [HasAVX10_2]
vminmaxss {src3, {sae}, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, {sae}, src3}
VMINMAXSSrrik_Int [HasAVX10_2]
vminmaxss {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMINMAXSSrrikz_Int [HasAVX10_2]
vminmaxss {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VMOVZPDILo2PDIZrr [HasAVX10_2]
vmovd {src, dst|dst, src}
VMOVZPWILo2PWIZrr [HasAVX10_2]
vmovw {src, dst|dst, src}
VMPSADBWZrmi [HasAVX10_2]
vmpsadbw {src3, src2, src1, dst|dst, src1, src2, src3}
VMPSADBWZrmik [HasAVX10_2]
vmpsadbw {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VMPSADBWZrmikz [HasAVX10_2]
vmpsadbw {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VMPSADBWZrri [HasAVX10_2]
vmpsadbw {src3, src2, src1, dst|dst, src1, src2, src3}
VMPSADBWZrrik [HasAVX10_2]
vmpsadbw {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VMPSADBWZrrikz [HasAVX10_2]
vmpsadbw {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VMULBF16Z128rm [HasAVX10_2]
vmulbf16 {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VMULBF16Z128rmb [HasAVX10_2]
vmulbf16 {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
VMULBF16Z128rmbk [HasAVX10_2]
vmulbf16 {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VMULBF16Z128rmbkz [HasAVX10_2]
vmulbf16 {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
VMULBF16Z128rmk [HasAVX10_2]
vmulbf16 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VMULBF16Z128rmkz [HasAVX10_2]
vmulbf16 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VMULBF16Z128rr [HasAVX10_2]
vmulbf16 {src2, src1, dst|dst, src1, src2}
VMULBF16Z128rrk [HasAVX10_2]
vmulbf16 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VMULBF16Z128rrkz [HasAVX10_2]
vmulbf16 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VMULBF16Z256rm [HasAVX10_2]
vmulbf16 {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VMULBF16Z256rmb [HasAVX10_2]
vmulbf16 {src2{1to16}, src1, dst|dst, src1, src2{1to16}}
|
Note
|
Properties: mayLoad |
VMULBF16Z256rmbk [HasAVX10_2]
vmulbf16 {src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VMULBF16Z256rmbkz [HasAVX10_2]
vmulbf16 {src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}}
|
Note
|
Properties: mayLoad |
VMULBF16Z256rmk [HasAVX10_2]
vmulbf16 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VMULBF16Z256rmkz [HasAVX10_2]
vmulbf16 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VMULBF16Z256rr [HasAVX10_2]
vmulbf16 {src2, src1, dst|dst, src1, src2}
VMULBF16Z256rrk [HasAVX10_2]
vmulbf16 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VMULBF16Z256rrkz [HasAVX10_2]
vmulbf16 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPDPBSSDSZ128m [HasAVX10_2]
vpdpbssds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSSDSZ128mb [HasAVX10_2]
vpdpbssds {src3{1to4}, src2, dst|dst, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPDPBSSDSZ128mbk [HasAVX10_2]
vpdpbssds {src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPDPBSSDSZ128mbkz [HasAVX10_2]
vpdpbssds {src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPDPBSSDSZ128mk [HasAVX10_2]
vpdpbssds {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSSDSZ128mkz [HasAVX10_2]
vpdpbssds {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSSDSZ128r [HasAVX10_2]
vpdpbssds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSSDSZ128rk [HasAVX10_2]
vpdpbssds {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSSDSZ128rkz [HasAVX10_2]
vpdpbssds {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSSDSZ256m [HasAVX10_2]
vpdpbssds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSSDSZ256mb [HasAVX10_2]
vpdpbssds {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPDPBSSDSZ256mbk [HasAVX10_2]
vpdpbssds {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPDPBSSDSZ256mbkz [HasAVX10_2]
vpdpbssds {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPDPBSSDSZ256mk [HasAVX10_2]
vpdpbssds {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSSDSZ256mkz [HasAVX10_2]
vpdpbssds {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSSDSZ256r [HasAVX10_2]
vpdpbssds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSSDSZ256rk [HasAVX10_2]
vpdpbssds {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSSDSZ256rkz [HasAVX10_2]
vpdpbssds {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSSDZ128m [HasAVX10_2]
vpdpbssd {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSSDZ128mb [HasAVX10_2]
vpdpbssd {src3{1to4}, src2, dst|dst, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPDPBSSDZ128mbk [HasAVX10_2]
vpdpbssd {src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPDPBSSDZ128mbkz [HasAVX10_2]
vpdpbssd {src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPDPBSSDZ128mk [HasAVX10_2]
vpdpbssd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSSDZ128mkz [HasAVX10_2]
vpdpbssd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSSDZ128r [HasAVX10_2]
vpdpbssd {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSSDZ128rk [HasAVX10_2]
vpdpbssd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSSDZ128rkz [HasAVX10_2]
vpdpbssd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSSDZ256m [HasAVX10_2]
vpdpbssd {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSSDZ256mb [HasAVX10_2]
vpdpbssd {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPDPBSSDZ256mbk [HasAVX10_2]
vpdpbssd {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPDPBSSDZ256mbkz [HasAVX10_2]
vpdpbssd {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPDPBSSDZ256mk [HasAVX10_2]
vpdpbssd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSSDZ256mkz [HasAVX10_2]
vpdpbssd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSSDZ256r [HasAVX10_2]
vpdpbssd {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSSDZ256rk [HasAVX10_2]
vpdpbssd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSSDZ256rkz [HasAVX10_2]
vpdpbssd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSUDSZ128m [HasAVX10_2]
vpdpbsuds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSUDSZ128mb [HasAVX10_2]
vpdpbsuds {src3{1to4}, src2, dst|dst, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPDPBSUDSZ128mbk [HasAVX10_2]
vpdpbsuds {src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPDPBSUDSZ128mbkz [HasAVX10_2]
vpdpbsuds {src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPDPBSUDSZ128mk [HasAVX10_2]
vpdpbsuds {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSUDSZ128mkz [HasAVX10_2]
vpdpbsuds {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSUDSZ128r [HasAVX10_2]
vpdpbsuds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSUDSZ128rk [HasAVX10_2]
vpdpbsuds {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSUDSZ128rkz [HasAVX10_2]
vpdpbsuds {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSUDSZ256m [HasAVX10_2]
vpdpbsuds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSUDSZ256mb [HasAVX10_2]
vpdpbsuds {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPDPBSUDSZ256mbk [HasAVX10_2]
vpdpbsuds {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPDPBSUDSZ256mbkz [HasAVX10_2]
vpdpbsuds {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPDPBSUDSZ256mk [HasAVX10_2]
vpdpbsuds {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSUDSZ256mkz [HasAVX10_2]
vpdpbsuds {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSUDSZ256r [HasAVX10_2]
vpdpbsuds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSUDSZ256rk [HasAVX10_2]
vpdpbsuds {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSUDSZ256rkz [HasAVX10_2]
vpdpbsuds {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSUDZ128m [HasAVX10_2]
vpdpbsud {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSUDZ128mb [HasAVX10_2]
vpdpbsud {src3{1to4}, src2, dst|dst, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPDPBSUDZ128mbk [HasAVX10_2]
vpdpbsud {src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPDPBSUDZ128mbkz [HasAVX10_2]
vpdpbsud {src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPDPBSUDZ128mk [HasAVX10_2]
vpdpbsud {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSUDZ128mkz [HasAVX10_2]
vpdpbsud {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSUDZ128r [HasAVX10_2]
vpdpbsud {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSUDZ128rk [HasAVX10_2]
vpdpbsud {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSUDZ128rkz [HasAVX10_2]
vpdpbsud {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSUDZ256m [HasAVX10_2]
vpdpbsud {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSUDZ256mb [HasAVX10_2]
vpdpbsud {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPDPBSUDZ256mbk [HasAVX10_2]
vpdpbsud {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPDPBSUDZ256mbkz [HasAVX10_2]
vpdpbsud {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPDPBSUDZ256mk [HasAVX10_2]
vpdpbsud {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSUDZ256mkz [HasAVX10_2]
vpdpbsud {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSUDZ256r [HasAVX10_2]
vpdpbsud {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSUDZ256rk [HasAVX10_2]
vpdpbsud {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSUDZ256rkz [HasAVX10_2]
vpdpbsud {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUUDSZ128m [HasAVX10_2]
vpdpbuuds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUUDSZ128mb [HasAVX10_2]
vpdpbuuds {src3{1to4}, src2, dst|dst, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPDPBUUDSZ128mbk [HasAVX10_2]
vpdpbuuds {src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPDPBUUDSZ128mbkz [HasAVX10_2]
vpdpbuuds {src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPDPBUUDSZ128mk [HasAVX10_2]
vpdpbuuds {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUUDSZ128mkz [HasAVX10_2]
vpdpbuuds {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUUDSZ128r [HasAVX10_2]
vpdpbuuds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUUDSZ128rk [HasAVX10_2]
vpdpbuuds {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUUDSZ128rkz [HasAVX10_2]
vpdpbuuds {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUUDSZ256m [HasAVX10_2]
vpdpbuuds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUUDSZ256mb [HasAVX10_2]
vpdpbuuds {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPDPBUUDSZ256mbk [HasAVX10_2]
vpdpbuuds {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPDPBUUDSZ256mbkz [HasAVX10_2]
vpdpbuuds {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPDPBUUDSZ256mk [HasAVX10_2]
vpdpbuuds {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUUDSZ256mkz [HasAVX10_2]
vpdpbuuds {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUUDSZ256r [HasAVX10_2]
vpdpbuuds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUUDSZ256rk [HasAVX10_2]
vpdpbuuds {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUUDSZ256rkz [HasAVX10_2]
vpdpbuuds {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUUDZ128m [HasAVX10_2]
vpdpbuud {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUUDZ128mb [HasAVX10_2]
vpdpbuud {src3{1to4}, src2, dst|dst, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPDPBUUDZ128mbk [HasAVX10_2]
vpdpbuud {src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPDPBUUDZ128mbkz [HasAVX10_2]
vpdpbuud {src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPDPBUUDZ128mk [HasAVX10_2]
vpdpbuud {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUUDZ128mkz [HasAVX10_2]
vpdpbuud {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUUDZ128r [HasAVX10_2]
vpdpbuud {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUUDZ128rk [HasAVX10_2]
vpdpbuud {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUUDZ128rkz [HasAVX10_2]
vpdpbuud {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUUDZ256m [HasAVX10_2]
vpdpbuud {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUUDZ256mb [HasAVX10_2]
vpdpbuud {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPDPBUUDZ256mbk [HasAVX10_2]
vpdpbuud {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPDPBUUDZ256mbkz [HasAVX10_2]
vpdpbuud {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPDPBUUDZ256mk [HasAVX10_2]
vpdpbuud {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUUDZ256mkz [HasAVX10_2]
vpdpbuud {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUUDZ256r [HasAVX10_2]
vpdpbuud {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUUDZ256rk [HasAVX10_2]
vpdpbuud {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUUDZ256rkz [HasAVX10_2]
vpdpbuud {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSUDSZ128m [HasAVX10_2]
vpdpwsuds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSUDSZ128mb [HasAVX10_2]
vpdpwsuds {src3{1to4}, src2, dst|dst, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPDPWSUDSZ128mbk [HasAVX10_2]
vpdpwsuds {src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPDPWSUDSZ128mbkz [HasAVX10_2]
vpdpwsuds {src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPDPWSUDSZ128mk [HasAVX10_2]
vpdpwsuds {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSUDSZ128mkz [HasAVX10_2]
vpdpwsuds {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSUDSZ128r [HasAVX10_2]
vpdpwsuds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSUDSZ128rk [HasAVX10_2]
vpdpwsuds {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSUDSZ128rkz [HasAVX10_2]
vpdpwsuds {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSUDSZ256m [HasAVX10_2]
vpdpwsuds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSUDSZ256mb [HasAVX10_2]
vpdpwsuds {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPDPWSUDSZ256mbk [HasAVX10_2]
vpdpwsuds {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPDPWSUDSZ256mbkz [HasAVX10_2]
vpdpwsuds {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPDPWSUDSZ256mk [HasAVX10_2]
vpdpwsuds {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSUDSZ256mkz [HasAVX10_2]
vpdpwsuds {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSUDSZ256r [HasAVX10_2]
vpdpwsuds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSUDSZ256rk [HasAVX10_2]
vpdpwsuds {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSUDSZ256rkz [HasAVX10_2]
vpdpwsuds {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSUDZ128m [HasAVX10_2]
vpdpwsud {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSUDZ128mb [HasAVX10_2]
vpdpwsud {src3{1to4}, src2, dst|dst, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPDPWSUDZ128mbk [HasAVX10_2]
vpdpwsud {src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPDPWSUDZ128mbkz [HasAVX10_2]
vpdpwsud {src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPDPWSUDZ128mk [HasAVX10_2]
vpdpwsud {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSUDZ128mkz [HasAVX10_2]
vpdpwsud {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSUDZ128r [HasAVX10_2]
vpdpwsud {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSUDZ128rk [HasAVX10_2]
vpdpwsud {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSUDZ128rkz [HasAVX10_2]
vpdpwsud {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSUDZ256m [HasAVX10_2]
vpdpwsud {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSUDZ256mb [HasAVX10_2]
vpdpwsud {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPDPWSUDZ256mbk [HasAVX10_2]
vpdpwsud {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPDPWSUDZ256mbkz [HasAVX10_2]
vpdpwsud {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPDPWSUDZ256mk [HasAVX10_2]
vpdpwsud {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSUDZ256mkz [HasAVX10_2]
vpdpwsud {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSUDZ256r [HasAVX10_2]
vpdpwsud {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSUDZ256rk [HasAVX10_2]
vpdpwsud {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSUDZ256rkz [HasAVX10_2]
vpdpwsud {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUSDSZ128m [HasAVX10_2]
vpdpwusds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUSDSZ128mb [HasAVX10_2]
vpdpwusds {src3{1to4}, src2, dst|dst, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPDPWUSDSZ128mbk [HasAVX10_2]
vpdpwusds {src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPDPWUSDSZ128mbkz [HasAVX10_2]
vpdpwusds {src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPDPWUSDSZ128mk [HasAVX10_2]
vpdpwusds {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUSDSZ128mkz [HasAVX10_2]
vpdpwusds {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUSDSZ128r [HasAVX10_2]
vpdpwusds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUSDSZ128rk [HasAVX10_2]
vpdpwusds {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUSDSZ128rkz [HasAVX10_2]
vpdpwusds {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUSDSZ256m [HasAVX10_2]
vpdpwusds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUSDSZ256mb [HasAVX10_2]
vpdpwusds {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPDPWUSDSZ256mbk [HasAVX10_2]
vpdpwusds {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPDPWUSDSZ256mbkz [HasAVX10_2]
vpdpwusds {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPDPWUSDSZ256mk [HasAVX10_2]
vpdpwusds {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUSDSZ256mkz [HasAVX10_2]
vpdpwusds {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUSDSZ256r [HasAVX10_2]
vpdpwusds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUSDSZ256rk [HasAVX10_2]
vpdpwusds {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUSDSZ256rkz [HasAVX10_2]
vpdpwusds {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUSDZ128m [HasAVX10_2]
vpdpwusd {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUSDZ128mb [HasAVX10_2]
vpdpwusd {src3{1to4}, src2, dst|dst, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPDPWUSDZ128mbk [HasAVX10_2]
vpdpwusd {src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPDPWUSDZ128mbkz [HasAVX10_2]
vpdpwusd {src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPDPWUSDZ128mk [HasAVX10_2]
vpdpwusd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUSDZ128mkz [HasAVX10_2]
vpdpwusd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUSDZ128r [HasAVX10_2]
vpdpwusd {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUSDZ128rk [HasAVX10_2]
vpdpwusd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUSDZ128rkz [HasAVX10_2]
vpdpwusd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUSDZ256m [HasAVX10_2]
vpdpwusd {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUSDZ256mb [HasAVX10_2]
vpdpwusd {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPDPWUSDZ256mbk [HasAVX10_2]
vpdpwusd {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPDPWUSDZ256mbkz [HasAVX10_2]
vpdpwusd {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPDPWUSDZ256mk [HasAVX10_2]
vpdpwusd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUSDZ256mkz [HasAVX10_2]
vpdpwusd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUSDZ256r [HasAVX10_2]
vpdpwusd {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUSDZ256rk [HasAVX10_2]
vpdpwusd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUSDZ256rkz [HasAVX10_2]
vpdpwusd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUUDSZ128m [HasAVX10_2]
vpdpwuuds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUUDSZ128mb [HasAVX10_2]
vpdpwuuds {src3{1to4}, src2, dst|dst, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPDPWUUDSZ128mbk [HasAVX10_2]
vpdpwuuds {src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPDPWUUDSZ128mbkz [HasAVX10_2]
vpdpwuuds {src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPDPWUUDSZ128mk [HasAVX10_2]
vpdpwuuds {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUUDSZ128mkz [HasAVX10_2]
vpdpwuuds {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUUDSZ128r [HasAVX10_2]
vpdpwuuds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUUDSZ128rk [HasAVX10_2]
vpdpwuuds {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUUDSZ128rkz [HasAVX10_2]
vpdpwuuds {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUUDSZ256m [HasAVX10_2]
vpdpwuuds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUUDSZ256mb [HasAVX10_2]
vpdpwuuds {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPDPWUUDSZ256mbk [HasAVX10_2]
vpdpwuuds {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPDPWUUDSZ256mbkz [HasAVX10_2]
vpdpwuuds {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPDPWUUDSZ256mk [HasAVX10_2]
vpdpwuuds {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUUDSZ256mkz [HasAVX10_2]
vpdpwuuds {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUUDSZ256r [HasAVX10_2]
vpdpwuuds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUUDSZ256rk [HasAVX10_2]
vpdpwuuds {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUUDSZ256rkz [HasAVX10_2]
vpdpwuuds {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUUDZ128m [HasAVX10_2]
vpdpwuud {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUUDZ128mb [HasAVX10_2]
vpdpwuud {src3{1to4}, src2, dst|dst, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPDPWUUDZ128mbk [HasAVX10_2]
vpdpwuud {src3{1to4}, src2, dst {mask}|dst {mask}, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPDPWUUDZ128mbkz [HasAVX10_2]
vpdpwuud {src3{1to4}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to4}}
|
Note
|
Constraints: src1 = dst |
VPDPWUUDZ128mk [HasAVX10_2]
vpdpwuud {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUUDZ128mkz [HasAVX10_2]
vpdpwuud {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUUDZ128r [HasAVX10_2]
vpdpwuud {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUUDZ128rk [HasAVX10_2]
vpdpwuud {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUUDZ128rkz [HasAVX10_2]
vpdpwuud {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUUDZ256m [HasAVX10_2]
vpdpwuud {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUUDZ256mb [HasAVX10_2]
vpdpwuud {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPDPWUUDZ256mbk [HasAVX10_2]
vpdpwuud {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPDPWUUDZ256mbkz [HasAVX10_2]
vpdpwuud {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPDPWUUDZ256mk [HasAVX10_2]
vpdpwuud {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUUDZ256mkz [HasAVX10_2]
vpdpwuud {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUUDZ256r [HasAVX10_2]
vpdpwuud {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUUDZ256rk [HasAVX10_2]
vpdpwuud {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUUDZ256rkz [HasAVX10_2]
vpdpwuud {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VRCPBF16Z128m [HasAVX10_2]
vrcpbf16 {src, dst|dst, src}
VRCPBF16Z128mb [HasAVX10_2]
vrcpbf16 {src{1to8}, dst|dst, src{1to8}}
VRCPBF16Z128mbk [HasAVX10_2]
vrcpbf16 {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Constraints: src0 = dst |
VRCPBF16Z128mbkz [HasAVX10_2]
vrcpbf16 {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
VRCPBF16Z128mk [HasAVX10_2]
vrcpbf16 {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VRCPBF16Z128mkz [HasAVX10_2]
vrcpbf16 {src, dst {mask} {z}|dst {mask} {z}, src}
VRCPBF16Z128r [HasAVX10_2]
vrcpbf16 {src, dst|dst, src}
VRCPBF16Z128rk [HasAVX10_2]
vrcpbf16 {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VRCPBF16Z128rkz [HasAVX10_2]
vrcpbf16 {src, dst {mask} {z}|dst {mask} {z}, src}
VRCPBF16Z256m [HasAVX10_2]
vrcpbf16 {src, dst|dst, src}
VRCPBF16Z256mb [HasAVX10_2]
vrcpbf16 {src{1to16}, dst|dst, src{1to16}}
VRCPBF16Z256mbk [HasAVX10_2]
vrcpbf16 {src{1to16}, dst {mask}|dst {mask}, src{1to16}}
|
Note
|
Constraints: src0 = dst |
VRCPBF16Z256mbkz [HasAVX10_2]
vrcpbf16 {src{1to16}, dst {mask} {z}|dst {mask} {z}, src{1to16}}
VRCPBF16Z256mk [HasAVX10_2]
vrcpbf16 {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VRCPBF16Z256mkz [HasAVX10_2]
vrcpbf16 {src, dst {mask} {z}|dst {mask} {z}, src}
VRCPBF16Z256r [HasAVX10_2]
vrcpbf16 {src, dst|dst, src}
VRCPBF16Z256rk [HasAVX10_2]
vrcpbf16 {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VRCPBF16Z256rkz [HasAVX10_2]
vrcpbf16 {src, dst {mask} {z}|dst {mask} {z}, src}
VREDUCEBF16Z128rmbi [HasAVX10_2]
vreducebf16 {src2, src1{1to8}, dst|dst, src1{1to8}, src2}
VREDUCEBF16Z128rmbik [HasAVX10_2]
vreducebf16 {src2, src1{1to8}, dst {mask}|dst {mask}, src1{1to8}, src2}
|
Note
|
Constraints: src0 = dst |
VREDUCEBF16Z128rmbikz [HasAVX10_2]
vreducebf16 {src2, src1{1to8}, dst {mask} {z}|dst {mask} {z}, src1{1to8}, src2}
VREDUCEBF16Z128rmi [HasAVX10_2]
vreducebf16 {src2, src1, dst|dst, src1, src2}
VREDUCEBF16Z128rmik [HasAVX10_2]
vreducebf16 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VREDUCEBF16Z128rmikz [HasAVX10_2]
vreducebf16 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VREDUCEBF16Z128rri [HasAVX10_2]
vreducebf16 {src2, src1, dst|dst, src1, src2}
VREDUCEBF16Z128rrik [HasAVX10_2]
vreducebf16 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VREDUCEBF16Z128rrikz [HasAVX10_2]
vreducebf16 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VREDUCEBF16Z256rmbi [HasAVX10_2]
vreducebf16 {src2, src1{1to16}, dst|dst, src1{1to16}, src2}
VREDUCEBF16Z256rmbik [HasAVX10_2]
vreducebf16 {src2, src1{1to16}, dst {mask}|dst {mask}, src1{1to16}, src2}
|
Note
|
Constraints: src0 = dst |
VREDUCEBF16Z256rmbikz [HasAVX10_2]
vreducebf16 {src2, src1{1to16}, dst {mask} {z}|dst {mask} {z}, src1{1to16}, src2}
VREDUCEBF16Z256rmi [HasAVX10_2]
vreducebf16 {src2, src1, dst|dst, src1, src2}
VREDUCEBF16Z256rmik [HasAVX10_2]
vreducebf16 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VREDUCEBF16Z256rmikz [HasAVX10_2]
vreducebf16 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VREDUCEBF16Z256rri [HasAVX10_2]
vreducebf16 {src2, src1, dst|dst, src1, src2}
VREDUCEBF16Z256rrik [HasAVX10_2]
vreducebf16 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VREDUCEBF16Z256rrikz [HasAVX10_2]
vreducebf16 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VRNDSCALEBF16Z128rmbi [HasAVX10_2]
vrndscalebf16 {src2, src1{1to8}, dst|dst, src1{1to8}, src2}
VRNDSCALEBF16Z128rmbik [HasAVX10_2]
vrndscalebf16 {src2, src1{1to8}, dst {mask}|dst {mask}, src1{1to8}, src2}
|
Note
|
Constraints: src0 = dst |
VRNDSCALEBF16Z128rmbikz [HasAVX10_2]
vrndscalebf16 {src2, src1{1to8}, dst {mask} {z}|dst {mask} {z}, src1{1to8}, src2}
VRNDSCALEBF16Z128rmi [HasAVX10_2]
vrndscalebf16 {src2, src1, dst|dst, src1, src2}
VRNDSCALEBF16Z128rmik [HasAVX10_2]
vrndscalebf16 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VRNDSCALEBF16Z128rmikz [HasAVX10_2]
vrndscalebf16 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VRNDSCALEBF16Z128rri [HasAVX10_2]
vrndscalebf16 {src2, src1, dst|dst, src1, src2}
VRNDSCALEBF16Z128rrik [HasAVX10_2]
vrndscalebf16 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VRNDSCALEBF16Z128rrikz [HasAVX10_2]
vrndscalebf16 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VRNDSCALEBF16Z256rmbi [HasAVX10_2]
vrndscalebf16 {src2, src1{1to16}, dst|dst, src1{1to16}, src2}
VRNDSCALEBF16Z256rmbik [HasAVX10_2]
vrndscalebf16 {src2, src1{1to16}, dst {mask}|dst {mask}, src1{1to16}, src2}
|
Note
|
Constraints: src0 = dst |
VRNDSCALEBF16Z256rmbikz [HasAVX10_2]
vrndscalebf16 {src2, src1{1to16}, dst {mask} {z}|dst {mask} {z}, src1{1to16}, src2}
VRNDSCALEBF16Z256rmi [HasAVX10_2]
vrndscalebf16 {src2, src1, dst|dst, src1, src2}
VRNDSCALEBF16Z256rmik [HasAVX10_2]
vrndscalebf16 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VRNDSCALEBF16Z256rmikz [HasAVX10_2]
vrndscalebf16 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VRNDSCALEBF16Z256rri [HasAVX10_2]
vrndscalebf16 {src2, src1, dst|dst, src1, src2}
VRNDSCALEBF16Z256rrik [HasAVX10_2]
vrndscalebf16 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VRNDSCALEBF16Z256rrikz [HasAVX10_2]
vrndscalebf16 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VRSQRTBF16Z128m [HasAVX10_2]
vrsqrtbf16 {src, dst|dst, src}
VRSQRTBF16Z128mb [HasAVX10_2]
vrsqrtbf16 {src{1to8}, dst|dst, src{1to8}}
VRSQRTBF16Z128mbk [HasAVX10_2]
vrsqrtbf16 {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Constraints: src0 = dst |
VRSQRTBF16Z128mbkz [HasAVX10_2]
vrsqrtbf16 {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
VRSQRTBF16Z128mk [HasAVX10_2]
vrsqrtbf16 {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VRSQRTBF16Z128mkz [HasAVX10_2]
vrsqrtbf16 {src, dst {mask} {z}|dst {mask} {z}, src}
VRSQRTBF16Z128r [HasAVX10_2]
vrsqrtbf16 {src, dst|dst, src}
VRSQRTBF16Z128rk [HasAVX10_2]
vrsqrtbf16 {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VRSQRTBF16Z128rkz [HasAVX10_2]
vrsqrtbf16 {src, dst {mask} {z}|dst {mask} {z}, src}
VRSQRTBF16Z256m [HasAVX10_2]
vrsqrtbf16 {src, dst|dst, src}
VRSQRTBF16Z256mb [HasAVX10_2]
vrsqrtbf16 {src{1to16}, dst|dst, src{1to16}}
VRSQRTBF16Z256mbk [HasAVX10_2]
vrsqrtbf16 {src{1to16}, dst {mask}|dst {mask}, src{1to16}}
|
Note
|
Constraints: src0 = dst |
VRSQRTBF16Z256mbkz [HasAVX10_2]
vrsqrtbf16 {src{1to16}, dst {mask} {z}|dst {mask} {z}, src{1to16}}
VRSQRTBF16Z256mk [HasAVX10_2]
vrsqrtbf16 {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VRSQRTBF16Z256mkz [HasAVX10_2]
vrsqrtbf16 {src, dst {mask} {z}|dst {mask} {z}, src}
VRSQRTBF16Z256r [HasAVX10_2]
vrsqrtbf16 {src, dst|dst, src}
VRSQRTBF16Z256rk [HasAVX10_2]
vrsqrtbf16 {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VRSQRTBF16Z256rkz [HasAVX10_2]
vrsqrtbf16 {src, dst {mask} {z}|dst {mask} {z}, src}
VSCALEFBF16Z128rm [HasAVX10_2]
vscalefbf16 {src2, src1, dst|dst, src1, src2}
VSCALEFBF16Z128rmb [HasAVX10_2]
vscalefbf16 {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
VSCALEFBF16Z128rmbk [HasAVX10_2]
vscalefbf16 {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Constraints: src0 = dst |
VSCALEFBF16Z128rmbkz [HasAVX10_2]
vscalefbf16 {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
VSCALEFBF16Z128rmk [HasAVX10_2]
vscalefbf16 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VSCALEFBF16Z128rmkz [HasAVX10_2]
vscalefbf16 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VSCALEFBF16Z128rr [HasAVX10_2]
vscalefbf16 {src2, src1, dst|dst, src1, src2}
VSCALEFBF16Z128rrk [HasAVX10_2]
vscalefbf16 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VSCALEFBF16Z128rrkz [HasAVX10_2]
vscalefbf16 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VSCALEFBF16Z256rm [HasAVX10_2]
vscalefbf16 {src2, src1, dst|dst, src1, src2}
VSCALEFBF16Z256rmb [HasAVX10_2]
vscalefbf16 {src2{1to16}, src1, dst|dst, src1, src2{1to16}}
VSCALEFBF16Z256rmbk [HasAVX10_2]
vscalefbf16 {src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}}
|
Note
|
Constraints: src0 = dst |
VSCALEFBF16Z256rmbkz [HasAVX10_2]
vscalefbf16 {src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}}
VSCALEFBF16Z256rmk [HasAVX10_2]
vscalefbf16 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VSCALEFBF16Z256rmkz [HasAVX10_2]
vscalefbf16 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VSCALEFBF16Z256rr [HasAVX10_2]
vscalefbf16 {src2, src1, dst|dst, src1, src2}
VSCALEFBF16Z256rrk [HasAVX10_2]
vscalefbf16 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VSCALEFBF16Z256rrkz [HasAVX10_2]
vscalefbf16 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VSQRTBF16Z128m [HasAVX10_2]
vsqrtbf16 {src, dst|dst, src}
VSQRTBF16Z128mb [HasAVX10_2]
vsqrtbf16 {src{1to8}, dst|dst, src{1to8}}
VSQRTBF16Z128mbk [HasAVX10_2]
vsqrtbf16 {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Constraints: src0 = dst |
VSQRTBF16Z128mbkz [HasAVX10_2]
vsqrtbf16 {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
VSQRTBF16Z128mk [HasAVX10_2]
vsqrtbf16 {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VSQRTBF16Z128mkz [HasAVX10_2]
vsqrtbf16 {src, dst {mask} {z}|dst {mask} {z}, src}
VSQRTBF16Z128r [HasAVX10_2]
vsqrtbf16 {src, dst|dst, src}
VSQRTBF16Z128rk [HasAVX10_2]
vsqrtbf16 {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VSQRTBF16Z128rkz [HasAVX10_2]
vsqrtbf16 {src, dst {mask} {z}|dst {mask} {z}, src}
VSQRTBF16Z256m [HasAVX10_2]
vsqrtbf16 {src, dst|dst, src}
VSQRTBF16Z256mb [HasAVX10_2]
vsqrtbf16 {src{1to16}, dst|dst, src{1to16}}
VSQRTBF16Z256mbk [HasAVX10_2]
vsqrtbf16 {src{1to16}, dst {mask}|dst {mask}, src{1to16}}
|
Note
|
Constraints: src0 = dst |
VSQRTBF16Z256mbkz [HasAVX10_2]
vsqrtbf16 {src{1to16}, dst {mask} {z}|dst {mask} {z}, src{1to16}}
VSQRTBF16Z256mk [HasAVX10_2]
vsqrtbf16 {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VSQRTBF16Z256mkz [HasAVX10_2]
vsqrtbf16 {src, dst {mask} {z}|dst {mask} {z}, src}
VSQRTBF16Z256r [HasAVX10_2]
vsqrtbf16 {src, dst|dst, src}
VSQRTBF16Z256rk [HasAVX10_2]
vsqrtbf16 {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VSQRTBF16Z256rkz [HasAVX10_2]
vsqrtbf16 {src, dst {mask} {z}|dst {mask} {z}, src}
VSUBBF16Z128rm [HasAVX10_2]
vsubbf16 {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VSUBBF16Z128rmb [HasAVX10_2]
vsubbf16 {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
VSUBBF16Z128rmbk [HasAVX10_2]
vsubbf16 {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VSUBBF16Z128rmbkz [HasAVX10_2]
vsubbf16 {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
VSUBBF16Z128rmk [HasAVX10_2]
vsubbf16 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VSUBBF16Z128rmkz [HasAVX10_2]
vsubbf16 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VSUBBF16Z128rr [HasAVX10_2]
vsubbf16 {src2, src1, dst|dst, src1, src2}
VSUBBF16Z128rrk [HasAVX10_2]
vsubbf16 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VSUBBF16Z128rrkz [HasAVX10_2]
vsubbf16 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VSUBBF16Z256rm [HasAVX10_2]
vsubbf16 {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VSUBBF16Z256rmb [HasAVX10_2]
vsubbf16 {src2{1to16}, src1, dst|dst, src1, src2{1to16}}
|
Note
|
Properties: mayLoad |
VSUBBF16Z256rmbk [HasAVX10_2]
vsubbf16 {src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VSUBBF16Z256rmbkz [HasAVX10_2]
vsubbf16 {src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}}
|
Note
|
Properties: mayLoad |
VSUBBF16Z256rmk [HasAVX10_2]
vsubbf16 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VSUBBF16Z256rmkz [HasAVX10_2]
vsubbf16 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VSUBBF16Z256rr [HasAVX10_2]
vsubbf16 {src2, src1, dst|dst, src1, src2}
VSUBBF16Z256rrk [HasAVX10_2]
vsubbf16 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VSUBBF16Z256rrkz [HasAVX10_2]
vsubbf16 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VUCOMXSDZrm_Int [HasAVX10_2]
vucomxsd {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VUCOMXSDZrr_Int [HasAVX10_2]
vucomxsd {src2, src1|src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VUCOMXSDZrrb_Int [HasAVX10_2]
vucomxsd {{sae}, src2, src1|src1, src2, {sae}}
|
Note
|
Properties: mayRaiseFPException |
VUCOMXSHZrm_Int [HasAVX10_2]
vucomxsh {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VUCOMXSHZrr_Int [HasAVX10_2]
vucomxsh {src2, src1|src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VUCOMXSHZrrb_Int [HasAVX10_2]
vucomxsh {{sae}, src2, src1|src1, src2, {sae}}
|
Note
|
Properties: mayRaiseFPException |
VUCOMXSSZrm_Int [HasAVX10_2]
vucomxss {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VUCOMXSSZrr_Int [HasAVX10_2]
vucomxss {src2, src1|src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VUCOMXSSZrrb_Int [HasAVX10_2]
vucomxss {{sae}, src2, src1|src1, src2, {sae}}
|
Note
|
Properties: mayRaiseFPException |
VSM4KEY4Z128rm [HasAVX10_2, HasSM4]
vsm4key4 {src2, src1, dst|dst, src1, src2}
VSM4KEY4Z128rr [HasAVX10_2, HasSM4]
vsm4key4 {src2, src1, dst|dst, src1, src2}
VSM4KEY4Z256rm [HasAVX10_2, HasSM4]
vsm4key4 {src2, src1, dst|dst, src1, src2}
VSM4KEY4Z256rr [HasAVX10_2, HasSM4]
vsm4key4 {src2, src1, dst|dst, src1, src2}
VSM4RNDS4Z128rm [HasAVX10_2, HasSM4]
vsm4rnds4 {src2, src1, dst|dst, src1, src2}
VSM4RNDS4Z128rr [HasAVX10_2, HasSM4]
vsm4rnds4 {src2, src1, dst|dst, src1, src2}
VSM4RNDS4Z256rm [HasAVX10_2, HasSM4]
vsm4rnds4 {src2, src1, dst|dst, src1, src2}
VSM4RNDS4Z256rr [HasAVX10_2, HasSM4]
vsm4rnds4 {src2, src1, dst|dst, src1, src2}
KADDDkk [HasBWI]
kaddd {src2, src1, dst|dst, src1, src2}
KADDQkk [HasBWI]
kaddq {src2, src1, dst|dst, src1, src2}
KANDDkk [HasBWI]
kandd {src2, src1, dst|dst, src1, src2}
KANDNDkk [HasBWI]
kandnd {src2, src1, dst|dst, src1, src2}
KANDNQkk [HasBWI]
kandnq {src2, src1, dst|dst, src1, src2}
KANDQkk [HasBWI]
kandq {src2, src1, dst|dst, src1, src2}
KNOTDkk [HasBWI]
knotd {src, dst|dst, src}
KNOTQkk [HasBWI]
knotq {src, dst|dst, src}
KORDkk [HasBWI]
kord {src2, src1, dst|dst, src1, src2}
KORQkk [HasBWI]
korq {src2, src1, dst|dst, src1, src2}
KORTESTDkk [HasBWI]
kortestd {src2, src1|src1, src2}
KORTESTQkk [HasBWI]
kortestq {src2, src1|src1, src2}
KSHIFTLDki [HasBWI]
kshiftld {imm, src, dst|dst, src, imm}
KSHIFTLQki [HasBWI]
kshiftlq {imm, src, dst|dst, src, imm}
KSHIFTRDki [HasBWI]
kshiftrd {imm, src, dst|dst, src, imm}
KSHIFTRQki [HasBWI]
kshiftrq {imm, src, dst|dst, src, imm}
KTESTDkk [HasBWI]
ktestd {src2, src1|src1, src2}
KTESTQkk [HasBWI]
ktestq {src2, src1|src1, src2}
KUNPCKDQkk [HasBWI]
kunpckdq {src2, src1, dst|dst, src1, src2}
KUNPCKWDkk [HasBWI]
kunpckwd {src2, src1, dst|dst, src1, src2}
KXNORDkk [HasBWI]
kxnord {src2, src1, dst|dst, src1, src2}
KXNORQkk [HasBWI]
kxnorq {src2, src1, dst|dst, src1, src2}
KXORDkk [HasBWI]
kxord {src2, src1, dst|dst, src1, src2}
KXORQkk [HasBWI]
kxorq {src2, src1, dst|dst, src1, src2}
VDBPSADBWZrmi [HasBWI]
vdbpsadbw {src3, src2, src1, dst|dst, src1, src2, src3}
VDBPSADBWZrmik [HasBWI]
vdbpsadbw {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VDBPSADBWZrmikz [HasBWI]
vdbpsadbw {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VDBPSADBWZrri [HasBWI]
vdbpsadbw {src3, src2, src1, dst|dst, src1, src2, src3}
VDBPSADBWZrrik [HasBWI]
vdbpsadbw {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VDBPSADBWZrrikz [HasBWI]
vdbpsadbw {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VMOVDQU16Zmr [HasBWI]
vmovdqu16 {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VMOVDQU16Zmrk [HasBWI]
vmovdqu16 {src, dst {mask}|dst {mask}, src}
VMOVDQU16Zrm [HasBWI]
vmovdqu16 {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
VMOVDQU16Zrmk [HasBWI]
vmovdqu16 {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVDQU16Zrmkz [HasBWI]
vmovdqu16 {src, dst {mask} {z}|dst {mask} {z}, src}
VMOVDQU16Zrr [HasBWI]
vmovdqu16 {src, dst|dst, src}
|
Note
|
Properties: isMoveReg |
VMOVDQU16Zrrk [HasBWI]
vmovdqu16 {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVDQU16Zrrkz [HasBWI]
vmovdqu16 {src, dst {mask} {z}|dst {mask} {z}, src}
VMOVDQU8Zmr [HasBWI]
vmovdqu8 {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VMOVDQU8Zmrk [HasBWI]
vmovdqu8 {src, dst {mask}|dst {mask}, src}
VMOVDQU8Zrm [HasBWI]
vmovdqu8 {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
VMOVDQU8Zrmk [HasBWI]
vmovdqu8 {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVDQU8Zrmkz [HasBWI]
vmovdqu8 {src, dst {mask} {z}|dst {mask} {z}, src}
VMOVDQU8Zrr [HasBWI]
vmovdqu8 {src, dst|dst, src}
|
Note
|
Properties: isMoveReg |
VMOVDQU8Zrrk [HasBWI]
vmovdqu8 {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VMOVDQU8Zrrkz [HasBWI]
vmovdqu8 {src, dst {mask} {z}|dst {mask} {z}, src}
VPABSBZrm [HasBWI]
vpabsb {src1, dst|dst, src1}
VPABSBZrmk [HasBWI]
vpabsb {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPABSBZrmkz [HasBWI]
vpabsb {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPABSBZrr [HasBWI]
vpabsb {src1, dst|dst, src1}
VPABSBZrrk [HasBWI]
vpabsb {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPABSBZrrkz [HasBWI]
vpabsb {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPABSWZrm [HasBWI]
vpabsw {src1, dst|dst, src1}
VPABSWZrmk [HasBWI]
vpabsw {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPABSWZrmkz [HasBWI]
vpabsw {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPABSWZrr [HasBWI]
vpabsw {src1, dst|dst, src1}
VPABSWZrrk [HasBWI]
vpabsw {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPABSWZrrkz [HasBWI]
vpabsw {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPACKSSDWZrm [HasBWI]
vpackssdw {src2, src1, dst|dst, src1, src2}
VPACKSSDWZrmb [HasBWI]
vpackssdw {src2{1to16}, src1, dst|dst, src1, src2{1to16}}
VPACKSSDWZrmbk [HasBWI]
vpackssdw {src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}}
|
Note
|
Constraints: src0 = dst |
VPACKSSDWZrmbkz [HasBWI]
vpackssdw {src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}}
VPACKSSDWZrmk [HasBWI]
vpackssdw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPACKSSDWZrmkz [HasBWI]
vpackssdw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPACKSSDWZrr [HasBWI]
vpackssdw {src2, src1, dst|dst, src1, src2}
VPACKSSDWZrrk [HasBWI]
vpackssdw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPACKSSDWZrrkz [HasBWI]
vpackssdw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPACKSSWBZrm [HasBWI]
vpacksswb {src2, src1, dst|dst, src1, src2}
VPACKSSWBZrmk [HasBWI]
vpacksswb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPACKSSWBZrmkz [HasBWI]
vpacksswb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPACKSSWBZrr [HasBWI]
vpacksswb {src2, src1, dst|dst, src1, src2}
VPACKSSWBZrrk [HasBWI]
vpacksswb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPACKSSWBZrrkz [HasBWI]
vpacksswb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPACKUSDWZrm [HasBWI]
vpackusdw {src2, src1, dst|dst, src1, src2}
VPACKUSDWZrmb [HasBWI]
vpackusdw {src2{1to16}, src1, dst|dst, src1, src2{1to16}}
VPACKUSDWZrmbk [HasBWI]
vpackusdw {src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}}
|
Note
|
Constraints: src0 = dst |
VPACKUSDWZrmbkz [HasBWI]
vpackusdw {src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}}
VPACKUSDWZrmk [HasBWI]
vpackusdw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPACKUSDWZrmkz [HasBWI]
vpackusdw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPACKUSDWZrr [HasBWI]
vpackusdw {src2, src1, dst|dst, src1, src2}
VPACKUSDWZrrk [HasBWI]
vpackusdw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPACKUSDWZrrkz [HasBWI]
vpackusdw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPACKUSWBZrm [HasBWI]
vpackuswb {src2, src1, dst|dst, src1, src2}
VPACKUSWBZrmk [HasBWI]
vpackuswb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPACKUSWBZrmkz [HasBWI]
vpackuswb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPACKUSWBZrr [HasBWI]
vpackuswb {src2, src1, dst|dst, src1, src2}
VPACKUSWBZrrk [HasBWI]
vpackuswb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPACKUSWBZrrkz [HasBWI]
vpackuswb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPADDBZrm [HasBWI]
vpaddb {src2, src1, dst|dst, src1, src2}
VPADDBZrmk [HasBWI]
vpaddb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPADDBZrmkz [HasBWI]
vpaddb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPADDBZrr [HasBWI]
vpaddb {src2, src1, dst|dst, src1, src2}
VPADDBZrrk [HasBWI]
vpaddb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPADDBZrrkz [HasBWI]
vpaddb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPADDSBZrm [HasBWI]
vpaddsb {src2, src1, dst|dst, src1, src2}
VPADDSBZrmk [HasBWI]
vpaddsb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPADDSBZrmkz [HasBWI]
vpaddsb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPADDSBZrr [HasBWI]
vpaddsb {src2, src1, dst|dst, src1, src2}
VPADDSBZrrk [HasBWI]
vpaddsb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPADDSBZrrkz [HasBWI]
vpaddsb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPADDSWZrm [HasBWI]
vpaddsw {src2, src1, dst|dst, src1, src2}
VPADDSWZrmk [HasBWI]
vpaddsw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPADDSWZrmkz [HasBWI]
vpaddsw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPADDSWZrr [HasBWI]
vpaddsw {src2, src1, dst|dst, src1, src2}
VPADDSWZrrk [HasBWI]
vpaddsw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPADDSWZrrkz [HasBWI]
vpaddsw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPADDUSBZrm [HasBWI]
vpaddusb {src2, src1, dst|dst, src1, src2}
VPADDUSBZrmk [HasBWI]
vpaddusb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPADDUSBZrmkz [HasBWI]
vpaddusb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPADDUSBZrr [HasBWI]
vpaddusb {src2, src1, dst|dst, src1, src2}
VPADDUSBZrrk [HasBWI]
vpaddusb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPADDUSBZrrkz [HasBWI]
vpaddusb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPADDUSWZrm [HasBWI]
vpaddusw {src2, src1, dst|dst, src1, src2}
VPADDUSWZrmk [HasBWI]
vpaddusw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPADDUSWZrmkz [HasBWI]
vpaddusw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPADDUSWZrr [HasBWI]
vpaddusw {src2, src1, dst|dst, src1, src2}
VPADDUSWZrrk [HasBWI]
vpaddusw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPADDUSWZrrkz [HasBWI]
vpaddusw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPADDWZrm [HasBWI]
vpaddw {src2, src1, dst|dst, src1, src2}
VPADDWZrmk [HasBWI]
vpaddw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPADDWZrmkz [HasBWI]
vpaddw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPADDWZrr [HasBWI]
vpaddw {src2, src1, dst|dst, src1, src2}
VPADDWZrrk [HasBWI]
vpaddw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPADDWZrrkz [HasBWI]
vpaddw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPALIGNRZrmi [HasBWI]
vpalignr {src3, src2, src1, dst|dst, src1, src2, src3}
VPALIGNRZrmik [HasBWI]
vpalignr {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VPALIGNRZrmikz [HasBWI]
vpalignr {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VPALIGNRZrri [HasBWI]
vpalignr {src3, src2, src1, dst|dst, src1, src2, src3}
VPALIGNRZrrik [HasBWI]
vpalignr {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VPALIGNRZrrikz [HasBWI]
vpalignr {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VPAVGBZrm [HasBWI]
vpavgb {src2, src1, dst|dst, src1, src2}
VPAVGBZrmk [HasBWI]
vpavgb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPAVGBZrmkz [HasBWI]
vpavgb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPAVGBZrr [HasBWI]
vpavgb {src2, src1, dst|dst, src1, src2}
VPAVGBZrrk [HasBWI]
vpavgb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPAVGBZrrkz [HasBWI]
vpavgb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPAVGWZrm [HasBWI]
vpavgw {src2, src1, dst|dst, src1, src2}
VPAVGWZrmk [HasBWI]
vpavgw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPAVGWZrmkz [HasBWI]
vpavgw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPAVGWZrr [HasBWI]
vpavgw {src2, src1, dst|dst, src1, src2}
VPAVGWZrrk [HasBWI]
vpavgw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPAVGWZrrkz [HasBWI]
vpavgw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPBLENDMBZrm [HasBWI]
vpblendmb {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VPBLENDMBZrmk [HasBWI]
vpblendmb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
VPBLENDMBZrmkz [HasBWI]
vpblendmb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VPBLENDMBZrr [HasBWI]
vpblendmb {src2, src1, dst|dst, src1, src2}
VPBLENDMBZrrk [HasBWI]
vpblendmb {src2, src1, dst {mask}|dst {mask}, src1, src2}
VPBLENDMBZrrkz [HasBWI]
vpblendmb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPBLENDMWZrm [HasBWI]
vpblendmw {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VPBLENDMWZrmk [HasBWI]
vpblendmw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
VPBLENDMWZrmkz [HasBWI]
vpblendmw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VPBLENDMWZrr [HasBWI]
vpblendmw {src2, src1, dst|dst, src1, src2}
VPBLENDMWZrrk [HasBWI]
vpblendmw {src2, src1, dst {mask}|dst {mask}, src1, src2}
VPBLENDMWZrrkz [HasBWI]
vpblendmw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPBROADCASTBZrm [HasBWI]
vpbroadcastb {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
VPBROADCASTBZrmk [HasBWI]
vpbroadcastb {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPBROADCASTBZrmkz [HasBWI]
vpbroadcastb {src, dst {mask} {z}|dst {mask} {z}, src}
VPBROADCASTBZrr [HasBWI]
vpbroadcastb {src, dst|dst, src}
VPBROADCASTBZrrk [HasBWI]
vpbroadcastb {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPBROADCASTBZrrkz [HasBWI]
vpbroadcastb {src, dst {mask} {z}|dst {mask} {z}, src}
VPBROADCASTBrZrr [HasBWI]
vpbroadcastb {src, dst|dst, src}
VPBROADCASTBrZrrk [HasBWI]
vpbroadcastb {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPBROADCASTBrZrrkz [HasBWI]
vpbroadcastb {src, dst {mask} {z}|dst {mask} {z}, src}
VPBROADCASTWZrm [HasBWI]
vpbroadcastw {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
VPBROADCASTWZrmk [HasBWI]
vpbroadcastw {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPBROADCASTWZrmkz [HasBWI]
vpbroadcastw {src, dst {mask} {z}|dst {mask} {z}, src}
VPBROADCASTWZrr [HasBWI]
vpbroadcastw {src, dst|dst, src}
VPBROADCASTWZrrk [HasBWI]
vpbroadcastw {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPBROADCASTWZrrkz [HasBWI]
vpbroadcastw {src, dst {mask} {z}|dst {mask} {z}, src}
VPBROADCASTWrZrr [HasBWI]
vpbroadcastw {src, dst|dst, src}
VPBROADCASTWrZrrk [HasBWI]
vpbroadcastw {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPBROADCASTWrZrrkz [HasBWI]
vpbroadcastw {src, dst {mask} {z}|dst {mask} {z}, src}
VPCMPBZrmi [HasBWI]
vpcmpb {cc, src2, src1, dst|dst, src1, src2, cc}
VPCMPBZrmik [HasBWI]
vpcmpb {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
VPCMPBZrri [HasBWI]
vpcmpb {cc, src2, src1, dst|dst, src1, src2, cc}
VPCMPBZrrik [HasBWI]
vpcmpb {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
VPCMPEQBZrm [HasBWI]
vpcmpeqb {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VPCMPEQBZrmk [HasBWI]
vpcmpeqb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
VPCMPEQBZrr [HasBWI]
vpcmpeqb {src2, src1, dst|dst, src1, src2}
VPCMPEQBZrrk [HasBWI]
vpcmpeqb {src2, src1, dst {mask}|dst {mask}, src1, src2}
VPCMPEQWZrm [HasBWI]
vpcmpeqw {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VPCMPEQWZrmk [HasBWI]
vpcmpeqw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
VPCMPEQWZrr [HasBWI]
vpcmpeqw {src2, src1, dst|dst, src1, src2}
VPCMPEQWZrrk [HasBWI]
vpcmpeqw {src2, src1, dst {mask}|dst {mask}, src1, src2}
VPCMPGTBZrm [HasBWI]
vpcmpgtb {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VPCMPGTBZrmk [HasBWI]
vpcmpgtb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
VPCMPGTBZrr [HasBWI]
vpcmpgtb {src2, src1, dst|dst, src1, src2}
VPCMPGTBZrrk [HasBWI]
vpcmpgtb {src2, src1, dst {mask}|dst {mask}, src1, src2}
VPCMPGTWZrm [HasBWI]
vpcmpgtw {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VPCMPGTWZrmk [HasBWI]
vpcmpgtw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
VPCMPGTWZrr [HasBWI]
vpcmpgtw {src2, src1, dst|dst, src1, src2}
VPCMPGTWZrrk [HasBWI]
vpcmpgtw {src2, src1, dst {mask}|dst {mask}, src1, src2}
VPCMPUBZrmi [HasBWI]
vpcmpub {cc, src2, src1, dst|dst, src1, src2, cc}
VPCMPUBZrmik [HasBWI]
vpcmpub {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
VPCMPUBZrri [HasBWI]
vpcmpub {cc, src2, src1, dst|dst, src1, src2, cc}
VPCMPUBZrrik [HasBWI]
vpcmpub {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
VPCMPUWZrmi [HasBWI]
vpcmpuw {cc, src2, src1, dst|dst, src1, src2, cc}
VPCMPUWZrmik [HasBWI]
vpcmpuw {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
VPCMPUWZrri [HasBWI]
vpcmpuw {cc, src2, src1, dst|dst, src1, src2, cc}
VPCMPUWZrrik [HasBWI]
vpcmpuw {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
VPCMPWZrmi [HasBWI]
vpcmpw {cc, src2, src1, dst|dst, src1, src2, cc}
VPCMPWZrmik [HasBWI]
vpcmpw {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
VPCMPWZrri [HasBWI]
vpcmpw {cc, src2, src1, dst|dst, src1, src2, cc}
VPCMPWZrrik [HasBWI]
vpcmpw {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
VPERMI2WZrm [HasBWI]
vpermi2w {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2WZrmk [HasBWI]
vpermi2w {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2WZrmkz [HasBWI]
vpermi2w {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2WZrr [HasBWI]
vpermi2w {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMI2WZrrk [HasBWI]
vpermi2w {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMI2WZrrkz [HasBWI]
vpermi2w {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2WZrm [HasBWI]
vpermt2w {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2WZrmk [HasBWI]
vpermt2w {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2WZrmkz [HasBWI]
vpermt2w {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2WZrr [HasBWI]
vpermt2w {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2WZrrk [HasBWI]
vpermt2w {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2WZrrkz [HasBWI]
vpermt2w {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMWZrm [HasBWI]
vpermw {src2, src1, dst|dst, src1, src2}
VPERMWZrmk [HasBWI]
vpermw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPERMWZrmkz [HasBWI]
vpermw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPERMWZrr [HasBWI]
vpermw {src2, src1, dst|dst, src1, src2}
VPERMWZrrk [HasBWI]
vpermw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPERMWZrrkz [HasBWI]
vpermw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPEXTRBZmri [HasBWI]
vpextrb {src2, src1, dst|dst, src1, src2}
VPEXTRBZrri [HasBWI]
vpextrb {src2, src1, dst|dst, src1, src2}
VPEXTRWZmri [HasBWI]
vpextrw {src2, src1, dst|dst, src1, src2}
VPEXTRWZrri [HasBWI]
vpextrw {src2, src1, dst|dst, src1, src2}
VPINSRBZrmi [HasBWI]
vpinsrb {src3, src2, src1, dst|dst, src1, src2, src3}
VPINSRBZrri [HasBWI]
vpinsrb {src3, src2, src1, dst|dst, src1, src2, src3}
VPINSRWZrmi [HasBWI]
vpinsrw {src3, src2, src1, dst|dst, src1, src2, src3}
VPINSRWZrri [HasBWI]
vpinsrw {src3, src2, src1, dst|dst, src1, src2, src3}
VPMADDUBSWZrm [HasBWI]
vpmaddubsw {src2, src1, dst|dst, src1, src2}
VPMADDUBSWZrmk [HasBWI]
vpmaddubsw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMADDUBSWZrmkz [HasBWI]
vpmaddubsw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMADDUBSWZrr [HasBWI]
vpmaddubsw {src2, src1, dst|dst, src1, src2}
VPMADDUBSWZrrk [HasBWI]
vpmaddubsw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMADDUBSWZrrkz [HasBWI]
vpmaddubsw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMADDWDZrm [HasBWI]
vpmaddwd {src2, src1, dst|dst, src1, src2}
VPMADDWDZrmk [HasBWI]
vpmaddwd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMADDWDZrmkz [HasBWI]
vpmaddwd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMADDWDZrr [HasBWI]
vpmaddwd {src2, src1, dst|dst, src1, src2}
VPMADDWDZrrk [HasBWI]
vpmaddwd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMADDWDZrrkz [HasBWI]
vpmaddwd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMAXSBZrm [HasBWI]
vpmaxsb {src2, src1, dst|dst, src1, src2}
VPMAXSBZrmk [HasBWI]
vpmaxsb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMAXSBZrmkz [HasBWI]
vpmaxsb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMAXSBZrr [HasBWI]
vpmaxsb {src2, src1, dst|dst, src1, src2}
VPMAXSBZrrk [HasBWI]
vpmaxsb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMAXSBZrrkz [HasBWI]
vpmaxsb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMAXSWZrm [HasBWI]
vpmaxsw {src2, src1, dst|dst, src1, src2}
VPMAXSWZrmk [HasBWI]
vpmaxsw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMAXSWZrmkz [HasBWI]
vpmaxsw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMAXSWZrr [HasBWI]
vpmaxsw {src2, src1, dst|dst, src1, src2}
VPMAXSWZrrk [HasBWI]
vpmaxsw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMAXSWZrrkz [HasBWI]
vpmaxsw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMAXUBZrm [HasBWI]
vpmaxub {src2, src1, dst|dst, src1, src2}
VPMAXUBZrmk [HasBWI]
vpmaxub {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMAXUBZrmkz [HasBWI]
vpmaxub {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMAXUBZrr [HasBWI]
vpmaxub {src2, src1, dst|dst, src1, src2}
VPMAXUBZrrk [HasBWI]
vpmaxub {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMAXUBZrrkz [HasBWI]
vpmaxub {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMAXUWZrm [HasBWI]
vpmaxuw {src2, src1, dst|dst, src1, src2}
VPMAXUWZrmk [HasBWI]
vpmaxuw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMAXUWZrmkz [HasBWI]
vpmaxuw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMAXUWZrr [HasBWI]
vpmaxuw {src2, src1, dst|dst, src1, src2}
VPMAXUWZrrk [HasBWI]
vpmaxuw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMAXUWZrrkz [HasBWI]
vpmaxuw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMINSBZrm [HasBWI]
vpminsb {src2, src1, dst|dst, src1, src2}
VPMINSBZrmk [HasBWI]
vpminsb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMINSBZrmkz [HasBWI]
vpminsb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMINSBZrr [HasBWI]
vpminsb {src2, src1, dst|dst, src1, src2}
VPMINSBZrrk [HasBWI]
vpminsb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMINSBZrrkz [HasBWI]
vpminsb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMINSWZrm [HasBWI]
vpminsw {src2, src1, dst|dst, src1, src2}
VPMINSWZrmk [HasBWI]
vpminsw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMINSWZrmkz [HasBWI]
vpminsw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMINSWZrr [HasBWI]
vpminsw {src2, src1, dst|dst, src1, src2}
VPMINSWZrrk [HasBWI]
vpminsw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMINSWZrrkz [HasBWI]
vpminsw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMINUBZrm [HasBWI]
vpminub {src2, src1, dst|dst, src1, src2}
VPMINUBZrmk [HasBWI]
vpminub {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMINUBZrmkz [HasBWI]
vpminub {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMINUBZrr [HasBWI]
vpminub {src2, src1, dst|dst, src1, src2}
VPMINUBZrrk [HasBWI]
vpminub {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMINUBZrrkz [HasBWI]
vpminub {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMINUWZrm [HasBWI]
vpminuw {src2, src1, dst|dst, src1, src2}
VPMINUWZrmk [HasBWI]
vpminuw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMINUWZrmkz [HasBWI]
vpminuw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMINUWZrr [HasBWI]
vpminuw {src2, src1, dst|dst, src1, src2}
VPMINUWZrrk [HasBWI]
vpminuw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMINUWZrrkz [HasBWI]
vpminuw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMOVB2MZkr [HasBWI]
vpmovb2m {src, dst|dst, src}
VPMOVM2BZrk [HasBWI]
vpmovm2b {src, dst|dst, src}
VPMOVM2WZrk [HasBWI]
vpmovm2w {src, dst|dst, src}
VPMOVSWBZmr [HasBWI]
vpmovswb {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VPMOVSWBZmrk [HasBWI]
vpmovswb {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
VPMOVSWBZrr [HasBWI]
vpmovswb {src, dst|dst, src}
VPMOVSWBZrrk [HasBWI]
vpmovswb {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVSWBZrrkz [HasBWI]
vpmovswb {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVSXBWZrm [HasBWI]
vpmovsxbw {src, dst|dst, src}
VPMOVSXBWZrmk [HasBWI]
vpmovsxbw {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVSXBWZrmkz [HasBWI]
vpmovsxbw {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVSXBWZrr [HasBWI]
vpmovsxbw {src, dst|dst, src}
VPMOVSXBWZrrk [HasBWI]
vpmovsxbw {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVSXBWZrrkz [HasBWI]
vpmovsxbw {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVUSWBZmr [HasBWI]
vpmovuswb {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VPMOVUSWBZmrk [HasBWI]
vpmovuswb {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
VPMOVUSWBZrr [HasBWI]
vpmovuswb {src, dst|dst, src}
VPMOVUSWBZrrk [HasBWI]
vpmovuswb {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVUSWBZrrkz [HasBWI]
vpmovuswb {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVW2MZkr [HasBWI]
vpmovw2m {src, dst|dst, src}
VPMOVWBZmr [HasBWI]
vpmovwb {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VPMOVWBZmrk [HasBWI]
vpmovwb {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayStore |
VPMOVWBZrr [HasBWI]
vpmovwb {src, dst|dst, src}
VPMOVWBZrrk [HasBWI]
vpmovwb {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVWBZrrkz [HasBWI]
vpmovwb {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVZXBWZrm [HasBWI]
vpmovzxbw {src, dst|dst, src}
VPMOVZXBWZrmk [HasBWI]
vpmovzxbw {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVZXBWZrmkz [HasBWI]
vpmovzxbw {src, dst {mask} {z}|dst {mask} {z}, src}
VPMOVZXBWZrr [HasBWI]
vpmovzxbw {src, dst|dst, src}
VPMOVZXBWZrrk [HasBWI]
vpmovzxbw {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VPMOVZXBWZrrkz [HasBWI]
vpmovzxbw {src, dst {mask} {z}|dst {mask} {z}, src}
VPMULHRSWZrm [HasBWI]
vpmulhrsw {src2, src1, dst|dst, src1, src2}
VPMULHRSWZrmk [HasBWI]
vpmulhrsw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMULHRSWZrmkz [HasBWI]
vpmulhrsw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMULHRSWZrr [HasBWI]
vpmulhrsw {src2, src1, dst|dst, src1, src2}
VPMULHRSWZrrk [HasBWI]
vpmulhrsw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMULHRSWZrrkz [HasBWI]
vpmulhrsw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMULHUWZrm [HasBWI]
vpmulhuw {src2, src1, dst|dst, src1, src2}
VPMULHUWZrmk [HasBWI]
vpmulhuw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMULHUWZrmkz [HasBWI]
vpmulhuw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMULHUWZrr [HasBWI]
vpmulhuw {src2, src1, dst|dst, src1, src2}
VPMULHUWZrrk [HasBWI]
vpmulhuw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMULHUWZrrkz [HasBWI]
vpmulhuw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMULHWZrm [HasBWI]
vpmulhw {src2, src1, dst|dst, src1, src2}
VPMULHWZrmk [HasBWI]
vpmulhw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMULHWZrmkz [HasBWI]
vpmulhw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMULHWZrr [HasBWI]
vpmulhw {src2, src1, dst|dst, src1, src2}
VPMULHWZrrk [HasBWI]
vpmulhw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMULHWZrrkz [HasBWI]
vpmulhw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMULLWZrm [HasBWI]
vpmullw {src2, src1, dst|dst, src1, src2}
VPMULLWZrmk [HasBWI]
vpmullw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMULLWZrmkz [HasBWI]
vpmullw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMULLWZrr [HasBWI]
vpmullw {src2, src1, dst|dst, src1, src2}
VPMULLWZrrk [HasBWI]
vpmullw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMULLWZrrkz [HasBWI]
vpmullw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSADBWZrm [HasBWI]
vpsadbw {src2, src1, dst|dst, src1, src2}
VPSADBWZrr [HasBWI]
vpsadbw {src2, src1, dst|dst, src1, src2}
VPSHUFBZrm [HasBWI]
vpshufb {src2, src1, dst|dst, src1, src2}
VPSHUFBZrmk [HasBWI]
vpshufb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSHUFBZrmkz [HasBWI]
vpshufb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSHUFBZrr [HasBWI]
vpshufb {src2, src1, dst|dst, src1, src2}
VPSHUFBZrrk [HasBWI]
vpshufb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSHUFBZrrkz [HasBWI]
vpshufb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSHUFHWZmi [HasBWI]
vpshufhw {src2, src1, dst|dst, src1, src2}
VPSHUFHWZmik [HasBWI]
vpshufhw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSHUFHWZmikz [HasBWI]
vpshufhw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSHUFHWZri [HasBWI]
vpshufhw {src2, src1, dst|dst, src1, src2}
VPSHUFHWZrik [HasBWI]
vpshufhw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSHUFHWZrikz [HasBWI]
vpshufhw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSHUFLWZmi [HasBWI]
vpshuflw {src2, src1, dst|dst, src1, src2}
VPSHUFLWZmik [HasBWI]
vpshuflw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSHUFLWZmikz [HasBWI]
vpshuflw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSHUFLWZri [HasBWI]
vpshuflw {src2, src1, dst|dst, src1, src2}
VPSHUFLWZrik [HasBWI]
vpshuflw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSHUFLWZrikz [HasBWI]
vpshuflw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSLLDQZmi [HasBWI]
vpslldq {src2, src1, dst|dst, src1, src2}
VPSLLDQZri [HasBWI]
vpslldq {src2, src1, dst|dst, src1, src2}
VPSLLVWZrm [HasBWI]
vpsllvw {src2, src1, dst|dst, src1, src2}
VPSLLVWZrmk [HasBWI]
vpsllvw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSLLVWZrmkz [HasBWI]
vpsllvw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSLLVWZrr [HasBWI]
vpsllvw {src2, src1, dst|dst, src1, src2}
VPSLLVWZrrk [HasBWI]
vpsllvw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSLLVWZrrkz [HasBWI]
vpsllvw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSLLWZmi [HasBWI]
vpsllw {src2, src1, dst|dst, src1, src2}
VPSLLWZmik [HasBWI]
vpsllw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSLLWZmikz [HasBWI]
vpsllw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSLLWZri [HasBWI]
vpsllw {src2, src1, dst|dst, src1, src2}
VPSLLWZrik [HasBWI]
vpsllw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSLLWZrikz [HasBWI]
vpsllw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSLLWZrm [HasBWI]
vpsllw {src2, src1, dst|dst, src1, src2}
VPSLLWZrmk [HasBWI]
vpsllw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSLLWZrmkz [HasBWI]
vpsllw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSLLWZrr [HasBWI]
vpsllw {src2, src1, dst|dst, src1, src2}
VPSLLWZrrk [HasBWI]
vpsllw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSLLWZrrkz [HasBWI]
vpsllw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRAVWZrm [HasBWI]
vpsravw {src2, src1, dst|dst, src1, src2}
VPSRAVWZrmk [HasBWI]
vpsravw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRAVWZrmkz [HasBWI]
vpsravw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRAVWZrr [HasBWI]
vpsravw {src2, src1, dst|dst, src1, src2}
VPSRAVWZrrk [HasBWI]
vpsravw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRAVWZrrkz [HasBWI]
vpsravw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRAWZmi [HasBWI]
vpsraw {src2, src1, dst|dst, src1, src2}
VPSRAWZmik [HasBWI]
vpsraw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRAWZmikz [HasBWI]
vpsraw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRAWZri [HasBWI]
vpsraw {src2, src1, dst|dst, src1, src2}
VPSRAWZrik [HasBWI]
vpsraw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRAWZrikz [HasBWI]
vpsraw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRAWZrm [HasBWI]
vpsraw {src2, src1, dst|dst, src1, src2}
VPSRAWZrmk [HasBWI]
vpsraw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRAWZrmkz [HasBWI]
vpsraw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRAWZrr [HasBWI]
vpsraw {src2, src1, dst|dst, src1, src2}
VPSRAWZrrk [HasBWI]
vpsraw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRAWZrrkz [HasBWI]
vpsraw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRLDQZmi [HasBWI]
vpsrldq {src2, src1, dst|dst, src1, src2}
VPSRLDQZri [HasBWI]
vpsrldq {src2, src1, dst|dst, src1, src2}
VPSRLVWZrm [HasBWI]
vpsrlvw {src2, src1, dst|dst, src1, src2}
VPSRLVWZrmk [HasBWI]
vpsrlvw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRLVWZrmkz [HasBWI]
vpsrlvw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRLVWZrr [HasBWI]
vpsrlvw {src2, src1, dst|dst, src1, src2}
VPSRLVWZrrk [HasBWI]
vpsrlvw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRLVWZrrkz [HasBWI]
vpsrlvw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRLWZmi [HasBWI]
vpsrlw {src2, src1, dst|dst, src1, src2}
VPSRLWZmik [HasBWI]
vpsrlw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRLWZmikz [HasBWI]
vpsrlw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRLWZri [HasBWI]
vpsrlw {src2, src1, dst|dst, src1, src2}
VPSRLWZrik [HasBWI]
vpsrlw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRLWZrikz [HasBWI]
vpsrlw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRLWZrm [HasBWI]
vpsrlw {src2, src1, dst|dst, src1, src2}
VPSRLWZrmk [HasBWI]
vpsrlw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRLWZrmkz [HasBWI]
vpsrlw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSRLWZrr [HasBWI]
vpsrlw {src2, src1, dst|dst, src1, src2}
VPSRLWZrrk [HasBWI]
vpsrlw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSRLWZrrkz [HasBWI]
vpsrlw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSUBBZrm [HasBWI]
vpsubb {src2, src1, dst|dst, src1, src2}
VPSUBBZrmk [HasBWI]
vpsubb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSUBBZrmkz [HasBWI]
vpsubb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSUBBZrr [HasBWI]
vpsubb {src2, src1, dst|dst, src1, src2}
VPSUBBZrrk [HasBWI]
vpsubb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSUBBZrrkz [HasBWI]
vpsubb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSUBSBZrm [HasBWI]
vpsubsb {src2, src1, dst|dst, src1, src2}
VPSUBSBZrmk [HasBWI]
vpsubsb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSUBSBZrmkz [HasBWI]
vpsubsb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSUBSBZrr [HasBWI]
vpsubsb {src2, src1, dst|dst, src1, src2}
VPSUBSBZrrk [HasBWI]
vpsubsb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSUBSBZrrkz [HasBWI]
vpsubsb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSUBSWZrm [HasBWI]
vpsubsw {src2, src1, dst|dst, src1, src2}
VPSUBSWZrmk [HasBWI]
vpsubsw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSUBSWZrmkz [HasBWI]
vpsubsw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSUBSWZrr [HasBWI]
vpsubsw {src2, src1, dst|dst, src1, src2}
VPSUBSWZrrk [HasBWI]
vpsubsw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSUBSWZrrkz [HasBWI]
vpsubsw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSUBUSBZrm [HasBWI]
vpsubusb {src2, src1, dst|dst, src1, src2}
VPSUBUSBZrmk [HasBWI]
vpsubusb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSUBUSBZrmkz [HasBWI]
vpsubusb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSUBUSBZrr [HasBWI]
vpsubusb {src2, src1, dst|dst, src1, src2}
VPSUBUSBZrrk [HasBWI]
vpsubusb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSUBUSBZrrkz [HasBWI]
vpsubusb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSUBUSWZrm [HasBWI]
vpsubusw {src2, src1, dst|dst, src1, src2}
VPSUBUSWZrmk [HasBWI]
vpsubusw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSUBUSWZrmkz [HasBWI]
vpsubusw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSUBUSWZrr [HasBWI]
vpsubusw {src2, src1, dst|dst, src1, src2}
VPSUBUSWZrrk [HasBWI]
vpsubusw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSUBUSWZrrkz [HasBWI]
vpsubusw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSUBWZrm [HasBWI]
vpsubw {src2, src1, dst|dst, src1, src2}
VPSUBWZrmk [HasBWI]
vpsubw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSUBWZrmkz [HasBWI]
vpsubw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPSUBWZrr [HasBWI]
vpsubw {src2, src1, dst|dst, src1, src2}
VPSUBWZrrk [HasBWI]
vpsubw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPSUBWZrrkz [HasBWI]
vpsubw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPTESTMBZrm [HasBWI]
vptestmb {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VPTESTMBZrmk [HasBWI]
vptestmb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
VPTESTMBZrr [HasBWI]
vptestmb {src2, src1, dst|dst, src1, src2}
VPTESTMBZrrk [HasBWI]
vptestmb {src2, src1, dst {mask}|dst {mask}, src1, src2}
VPTESTMWZrm [HasBWI]
vptestmw {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VPTESTMWZrmk [HasBWI]
vptestmw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
VPTESTMWZrr [HasBWI]
vptestmw {src2, src1, dst|dst, src1, src2}
VPTESTMWZrrk [HasBWI]
vptestmw {src2, src1, dst {mask}|dst {mask}, src1, src2}
VPTESTNMBZrm [HasBWI]
vptestnmb {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VPTESTNMBZrmk [HasBWI]
vptestnmb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
VPTESTNMBZrr [HasBWI]
vptestnmb {src2, src1, dst|dst, src1, src2}
VPTESTNMBZrrk [HasBWI]
vptestnmb {src2, src1, dst {mask}|dst {mask}, src1, src2}
VPTESTNMWZrm [HasBWI]
vptestnmw {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VPTESTNMWZrmk [HasBWI]
vptestnmw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
VPTESTNMWZrr [HasBWI]
vptestnmw {src2, src1, dst|dst, src1, src2}
VPTESTNMWZrrk [HasBWI]
vptestnmw {src2, src1, dst {mask}|dst {mask}, src1, src2}
VPUNPCKHBWZrm [HasBWI]
vpunpckhbw {src2, src1, dst|dst, src1, src2}
VPUNPCKHBWZrmk [HasBWI]
vpunpckhbw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPUNPCKHBWZrmkz [HasBWI]
vpunpckhbw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPUNPCKHBWZrr [HasBWI]
vpunpckhbw {src2, src1, dst|dst, src1, src2}
VPUNPCKHBWZrrk [HasBWI]
vpunpckhbw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPUNPCKHBWZrrkz [HasBWI]
vpunpckhbw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPUNPCKHWDZrm [HasBWI]
vpunpckhwd {src2, src1, dst|dst, src1, src2}
VPUNPCKHWDZrmk [HasBWI]
vpunpckhwd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPUNPCKHWDZrmkz [HasBWI]
vpunpckhwd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPUNPCKHWDZrr [HasBWI]
vpunpckhwd {src2, src1, dst|dst, src1, src2}
VPUNPCKHWDZrrk [HasBWI]
vpunpckhwd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPUNPCKHWDZrrkz [HasBWI]
vpunpckhwd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPUNPCKLBWZrm [HasBWI]
vpunpcklbw {src2, src1, dst|dst, src1, src2}
VPUNPCKLBWZrmk [HasBWI]
vpunpcklbw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPUNPCKLBWZrmkz [HasBWI]
vpunpcklbw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPUNPCKLBWZrr [HasBWI]
vpunpcklbw {src2, src1, dst|dst, src1, src2}
VPUNPCKLBWZrrk [HasBWI]
vpunpcklbw {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPUNPCKLBWZrrkz [HasBWI]
vpunpcklbw {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPUNPCKLWDZrm [HasBWI]
vpunpcklwd {src2, src1, dst|dst, src1, src2}
VPUNPCKLWDZrmk [HasBWI]
vpunpcklwd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPUNPCKLWDZrmkz [HasBWI]
vpunpcklwd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPUNPCKLWDZrr [HasBWI]
vpunpcklwd {src2, src1, dst|dst, src1, src2}
VPUNPCKLWDZrrk [HasBWI]
vpunpcklwd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPUNPCKLWDZrrkz [HasBWI]
vpunpcklwd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
KMOVDkk [HasBWI, NoEGPR]
kmovd {src, dst|dst, src}
|
Note
|
Properties: isMoveReg |
KMOVDkm [HasBWI, NoEGPR]
kmovd {src, dst|dst, src}
KMOVDkr [HasBWI, NoEGPR]
kmovd {src, dst|dst, src}
KMOVDmk [HasBWI, NoEGPR]
kmovd {src, dst|dst, src}
KMOVDrk [HasBWI, NoEGPR]
kmovd {src, dst|dst, src}
KMOVQkk [HasBWI, NoEGPR]
kmovq {src, dst|dst, src}
|
Note
|
Properties: isMoveReg |
KMOVQkm [HasBWI, NoEGPR]
kmovq {src, dst|dst, src}
KMOVQkr [HasBWI, NoEGPR]
kmovq {src, dst|dst, src}
KMOVQmk [HasBWI, NoEGPR]
kmovq {src, dst|dst, src}
KMOVQrk [HasBWI, NoEGPR]
kmovq {src, dst|dst, src}
KADDBkk [HasDQI]
kaddb {src2, src1, dst|dst, src1, src2}
KADDWkk [HasDQI]
kaddw {src2, src1, dst|dst, src1, src2}
KANDBkk [HasDQI]
kandb {src2, src1, dst|dst, src1, src2}
KANDNBkk [HasDQI]
kandnb {src2, src1, dst|dst, src1, src2}
KNOTBkk [HasDQI]
knotb {src, dst|dst, src}
KORBkk [HasDQI]
korb {src2, src1, dst|dst, src1, src2}
KORTESTBkk [HasDQI]
kortestb {src2, src1|src1, src2}
KSHIFTLBki [HasDQI]
kshiftlb {imm, src, dst|dst, src, imm}
KSHIFTRBki [HasDQI]
kshiftrb {imm, src, dst|dst, src, imm}
KTESTBkk [HasDQI]
ktestb {src2, src1|src1, src2}
KTESTWkk [HasDQI]
ktestw {src2, src1|src1, src2}
KXNORBkk [HasDQI]
kxnorb {src2, src1, dst|dst, src1, src2}
KXORBkk [HasDQI]
kxorb {src2, src1, dst|dst, src1, src2}
VANDNPDZrm [HasDQI]
vandnpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VANDNPDZrmb [HasDQI]
vandnpd {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
VANDNPDZrmbk [HasDQI]
vandnpd {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VANDNPDZrmbkz [HasDQI]
vandnpd {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
VANDNPDZrmk [HasDQI]
vandnpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VANDNPDZrmkz [HasDQI]
vandnpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VANDNPDZrr [HasDQI]
vandnpd {src2, src1, dst|dst, src1, src2}
VANDNPDZrrk [HasDQI]
vandnpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VANDNPDZrrkz [HasDQI]
vandnpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VANDNPSZrm [HasDQI]
vandnps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VANDNPSZrmb [HasDQI]
vandnps {src2{1to16}, src1, dst|dst, src1, src2{1to16}}
|
Note
|
Properties: mayLoad |
VANDNPSZrmbk [HasDQI]
vandnps {src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VANDNPSZrmbkz [HasDQI]
vandnps {src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}}
|
Note
|
Properties: mayLoad |
VANDNPSZrmk [HasDQI]
vandnps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VANDNPSZrmkz [HasDQI]
vandnps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VANDNPSZrr [HasDQI]
vandnps {src2, src1, dst|dst, src1, src2}
VANDNPSZrrk [HasDQI]
vandnps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VANDNPSZrrkz [HasDQI]
vandnps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VANDPDZrm [HasDQI]
vandpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VANDPDZrmb [HasDQI]
vandpd {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
VANDPDZrmbk [HasDQI]
vandpd {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VANDPDZrmbkz [HasDQI]
vandpd {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
VANDPDZrmk [HasDQI]
vandpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VANDPDZrmkz [HasDQI]
vandpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VANDPDZrr [HasDQI]
vandpd {src2, src1, dst|dst, src1, src2}
VANDPDZrrk [HasDQI]
vandpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VANDPDZrrkz [HasDQI]
vandpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VANDPSZrm [HasDQI]
vandps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VANDPSZrmb [HasDQI]
vandps {src2{1to16}, src1, dst|dst, src1, src2{1to16}}
|
Note
|
Properties: mayLoad |
VANDPSZrmbk [HasDQI]
vandps {src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VANDPSZrmbkz [HasDQI]
vandps {src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}}
|
Note
|
Properties: mayLoad |
VANDPSZrmk [HasDQI]
vandps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VANDPSZrmkz [HasDQI]
vandps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VANDPSZrr [HasDQI]
vandps {src2, src1, dst|dst, src1, src2}
VANDPSZrrk [HasDQI]
vandps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VANDPSZrrkz [HasDQI]
vandps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VBROADCASTF32X2Zrm [HasDQI]
vbroadcastf32x2 {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
VBROADCASTF32X2Zrmk [HasDQI]
vbroadcastf32x2 {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VBROADCASTF32X2Zrmkz [HasDQI]
vbroadcastf32x2 {src, dst {mask} {z}|dst {mask} {z}, src}
VBROADCASTF32X2Zrr [HasDQI]
vbroadcastf32x2 {src, dst|dst, src}
VBROADCASTF32X2Zrrk [HasDQI]
vbroadcastf32x2 {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VBROADCASTF32X2Zrrkz [HasDQI]
vbroadcastf32x2 {src, dst {mask} {z}|dst {mask} {z}, src}
VBROADCASTF32X8Zrm [HasDQI]
vbroadcastf32x8 {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
VBROADCASTF32X8Zrmk [HasDQI]
vbroadcastf32x8 {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VBROADCASTF32X8Zrmkz [HasDQI]
vbroadcastf32x8 {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayLoad |
VBROADCASTF64X2Zrm [HasDQI]
vbroadcastf64x2 {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
VBROADCASTF64X2Zrmk [HasDQI]
vbroadcastf64x2 {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VBROADCASTF64X2Zrmkz [HasDQI]
vbroadcastf64x2 {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayLoad |
VBROADCASTI32X2Zrm [HasDQI]
vbroadcasti32x2 {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
VBROADCASTI32X2Zrmk [HasDQI]
vbroadcasti32x2 {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VBROADCASTI32X2Zrmkz [HasDQI]
vbroadcasti32x2 {src, dst {mask} {z}|dst {mask} {z}, src}
VBROADCASTI32X2Zrr [HasDQI]
vbroadcasti32x2 {src, dst|dst, src}
VBROADCASTI32X2Zrrk [HasDQI]
vbroadcasti32x2 {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VBROADCASTI32X2Zrrkz [HasDQI]
vbroadcasti32x2 {src, dst {mask} {z}|dst {mask} {z}, src}
VBROADCASTI32X8Zrm [HasDQI]
vbroadcasti32x8 {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
VBROADCASTI32X8Zrmk [HasDQI]
vbroadcasti32x8 {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VBROADCASTI32X8Zrmkz [HasDQI]
vbroadcasti32x8 {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayLoad |
VBROADCASTI64X2Zrm [HasDQI]
vbroadcasti64x2 {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
VBROADCASTI64X2Zrmk [HasDQI]
vbroadcasti64x2 {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VBROADCASTI64X2Zrmkz [HasDQI]
vbroadcasti64x2 {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayLoad |
VCVTPD2QQZrm [HasDQI]
vcvtpd2qq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2QQZrmb [HasDQI]
vcvtpd2qq {src{1to8}, dst|dst, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2QQZrmbk [HasDQI]
vcvtpd2qq {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPD2QQZrmbkz [HasDQI]
vcvtpd2qq {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2QQZrmk [HasDQI]
vcvtpd2qq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPD2QQZrmkz [HasDQI]
vcvtpd2qq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2QQZrr [HasDQI]
vcvtpd2qq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2QQZrrb [HasDQI]
vcvtpd2qq {rc, src, dst|dst, src, rc}
VCVTPD2QQZrrbk [HasDQI]
vcvtpd2qq {rc, src, dst {mask}|dst {mask}, src, rc}
|
Note
|
Constraints: src0 = dst |
VCVTPD2QQZrrbkz [HasDQI]
vcvtpd2qq {rc, src, dst {mask} {z}|dst {mask} {z}, src, rc}
VCVTPD2QQZrrk [HasDQI]
vcvtpd2qq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPD2QQZrrkz [HasDQI]
vcvtpd2qq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2UQQZrm [HasDQI]
vcvtpd2uqq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2UQQZrmb [HasDQI]
vcvtpd2uqq {src{1to8}, dst|dst, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2UQQZrmbk [HasDQI]
vcvtpd2uqq {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPD2UQQZrmbkz [HasDQI]
vcvtpd2uqq {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2UQQZrmk [HasDQI]
vcvtpd2uqq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPD2UQQZrmkz [HasDQI]
vcvtpd2uqq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2UQQZrr [HasDQI]
vcvtpd2uqq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2UQQZrrb [HasDQI]
vcvtpd2uqq {rc, src, dst|dst, src, rc}
VCVTPD2UQQZrrbk [HasDQI]
vcvtpd2uqq {rc, src, dst {mask}|dst {mask}, src, rc}
|
Note
|
Constraints: src0 = dst |
VCVTPD2UQQZrrbkz [HasDQI]
vcvtpd2uqq {rc, src, dst {mask} {z}|dst {mask} {z}, src, rc}
VCVTPD2UQQZrrk [HasDQI]
vcvtpd2uqq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPD2UQQZrrkz [HasDQI]
vcvtpd2uqq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2QQZrm [HasDQI]
vcvtps2qq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2QQZrmb [HasDQI]
vcvtps2qq {src{1to8}, dst|dst, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2QQZrmbk [HasDQI]
vcvtps2qq {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPS2QQZrmbkz [HasDQI]
vcvtps2qq {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2QQZrmk [HasDQI]
vcvtps2qq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPS2QQZrmkz [HasDQI]
vcvtps2qq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2QQZrr [HasDQI]
vcvtps2qq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2QQZrrb [HasDQI]
vcvtps2qq {rc, src, dst|dst, src, rc}
VCVTPS2QQZrrbk [HasDQI]
vcvtps2qq {rc, src, dst {mask}|dst {mask}, src, rc}
|
Note
|
Constraints: src0 = dst |
VCVTPS2QQZrrbkz [HasDQI]
vcvtps2qq {rc, src, dst {mask} {z}|dst {mask} {z}, src, rc}
VCVTPS2QQZrrk [HasDQI]
vcvtps2qq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPS2QQZrrkz [HasDQI]
vcvtps2qq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2UQQZrm [HasDQI]
vcvtps2uqq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2UQQZrmb [HasDQI]
vcvtps2uqq {src{1to8}, dst|dst, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2UQQZrmbk [HasDQI]
vcvtps2uqq {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPS2UQQZrmbkz [HasDQI]
vcvtps2uqq {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2UQQZrmk [HasDQI]
vcvtps2uqq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPS2UQQZrmkz [HasDQI]
vcvtps2uqq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2UQQZrr [HasDQI]
vcvtps2uqq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2UQQZrrb [HasDQI]
vcvtps2uqq {rc, src, dst|dst, src, rc}
VCVTPS2UQQZrrbk [HasDQI]
vcvtps2uqq {rc, src, dst {mask}|dst {mask}, src, rc}
|
Note
|
Constraints: src0 = dst |
VCVTPS2UQQZrrbkz [HasDQI]
vcvtps2uqq {rc, src, dst {mask} {z}|dst {mask} {z}, src, rc}
VCVTPS2UQQZrrk [HasDQI]
vcvtps2uqq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTPS2UQQZrrkz [HasDQI]
vcvtps2uqq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTQQ2PDZrm [HasDQI]
vcvtqq2pd {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTQQ2PDZrmb [HasDQI]
vcvtqq2pd {src{1to8}, dst|dst, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTQQ2PDZrmbk [HasDQI]
vcvtqq2pd {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTQQ2PDZrmbkz [HasDQI]
vcvtqq2pd {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTQQ2PDZrmk [HasDQI]
vcvtqq2pd {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTQQ2PDZrmkz [HasDQI]
vcvtqq2pd {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTQQ2PDZrr [HasDQI]
vcvtqq2pd {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTQQ2PDZrrb [HasDQI]
vcvtqq2pd {rc, src, dst|dst, src, rc}
VCVTQQ2PDZrrbk [HasDQI]
vcvtqq2pd {rc, src, dst {mask}|dst {mask}, src, rc}
|
Note
|
Constraints: src0 = dst |
VCVTQQ2PDZrrbkz [HasDQI]
vcvtqq2pd {rc, src, dst {mask} {z}|dst {mask} {z}, src, rc}
VCVTQQ2PDZrrk [HasDQI]
vcvtqq2pd {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTQQ2PDZrrkz [HasDQI]
vcvtqq2pd {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTQQ2PSZrm [HasDQI]
vcvtqq2ps {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTQQ2PSZrmb [HasDQI]
vcvtqq2ps {src{1to8}, dst|dst, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTQQ2PSZrmbk [HasDQI]
vcvtqq2ps {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTQQ2PSZrmbkz [HasDQI]
vcvtqq2ps {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTQQ2PSZrmk [HasDQI]
vcvtqq2ps {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTQQ2PSZrmkz [HasDQI]
vcvtqq2ps {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTQQ2PSZrr [HasDQI]
vcvtqq2ps {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTQQ2PSZrrb [HasDQI]
vcvtqq2ps {rc, src, dst|dst, src, rc}
VCVTQQ2PSZrrbk [HasDQI]
vcvtqq2ps {rc, src, dst {mask}|dst {mask}, src, rc}
|
Note
|
Constraints: src0 = dst |
VCVTQQ2PSZrrbkz [HasDQI]
vcvtqq2ps {rc, src, dst {mask} {z}|dst {mask} {z}, src, rc}
VCVTQQ2PSZrrk [HasDQI]
vcvtqq2ps {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTQQ2PSZrrkz [HasDQI]
vcvtqq2ps {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2QQZrm [HasDQI]
vcvttpd2qq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2QQZrmb [HasDQI]
vcvttpd2qq {src{1to8}, dst|dst, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2QQZrmbk [HasDQI]
vcvttpd2qq {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPD2QQZrmbkz [HasDQI]
vcvttpd2qq {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2QQZrmk [HasDQI]
vcvttpd2qq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPD2QQZrmkz [HasDQI]
vcvttpd2qq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2QQZrr [HasDQI]
vcvttpd2qq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2QQZrrb [HasDQI]
vcvttpd2qq {{sae}, src, dst|dst, src, {sae}}
VCVTTPD2QQZrrbk [HasDQI]
vcvttpd2qq {{sae}, src, dst {mask}|dst {mask}, src, {sae}}
|
Note
|
Constraints: src0 = dst |
VCVTTPD2QQZrrbkz [HasDQI]
vcvttpd2qq {{sae}, src, dst {mask} {z}|dst {mask} {z}, src, {sae}}
VCVTTPD2QQZrrk [HasDQI]
vcvttpd2qq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPD2QQZrrkz [HasDQI]
vcvttpd2qq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2UQQZrm [HasDQI]
vcvttpd2uqq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2UQQZrmb [HasDQI]
vcvttpd2uqq {src{1to8}, dst|dst, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2UQQZrmbk [HasDQI]
vcvttpd2uqq {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPD2UQQZrmbkz [HasDQI]
vcvttpd2uqq {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2UQQZrmk [HasDQI]
vcvttpd2uqq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPD2UQQZrmkz [HasDQI]
vcvttpd2uqq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2UQQZrr [HasDQI]
vcvttpd2uqq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2UQQZrrb [HasDQI]
vcvttpd2uqq {{sae}, src, dst|dst, src, {sae}}
VCVTTPD2UQQZrrbk [HasDQI]
vcvttpd2uqq {{sae}, src, dst {mask}|dst {mask}, src, {sae}}
|
Note
|
Constraints: src0 = dst |
VCVTTPD2UQQZrrbkz [HasDQI]
vcvttpd2uqq {{sae}, src, dst {mask} {z}|dst {mask} {z}, src, {sae}}
VCVTTPD2UQQZrrk [HasDQI]
vcvttpd2uqq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPD2UQQZrrkz [HasDQI]
vcvttpd2uqq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2QQZrm [HasDQI]
vcvttps2qq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2QQZrmb [HasDQI]
vcvttps2qq {src{1to8}, dst|dst, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2QQZrmbk [HasDQI]
vcvttps2qq {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPS2QQZrmbkz [HasDQI]
vcvttps2qq {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2QQZrmk [HasDQI]
vcvttps2qq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPS2QQZrmkz [HasDQI]
vcvttps2qq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2QQZrr [HasDQI]
vcvttps2qq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2QQZrrb [HasDQI]
vcvttps2qq {{sae}, src, dst|dst, src, {sae}}
VCVTTPS2QQZrrbk [HasDQI]
vcvttps2qq {{sae}, src, dst {mask}|dst {mask}, src, {sae}}
|
Note
|
Constraints: src0 = dst |
VCVTTPS2QQZrrbkz [HasDQI]
vcvttps2qq {{sae}, src, dst {mask} {z}|dst {mask} {z}, src, {sae}}
VCVTTPS2QQZrrk [HasDQI]
vcvttps2qq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPS2QQZrrkz [HasDQI]
vcvttps2qq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2UQQZrm [HasDQI]
vcvttps2uqq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2UQQZrmb [HasDQI]
vcvttps2uqq {src{1to8}, dst|dst, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2UQQZrmbk [HasDQI]
vcvttps2uqq {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPS2UQQZrmbkz [HasDQI]
vcvttps2uqq {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2UQQZrmk [HasDQI]
vcvttps2uqq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPS2UQQZrmkz [HasDQI]
vcvttps2uqq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2UQQZrr [HasDQI]
vcvttps2uqq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2UQQZrrb [HasDQI]
vcvttps2uqq {{sae}, src, dst|dst, src, {sae}}
VCVTTPS2UQQZrrbk [HasDQI]
vcvttps2uqq {{sae}, src, dst {mask}|dst {mask}, src, {sae}}
|
Note
|
Constraints: src0 = dst |
VCVTTPS2UQQZrrbkz [HasDQI]
vcvttps2uqq {{sae}, src, dst {mask} {z}|dst {mask} {z}, src, {sae}}
VCVTTPS2UQQZrrk [HasDQI]
vcvttps2uqq {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPS2UQQZrrkz [HasDQI]
vcvttps2uqq {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTUQQ2PDZrm [HasDQI]
vcvtuqq2pd {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTUQQ2PDZrmb [HasDQI]
vcvtuqq2pd {src{1to8}, dst|dst, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTUQQ2PDZrmbk [HasDQI]
vcvtuqq2pd {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTUQQ2PDZrmbkz [HasDQI]
vcvtuqq2pd {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTUQQ2PDZrmk [HasDQI]
vcvtuqq2pd {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTUQQ2PDZrmkz [HasDQI]
vcvtuqq2pd {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTUQQ2PDZrr [HasDQI]
vcvtuqq2pd {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTUQQ2PDZrrb [HasDQI]
vcvtuqq2pd {rc, src, dst|dst, src, rc}
VCVTUQQ2PDZrrbk [HasDQI]
vcvtuqq2pd {rc, src, dst {mask}|dst {mask}, src, rc}
|
Note
|
Constraints: src0 = dst |
VCVTUQQ2PDZrrbkz [HasDQI]
vcvtuqq2pd {rc, src, dst {mask} {z}|dst {mask} {z}, src, rc}
VCVTUQQ2PDZrrk [HasDQI]
vcvtuqq2pd {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTUQQ2PDZrrkz [HasDQI]
vcvtuqq2pd {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTUQQ2PSZrm [HasDQI]
vcvtuqq2ps {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTUQQ2PSZrmb [HasDQI]
vcvtuqq2ps {src{1to8}, dst|dst, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTUQQ2PSZrmbk [HasDQI]
vcvtuqq2ps {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTUQQ2PSZrmbkz [HasDQI]
vcvtuqq2ps {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTUQQ2PSZrmk [HasDQI]
vcvtuqq2ps {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTUQQ2PSZrmkz [HasDQI]
vcvtuqq2ps {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTUQQ2PSZrr [HasDQI]
vcvtuqq2ps {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTUQQ2PSZrrb [HasDQI]
vcvtuqq2ps {rc, src, dst|dst, src, rc}
VCVTUQQ2PSZrrbk [HasDQI]
vcvtuqq2ps {rc, src, dst {mask}|dst {mask}, src, rc}
|
Note
|
Constraints: src0 = dst |
VCVTUQQ2PSZrrbkz [HasDQI]
vcvtuqq2ps {rc, src, dst {mask} {z}|dst {mask} {z}, src, rc}
VCVTUQQ2PSZrrk [HasDQI]
vcvtuqq2ps {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTUQQ2PSZrrkz [HasDQI]
vcvtuqq2ps {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VEXTRACTF32X8Zmri [HasDQI]
vextractf32x8 {idx, src1, dst|dst, src1, idx}
VEXTRACTF32X8Zmrik [HasDQI]
vextractf32x8 {idx, src1, dst {mask}|dst {mask}, src1, idx}
|
Note
|
Properties: mayStore |
VEXTRACTF32X8Zrri [HasDQI]
vextractf32x8 {idx, src1, dst|dst, src1, idx}
VEXTRACTF32X8Zrrik [HasDQI]
vextractf32x8 {idx, src1, dst {mask}|dst {mask}, src1, idx}
|
Note
|
Constraints: src0 = dst |
VEXTRACTF32X8Zrrikz [HasDQI]
vextractf32x8 {idx, src1, dst {mask} {z}|dst {mask} {z}, src1, idx}
VEXTRACTF64X2Zmri [HasDQI]
vextractf64x2 {idx, src1, dst|dst, src1, idx}
VEXTRACTF64X2Zmrik [HasDQI]
vextractf64x2 {idx, src1, dst {mask}|dst {mask}, src1, idx}
|
Note
|
Properties: mayStore |
VEXTRACTF64X2Zrri [HasDQI]
vextractf64x2 {idx, src1, dst|dst, src1, idx}
VEXTRACTF64X2Zrrik [HasDQI]
vextractf64x2 {idx, src1, dst {mask}|dst {mask}, src1, idx}
|
Note
|
Constraints: src0 = dst |
VEXTRACTF64X2Zrrikz [HasDQI]
vextractf64x2 {idx, src1, dst {mask} {z}|dst {mask} {z}, src1, idx}
VEXTRACTI32X8Zmri [HasDQI]
vextracti32x8 {idx, src1, dst|dst, src1, idx}
VEXTRACTI32X8Zmrik [HasDQI]
vextracti32x8 {idx, src1, dst {mask}|dst {mask}, src1, idx}
|
Note
|
Properties: mayStore |
VEXTRACTI32X8Zrri [HasDQI]
vextracti32x8 {idx, src1, dst|dst, src1, idx}
VEXTRACTI32X8Zrrik [HasDQI]
vextracti32x8 {idx, src1, dst {mask}|dst {mask}, src1, idx}
|
Note
|
Constraints: src0 = dst |
VEXTRACTI32X8Zrrikz [HasDQI]
vextracti32x8 {idx, src1, dst {mask} {z}|dst {mask} {z}, src1, idx}
VEXTRACTI64X2Zmri [HasDQI]
vextracti64x2 {idx, src1, dst|dst, src1, idx}
VEXTRACTI64X2Zmrik [HasDQI]
vextracti64x2 {idx, src1, dst {mask}|dst {mask}, src1, idx}
|
Note
|
Properties: mayStore |
VEXTRACTI64X2Zrri [HasDQI]
vextracti64x2 {idx, src1, dst|dst, src1, idx}
VEXTRACTI64X2Zrrik [HasDQI]
vextracti64x2 {idx, src1, dst {mask}|dst {mask}, src1, idx}
|
Note
|
Constraints: src0 = dst |
VEXTRACTI64X2Zrrikz [HasDQI]
vextracti64x2 {idx, src1, dst {mask} {z}|dst {mask} {z}, src1, idx}
VFPCLASSPDZmbi [HasDQI]
vfpclasspd {src2, src1{1to8}, dst|dst, src1{1to8}, src2}
VFPCLASSPDZmbik [HasDQI]
vfpclasspd {src2, src1{1to8}, dst {mask}|dst {mask}, src1{1to8}, src2}
VFPCLASSPDZmi [HasDQI]
vfpclasspd{z} {src2, src1, dst|dst, src1, src2}
VFPCLASSPDZmik [HasDQI]
vfpclasspd{z} {src2, src1, dst {mask}|dst {mask}, src1, src2}
VFPCLASSPDZri [HasDQI]
vfpclasspd {src2, src1, dst|dst, src1, src2}
VFPCLASSPDZrik [HasDQI]
vfpclasspd {src2, src1, dst {mask}|dst {mask}, src1, src2}
VFPCLASSPSZmbi [HasDQI]
vfpclassps {src2, src1{1to16}, dst|dst, src1{1to16}, src2}
VFPCLASSPSZmbik [HasDQI]
vfpclassps {src2, src1{1to16}, dst {mask}|dst {mask}, src1{1to16}, src2}
VFPCLASSPSZmi [HasDQI]
vfpclassps{z} {src2, src1, dst|dst, src1, src2}
VFPCLASSPSZmik [HasDQI]
vfpclassps{z} {src2, src1, dst {mask}|dst {mask}, src1, src2}
VFPCLASSPSZri [HasDQI]
vfpclassps {src2, src1, dst|dst, src1, src2}
VFPCLASSPSZrik [HasDQI]
vfpclassps {src2, src1, dst {mask}|dst {mask}, src1, src2}
VFPCLASSSDZmi [HasDQI]
vfpclasssd {src2, src1, dst|dst, src1, src2}
VFPCLASSSDZmik [HasDQI]
vfpclasssd {src2, src1, dst {mask}|dst {mask}, src1, src2}
VFPCLASSSDZri [HasDQI]
vfpclasssd {src2, src1, dst|dst, src1, src2}
VFPCLASSSDZrik [HasDQI]
vfpclasssd {src2, src1, dst {mask}|dst {mask}, src1, src2}
VFPCLASSSSZmi [HasDQI]
vfpclassss {src2, src1, dst|dst, src1, src2}
VFPCLASSSSZmik [HasDQI]
vfpclassss {src2, src1, dst {mask}|dst {mask}, src1, src2}
VFPCLASSSSZri [HasDQI]
vfpclassss {src2, src1, dst|dst, src1, src2}
VFPCLASSSSZrik [HasDQI]
vfpclassss {src2, src1, dst {mask}|dst {mask}, src1, src2}
VINSERTF32X8Zrmi [HasDQI]
vinsertf32x8 {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayLoad |
VINSERTF32X8Zrmik [HasDQI]
vinsertf32x8 {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VINSERTF32X8Zrmikz [HasDQI]
vinsertf32x8 {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
|
Note
|
Properties: mayLoad |
VINSERTF32X8Zrri [HasDQI]
vinsertf32x8 {src3, src2, src1, dst|dst, src1, src2, src3}
VINSERTF32X8Zrrik [HasDQI]
vinsertf32x8 {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VINSERTF32X8Zrrikz [HasDQI]
vinsertf32x8 {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VINSERTF64X2Zrmi [HasDQI]
vinsertf64x2 {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayLoad |
VINSERTF64X2Zrmik [HasDQI]
vinsertf64x2 {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VINSERTF64X2Zrmikz [HasDQI]
vinsertf64x2 {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
|
Note
|
Properties: mayLoad |
VINSERTF64X2Zrri [HasDQI]
vinsertf64x2 {src3, src2, src1, dst|dst, src1, src2, src3}
VINSERTF64X2Zrrik [HasDQI]
vinsertf64x2 {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VINSERTF64X2Zrrikz [HasDQI]
vinsertf64x2 {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VINSERTI32X8Zrmi [HasDQI]
vinserti32x8 {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayLoad |
VINSERTI32X8Zrmik [HasDQI]
vinserti32x8 {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VINSERTI32X8Zrmikz [HasDQI]
vinserti32x8 {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
|
Note
|
Properties: mayLoad |
VINSERTI32X8Zrri [HasDQI]
vinserti32x8 {src3, src2, src1, dst|dst, src1, src2, src3}
VINSERTI32X8Zrrik [HasDQI]
vinserti32x8 {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VINSERTI32X8Zrrikz [HasDQI]
vinserti32x8 {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VINSERTI64X2Zrmi [HasDQI]
vinserti64x2 {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayLoad |
VINSERTI64X2Zrmik [HasDQI]
vinserti64x2 {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VINSERTI64X2Zrmikz [HasDQI]
vinserti64x2 {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
|
Note
|
Properties: mayLoad |
VINSERTI64X2Zrri [HasDQI]
vinserti64x2 {src3, src2, src1, dst|dst, src1, src2, src3}
VINSERTI64X2Zrrik [HasDQI]
vinserti64x2 {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VINSERTI64X2Zrrikz [HasDQI]
vinserti64x2 {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VORPDZrm [HasDQI]
vorpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VORPDZrmb [HasDQI]
vorpd {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
VORPDZrmbk [HasDQI]
vorpd {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VORPDZrmbkz [HasDQI]
vorpd {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
VORPDZrmk [HasDQI]
vorpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VORPDZrmkz [HasDQI]
vorpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VORPDZrr [HasDQI]
vorpd {src2, src1, dst|dst, src1, src2}
VORPDZrrk [HasDQI]
vorpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VORPDZrrkz [HasDQI]
vorpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VORPSZrm [HasDQI]
vorps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VORPSZrmb [HasDQI]
vorps {src2{1to16}, src1, dst|dst, src1, src2{1to16}}
|
Note
|
Properties: mayLoad |
VORPSZrmbk [HasDQI]
vorps {src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VORPSZrmbkz [HasDQI]
vorps {src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}}
|
Note
|
Properties: mayLoad |
VORPSZrmk [HasDQI]
vorps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VORPSZrmkz [HasDQI]
vorps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VORPSZrr [HasDQI]
vorps {src2, src1, dst|dst, src1, src2}
VORPSZrrk [HasDQI]
vorps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VORPSZrrkz [HasDQI]
vorps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPEXTRDZmri [HasDQI]
vpextrd {src2, src1, dst|dst, src1, src2}
VPEXTRDZrri [HasDQI]
vpextrd {src2, src1, dst|dst, src1, src2}
VPEXTRQZmri [HasDQI]
vpextrq {src2, src1, dst|dst, src1, src2}
VPEXTRQZrri [HasDQI]
vpextrq {src2, src1, dst|dst, src1, src2}
VPINSRDZrmi [HasDQI]
vpinsrd {src3, src2, src1, dst|dst, src1, src2, src3}
VPINSRDZrri [HasDQI]
vpinsrd {src3, src2, src1, dst|dst, src1, src2, src3}
VPINSRQZrmi [HasDQI]
vpinsrq {src3, src2, src1, dst|dst, src1, src2, src3}
VPINSRQZrri [HasDQI]
vpinsrq {src3, src2, src1, dst|dst, src1, src2, src3}
VPMOVD2MZkr [HasDQI]
vpmovd2m {src, dst|dst, src}
VPMOVM2DZrk [HasDQI]
vpmovm2d {src, dst|dst, src}
VPMOVM2QZrk [HasDQI]
vpmovm2q {src, dst|dst, src}
VPMOVQ2MZkr [HasDQI]
vpmovq2m {src, dst|dst, src}
VPMULLQZrm [HasDQI]
vpmullq {src2, src1, dst|dst, src1, src2}
VPMULLQZrmb [HasDQI]
vpmullq {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
VPMULLQZrmbk [HasDQI]
vpmullq {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Constraints: src0 = dst |
VPMULLQZrmbkz [HasDQI]
vpmullq {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
VPMULLQZrmk [HasDQI]
vpmullq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMULLQZrmkz [HasDQI]
vpmullq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMULLQZrr [HasDQI]
vpmullq {src2, src1, dst|dst, src1, src2}
VPMULLQZrrk [HasDQI]
vpmullq {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMULLQZrrkz [HasDQI]
vpmullq {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VRANGEPDZrmbi [HasDQI]
vrangepd {src3, src2{1to8}, src1, dst|dst, src1, src2{1to8}, src3}
|
Note
|
Properties: mayRaiseFPException |
VRANGEPDZrmbik [HasDQI]
vrangepd {src3, src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRANGEPDZrmbikz [HasDQI]
vrangepd {src3, src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}, src3}
|
Note
|
Properties: mayRaiseFPException |
VRANGEPDZrmi [HasDQI]
vrangepd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VRANGEPDZrmik [HasDQI]
vrangepd {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRANGEPDZrmikz [HasDQI]
vrangepd {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VRANGEPDZrri [HasDQI]
vrangepd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VRANGEPDZrrib [HasDQI]
vrangepd {src3, {sae}, src2, src1, dst|dst, src1, src2, {sae}, src3}
VRANGEPDZrribk [HasDQI]
vrangepd {src3, {sae}, src2, src1, dst {mask}|dst {mask}, src1, src2, {sae}, src3}
|
Note
|
Constraints: src0 = dst |
VRANGEPDZrribkz [HasDQI]
vrangepd {src3, {sae}, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, {sae}, src3}
VRANGEPDZrrik [HasDQI]
vrangepd {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRANGEPDZrrikz [HasDQI]
vrangepd {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VRANGEPSZrmbi [HasDQI]
vrangeps {src3, src2{1to16}, src1, dst|dst, src1, src2{1to16}, src3}
|
Note
|
Properties: mayRaiseFPException |
VRANGEPSZrmbik [HasDQI]
vrangeps {src3, src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRANGEPSZrmbikz [HasDQI]
vrangeps {src3, src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}, src3}
|
Note
|
Properties: mayRaiseFPException |
VRANGEPSZrmi [HasDQI]
vrangeps {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VRANGEPSZrmik [HasDQI]
vrangeps {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRANGEPSZrmikz [HasDQI]
vrangeps {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VRANGEPSZrri [HasDQI]
vrangeps {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VRANGEPSZrrib [HasDQI]
vrangeps {src3, {sae}, src2, src1, dst|dst, src1, src2, {sae}, src3}
VRANGEPSZrribk [HasDQI]
vrangeps {src3, {sae}, src2, src1, dst {mask}|dst {mask}, src1, src2, {sae}, src3}
|
Note
|
Constraints: src0 = dst |
VRANGEPSZrribkz [HasDQI]
vrangeps {src3, {sae}, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, {sae}, src3}
VRANGEPSZrrik [HasDQI]
vrangeps {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRANGEPSZrrikz [HasDQI]
vrangeps {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VRANGESDZrmi [HasDQI]
vrangesd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VRANGESDZrmik [HasDQI]
vrangesd {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRANGESDZrmikz [HasDQI]
vrangesd {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VRANGESDZrri [HasDQI]
vrangesd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VRANGESDZrrib [HasDQI]
vrangesd {src3, {sae}, src2, src1, dst|dst, src1, src2, {sae}, src3}
VRANGESDZrribk [HasDQI]
vrangesd {src3, {sae}, src2, src1, dst {mask}|dst {mask}, src1, src2, {sae}, src3}
|
Note
|
Constraints: src0 = dst |
VRANGESDZrribkz [HasDQI]
vrangesd {src3, {sae}, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, {sae}, src3}
VRANGESDZrrik [HasDQI]
vrangesd {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRANGESDZrrikz [HasDQI]
vrangesd {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VRANGESSZrmi [HasDQI]
vrangess {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VRANGESSZrmik [HasDQI]
vrangess {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRANGESSZrmikz [HasDQI]
vrangess {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VRANGESSZrri [HasDQI]
vrangess {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VRANGESSZrrib [HasDQI]
vrangess {src3, {sae}, src2, src1, dst|dst, src1, src2, {sae}, src3}
VRANGESSZrribk [HasDQI]
vrangess {src3, {sae}, src2, src1, dst {mask}|dst {mask}, src1, src2, {sae}, src3}
|
Note
|
Constraints: src0 = dst |
VRANGESSZrribkz [HasDQI]
vrangess {src3, {sae}, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, {sae}, src3}
VRANGESSZrrik [HasDQI]
vrangess {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VRANGESSZrrikz [HasDQI]
vrangess {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VREDUCEPDZrmbi [HasDQI]
vreducepd {src2, src1{1to8}, dst|dst, src1{1to8}, src2}
|
Note
|
Properties: mayRaiseFPException |
VREDUCEPDZrmbik [HasDQI]
vreducepd {src2, src1{1to8}, dst {mask}|dst {mask}, src1{1to8}, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VREDUCEPDZrmbikz [HasDQI]
vreducepd {src2, src1{1to8}, dst {mask} {z}|dst {mask} {z}, src1{1to8}, src2}
|
Note
|
Properties: mayRaiseFPException |
VREDUCEPDZrmi [HasDQI]
vreducepd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VREDUCEPDZrmik [HasDQI]
vreducepd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VREDUCEPDZrmikz [HasDQI]
vreducepd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VREDUCEPDZrri [HasDQI]
vreducepd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VREDUCEPDZrrib [HasDQI]
vreducepd {src2, {sae}, src1, dst|dst, src1, {sae}, src2}
VREDUCEPDZrribk [HasDQI]
vreducepd {src2, {sae}, src1, dst {mask}|dst {mask}, src1, {sae}, src2}
|
Note
|
Constraints: src0 = dst |
VREDUCEPDZrribkz [HasDQI]
vreducepd {src2, {sae}, src1, dst {mask} {z}|dst {mask} {z}, src1, {sae}, src2}
VREDUCEPDZrrik [HasDQI]
vreducepd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VREDUCEPDZrrikz [HasDQI]
vreducepd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VREDUCEPSZrmbi [HasDQI]
vreduceps {src2, src1{1to16}, dst|dst, src1{1to16}, src2}
|
Note
|
Properties: mayRaiseFPException |
VREDUCEPSZrmbik [HasDQI]
vreduceps {src2, src1{1to16}, dst {mask}|dst {mask}, src1{1to16}, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VREDUCEPSZrmbikz [HasDQI]
vreduceps {src2, src1{1to16}, dst {mask} {z}|dst {mask} {z}, src1{1to16}, src2}
|
Note
|
Properties: mayRaiseFPException |
VREDUCEPSZrmi [HasDQI]
vreduceps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VREDUCEPSZrmik [HasDQI]
vreduceps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VREDUCEPSZrmikz [HasDQI]
vreduceps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VREDUCEPSZrri [HasDQI]
vreduceps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VREDUCEPSZrrib [HasDQI]
vreduceps {src2, {sae}, src1, dst|dst, src1, {sae}, src2}
VREDUCEPSZrribk [HasDQI]
vreduceps {src2, {sae}, src1, dst {mask}|dst {mask}, src1, {sae}, src2}
|
Note
|
Constraints: src0 = dst |
VREDUCEPSZrribkz [HasDQI]
vreduceps {src2, {sae}, src1, dst {mask} {z}|dst {mask} {z}, src1, {sae}, src2}
VREDUCEPSZrrik [HasDQI]
vreduceps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VREDUCEPSZrrikz [HasDQI]
vreduceps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VREDUCESDZrmi [HasDQI]
vreducesd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VREDUCESDZrmik [HasDQI]
vreducesd {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VREDUCESDZrmikz [HasDQI]
vreducesd {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VREDUCESDZrri [HasDQI]
vreducesd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VREDUCESDZrrib [HasDQI]
vreducesd {src3, {sae}, src2, src1, dst|dst, src1, src2, {sae}, src3}
VREDUCESDZrribk [HasDQI]
vreducesd {src3, {sae}, src2, src1, dst {mask}|dst {mask}, src1, src2, {sae}, src3}
|
Note
|
Constraints: src0 = dst |
VREDUCESDZrribkz [HasDQI]
vreducesd {src3, {sae}, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, {sae}, src3}
VREDUCESDZrrik [HasDQI]
vreducesd {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VREDUCESDZrrikz [HasDQI]
vreducesd {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VREDUCESSZrmi [HasDQI]
vreducess {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VREDUCESSZrmik [HasDQI]
vreducess {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VREDUCESSZrmikz [HasDQI]
vreducess {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VREDUCESSZrri [HasDQI]
vreducess {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VREDUCESSZrrib [HasDQI]
vreducess {src3, {sae}, src2, src1, dst|dst, src1, src2, {sae}, src3}
VREDUCESSZrribk [HasDQI]
vreducess {src3, {sae}, src2, src1, dst {mask}|dst {mask}, src1, src2, {sae}, src3}
|
Note
|
Constraints: src0 = dst |
VREDUCESSZrribkz [HasDQI]
vreducess {src3, {sae}, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, {sae}, src3}
VREDUCESSZrrik [HasDQI]
vreducess {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VREDUCESSZrrikz [HasDQI]
vreducess {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VXORPDZrm [HasDQI]
vxorpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VXORPDZrmb [HasDQI]
vxorpd {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
VXORPDZrmbk [HasDQI]
vxorpd {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VXORPDZrmbkz [HasDQI]
vxorpd {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
|
Note
|
Properties: mayLoad |
VXORPDZrmk [HasDQI]
vxorpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VXORPDZrmkz [HasDQI]
vxorpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VXORPDZrr [HasDQI]
vxorpd {src2, src1, dst|dst, src1, src2}
VXORPDZrrk [HasDQI]
vxorpd {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VXORPDZrrkz [HasDQI]
vxorpd {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VXORPSZrm [HasDQI]
vxorps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VXORPSZrmb [HasDQI]
vxorps {src2{1to16}, src1, dst|dst, src1, src2{1to16}}
|
Note
|
Properties: mayLoad |
VXORPSZrmbk [HasDQI]
vxorps {src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VXORPSZrmbkz [HasDQI]
vxorps {src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}}
|
Note
|
Properties: mayLoad |
VXORPSZrmk [HasDQI]
vxorps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VXORPSZrmkz [HasDQI]
vxorps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VXORPSZrr [HasDQI]
vxorps {src2, src1, dst|dst, src1, src2}
VXORPSZrrk [HasDQI]
vxorps {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VXORPSZrrkz [HasDQI]
vxorps {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
KMOVBkk [HasDQI, NoEGPR]
kmovb {src, dst|dst, src}
|
Note
|
Properties: isMoveReg |
KMOVBkm [HasDQI, NoEGPR]
kmovb {src, dst|dst, src}
KMOVBkr [HasDQI, NoEGPR]
kmovb {src, dst|dst, src}
KMOVBmk [HasDQI, NoEGPR]
kmovb {src, dst|dst, src}
KMOVBrk [HasDQI, NoEGPR]
kmovb {src, dst|dst, src}
VADDBF16Zrm [HasAVX10_2_512]
vaddbf16 {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VADDBF16Zrmb [HasAVX10_2_512]
vaddbf16 {src2{1to32}, src1, dst|dst, src1, src2{1to32}}
|
Note
|
Properties: mayLoad |
VADDBF16Zrmbk [HasAVX10_2_512]
vaddbf16 {src2{1to32}, src1, dst {mask}|dst {mask}, src1, src2{1to32}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VADDBF16Zrmbkz [HasAVX10_2_512]
vaddbf16 {src2{1to32}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to32}}
|
Note
|
Properties: mayLoad |
VADDBF16Zrmk [HasAVX10_2_512]
vaddbf16 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VADDBF16Zrmkz [HasAVX10_2_512]
vaddbf16 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VADDBF16Zrr [HasAVX10_2_512]
vaddbf16 {src2, src1, dst|dst, src1, src2}
VADDBF16Zrrk [HasAVX10_2_512]
vaddbf16 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VADDBF16Zrrkz [HasAVX10_2_512]
vaddbf16 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VCMPBF16Zrmbi [HasAVX10_2_512]
vcmpbf16 {cc, src2{1to32}, src1, dst|dst, src1, src2{1to32}, cc}
VCMPBF16Zrmbik [HasAVX10_2_512]
vcmpbf16 {cc, src2{1to32}, src1, dst {mask}|dst {mask}, src1, src2{1to32}, cc}
VCMPBF16Zrmi [HasAVX10_2_512]
vcmpbf16 {cc, src2, src1, dst|dst, src1, src2, cc}
VCMPBF16Zrmik [HasAVX10_2_512]
vcmpbf16 {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
VCMPBF16Zrri [HasAVX10_2_512]
vcmpbf16 {cc, src2, src1, dst|dst, src1, src2, cc}
VCMPBF16Zrrik [HasAVX10_2_512]
vcmpbf16 {cc, src2, src1, dst {mask}|dst {mask}, src1, src2, cc}
VCVT2PH2BF8SZrm [HasAVX10_2_512]
vcvt2ph2bf8s {src2, src1, dst|dst, src1, src2}
VCVT2PH2BF8SZrmb [HasAVX10_2_512]
vcvt2ph2bf8s {src2{1to32}, src1, dst|dst, src1, src2{1to32}}
VCVT2PH2BF8SZrmbk [HasAVX10_2_512]
vcvt2ph2bf8s {src2{1to32}, src1, dst {mask}|dst {mask}, src1, src2{1to32}}
|
Note
|
Constraints: src0 = dst |
VCVT2PH2BF8SZrmbkz [HasAVX10_2_512]
vcvt2ph2bf8s {src2{1to32}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to32}}
VCVT2PH2BF8SZrmk [HasAVX10_2_512]
vcvt2ph2bf8s {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VCVT2PH2BF8SZrmkz [HasAVX10_2_512]
vcvt2ph2bf8s {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VCVT2PH2BF8SZrr [HasAVX10_2_512]
vcvt2ph2bf8s {src2, src1, dst|dst, src1, src2}
VCVT2PH2BF8SZrrk [HasAVX10_2_512]
vcvt2ph2bf8s {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VCVT2PH2BF8SZrrkz [HasAVX10_2_512]
vcvt2ph2bf8s {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VCVT2PH2BF8Zrm [HasAVX10_2_512]
vcvt2ph2bf8 {src2, src1, dst|dst, src1, src2}
VCVT2PH2BF8Zrmb [HasAVX10_2_512]
vcvt2ph2bf8 {src2{1to32}, src1, dst|dst, src1, src2{1to32}}
VCVT2PH2BF8Zrmbk [HasAVX10_2_512]
vcvt2ph2bf8 {src2{1to32}, src1, dst {mask}|dst {mask}, src1, src2{1to32}}
|
Note
|
Constraints: src0 = dst |
VCVT2PH2BF8Zrmbkz [HasAVX10_2_512]
vcvt2ph2bf8 {src2{1to32}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to32}}
VCVT2PH2BF8Zrmk [HasAVX10_2_512]
vcvt2ph2bf8 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VCVT2PH2BF8Zrmkz [HasAVX10_2_512]
vcvt2ph2bf8 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VCVT2PH2BF8Zrr [HasAVX10_2_512]
vcvt2ph2bf8 {src2, src1, dst|dst, src1, src2}
VCVT2PH2BF8Zrrk [HasAVX10_2_512]
vcvt2ph2bf8 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VCVT2PH2BF8Zrrkz [HasAVX10_2_512]
vcvt2ph2bf8 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VCVT2PH2HF8SZrm [HasAVX10_2_512]
vcvt2ph2hf8s {src2, src1, dst|dst, src1, src2}
VCVT2PH2HF8SZrmb [HasAVX10_2_512]
vcvt2ph2hf8s {src2{1to32}, src1, dst|dst, src1, src2{1to32}}
VCVT2PH2HF8SZrmbk [HasAVX10_2_512]
vcvt2ph2hf8s {src2{1to32}, src1, dst {mask}|dst {mask}, src1, src2{1to32}}
|
Note
|
Constraints: src0 = dst |
VCVT2PH2HF8SZrmbkz [HasAVX10_2_512]
vcvt2ph2hf8s {src2{1to32}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to32}}
VCVT2PH2HF8SZrmk [HasAVX10_2_512]
vcvt2ph2hf8s {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VCVT2PH2HF8SZrmkz [HasAVX10_2_512]
vcvt2ph2hf8s {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VCVT2PH2HF8SZrr [HasAVX10_2_512]
vcvt2ph2hf8s {src2, src1, dst|dst, src1, src2}
VCVT2PH2HF8SZrrk [HasAVX10_2_512]
vcvt2ph2hf8s {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VCVT2PH2HF8SZrrkz [HasAVX10_2_512]
vcvt2ph2hf8s {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VCVT2PH2HF8Zrm [HasAVX10_2_512]
vcvt2ph2hf8 {src2, src1, dst|dst, src1, src2}
VCVT2PH2HF8Zrmb [HasAVX10_2_512]
vcvt2ph2hf8 {src2{1to32}, src1, dst|dst, src1, src2{1to32}}
VCVT2PH2HF8Zrmbk [HasAVX10_2_512]
vcvt2ph2hf8 {src2{1to32}, src1, dst {mask}|dst {mask}, src1, src2{1to32}}
|
Note
|
Constraints: src0 = dst |
VCVT2PH2HF8Zrmbkz [HasAVX10_2_512]
vcvt2ph2hf8 {src2{1to32}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to32}}
VCVT2PH2HF8Zrmk [HasAVX10_2_512]
vcvt2ph2hf8 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VCVT2PH2HF8Zrmkz [HasAVX10_2_512]
vcvt2ph2hf8 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VCVT2PH2HF8Zrr [HasAVX10_2_512]
vcvt2ph2hf8 {src2, src1, dst|dst, src1, src2}
VCVT2PH2HF8Zrrk [HasAVX10_2_512]
vcvt2ph2hf8 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VCVT2PH2HF8Zrrkz [HasAVX10_2_512]
vcvt2ph2hf8 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VCVT2PS2PHXZrm [HasAVX10_2_512]
vcvt2ps2phx {src2, src1, dst|dst, src1, src2}
VCVT2PS2PHXZrmb [HasAVX10_2_512]
vcvt2ps2phx {src2{1to16}, src1, dst|dst, src1, src2{1to16}}
VCVT2PS2PHXZrmbk [HasAVX10_2_512]
vcvt2ps2phx {src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}}
|
Note
|
Constraints: src0 = dst |
VCVT2PS2PHXZrmbkz [HasAVX10_2_512]
vcvt2ps2phx {src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}}
VCVT2PS2PHXZrmk [HasAVX10_2_512]
vcvt2ps2phx {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VCVT2PS2PHXZrmkz [HasAVX10_2_512]
vcvt2ps2phx {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VCVT2PS2PHXZrr [HasAVX10_2_512]
vcvt2ps2phx {src2, src1, dst|dst, src1, src2}
VCVT2PS2PHXZrrb [HasAVX10_2_512]
vcvt2ps2phx {rc, src2, src1, dst|dst, src1, src2, rc}
VCVT2PS2PHXZrrbk [HasAVX10_2_512]
vcvt2ps2phx {rc, src2, src1, dst {mask}|dst {mask}, src1, src2, rc}
|
Note
|
Constraints: src0 = dst |
VCVT2PS2PHXZrrbkz [HasAVX10_2_512]
vcvt2ps2phx {rc, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, rc}
VCVT2PS2PHXZrrk [HasAVX10_2_512]
vcvt2ps2phx {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VCVT2PS2PHXZrrkz [HasAVX10_2_512]
vcvt2ps2phx {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VCVTBF162IBSZrm [HasAVX10_2_512]
vcvtbf162ibs {src, dst|dst, src}
VCVTBF162IBSZrmb [HasAVX10_2_512]
vcvtbf162ibs {src{1to32}, dst|dst, src{1to32}}
VCVTBF162IBSZrmbk [HasAVX10_2_512]
vcvtbf162ibs {src{1to32}, dst {mask}|dst {mask}, src{1to32}}
|
Note
|
Constraints: src0 = dst |
VCVTBF162IBSZrmbkz [HasAVX10_2_512]
vcvtbf162ibs {src{1to32}, dst {mask} {z}|dst {mask} {z}, src{1to32}}
VCVTBF162IBSZrmk [HasAVX10_2_512]
vcvtbf162ibs {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTBF162IBSZrmkz [HasAVX10_2_512]
vcvtbf162ibs {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTBF162IBSZrr [HasAVX10_2_512]
vcvtbf162ibs {src, dst|dst, src}
VCVTBF162IBSZrrk [HasAVX10_2_512]
vcvtbf162ibs {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTBF162IBSZrrkz [HasAVX10_2_512]
vcvtbf162ibs {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTBF162IUBSZrm [HasAVX10_2_512]
vcvtbf162iubs {src, dst|dst, src}
VCVTBF162IUBSZrmb [HasAVX10_2_512]
vcvtbf162iubs {src{1to32}, dst|dst, src{1to32}}
VCVTBF162IUBSZrmbk [HasAVX10_2_512]
vcvtbf162iubs {src{1to32}, dst {mask}|dst {mask}, src{1to32}}
|
Note
|
Constraints: src0 = dst |
VCVTBF162IUBSZrmbkz [HasAVX10_2_512]
vcvtbf162iubs {src{1to32}, dst {mask} {z}|dst {mask} {z}, src{1to32}}
VCVTBF162IUBSZrmk [HasAVX10_2_512]
vcvtbf162iubs {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTBF162IUBSZrmkz [HasAVX10_2_512]
vcvtbf162iubs {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTBF162IUBSZrr [HasAVX10_2_512]
vcvtbf162iubs {src, dst|dst, src}
VCVTBF162IUBSZrrk [HasAVX10_2_512]
vcvtbf162iubs {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTBF162IUBSZrrkz [HasAVX10_2_512]
vcvtbf162iubs {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTBIASPH2BF8SZrm [HasAVX10_2_512]
vcvtbiasph2bf8s {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VCVTBIASPH2BF8SZrmb [HasAVX10_2_512]
vcvtbiasph2bf8s {src2{1to32}, src1, dst|dst, src1, src2{1to32}}
|
Note
|
Properties: mayLoad |
VCVTBIASPH2BF8SZrmbk [HasAVX10_2_512]
vcvtbiasph2bf8s {src2{1to32}, src1, dst {mask}|dst {mask}, src1, src2{1to32}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VCVTBIASPH2BF8SZrmbkz [HasAVX10_2_512]
vcvtbiasph2bf8s {src2{1to32}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to32}}
|
Note
|
Properties: mayLoad |
VCVTBIASPH2BF8SZrmk [HasAVX10_2_512]
vcvtbiasph2bf8s {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VCVTBIASPH2BF8SZrmkz [HasAVX10_2_512]
vcvtbiasph2bf8s {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VCVTBIASPH2BF8SZrr [HasAVX10_2_512]
vcvtbiasph2bf8s {src2, src1, dst|dst, src1, src2}
VCVTBIASPH2BF8SZrrk [HasAVX10_2_512]
vcvtbiasph2bf8s {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VCVTBIASPH2BF8SZrrkz [HasAVX10_2_512]
vcvtbiasph2bf8s {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VCVTBIASPH2BF8Zrm [HasAVX10_2_512]
vcvtbiasph2bf8 {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VCVTBIASPH2BF8Zrmb [HasAVX10_2_512]
vcvtbiasph2bf8 {src2{1to32}, src1, dst|dst, src1, src2{1to32}}
|
Note
|
Properties: mayLoad |
VCVTBIASPH2BF8Zrmbk [HasAVX10_2_512]
vcvtbiasph2bf8 {src2{1to32}, src1, dst {mask}|dst {mask}, src1, src2{1to32}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VCVTBIASPH2BF8Zrmbkz [HasAVX10_2_512]
vcvtbiasph2bf8 {src2{1to32}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to32}}
|
Note
|
Properties: mayLoad |
VCVTBIASPH2BF8Zrmk [HasAVX10_2_512]
vcvtbiasph2bf8 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VCVTBIASPH2BF8Zrmkz [HasAVX10_2_512]
vcvtbiasph2bf8 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VCVTBIASPH2BF8Zrr [HasAVX10_2_512]
vcvtbiasph2bf8 {src2, src1, dst|dst, src1, src2}
VCVTBIASPH2BF8Zrrk [HasAVX10_2_512]
vcvtbiasph2bf8 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VCVTBIASPH2BF8Zrrkz [HasAVX10_2_512]
vcvtbiasph2bf8 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VCVTBIASPH2HF8SZrm [HasAVX10_2_512]
vcvtbiasph2hf8s {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VCVTBIASPH2HF8SZrmb [HasAVX10_2_512]
vcvtbiasph2hf8s {src2{1to32}, src1, dst|dst, src1, src2{1to32}}
|
Note
|
Properties: mayLoad |
VCVTBIASPH2HF8SZrmbk [HasAVX10_2_512]
vcvtbiasph2hf8s {src2{1to32}, src1, dst {mask}|dst {mask}, src1, src2{1to32}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VCVTBIASPH2HF8SZrmbkz [HasAVX10_2_512]
vcvtbiasph2hf8s {src2{1to32}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to32}}
|
Note
|
Properties: mayLoad |
VCVTBIASPH2HF8SZrmk [HasAVX10_2_512]
vcvtbiasph2hf8s {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VCVTBIASPH2HF8SZrmkz [HasAVX10_2_512]
vcvtbiasph2hf8s {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VCVTBIASPH2HF8SZrr [HasAVX10_2_512]
vcvtbiasph2hf8s {src2, src1, dst|dst, src1, src2}
VCVTBIASPH2HF8SZrrk [HasAVX10_2_512]
vcvtbiasph2hf8s {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VCVTBIASPH2HF8SZrrkz [HasAVX10_2_512]
vcvtbiasph2hf8s {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VCVTBIASPH2HF8Zrm [HasAVX10_2_512]
vcvtbiasph2hf8 {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VCVTBIASPH2HF8Zrmb [HasAVX10_2_512]
vcvtbiasph2hf8 {src2{1to32}, src1, dst|dst, src1, src2{1to32}}
|
Note
|
Properties: mayLoad |
VCVTBIASPH2HF8Zrmbk [HasAVX10_2_512]
vcvtbiasph2hf8 {src2{1to32}, src1, dst {mask}|dst {mask}, src1, src2{1to32}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VCVTBIASPH2HF8Zrmbkz [HasAVX10_2_512]
vcvtbiasph2hf8 {src2{1to32}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to32}}
|
Note
|
Properties: mayLoad |
VCVTBIASPH2HF8Zrmk [HasAVX10_2_512]
vcvtbiasph2hf8 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VCVTBIASPH2HF8Zrmkz [HasAVX10_2_512]
vcvtbiasph2hf8 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VCVTBIASPH2HF8Zrr [HasAVX10_2_512]
vcvtbiasph2hf8 {src2, src1, dst|dst, src1, src2}
VCVTBIASPH2HF8Zrrk [HasAVX10_2_512]
vcvtbiasph2hf8 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VCVTBIASPH2HF8Zrrkz [HasAVX10_2_512]
vcvtbiasph2hf8 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VCVTHF82PHZrm [HasAVX10_2_512]
vcvthf82ph {src, dst|dst, src}
VCVTHF82PHZrmk [HasAVX10_2_512]
vcvthf82ph {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTHF82PHZrmkz [HasAVX10_2_512]
vcvthf82ph {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTHF82PHZrr [HasAVX10_2_512]
vcvthf82ph {src, dst|dst, src}
VCVTHF82PHZrrk [HasAVX10_2_512]
vcvthf82ph {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTHF82PHZrrkz [HasAVX10_2_512]
vcvthf82ph {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTPH2BF8SZrm [HasAVX10_2_512]
vcvtph2bf8s {src, dst|dst, src}
VCVTPH2BF8SZrmb [HasAVX10_2_512]
vcvtph2bf8s {src{1to32}, dst|dst, src{1to32}}
VCVTPH2BF8SZrmbk [HasAVX10_2_512]
vcvtph2bf8s {src{1to32}, dst {mask}|dst {mask}, src{1to32}}
|
Note
|
Constraints: src0 = dst |
VCVTPH2BF8SZrmbkz [HasAVX10_2_512]
vcvtph2bf8s {src{1to32}, dst {mask} {z}|dst {mask} {z}, src{1to32}}
VCVTPH2BF8SZrmk [HasAVX10_2_512]
vcvtph2bf8s {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTPH2BF8SZrmkz [HasAVX10_2_512]
vcvtph2bf8s {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTPH2BF8SZrr [HasAVX10_2_512]
vcvtph2bf8s {src, dst|dst, src}
VCVTPH2BF8SZrrk [HasAVX10_2_512]
vcvtph2bf8s {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTPH2BF8SZrrkz [HasAVX10_2_512]
vcvtph2bf8s {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTPH2BF8Zrm [HasAVX10_2_512]
vcvtph2bf8 {src, dst|dst, src}
VCVTPH2BF8Zrmb [HasAVX10_2_512]
vcvtph2bf8 {src{1to32}, dst|dst, src{1to32}}
VCVTPH2BF8Zrmbk [HasAVX10_2_512]
vcvtph2bf8 {src{1to32}, dst {mask}|dst {mask}, src{1to32}}
|
Note
|
Constraints: src0 = dst |
VCVTPH2BF8Zrmbkz [HasAVX10_2_512]
vcvtph2bf8 {src{1to32}, dst {mask} {z}|dst {mask} {z}, src{1to32}}
VCVTPH2BF8Zrmk [HasAVX10_2_512]
vcvtph2bf8 {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTPH2BF8Zrmkz [HasAVX10_2_512]
vcvtph2bf8 {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTPH2BF8Zrr [HasAVX10_2_512]
vcvtph2bf8 {src, dst|dst, src}
VCVTPH2BF8Zrrk [HasAVX10_2_512]
vcvtph2bf8 {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTPH2BF8Zrrkz [HasAVX10_2_512]
vcvtph2bf8 {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTPH2HF8SZrm [HasAVX10_2_512]
vcvtph2hf8s {src, dst|dst, src}
VCVTPH2HF8SZrmb [HasAVX10_2_512]
vcvtph2hf8s {src{1to32}, dst|dst, src{1to32}}
VCVTPH2HF8SZrmbk [HasAVX10_2_512]
vcvtph2hf8s {src{1to32}, dst {mask}|dst {mask}, src{1to32}}
|
Note
|
Constraints: src0 = dst |
VCVTPH2HF8SZrmbkz [HasAVX10_2_512]
vcvtph2hf8s {src{1to32}, dst {mask} {z}|dst {mask} {z}, src{1to32}}
VCVTPH2HF8SZrmk [HasAVX10_2_512]
vcvtph2hf8s {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTPH2HF8SZrmkz [HasAVX10_2_512]
vcvtph2hf8s {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTPH2HF8SZrr [HasAVX10_2_512]
vcvtph2hf8s {src, dst|dst, src}
VCVTPH2HF8SZrrk [HasAVX10_2_512]
vcvtph2hf8s {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTPH2HF8SZrrkz [HasAVX10_2_512]
vcvtph2hf8s {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTPH2HF8Zrm [HasAVX10_2_512]
vcvtph2hf8 {src, dst|dst, src}
VCVTPH2HF8Zrmb [HasAVX10_2_512]
vcvtph2hf8 {src{1to32}, dst|dst, src{1to32}}
VCVTPH2HF8Zrmbk [HasAVX10_2_512]
vcvtph2hf8 {src{1to32}, dst {mask}|dst {mask}, src{1to32}}
|
Note
|
Constraints: src0 = dst |
VCVTPH2HF8Zrmbkz [HasAVX10_2_512]
vcvtph2hf8 {src{1to32}, dst {mask} {z}|dst {mask} {z}, src{1to32}}
VCVTPH2HF8Zrmk [HasAVX10_2_512]
vcvtph2hf8 {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTPH2HF8Zrmkz [HasAVX10_2_512]
vcvtph2hf8 {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTPH2HF8Zrr [HasAVX10_2_512]
vcvtph2hf8 {src, dst|dst, src}
VCVTPH2HF8Zrrk [HasAVX10_2_512]
vcvtph2hf8 {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTPH2HF8Zrrkz [HasAVX10_2_512]
vcvtph2hf8 {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTPH2IBSZrm [HasAVX10_2_512]
vcvtph2ibs {src, dst|dst, src}
VCVTPH2IBSZrmb [HasAVX10_2_512]
vcvtph2ibs {src{1to32}, dst|dst, src{1to32}}
VCVTPH2IBSZrmbk [HasAVX10_2_512]
vcvtph2ibs {src{1to32}, dst {mask}|dst {mask}, src{1to32}}
|
Note
|
Constraints: src0 = dst |
VCVTPH2IBSZrmbkz [HasAVX10_2_512]
vcvtph2ibs {src{1to32}, dst {mask} {z}|dst {mask} {z}, src{1to32}}
VCVTPH2IBSZrmk [HasAVX10_2_512]
vcvtph2ibs {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTPH2IBSZrmkz [HasAVX10_2_512]
vcvtph2ibs {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTPH2IBSZrr [HasAVX10_2_512]
vcvtph2ibs {src, dst|dst, src}
VCVTPH2IBSZrrb [HasAVX10_2_512]
vcvtph2ibs {rc, src, dst|dst, src, rc}
VCVTPH2IBSZrrbk [HasAVX10_2_512]
vcvtph2ibs {rc, src, dst {mask}|dst {mask}, src, rc}
|
Note
|
Constraints: src0 = dst |
VCVTPH2IBSZrrbkz [HasAVX10_2_512]
vcvtph2ibs {rc, src, dst {mask} {z}|dst {mask} {z}, src, rc}
VCVTPH2IBSZrrk [HasAVX10_2_512]
vcvtph2ibs {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTPH2IBSZrrkz [HasAVX10_2_512]
vcvtph2ibs {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTPH2IUBSZrm [HasAVX10_2_512]
vcvtph2iubs {src, dst|dst, src}
VCVTPH2IUBSZrmb [HasAVX10_2_512]
vcvtph2iubs {src{1to32}, dst|dst, src{1to32}}
VCVTPH2IUBSZrmbk [HasAVX10_2_512]
vcvtph2iubs {src{1to32}, dst {mask}|dst {mask}, src{1to32}}
|
Note
|
Constraints: src0 = dst |
VCVTPH2IUBSZrmbkz [HasAVX10_2_512]
vcvtph2iubs {src{1to32}, dst {mask} {z}|dst {mask} {z}, src{1to32}}
VCVTPH2IUBSZrmk [HasAVX10_2_512]
vcvtph2iubs {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTPH2IUBSZrmkz [HasAVX10_2_512]
vcvtph2iubs {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTPH2IUBSZrr [HasAVX10_2_512]
vcvtph2iubs {src, dst|dst, src}
VCVTPH2IUBSZrrb [HasAVX10_2_512]
vcvtph2iubs {rc, src, dst|dst, src, rc}
VCVTPH2IUBSZrrbk [HasAVX10_2_512]
vcvtph2iubs {rc, src, dst {mask}|dst {mask}, src, rc}
|
Note
|
Constraints: src0 = dst |
VCVTPH2IUBSZrrbkz [HasAVX10_2_512]
vcvtph2iubs {rc, src, dst {mask} {z}|dst {mask} {z}, src, rc}
VCVTPH2IUBSZrrk [HasAVX10_2_512]
vcvtph2iubs {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTPH2IUBSZrrkz [HasAVX10_2_512]
vcvtph2iubs {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTPS2IBSZrm [HasAVX10_2_512]
vcvtps2ibs {src, dst|dst, src}
VCVTPS2IBSZrmb [HasAVX10_2_512]
vcvtps2ibs {src{1to16}, dst|dst, src{1to16}}
VCVTPS2IBSZrmbk [HasAVX10_2_512]
vcvtps2ibs {src{1to16}, dst {mask}|dst {mask}, src{1to16}}
|
Note
|
Constraints: src0 = dst |
VCVTPS2IBSZrmbkz [HasAVX10_2_512]
vcvtps2ibs {src{1to16}, dst {mask} {z}|dst {mask} {z}, src{1to16}}
VCVTPS2IBSZrmk [HasAVX10_2_512]
vcvtps2ibs {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTPS2IBSZrmkz [HasAVX10_2_512]
vcvtps2ibs {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTPS2IBSZrr [HasAVX10_2_512]
vcvtps2ibs {src, dst|dst, src}
VCVTPS2IBSZrrb [HasAVX10_2_512]
vcvtps2ibs {rc, src, dst|dst, src, rc}
VCVTPS2IBSZrrbk [HasAVX10_2_512]
vcvtps2ibs {rc, src, dst {mask}|dst {mask}, src, rc}
|
Note
|
Constraints: src0 = dst |
VCVTPS2IBSZrrbkz [HasAVX10_2_512]
vcvtps2ibs {rc, src, dst {mask} {z}|dst {mask} {z}, src, rc}
VCVTPS2IBSZrrk [HasAVX10_2_512]
vcvtps2ibs {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTPS2IBSZrrkz [HasAVX10_2_512]
vcvtps2ibs {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTPS2IUBSZrm [HasAVX10_2_512]
vcvtps2iubs {src, dst|dst, src}
VCVTPS2IUBSZrmb [HasAVX10_2_512]
vcvtps2iubs {src{1to16}, dst|dst, src{1to16}}
VCVTPS2IUBSZrmbk [HasAVX10_2_512]
vcvtps2iubs {src{1to16}, dst {mask}|dst {mask}, src{1to16}}
|
Note
|
Constraints: src0 = dst |
VCVTPS2IUBSZrmbkz [HasAVX10_2_512]
vcvtps2iubs {src{1to16}, dst {mask} {z}|dst {mask} {z}, src{1to16}}
VCVTPS2IUBSZrmk [HasAVX10_2_512]
vcvtps2iubs {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTPS2IUBSZrmkz [HasAVX10_2_512]
vcvtps2iubs {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTPS2IUBSZrr [HasAVX10_2_512]
vcvtps2iubs {src, dst|dst, src}
VCVTPS2IUBSZrrb [HasAVX10_2_512]
vcvtps2iubs {rc, src, dst|dst, src, rc}
VCVTPS2IUBSZrrbk [HasAVX10_2_512]
vcvtps2iubs {rc, src, dst {mask}|dst {mask}, src, rc}
|
Note
|
Constraints: src0 = dst |
VCVTPS2IUBSZrrbkz [HasAVX10_2_512]
vcvtps2iubs {rc, src, dst {mask} {z}|dst {mask} {z}, src, rc}
VCVTPS2IUBSZrrk [HasAVX10_2_512]
vcvtps2iubs {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTPS2IUBSZrrkz [HasAVX10_2_512]
vcvtps2iubs {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTTBF162IBSZrm [HasAVX10_2_512]
vcvttbf162ibs {src, dst|dst, src}
VCVTTBF162IBSZrmb [HasAVX10_2_512]
vcvttbf162ibs {src{1to32}, dst|dst, src{1to32}}
VCVTTBF162IBSZrmbk [HasAVX10_2_512]
vcvttbf162ibs {src{1to32}, dst {mask}|dst {mask}, src{1to32}}
|
Note
|
Constraints: src0 = dst |
VCVTTBF162IBSZrmbkz [HasAVX10_2_512]
vcvttbf162ibs {src{1to32}, dst {mask} {z}|dst {mask} {z}, src{1to32}}
VCVTTBF162IBSZrmk [HasAVX10_2_512]
vcvttbf162ibs {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTTBF162IBSZrmkz [HasAVX10_2_512]
vcvttbf162ibs {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTTBF162IBSZrr [HasAVX10_2_512]
vcvttbf162ibs {src, dst|dst, src}
VCVTTBF162IBSZrrk [HasAVX10_2_512]
vcvttbf162ibs {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTTBF162IBSZrrkz [HasAVX10_2_512]
vcvttbf162ibs {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTTBF162IUBSZrm [HasAVX10_2_512]
vcvttbf162iubs {src, dst|dst, src}
VCVTTBF162IUBSZrmb [HasAVX10_2_512]
vcvttbf162iubs {src{1to32}, dst|dst, src{1to32}}
VCVTTBF162IUBSZrmbk [HasAVX10_2_512]
vcvttbf162iubs {src{1to32}, dst {mask}|dst {mask}, src{1to32}}
|
Note
|
Constraints: src0 = dst |
VCVTTBF162IUBSZrmbkz [HasAVX10_2_512]
vcvttbf162iubs {src{1to32}, dst {mask} {z}|dst {mask} {z}, src{1to32}}
VCVTTBF162IUBSZrmk [HasAVX10_2_512]
vcvttbf162iubs {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTTBF162IUBSZrmkz [HasAVX10_2_512]
vcvttbf162iubs {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTTBF162IUBSZrr [HasAVX10_2_512]
vcvttbf162iubs {src, dst|dst, src}
VCVTTBF162IUBSZrrk [HasAVX10_2_512]
vcvttbf162iubs {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTTBF162IUBSZrrkz [HasAVX10_2_512]
vcvttbf162iubs {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTTPD2DQSZrm [HasAVX10_2_512]
vcvttpd2dqs {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2DQSZrmb [HasAVX10_2_512]
vcvttpd2dqs {src{1to8}, dst|dst, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2DQSZrmbk [HasAVX10_2_512]
vcvttpd2dqs {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPD2DQSZrmbkz [HasAVX10_2_512]
vcvttpd2dqs {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2DQSZrmk [HasAVX10_2_512]
vcvttpd2dqs {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPD2DQSZrmkz [HasAVX10_2_512]
vcvttpd2dqs {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2DQSZrr [HasAVX10_2_512]
vcvttpd2dqs {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2DQSZrrb [HasAVX10_2_512]
vcvttpd2dqs {{sae}, src, dst|dst, src, {sae}}
VCVTTPD2DQSZrrbk [HasAVX10_2_512]
vcvttpd2dqs {{sae}, src, dst {mask}|dst {mask}, src, {sae}}
|
Note
|
Constraints: src0 = dst |
VCVTTPD2DQSZrrbkz [HasAVX10_2_512]
vcvttpd2dqs {{sae}, src, dst {mask} {z}|dst {mask} {z}, src, {sae}}
VCVTTPD2DQSZrrk [HasAVX10_2_512]
vcvttpd2dqs {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPD2DQSZrrkz [HasAVX10_2_512]
vcvttpd2dqs {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2QQSZrm [HasAVX10_2_512]
vcvttpd2qqs {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2QQSZrmb [HasAVX10_2_512]
vcvttpd2qqs {src{1to8}, dst|dst, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2QQSZrmbk [HasAVX10_2_512]
vcvttpd2qqs {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPD2QQSZrmbkz [HasAVX10_2_512]
vcvttpd2qqs {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2QQSZrmk [HasAVX10_2_512]
vcvttpd2qqs {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPD2QQSZrmkz [HasAVX10_2_512]
vcvttpd2qqs {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2QQSZrr [HasAVX10_2_512]
vcvttpd2qqs {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2QQSZrrb [HasAVX10_2_512]
vcvttpd2qqs {{sae}, src, dst|dst, src, {sae}}
VCVTTPD2QQSZrrbk [HasAVX10_2_512]
vcvttpd2qqs {{sae}, src, dst {mask}|dst {mask}, src, {sae}}
|
Note
|
Constraints: src0 = dst |
VCVTTPD2QQSZrrbkz [HasAVX10_2_512]
vcvttpd2qqs {{sae}, src, dst {mask} {z}|dst {mask} {z}, src, {sae}}
VCVTTPD2QQSZrrk [HasAVX10_2_512]
vcvttpd2qqs {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPD2QQSZrrkz [HasAVX10_2_512]
vcvttpd2qqs {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2UDQSZrm [HasAVX10_2_512]
vcvttpd2udqs {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2UDQSZrmb [HasAVX10_2_512]
vcvttpd2udqs {src{1to8}, dst|dst, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2UDQSZrmbk [HasAVX10_2_512]
vcvttpd2udqs {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPD2UDQSZrmbkz [HasAVX10_2_512]
vcvttpd2udqs {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2UDQSZrmk [HasAVX10_2_512]
vcvttpd2udqs {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPD2UDQSZrmkz [HasAVX10_2_512]
vcvttpd2udqs {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2UDQSZrr [HasAVX10_2_512]
vcvttpd2udqs {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2UDQSZrrb [HasAVX10_2_512]
vcvttpd2udqs {{sae}, src, dst|dst, src, {sae}}
VCVTTPD2UDQSZrrbk [HasAVX10_2_512]
vcvttpd2udqs {{sae}, src, dst {mask}|dst {mask}, src, {sae}}
|
Note
|
Constraints: src0 = dst |
VCVTTPD2UDQSZrrbkz [HasAVX10_2_512]
vcvttpd2udqs {{sae}, src, dst {mask} {z}|dst {mask} {z}, src, {sae}}
VCVTTPD2UDQSZrrk [HasAVX10_2_512]
vcvttpd2udqs {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPD2UDQSZrrkz [HasAVX10_2_512]
vcvttpd2udqs {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2UQQSZrm [HasAVX10_2_512]
vcvttpd2uqqs {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2UQQSZrmb [HasAVX10_2_512]
vcvttpd2uqqs {src{1to8}, dst|dst, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2UQQSZrmbk [HasAVX10_2_512]
vcvttpd2uqqs {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPD2UQQSZrmbkz [HasAVX10_2_512]
vcvttpd2uqqs {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2UQQSZrmk [HasAVX10_2_512]
vcvttpd2uqqs {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPD2UQQSZrmkz [HasAVX10_2_512]
vcvttpd2uqqs {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2UQQSZrr [HasAVX10_2_512]
vcvttpd2uqqs {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2UQQSZrrb [HasAVX10_2_512]
vcvttpd2uqqs {{sae}, src, dst|dst, src, {sae}}
VCVTTPD2UQQSZrrbk [HasAVX10_2_512]
vcvttpd2uqqs {{sae}, src, dst {mask}|dst {mask}, src, {sae}}
|
Note
|
Constraints: src0 = dst |
VCVTTPD2UQQSZrrbkz [HasAVX10_2_512]
vcvttpd2uqqs {{sae}, src, dst {mask} {z}|dst {mask} {z}, src, {sae}}
VCVTTPD2UQQSZrrk [HasAVX10_2_512]
vcvttpd2uqqs {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPD2UQQSZrrkz [HasAVX10_2_512]
vcvttpd2uqqs {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPH2IBSZrm [HasAVX10_2_512]
vcvttph2ibs {src, dst|dst, src}
VCVTTPH2IBSZrmb [HasAVX10_2_512]
vcvttph2ibs {src{1to32}, dst|dst, src{1to32}}
VCVTTPH2IBSZrmbk [HasAVX10_2_512]
vcvttph2ibs {src{1to32}, dst {mask}|dst {mask}, src{1to32}}
|
Note
|
Constraints: src0 = dst |
VCVTTPH2IBSZrmbkz [HasAVX10_2_512]
vcvttph2ibs {src{1to32}, dst {mask} {z}|dst {mask} {z}, src{1to32}}
VCVTTPH2IBSZrmk [HasAVX10_2_512]
vcvttph2ibs {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTTPH2IBSZrmkz [HasAVX10_2_512]
vcvttph2ibs {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTTPH2IBSZrr [HasAVX10_2_512]
vcvttph2ibs {src, dst|dst, src}
VCVTTPH2IBSZrrb [HasAVX10_2_512]
vcvttph2ibs {{sae}, src, dst|dst, src, {sae}}
VCVTTPH2IBSZrrbk [HasAVX10_2_512]
vcvttph2ibs {{sae}, src, dst {mask}|dst {mask}, src, {sae}}
|
Note
|
Constraints: src0 = dst |
VCVTTPH2IBSZrrbkz [HasAVX10_2_512]
vcvttph2ibs {{sae}, src, dst {mask} {z}|dst {mask} {z}, src, {sae}}
VCVTTPH2IBSZrrk [HasAVX10_2_512]
vcvttph2ibs {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTTPH2IBSZrrkz [HasAVX10_2_512]
vcvttph2ibs {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTTPH2IUBSZrm [HasAVX10_2_512]
vcvttph2iubs {src, dst|dst, src}
VCVTTPH2IUBSZrmb [HasAVX10_2_512]
vcvttph2iubs {src{1to32}, dst|dst, src{1to32}}
VCVTTPH2IUBSZrmbk [HasAVX10_2_512]
vcvttph2iubs {src{1to32}, dst {mask}|dst {mask}, src{1to32}}
|
Note
|
Constraints: src0 = dst |
VCVTTPH2IUBSZrmbkz [HasAVX10_2_512]
vcvttph2iubs {src{1to32}, dst {mask} {z}|dst {mask} {z}, src{1to32}}
VCVTTPH2IUBSZrmk [HasAVX10_2_512]
vcvttph2iubs {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTTPH2IUBSZrmkz [HasAVX10_2_512]
vcvttph2iubs {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTTPH2IUBSZrr [HasAVX10_2_512]
vcvttph2iubs {src, dst|dst, src}
VCVTTPH2IUBSZrrb [HasAVX10_2_512]
vcvttph2iubs {{sae}, src, dst|dst, src, {sae}}
VCVTTPH2IUBSZrrbk [HasAVX10_2_512]
vcvttph2iubs {{sae}, src, dst {mask}|dst {mask}, src, {sae}}
|
Note
|
Constraints: src0 = dst |
VCVTTPH2IUBSZrrbkz [HasAVX10_2_512]
vcvttph2iubs {{sae}, src, dst {mask} {z}|dst {mask} {z}, src, {sae}}
VCVTTPH2IUBSZrrk [HasAVX10_2_512]
vcvttph2iubs {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTTPH2IUBSZrrkz [HasAVX10_2_512]
vcvttph2iubs {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTTPS2DQSZrm [HasAVX10_2_512]
vcvttps2dqs {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2DQSZrmb [HasAVX10_2_512]
vcvttps2dqs {src{1to16}, dst|dst, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2DQSZrmbk [HasAVX10_2_512]
vcvttps2dqs {src{1to16}, dst {mask}|dst {mask}, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPS2DQSZrmbkz [HasAVX10_2_512]
vcvttps2dqs {src{1to16}, dst {mask} {z}|dst {mask} {z}, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2DQSZrmk [HasAVX10_2_512]
vcvttps2dqs {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPS2DQSZrmkz [HasAVX10_2_512]
vcvttps2dqs {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2DQSZrr [HasAVX10_2_512]
vcvttps2dqs {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2DQSZrrb [HasAVX10_2_512]
vcvttps2dqs {{sae}, src, dst|dst, src, {sae}}
VCVTTPS2DQSZrrbk [HasAVX10_2_512]
vcvttps2dqs {{sae}, src, dst {mask}|dst {mask}, src, {sae}}
|
Note
|
Constraints: src0 = dst |
VCVTTPS2DQSZrrbkz [HasAVX10_2_512]
vcvttps2dqs {{sae}, src, dst {mask} {z}|dst {mask} {z}, src, {sae}}
VCVTTPS2DQSZrrk [HasAVX10_2_512]
vcvttps2dqs {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPS2DQSZrrkz [HasAVX10_2_512]
vcvttps2dqs {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2IBSZrm [HasAVX10_2_512]
vcvttps2ibs {src, dst|dst, src}
VCVTTPS2IBSZrmb [HasAVX10_2_512]
vcvttps2ibs {src{1to16}, dst|dst, src{1to16}}
VCVTTPS2IBSZrmbk [HasAVX10_2_512]
vcvttps2ibs {src{1to16}, dst {mask}|dst {mask}, src{1to16}}
|
Note
|
Constraints: src0 = dst |
VCVTTPS2IBSZrmbkz [HasAVX10_2_512]
vcvttps2ibs {src{1to16}, dst {mask} {z}|dst {mask} {z}, src{1to16}}
VCVTTPS2IBSZrmk [HasAVX10_2_512]
vcvttps2ibs {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTTPS2IBSZrmkz [HasAVX10_2_512]
vcvttps2ibs {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTTPS2IBSZrr [HasAVX10_2_512]
vcvttps2ibs {src, dst|dst, src}
VCVTTPS2IBSZrrb [HasAVX10_2_512]
vcvttps2ibs {{sae}, src, dst|dst, src, {sae}}
VCVTTPS2IBSZrrbk [HasAVX10_2_512]
vcvttps2ibs {{sae}, src, dst {mask}|dst {mask}, src, {sae}}
|
Note
|
Constraints: src0 = dst |
VCVTTPS2IBSZrrbkz [HasAVX10_2_512]
vcvttps2ibs {{sae}, src, dst {mask} {z}|dst {mask} {z}, src, {sae}}
VCVTTPS2IBSZrrk [HasAVX10_2_512]
vcvttps2ibs {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTTPS2IBSZrrkz [HasAVX10_2_512]
vcvttps2ibs {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTTPS2IUBSZrm [HasAVX10_2_512]
vcvttps2iubs {src, dst|dst, src}
VCVTTPS2IUBSZrmb [HasAVX10_2_512]
vcvttps2iubs {src{1to16}, dst|dst, src{1to16}}
VCVTTPS2IUBSZrmbk [HasAVX10_2_512]
vcvttps2iubs {src{1to16}, dst {mask}|dst {mask}, src{1to16}}
|
Note
|
Constraints: src0 = dst |
VCVTTPS2IUBSZrmbkz [HasAVX10_2_512]
vcvttps2iubs {src{1to16}, dst {mask} {z}|dst {mask} {z}, src{1to16}}
VCVTTPS2IUBSZrmk [HasAVX10_2_512]
vcvttps2iubs {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTTPS2IUBSZrmkz [HasAVX10_2_512]
vcvttps2iubs {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTTPS2IUBSZrr [HasAVX10_2_512]
vcvttps2iubs {src, dst|dst, src}
VCVTTPS2IUBSZrrb [HasAVX10_2_512]
vcvttps2iubs {{sae}, src, dst|dst, src, {sae}}
VCVTTPS2IUBSZrrbk [HasAVX10_2_512]
vcvttps2iubs {{sae}, src, dst {mask}|dst {mask}, src, {sae}}
|
Note
|
Constraints: src0 = dst |
VCVTTPS2IUBSZrrbkz [HasAVX10_2_512]
vcvttps2iubs {{sae}, src, dst {mask} {z}|dst {mask} {z}, src, {sae}}
VCVTTPS2IUBSZrrk [HasAVX10_2_512]
vcvttps2iubs {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTTPS2IUBSZrrkz [HasAVX10_2_512]
vcvttps2iubs {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTTPS2QQSZrm [HasAVX10_2_512]
vcvttps2qqs {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2QQSZrmb [HasAVX10_2_512]
vcvttps2qqs {src{1to8}, dst|dst, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2QQSZrmbk [HasAVX10_2_512]
vcvttps2qqs {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPS2QQSZrmbkz [HasAVX10_2_512]
vcvttps2qqs {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2QQSZrmk [HasAVX10_2_512]
vcvttps2qqs {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPS2QQSZrmkz [HasAVX10_2_512]
vcvttps2qqs {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2QQSZrr [HasAVX10_2_512]
vcvttps2qqs {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2QQSZrrb [HasAVX10_2_512]
vcvttps2qqs {{sae}, src, dst|dst, src, {sae}}
VCVTTPS2QQSZrrbk [HasAVX10_2_512]
vcvttps2qqs {{sae}, src, dst {mask}|dst {mask}, src, {sae}}
|
Note
|
Constraints: src0 = dst |
VCVTTPS2QQSZrrbkz [HasAVX10_2_512]
vcvttps2qqs {{sae}, src, dst {mask} {z}|dst {mask} {z}, src, {sae}}
VCVTTPS2QQSZrrk [HasAVX10_2_512]
vcvttps2qqs {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPS2QQSZrrkz [HasAVX10_2_512]
vcvttps2qqs {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2UDQSZrm [HasAVX10_2_512]
vcvttps2udqs {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2UDQSZrmb [HasAVX10_2_512]
vcvttps2udqs {src{1to16}, dst|dst, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2UDQSZrmbk [HasAVX10_2_512]
vcvttps2udqs {src{1to16}, dst {mask}|dst {mask}, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPS2UDQSZrmbkz [HasAVX10_2_512]
vcvttps2udqs {src{1to16}, dst {mask} {z}|dst {mask} {z}, src{1to16}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2UDQSZrmk [HasAVX10_2_512]
vcvttps2udqs {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPS2UDQSZrmkz [HasAVX10_2_512]
vcvttps2udqs {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2UDQSZrr [HasAVX10_2_512]
vcvttps2udqs {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2UDQSZrrb [HasAVX10_2_512]
vcvttps2udqs {{sae}, src, dst|dst, src, {sae}}
VCVTTPS2UDQSZrrbk [HasAVX10_2_512]
vcvttps2udqs {{sae}, src, dst {mask}|dst {mask}, src, {sae}}
|
Note
|
Constraints: src0 = dst |
VCVTTPS2UDQSZrrbkz [HasAVX10_2_512]
vcvttps2udqs {{sae}, src, dst {mask} {z}|dst {mask} {z}, src, {sae}}
VCVTTPS2UDQSZrrk [HasAVX10_2_512]
vcvttps2udqs {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPS2UDQSZrrkz [HasAVX10_2_512]
vcvttps2udqs {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2UQQSZrm [HasAVX10_2_512]
vcvttps2uqqs {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2UQQSZrmb [HasAVX10_2_512]
vcvttps2uqqs {src{1to8}, dst|dst, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2UQQSZrmbk [HasAVX10_2_512]
vcvttps2uqqs {src{1to8}, dst {mask}|dst {mask}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPS2UQQSZrmbkz [HasAVX10_2_512]
vcvttps2uqqs {src{1to8}, dst {mask} {z}|dst {mask} {z}, src{1to8}}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2UQQSZrmk [HasAVX10_2_512]
vcvttps2uqqs {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPS2UQQSZrmkz [HasAVX10_2_512]
vcvttps2uqqs {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2UQQSZrr [HasAVX10_2_512]
vcvttps2uqqs {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2UQQSZrrb [HasAVX10_2_512]
vcvttps2uqqs {{sae}, src, dst|dst, src, {sae}}
VCVTTPS2UQQSZrrbk [HasAVX10_2_512]
vcvttps2uqqs {{sae}, src, dst {mask}|dst {mask}, src, {sae}}
|
Note
|
Constraints: src0 = dst |
VCVTTPS2UQQSZrrbkz [HasAVX10_2_512]
vcvttps2uqqs {{sae}, src, dst {mask} {z}|dst {mask} {z}, src, {sae}}
VCVTTPS2UQQSZrrk [HasAVX10_2_512]
vcvttps2uqqs {src, dst {mask}|dst {mask}, src}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VCVTTPS2UQQSZrrkz [HasAVX10_2_512]
vcvttps2uqqs {src, dst {mask} {z}|dst {mask} {z}, src}
|
Note
|
Properties: mayRaiseFPException |
VDIVBF16Zrm [HasAVX10_2_512]
vdivbf16 {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VDIVBF16Zrmb [HasAVX10_2_512]
vdivbf16 {src2{1to32}, src1, dst|dst, src1, src2{1to32}}
|
Note
|
Properties: mayLoad |
VDIVBF16Zrmbk [HasAVX10_2_512]
vdivbf16 {src2{1to32}, src1, dst {mask}|dst {mask}, src1, src2{1to32}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VDIVBF16Zrmbkz [HasAVX10_2_512]
vdivbf16 {src2{1to32}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to32}}
|
Note
|
Properties: mayLoad |
VDIVBF16Zrmk [HasAVX10_2_512]
vdivbf16 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VDIVBF16Zrmkz [HasAVX10_2_512]
vdivbf16 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VDIVBF16Zrr [HasAVX10_2_512]
vdivbf16 {src2, src1, dst|dst, src1, src2}
VDIVBF16Zrrk [HasAVX10_2_512]
vdivbf16 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VDIVBF16Zrrkz [HasAVX10_2_512]
vdivbf16 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VDPPHPSZm [HasAVX10_2_512]
vdpphps {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VDPPHPSZmb [HasAVX10_2_512]
vdpphps {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VDPPHPSZmbk [HasAVX10_2_512]
vdpphps {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VDPPHPSZmbkz [HasAVX10_2_512]
vdpphps {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VDPPHPSZmk [HasAVX10_2_512]
vdpphps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VDPPHPSZmkz [HasAVX10_2_512]
vdpphps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VDPPHPSZr [HasAVX10_2_512]
vdpphps {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VDPPHPSZrk [HasAVX10_2_512]
vdpphps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VDPPHPSZrkz [HasAVX10_2_512]
vdpphps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMADD132BF16Zm [HasAVX10_2_512]
vfmadd132bf16 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMADD132BF16Zmb [HasAVX10_2_512]
vfmadd132bf16 {src3{1to32}, src2, dst|dst, src2, src3{1to32}}
|
Note
|
Constraints: src1 = dst |
VFMADD132BF16Zmbk [HasAVX10_2_512]
vfmadd132bf16 {src3{1to32}, src2, dst {mask}|dst {mask}, src2, src3{1to32}}
|
Note
|
Constraints: src1 = dst |
VFMADD132BF16Zmbkz [HasAVX10_2_512]
vfmadd132bf16 {src3{1to32}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to32}}
|
Note
|
Constraints: src1 = dst |
VFMADD132BF16Zmk [HasAVX10_2_512]
vfmadd132bf16 {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMADD132BF16Zmkz [HasAVX10_2_512]
vfmadd132bf16 {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMADD132BF16Zr [HasAVX10_2_512]
vfmadd132bf16 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMADD132BF16Zrk [HasAVX10_2_512]
vfmadd132bf16 {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMADD132BF16Zrkz [HasAVX10_2_512]
vfmadd132bf16 {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMADD213BF16Zm [HasAVX10_2_512]
vfmadd213bf16 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMADD213BF16Zmb [HasAVX10_2_512]
vfmadd213bf16 {src3{1to32}, src2, dst|dst, src2, src3{1to32}}
|
Note
|
Constraints: src1 = dst |
VFMADD213BF16Zmbk [HasAVX10_2_512]
vfmadd213bf16 {src3{1to32}, src2, dst {mask}|dst {mask}, src2, src3{1to32}}
|
Note
|
Constraints: src1 = dst |
VFMADD213BF16Zmbkz [HasAVX10_2_512]
vfmadd213bf16 {src3{1to32}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to32}}
|
Note
|
Constraints: src1 = dst |
VFMADD213BF16Zmk [HasAVX10_2_512]
vfmadd213bf16 {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMADD213BF16Zmkz [HasAVX10_2_512]
vfmadd213bf16 {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMADD213BF16Zr [HasAVX10_2_512]
vfmadd213bf16 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMADD213BF16Zrk [HasAVX10_2_512]
vfmadd213bf16 {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMADD213BF16Zrkz [HasAVX10_2_512]
vfmadd213bf16 {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMADD231BF16Zm [HasAVX10_2_512]
vfmadd231bf16 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMADD231BF16Zmb [HasAVX10_2_512]
vfmadd231bf16 {src3{1to32}, src2, dst|dst, src2, src3{1to32}}
|
Note
|
Constraints: src1 = dst |
VFMADD231BF16Zmbk [HasAVX10_2_512]
vfmadd231bf16 {src3{1to32}, src2, dst {mask}|dst {mask}, src2, src3{1to32}}
|
Note
|
Constraints: src1 = dst |
VFMADD231BF16Zmbkz [HasAVX10_2_512]
vfmadd231bf16 {src3{1to32}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to32}}
|
Note
|
Constraints: src1 = dst |
VFMADD231BF16Zmk [HasAVX10_2_512]
vfmadd231bf16 {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMADD231BF16Zmkz [HasAVX10_2_512]
vfmadd231bf16 {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMADD231BF16Zr [HasAVX10_2_512]
vfmadd231bf16 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMADD231BF16Zrk [HasAVX10_2_512]
vfmadd231bf16 {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMADD231BF16Zrkz [HasAVX10_2_512]
vfmadd231bf16 {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMSUB132BF16Zm [HasAVX10_2_512]
vfmsub132bf16 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMSUB132BF16Zmb [HasAVX10_2_512]
vfmsub132bf16 {src3{1to32}, src2, dst|dst, src2, src3{1to32}}
|
Note
|
Constraints: src1 = dst |
VFMSUB132BF16Zmbk [HasAVX10_2_512]
vfmsub132bf16 {src3{1to32}, src2, dst {mask}|dst {mask}, src2, src3{1to32}}
|
Note
|
Constraints: src1 = dst |
VFMSUB132BF16Zmbkz [HasAVX10_2_512]
vfmsub132bf16 {src3{1to32}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to32}}
|
Note
|
Constraints: src1 = dst |
VFMSUB132BF16Zmk [HasAVX10_2_512]
vfmsub132bf16 {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMSUB132BF16Zmkz [HasAVX10_2_512]
vfmsub132bf16 {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMSUB132BF16Zr [HasAVX10_2_512]
vfmsub132bf16 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMSUB132BF16Zrk [HasAVX10_2_512]
vfmsub132bf16 {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMSUB132BF16Zrkz [HasAVX10_2_512]
vfmsub132bf16 {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMSUB213BF16Zm [HasAVX10_2_512]
vfmsub213bf16 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMSUB213BF16Zmb [HasAVX10_2_512]
vfmsub213bf16 {src3{1to32}, src2, dst|dst, src2, src3{1to32}}
|
Note
|
Constraints: src1 = dst |
VFMSUB213BF16Zmbk [HasAVX10_2_512]
vfmsub213bf16 {src3{1to32}, src2, dst {mask}|dst {mask}, src2, src3{1to32}}
|
Note
|
Constraints: src1 = dst |
VFMSUB213BF16Zmbkz [HasAVX10_2_512]
vfmsub213bf16 {src3{1to32}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to32}}
|
Note
|
Constraints: src1 = dst |
VFMSUB213BF16Zmk [HasAVX10_2_512]
vfmsub213bf16 {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMSUB213BF16Zmkz [HasAVX10_2_512]
vfmsub213bf16 {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMSUB213BF16Zr [HasAVX10_2_512]
vfmsub213bf16 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMSUB213BF16Zrk [HasAVX10_2_512]
vfmsub213bf16 {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMSUB213BF16Zrkz [HasAVX10_2_512]
vfmsub213bf16 {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMSUB231BF16Zm [HasAVX10_2_512]
vfmsub231bf16 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMSUB231BF16Zmb [HasAVX10_2_512]
vfmsub231bf16 {src3{1to32}, src2, dst|dst, src2, src3{1to32}}
|
Note
|
Constraints: src1 = dst |
VFMSUB231BF16Zmbk [HasAVX10_2_512]
vfmsub231bf16 {src3{1to32}, src2, dst {mask}|dst {mask}, src2, src3{1to32}}
|
Note
|
Constraints: src1 = dst |
VFMSUB231BF16Zmbkz [HasAVX10_2_512]
vfmsub231bf16 {src3{1to32}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to32}}
|
Note
|
Constraints: src1 = dst |
VFMSUB231BF16Zmk [HasAVX10_2_512]
vfmsub231bf16 {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMSUB231BF16Zmkz [HasAVX10_2_512]
vfmsub231bf16 {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMSUB231BF16Zr [HasAVX10_2_512]
vfmsub231bf16 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMSUB231BF16Zrk [HasAVX10_2_512]
vfmsub231bf16 {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFMSUB231BF16Zrkz [HasAVX10_2_512]
vfmsub231bf16 {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMADD132BF16Zm [HasAVX10_2_512]
vfnmadd132bf16 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMADD132BF16Zmb [HasAVX10_2_512]
vfnmadd132bf16 {src3{1to32}, src2, dst|dst, src2, src3{1to32}}
|
Note
|
Constraints: src1 = dst |
VFNMADD132BF16Zmbk [HasAVX10_2_512]
vfnmadd132bf16 {src3{1to32}, src2, dst {mask}|dst {mask}, src2, src3{1to32}}
|
Note
|
Constraints: src1 = dst |
VFNMADD132BF16Zmbkz [HasAVX10_2_512]
vfnmadd132bf16 {src3{1to32}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to32}}
|
Note
|
Constraints: src1 = dst |
VFNMADD132BF16Zmk [HasAVX10_2_512]
vfnmadd132bf16 {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMADD132BF16Zmkz [HasAVX10_2_512]
vfnmadd132bf16 {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMADD132BF16Zr [HasAVX10_2_512]
vfnmadd132bf16 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMADD132BF16Zrk [HasAVX10_2_512]
vfnmadd132bf16 {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMADD132BF16Zrkz [HasAVX10_2_512]
vfnmadd132bf16 {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMADD213BF16Zm [HasAVX10_2_512]
vfnmadd213bf16 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMADD213BF16Zmb [HasAVX10_2_512]
vfnmadd213bf16 {src3{1to32}, src2, dst|dst, src2, src3{1to32}}
|
Note
|
Constraints: src1 = dst |
VFNMADD213BF16Zmbk [HasAVX10_2_512]
vfnmadd213bf16 {src3{1to32}, src2, dst {mask}|dst {mask}, src2, src3{1to32}}
|
Note
|
Constraints: src1 = dst |
VFNMADD213BF16Zmbkz [HasAVX10_2_512]
vfnmadd213bf16 {src3{1to32}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to32}}
|
Note
|
Constraints: src1 = dst |
VFNMADD213BF16Zmk [HasAVX10_2_512]
vfnmadd213bf16 {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMADD213BF16Zmkz [HasAVX10_2_512]
vfnmadd213bf16 {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMADD213BF16Zr [HasAVX10_2_512]
vfnmadd213bf16 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMADD213BF16Zrk [HasAVX10_2_512]
vfnmadd213bf16 {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMADD213BF16Zrkz [HasAVX10_2_512]
vfnmadd213bf16 {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMADD231BF16Zm [HasAVX10_2_512]
vfnmadd231bf16 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMADD231BF16Zmb [HasAVX10_2_512]
vfnmadd231bf16 {src3{1to32}, src2, dst|dst, src2, src3{1to32}}
|
Note
|
Constraints: src1 = dst |
VFNMADD231BF16Zmbk [HasAVX10_2_512]
vfnmadd231bf16 {src3{1to32}, src2, dst {mask}|dst {mask}, src2, src3{1to32}}
|
Note
|
Constraints: src1 = dst |
VFNMADD231BF16Zmbkz [HasAVX10_2_512]
vfnmadd231bf16 {src3{1to32}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to32}}
|
Note
|
Constraints: src1 = dst |
VFNMADD231BF16Zmk [HasAVX10_2_512]
vfnmadd231bf16 {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMADD231BF16Zmkz [HasAVX10_2_512]
vfnmadd231bf16 {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMADD231BF16Zr [HasAVX10_2_512]
vfnmadd231bf16 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMADD231BF16Zrk [HasAVX10_2_512]
vfnmadd231bf16 {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMADD231BF16Zrkz [HasAVX10_2_512]
vfnmadd231bf16 {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMSUB132BF16Zm [HasAVX10_2_512]
vfnmsub132bf16 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMSUB132BF16Zmb [HasAVX10_2_512]
vfnmsub132bf16 {src3{1to32}, src2, dst|dst, src2, src3{1to32}}
|
Note
|
Constraints: src1 = dst |
VFNMSUB132BF16Zmbk [HasAVX10_2_512]
vfnmsub132bf16 {src3{1to32}, src2, dst {mask}|dst {mask}, src2, src3{1to32}}
|
Note
|
Constraints: src1 = dst |
VFNMSUB132BF16Zmbkz [HasAVX10_2_512]
vfnmsub132bf16 {src3{1to32}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to32}}
|
Note
|
Constraints: src1 = dst |
VFNMSUB132BF16Zmk [HasAVX10_2_512]
vfnmsub132bf16 {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMSUB132BF16Zmkz [HasAVX10_2_512]
vfnmsub132bf16 {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMSUB132BF16Zr [HasAVX10_2_512]
vfnmsub132bf16 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMSUB132BF16Zrk [HasAVX10_2_512]
vfnmsub132bf16 {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMSUB132BF16Zrkz [HasAVX10_2_512]
vfnmsub132bf16 {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMSUB213BF16Zm [HasAVX10_2_512]
vfnmsub213bf16 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMSUB213BF16Zmb [HasAVX10_2_512]
vfnmsub213bf16 {src3{1to32}, src2, dst|dst, src2, src3{1to32}}
|
Note
|
Constraints: src1 = dst |
VFNMSUB213BF16Zmbk [HasAVX10_2_512]
vfnmsub213bf16 {src3{1to32}, src2, dst {mask}|dst {mask}, src2, src3{1to32}}
|
Note
|
Constraints: src1 = dst |
VFNMSUB213BF16Zmbkz [HasAVX10_2_512]
vfnmsub213bf16 {src3{1to32}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to32}}
|
Note
|
Constraints: src1 = dst |
VFNMSUB213BF16Zmk [HasAVX10_2_512]
vfnmsub213bf16 {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMSUB213BF16Zmkz [HasAVX10_2_512]
vfnmsub213bf16 {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMSUB213BF16Zr [HasAVX10_2_512]
vfnmsub213bf16 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMSUB213BF16Zrk [HasAVX10_2_512]
vfnmsub213bf16 {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMSUB213BF16Zrkz [HasAVX10_2_512]
vfnmsub213bf16 {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMSUB231BF16Zm [HasAVX10_2_512]
vfnmsub231bf16 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMSUB231BF16Zmb [HasAVX10_2_512]
vfnmsub231bf16 {src3{1to32}, src2, dst|dst, src2, src3{1to32}}
|
Note
|
Constraints: src1 = dst |
VFNMSUB231BF16Zmbk [HasAVX10_2_512]
vfnmsub231bf16 {src3{1to32}, src2, dst {mask}|dst {mask}, src2, src3{1to32}}
|
Note
|
Constraints: src1 = dst |
VFNMSUB231BF16Zmbkz [HasAVX10_2_512]
vfnmsub231bf16 {src3{1to32}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to32}}
|
Note
|
Constraints: src1 = dst |
VFNMSUB231BF16Zmk [HasAVX10_2_512]
vfnmsub231bf16 {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMSUB231BF16Zmkz [HasAVX10_2_512]
vfnmsub231bf16 {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMSUB231BF16Zr [HasAVX10_2_512]
vfnmsub231bf16 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMSUB231BF16Zrk [HasAVX10_2_512]
vfnmsub231bf16 {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFNMSUB231BF16Zrkz [HasAVX10_2_512]
vfnmsub231bf16 {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VFPCLASSBF16Zmbi [HasAVX10_2_512]
vfpclassbf16 {src2, src1{1to32}, dst|dst, src1{1to32}, src2}
VFPCLASSBF16Zmbik [HasAVX10_2_512]
vfpclassbf16 {src2, src1{1to32}, dst {mask}|dst {mask}, src1{1to32}, src2}
VFPCLASSBF16Zmi [HasAVX10_2_512]
vfpclassbf16{z} {src2, src1, dst|dst, src1, src2}
VFPCLASSBF16Zmik [HasAVX10_2_512]
vfpclassbf16{z} {src2, src1, dst {mask}|dst {mask}, src1, src2}
VFPCLASSBF16Zri [HasAVX10_2_512]
vfpclassbf16 {src2, src1, dst|dst, src1, src2}
VFPCLASSBF16Zrik [HasAVX10_2_512]
vfpclassbf16 {src2, src1, dst {mask}|dst {mask}, src1, src2}
VGETEXPBF16Zm [HasAVX10_2_512]
vgetexpbf16 {src, dst|dst, src}
VGETEXPBF16Zmb [HasAVX10_2_512]
vgetexpbf16 {src{1to32}, dst|dst, src{1to32}}
VGETEXPBF16Zmbk [HasAVX10_2_512]
vgetexpbf16 {src{1to32}, dst {mask}|dst {mask}, src{1to32}}
|
Note
|
Constraints: src0 = dst |
VGETEXPBF16Zmbkz [HasAVX10_2_512]
vgetexpbf16 {src{1to32}, dst {mask} {z}|dst {mask} {z}, src{1to32}}
VGETEXPBF16Zmk [HasAVX10_2_512]
vgetexpbf16 {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VGETEXPBF16Zmkz [HasAVX10_2_512]
vgetexpbf16 {src, dst {mask} {z}|dst {mask} {z}, src}
VGETEXPBF16Zr [HasAVX10_2_512]
vgetexpbf16 {src, dst|dst, src}
VGETEXPBF16Zrk [HasAVX10_2_512]
vgetexpbf16 {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VGETEXPBF16Zrkz [HasAVX10_2_512]
vgetexpbf16 {src, dst {mask} {z}|dst {mask} {z}, src}
VGETMANTBF16Zrmbi [HasAVX10_2_512]
vgetmantbf16 {src2, src1{1to32}, dst|dst, src1{1to32}, src2}
VGETMANTBF16Zrmbik [HasAVX10_2_512]
vgetmantbf16 {src2, src1{1to32}, dst {mask}|dst {mask}, src1{1to32}, src2}
|
Note
|
Constraints: src0 = dst |
VGETMANTBF16Zrmbikz [HasAVX10_2_512]
vgetmantbf16 {src2, src1{1to32}, dst {mask} {z}|dst {mask} {z}, src1{1to32}, src2}
VGETMANTBF16Zrmi [HasAVX10_2_512]
vgetmantbf16 {src2, src1, dst|dst, src1, src2}
VGETMANTBF16Zrmik [HasAVX10_2_512]
vgetmantbf16 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VGETMANTBF16Zrmikz [HasAVX10_2_512]
vgetmantbf16 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VGETMANTBF16Zrri [HasAVX10_2_512]
vgetmantbf16 {src2, src1, dst|dst, src1, src2}
VGETMANTBF16Zrrik [HasAVX10_2_512]
vgetmantbf16 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VGETMANTBF16Zrrikz [HasAVX10_2_512]
vgetmantbf16 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VMAXBF16Zrm [HasAVX10_2_512]
vmaxbf16 {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VMAXBF16Zrmb [HasAVX10_2_512]
vmaxbf16 {src2{1to32}, src1, dst|dst, src1, src2{1to32}}
|
Note
|
Properties: mayLoad |
VMAXBF16Zrmbk [HasAVX10_2_512]
vmaxbf16 {src2{1to32}, src1, dst {mask}|dst {mask}, src1, src2{1to32}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VMAXBF16Zrmbkz [HasAVX10_2_512]
vmaxbf16 {src2{1to32}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to32}}
|
Note
|
Properties: mayLoad |
VMAXBF16Zrmk [HasAVX10_2_512]
vmaxbf16 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VMAXBF16Zrmkz [HasAVX10_2_512]
vmaxbf16 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VMAXBF16Zrr [HasAVX10_2_512]
vmaxbf16 {src2, src1, dst|dst, src1, src2}
VMAXBF16Zrrk [HasAVX10_2_512]
vmaxbf16 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VMAXBF16Zrrkz [HasAVX10_2_512]
vmaxbf16 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VMINBF16Zrm [HasAVX10_2_512]
vminbf16 {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VMINBF16Zrmb [HasAVX10_2_512]
vminbf16 {src2{1to32}, src1, dst|dst, src1, src2{1to32}}
|
Note
|
Properties: mayLoad |
VMINBF16Zrmbk [HasAVX10_2_512]
vminbf16 {src2{1to32}, src1, dst {mask}|dst {mask}, src1, src2{1to32}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VMINBF16Zrmbkz [HasAVX10_2_512]
vminbf16 {src2{1to32}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to32}}
|
Note
|
Properties: mayLoad |
VMINBF16Zrmk [HasAVX10_2_512]
vminbf16 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VMINBF16Zrmkz [HasAVX10_2_512]
vminbf16 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VMINBF16Zrr [HasAVX10_2_512]
vminbf16 {src2, src1, dst|dst, src1, src2}
VMINBF16Zrrk [HasAVX10_2_512]
vminbf16 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VMINBF16Zrrkz [HasAVX10_2_512]
vminbf16 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VMINMAXBF16Zrmbi [HasAVX10_2_512]
vminmaxbf16 {src3, src2{1to32}, src1, dst|dst, src1, src2{1to32}, src3}
VMINMAXBF16Zrmbik [HasAVX10_2_512]
vminmaxbf16 {src3, src2{1to32}, src1, dst {mask}|dst {mask}, src1, src2{1to32}, src3}
|
Note
|
Constraints: src0 = dst |
VMINMAXBF16Zrmbikz [HasAVX10_2_512]
vminmaxbf16 {src3, src2{1to32}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to32}, src3}
VMINMAXBF16Zrmi [HasAVX10_2_512]
vminmaxbf16 {src3, src2, src1, dst|dst, src1, src2, src3}
VMINMAXBF16Zrmik [HasAVX10_2_512]
vminmaxbf16 {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VMINMAXBF16Zrmikz [HasAVX10_2_512]
vminmaxbf16 {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VMINMAXBF16Zrri [HasAVX10_2_512]
vminmaxbf16 {src3, src2, src1, dst|dst, src1, src2, src3}
VMINMAXBF16Zrrik [HasAVX10_2_512]
vminmaxbf16 {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VMINMAXBF16Zrrikz [HasAVX10_2_512]
vminmaxbf16 {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VMINMAXPDZrmbi [HasAVX10_2_512]
vminmaxpd {src3, src2{1to8}, src1, dst|dst, src1, src2{1to8}, src3}
|
Note
|
Properties: mayRaiseFPException |
VMINMAXPDZrmbik [HasAVX10_2_512]
vminmaxpd {src3, src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMINMAXPDZrmbikz [HasAVX10_2_512]
vminmaxpd {src3, src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}, src3}
|
Note
|
Properties: mayRaiseFPException |
VMINMAXPDZrmi [HasAVX10_2_512]
vminmaxpd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VMINMAXPDZrmik [HasAVX10_2_512]
vminmaxpd {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMINMAXPDZrmikz [HasAVX10_2_512]
vminmaxpd {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VMINMAXPDZrri [HasAVX10_2_512]
vminmaxpd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VMINMAXPDZrrik [HasAVX10_2_512]
vminmaxpd {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMINMAXPDZrrikz [HasAVX10_2_512]
vminmaxpd {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VMINMAXPHZrmbi [HasAVX10_2_512]
vminmaxph {src3, src2{1to32}, src1, dst|dst, src1, src2{1to32}, src3}
|
Note
|
Properties: mayRaiseFPException |
VMINMAXPHZrmbik [HasAVX10_2_512]
vminmaxph {src3, src2{1to32}, src1, dst {mask}|dst {mask}, src1, src2{1to32}, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMINMAXPHZrmbikz [HasAVX10_2_512]
vminmaxph {src3, src2{1to32}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to32}, src3}
|
Note
|
Properties: mayRaiseFPException |
VMINMAXPHZrmi [HasAVX10_2_512]
vminmaxph {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VMINMAXPHZrmik [HasAVX10_2_512]
vminmaxph {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMINMAXPHZrmikz [HasAVX10_2_512]
vminmaxph {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VMINMAXPHZrri [HasAVX10_2_512]
vminmaxph {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VMINMAXPHZrrik [HasAVX10_2_512]
vminmaxph {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMINMAXPHZrrikz [HasAVX10_2_512]
vminmaxph {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VMINMAXPSZrmbi [HasAVX10_2_512]
vminmaxps {src3, src2{1to16}, src1, dst|dst, src1, src2{1to16}, src3}
|
Note
|
Properties: mayRaiseFPException |
VMINMAXPSZrmbik [HasAVX10_2_512]
vminmaxps {src3, src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMINMAXPSZrmbikz [HasAVX10_2_512]
vminmaxps {src3, src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}, src3}
|
Note
|
Properties: mayRaiseFPException |
VMINMAXPSZrmi [HasAVX10_2_512]
vminmaxps {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VMINMAXPSZrmik [HasAVX10_2_512]
vminmaxps {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMINMAXPSZrmikz [HasAVX10_2_512]
vminmaxps {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VMINMAXPSZrri [HasAVX10_2_512]
vminmaxps {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VMINMAXPSZrrik [HasAVX10_2_512]
vminmaxps {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src0 = dst |
VMINMAXPSZrrikz [HasAVX10_2_512]
vminmaxps {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VMULBF16Zrm [HasAVX10_2_512]
vmulbf16 {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VMULBF16Zrmb [HasAVX10_2_512]
vmulbf16 {src2{1to32}, src1, dst|dst, src1, src2{1to32}}
|
Note
|
Properties: mayLoad |
VMULBF16Zrmbk [HasAVX10_2_512]
vmulbf16 {src2{1to32}, src1, dst {mask}|dst {mask}, src1, src2{1to32}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VMULBF16Zrmbkz [HasAVX10_2_512]
vmulbf16 {src2{1to32}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to32}}
|
Note
|
Properties: mayLoad |
VMULBF16Zrmk [HasAVX10_2_512]
vmulbf16 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VMULBF16Zrmkz [HasAVX10_2_512]
vmulbf16 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VMULBF16Zrr [HasAVX10_2_512]
vmulbf16 {src2, src1, dst|dst, src1, src2}
VMULBF16Zrrk [HasAVX10_2_512]
vmulbf16 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VMULBF16Zrrkz [HasAVX10_2_512]
vmulbf16 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPDPBSSDSZm [HasAVX10_2_512]
vpdpbssds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSSDSZmb [HasAVX10_2_512]
vpdpbssds {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VPDPBSSDSZmbk [HasAVX10_2_512]
vpdpbssds {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VPDPBSSDSZmbkz [HasAVX10_2_512]
vpdpbssds {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VPDPBSSDSZmk [HasAVX10_2_512]
vpdpbssds {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSSDSZmkz [HasAVX10_2_512]
vpdpbssds {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSSDSZr [HasAVX10_2_512]
vpdpbssds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSSDSZrk [HasAVX10_2_512]
vpdpbssds {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSSDSZrkz [HasAVX10_2_512]
vpdpbssds {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSSDZm [HasAVX10_2_512]
vpdpbssd {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSSDZmb [HasAVX10_2_512]
vpdpbssd {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VPDPBSSDZmbk [HasAVX10_2_512]
vpdpbssd {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VPDPBSSDZmbkz [HasAVX10_2_512]
vpdpbssd {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VPDPBSSDZmk [HasAVX10_2_512]
vpdpbssd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSSDZmkz [HasAVX10_2_512]
vpdpbssd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSSDZr [HasAVX10_2_512]
vpdpbssd {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSSDZrk [HasAVX10_2_512]
vpdpbssd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSSDZrkz [HasAVX10_2_512]
vpdpbssd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSUDSZm [HasAVX10_2_512]
vpdpbsuds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSUDSZmb [HasAVX10_2_512]
vpdpbsuds {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VPDPBSUDSZmbk [HasAVX10_2_512]
vpdpbsuds {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VPDPBSUDSZmbkz [HasAVX10_2_512]
vpdpbsuds {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VPDPBSUDSZmk [HasAVX10_2_512]
vpdpbsuds {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSUDSZmkz [HasAVX10_2_512]
vpdpbsuds {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSUDSZr [HasAVX10_2_512]
vpdpbsuds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSUDSZrk [HasAVX10_2_512]
vpdpbsuds {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSUDSZrkz [HasAVX10_2_512]
vpdpbsuds {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSUDZm [HasAVX10_2_512]
vpdpbsud {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSUDZmb [HasAVX10_2_512]
vpdpbsud {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VPDPBSUDZmbk [HasAVX10_2_512]
vpdpbsud {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VPDPBSUDZmbkz [HasAVX10_2_512]
vpdpbsud {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VPDPBSUDZmk [HasAVX10_2_512]
vpdpbsud {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSUDZmkz [HasAVX10_2_512]
vpdpbsud {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSUDZr [HasAVX10_2_512]
vpdpbsud {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSUDZrk [HasAVX10_2_512]
vpdpbsud {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSUDZrkz [HasAVX10_2_512]
vpdpbsud {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUUDSZm [HasAVX10_2_512]
vpdpbuuds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUUDSZmb [HasAVX10_2_512]
vpdpbuuds {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VPDPBUUDSZmbk [HasAVX10_2_512]
vpdpbuuds {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VPDPBUUDSZmbkz [HasAVX10_2_512]
vpdpbuuds {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VPDPBUUDSZmk [HasAVX10_2_512]
vpdpbuuds {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUUDSZmkz [HasAVX10_2_512]
vpdpbuuds {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUUDSZr [HasAVX10_2_512]
vpdpbuuds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUUDSZrk [HasAVX10_2_512]
vpdpbuuds {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUUDSZrkz [HasAVX10_2_512]
vpdpbuuds {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUUDZm [HasAVX10_2_512]
vpdpbuud {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUUDZmb [HasAVX10_2_512]
vpdpbuud {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VPDPBUUDZmbk [HasAVX10_2_512]
vpdpbuud {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VPDPBUUDZmbkz [HasAVX10_2_512]
vpdpbuud {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VPDPBUUDZmk [HasAVX10_2_512]
vpdpbuud {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUUDZmkz [HasAVX10_2_512]
vpdpbuud {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUUDZr [HasAVX10_2_512]
vpdpbuud {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUUDZrk [HasAVX10_2_512]
vpdpbuud {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUUDZrkz [HasAVX10_2_512]
vpdpbuud {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSUDSZm [HasAVX10_2_512]
vpdpwsuds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSUDSZmb [HasAVX10_2_512]
vpdpwsuds {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VPDPWSUDSZmbk [HasAVX10_2_512]
vpdpwsuds {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VPDPWSUDSZmbkz [HasAVX10_2_512]
vpdpwsuds {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VPDPWSUDSZmk [HasAVX10_2_512]
vpdpwsuds {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSUDSZmkz [HasAVX10_2_512]
vpdpwsuds {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSUDSZr [HasAVX10_2_512]
vpdpwsuds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSUDSZrk [HasAVX10_2_512]
vpdpwsuds {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSUDSZrkz [HasAVX10_2_512]
vpdpwsuds {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSUDZm [HasAVX10_2_512]
vpdpwsud {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSUDZmb [HasAVX10_2_512]
vpdpwsud {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VPDPWSUDZmbk [HasAVX10_2_512]
vpdpwsud {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VPDPWSUDZmbkz [HasAVX10_2_512]
vpdpwsud {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VPDPWSUDZmk [HasAVX10_2_512]
vpdpwsud {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSUDZmkz [HasAVX10_2_512]
vpdpwsud {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSUDZr [HasAVX10_2_512]
vpdpwsud {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSUDZrk [HasAVX10_2_512]
vpdpwsud {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSUDZrkz [HasAVX10_2_512]
vpdpwsud {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUSDSZm [HasAVX10_2_512]
vpdpwusds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUSDSZmb [HasAVX10_2_512]
vpdpwusds {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VPDPWUSDSZmbk [HasAVX10_2_512]
vpdpwusds {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VPDPWUSDSZmbkz [HasAVX10_2_512]
vpdpwusds {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VPDPWUSDSZmk [HasAVX10_2_512]
vpdpwusds {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUSDSZmkz [HasAVX10_2_512]
vpdpwusds {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUSDSZr [HasAVX10_2_512]
vpdpwusds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUSDSZrk [HasAVX10_2_512]
vpdpwusds {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUSDSZrkz [HasAVX10_2_512]
vpdpwusds {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUSDZm [HasAVX10_2_512]
vpdpwusd {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUSDZmb [HasAVX10_2_512]
vpdpwusd {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VPDPWUSDZmbk [HasAVX10_2_512]
vpdpwusd {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VPDPWUSDZmbkz [HasAVX10_2_512]
vpdpwusd {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VPDPWUSDZmk [HasAVX10_2_512]
vpdpwusd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUSDZmkz [HasAVX10_2_512]
vpdpwusd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUSDZr [HasAVX10_2_512]
vpdpwusd {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUSDZrk [HasAVX10_2_512]
vpdpwusd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUSDZrkz [HasAVX10_2_512]
vpdpwusd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUUDSZm [HasAVX10_2_512]
vpdpwuuds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUUDSZmb [HasAVX10_2_512]
vpdpwuuds {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VPDPWUUDSZmbk [HasAVX10_2_512]
vpdpwuuds {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VPDPWUUDSZmbkz [HasAVX10_2_512]
vpdpwuuds {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VPDPWUUDSZmk [HasAVX10_2_512]
vpdpwuuds {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUUDSZmkz [HasAVX10_2_512]
vpdpwuuds {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUUDSZr [HasAVX10_2_512]
vpdpwuuds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUUDSZrk [HasAVX10_2_512]
vpdpwuuds {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUUDSZrkz [HasAVX10_2_512]
vpdpwuuds {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUUDZm [HasAVX10_2_512]
vpdpwuud {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUUDZmb [HasAVX10_2_512]
vpdpwuud {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VPDPWUUDZmbk [HasAVX10_2_512]
vpdpwuud {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VPDPWUUDZmbkz [HasAVX10_2_512]
vpdpwuud {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VPDPWUUDZmk [HasAVX10_2_512]
vpdpwuud {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUUDZmkz [HasAVX10_2_512]
vpdpwuud {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUUDZr [HasAVX10_2_512]
vpdpwuud {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUUDZrk [HasAVX10_2_512]
vpdpwuud {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUUDZrkz [HasAVX10_2_512]
vpdpwuud {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VRCPBF16Zm [HasAVX10_2_512]
vrcpbf16 {src, dst|dst, src}
VRCPBF16Zmb [HasAVX10_2_512]
vrcpbf16 {src{1to32}, dst|dst, src{1to32}}
VRCPBF16Zmbk [HasAVX10_2_512]
vrcpbf16 {src{1to32}, dst {mask}|dst {mask}, src{1to32}}
|
Note
|
Constraints: src0 = dst |
VRCPBF16Zmbkz [HasAVX10_2_512]
vrcpbf16 {src{1to32}, dst {mask} {z}|dst {mask} {z}, src{1to32}}
VRCPBF16Zmk [HasAVX10_2_512]
vrcpbf16 {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VRCPBF16Zmkz [HasAVX10_2_512]
vrcpbf16 {src, dst {mask} {z}|dst {mask} {z}, src}
VRCPBF16Zr [HasAVX10_2_512]
vrcpbf16 {src, dst|dst, src}
VRCPBF16Zrk [HasAVX10_2_512]
vrcpbf16 {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VRCPBF16Zrkz [HasAVX10_2_512]
vrcpbf16 {src, dst {mask} {z}|dst {mask} {z}, src}
VREDUCEBF16Zrmbi [HasAVX10_2_512]
vreducebf16 {src2, src1{1to32}, dst|dst, src1{1to32}, src2}
VREDUCEBF16Zrmbik [HasAVX10_2_512]
vreducebf16 {src2, src1{1to32}, dst {mask}|dst {mask}, src1{1to32}, src2}
|
Note
|
Constraints: src0 = dst |
VREDUCEBF16Zrmbikz [HasAVX10_2_512]
vreducebf16 {src2, src1{1to32}, dst {mask} {z}|dst {mask} {z}, src1{1to32}, src2}
VREDUCEBF16Zrmi [HasAVX10_2_512]
vreducebf16 {src2, src1, dst|dst, src1, src2}
VREDUCEBF16Zrmik [HasAVX10_2_512]
vreducebf16 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VREDUCEBF16Zrmikz [HasAVX10_2_512]
vreducebf16 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VREDUCEBF16Zrri [HasAVX10_2_512]
vreducebf16 {src2, src1, dst|dst, src1, src2}
VREDUCEBF16Zrrik [HasAVX10_2_512]
vreducebf16 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VREDUCEBF16Zrrikz [HasAVX10_2_512]
vreducebf16 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VRNDSCALEBF16Zrmbi [HasAVX10_2_512]
vrndscalebf16 {src2, src1{1to32}, dst|dst, src1{1to32}, src2}
VRNDSCALEBF16Zrmbik [HasAVX10_2_512]
vrndscalebf16 {src2, src1{1to32}, dst {mask}|dst {mask}, src1{1to32}, src2}
|
Note
|
Constraints: src0 = dst |
VRNDSCALEBF16Zrmbikz [HasAVX10_2_512]
vrndscalebf16 {src2, src1{1to32}, dst {mask} {z}|dst {mask} {z}, src1{1to32}, src2}
VRNDSCALEBF16Zrmi [HasAVX10_2_512]
vrndscalebf16 {src2, src1, dst|dst, src1, src2}
VRNDSCALEBF16Zrmik [HasAVX10_2_512]
vrndscalebf16 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VRNDSCALEBF16Zrmikz [HasAVX10_2_512]
vrndscalebf16 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VRNDSCALEBF16Zrri [HasAVX10_2_512]
vrndscalebf16 {src2, src1, dst|dst, src1, src2}
VRNDSCALEBF16Zrrik [HasAVX10_2_512]
vrndscalebf16 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VRNDSCALEBF16Zrrikz [HasAVX10_2_512]
vrndscalebf16 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VRSQRTBF16Zm [HasAVX10_2_512]
vrsqrtbf16 {src, dst|dst, src}
VRSQRTBF16Zmb [HasAVX10_2_512]
vrsqrtbf16 {src{1to32}, dst|dst, src{1to32}}
VRSQRTBF16Zmbk [HasAVX10_2_512]
vrsqrtbf16 {src{1to32}, dst {mask}|dst {mask}, src{1to32}}
|
Note
|
Constraints: src0 = dst |
VRSQRTBF16Zmbkz [HasAVX10_2_512]
vrsqrtbf16 {src{1to32}, dst {mask} {z}|dst {mask} {z}, src{1to32}}
VRSQRTBF16Zmk [HasAVX10_2_512]
vrsqrtbf16 {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VRSQRTBF16Zmkz [HasAVX10_2_512]
vrsqrtbf16 {src, dst {mask} {z}|dst {mask} {z}, src}
VRSQRTBF16Zr [HasAVX10_2_512]
vrsqrtbf16 {src, dst|dst, src}
VRSQRTBF16Zrk [HasAVX10_2_512]
vrsqrtbf16 {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VRSQRTBF16Zrkz [HasAVX10_2_512]
vrsqrtbf16 {src, dst {mask} {z}|dst {mask} {z}, src}
VSCALEFBF16Zrm [HasAVX10_2_512]
vscalefbf16 {src2, src1, dst|dst, src1, src2}
VSCALEFBF16Zrmb [HasAVX10_2_512]
vscalefbf16 {src2{1to32}, src1, dst|dst, src1, src2{1to32}}
VSCALEFBF16Zrmbk [HasAVX10_2_512]
vscalefbf16 {src2{1to32}, src1, dst {mask}|dst {mask}, src1, src2{1to32}}
|
Note
|
Constraints: src0 = dst |
VSCALEFBF16Zrmbkz [HasAVX10_2_512]
vscalefbf16 {src2{1to32}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to32}}
VSCALEFBF16Zrmk [HasAVX10_2_512]
vscalefbf16 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VSCALEFBF16Zrmkz [HasAVX10_2_512]
vscalefbf16 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VSCALEFBF16Zrr [HasAVX10_2_512]
vscalefbf16 {src2, src1, dst|dst, src1, src2}
VSCALEFBF16Zrrk [HasAVX10_2_512]
vscalefbf16 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VSCALEFBF16Zrrkz [HasAVX10_2_512]
vscalefbf16 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VSQRTBF16Zm [HasAVX10_2_512]
vsqrtbf16 {src, dst|dst, src}
VSQRTBF16Zmb [HasAVX10_2_512]
vsqrtbf16 {src{1to32}, dst|dst, src{1to32}}
VSQRTBF16Zmbk [HasAVX10_2_512]
vsqrtbf16 {src{1to32}, dst {mask}|dst {mask}, src{1to32}}
|
Note
|
Constraints: src0 = dst |
VSQRTBF16Zmbkz [HasAVX10_2_512]
vsqrtbf16 {src{1to32}, dst {mask} {z}|dst {mask} {z}, src{1to32}}
VSQRTBF16Zmk [HasAVX10_2_512]
vsqrtbf16 {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VSQRTBF16Zmkz [HasAVX10_2_512]
vsqrtbf16 {src, dst {mask} {z}|dst {mask} {z}, src}
VSQRTBF16Zr [HasAVX10_2_512]
vsqrtbf16 {src, dst|dst, src}
VSQRTBF16Zrk [HasAVX10_2_512]
vsqrtbf16 {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VSQRTBF16Zrkz [HasAVX10_2_512]
vsqrtbf16 {src, dst {mask} {z}|dst {mask} {z}, src}
VSUBBF16Zrm [HasAVX10_2_512]
vsubbf16 {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VSUBBF16Zrmb [HasAVX10_2_512]
vsubbf16 {src2{1to32}, src1, dst|dst, src1, src2{1to32}}
|
Note
|
Properties: mayLoad |
VSUBBF16Zrmbk [HasAVX10_2_512]
vsubbf16 {src2{1to32}, src1, dst {mask}|dst {mask}, src1, src2{1to32}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VSUBBF16Zrmbkz [HasAVX10_2_512]
vsubbf16 {src2{1to32}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to32}}
|
Note
|
Properties: mayLoad |
VSUBBF16Zrmk [HasAVX10_2_512]
vsubbf16 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src0 = dst |
VSUBBF16Zrmkz [HasAVX10_2_512]
vsubbf16 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
|
Note
|
Properties: mayLoad |
VSUBBF16Zrr [HasAVX10_2_512]
vsubbf16 {src2, src1, dst|dst, src1, src2}
VSUBBF16Zrrk [HasAVX10_2_512]
vsubbf16 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VSUBBF16Zrrkz [HasAVX10_2_512]
vsubbf16 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VSM4KEY4Zrm [HasAVX10_2_512, HasSM4]
vsm4key4 {src2, src1, dst|dst, src1, src2}
VSM4KEY4Zrr [HasAVX10_2_512, HasSM4]
vsm4key4 {src2, src1, dst|dst, src1, src2}
VSM4RNDS4Zrm [HasAVX10_2_512, HasSM4]
vsm4rnds4 {src2, src1, dst|dst, src1, src2}
VSM4RNDS4Zrr [HasAVX10_2_512, HasSM4]
vsm4rnds4 {src2, src1, dst|dst, src1, src2}
VADDPDYrm [NoVLX, HasAVX]
vaddpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VADDPDYrr [NoVLX, HasAVX]
vaddpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VADDPDrm [NoVLX, HasAVX]
vaddpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VADDPDrr [NoVLX, HasAVX]
vaddpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VADDPSYrm [NoVLX, HasAVX]
vaddps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VADDPSYrr [NoVLX, HasAVX]
vaddps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VADDPSrm [NoVLX, HasAVX]
vaddps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VADDPSrr [NoVLX, HasAVX]
vaddps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VANDNPDYrm [NoVLX, HasAVX]
vandnpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VANDNPDYrr [NoVLX, HasAVX]
vandnpd {src2, src1, dst|dst, src1, src2}
VANDNPDrm [NoVLX, HasAVX]
vandnpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VANDNPDrr [NoVLX, HasAVX]
vandnpd {src2, src1, dst|dst, src1, src2}
VANDNPSYrm [NoVLX, HasAVX]
vandnps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VANDNPSYrr [NoVLX, HasAVX]
vandnps {src2, src1, dst|dst, src1, src2}
VANDNPSrm [NoVLX, HasAVX]
vandnps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VANDNPSrr [NoVLX, HasAVX]
vandnps {src2, src1, dst|dst, src1, src2}
VANDPDYrm [NoVLX, HasAVX]
vandpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VANDPDYrr [NoVLX, HasAVX]
vandpd {src2, src1, dst|dst, src1, src2}
VANDPDrm [NoVLX, HasAVX]
vandpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VANDPDrr [NoVLX, HasAVX]
vandpd {src2, src1, dst|dst, src1, src2}
VANDPSYrm [NoVLX, HasAVX]
vandps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VANDPSYrr [NoVLX, HasAVX]
vandps {src2, src1, dst|dst, src1, src2}
VANDPSrm [NoVLX, HasAVX]
vandps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VANDPSrr [NoVLX, HasAVX]
vandps {src2, src1, dst|dst, src1, src2}
VBROADCASTSDYrm [NoVLX, HasAVX]
vbroadcastsd {src, dst|dst, src}
VBROADCASTSSYrm [NoVLX, HasAVX]
vbroadcastss {src, dst|dst, src}
VBROADCASTSSrm [NoVLX, HasAVX]
vbroadcastss {src, dst|dst, src}
VCVTDQ2PDYrm [NoVLX, HasAVX]
vcvtdq2pd {src, dst|dst, src}
VCVTDQ2PDYrr [NoVLX, HasAVX]
vcvtdq2pd {src, dst|dst, src}
VCVTDQ2PDrm [NoVLX, HasAVX]
vcvtdq2pd {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
VCVTDQ2PDrr [NoVLX, HasAVX]
vcvtdq2pd {src, dst|dst, src}
VCVTDQ2PSYrm [NoVLX, HasAVX]
vcvtdq2ps {src, dst|dst, src}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VCVTDQ2PSYrr [NoVLX, HasAVX]
vcvtdq2ps {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTDQ2PSrm [NoVLX, HasAVX]
vcvtdq2ps {src, dst|dst, src}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VCVTDQ2PSrr [NoVLX, HasAVX]
vcvtdq2ps {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2DQYrm [NoVLX, HasAVX]
vcvtpd2dq{y} {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2DQYrr [NoVLX, HasAVX]
vcvtpd2dq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2DQrm [NoVLX, HasAVX]
vcvtpd2dq{x} {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2DQrr [NoVLX, HasAVX]
vcvtpd2dq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2PSYrm [NoVLX, HasAVX]
vcvtpd2ps{y} {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2PSYrr [NoVLX, HasAVX]
vcvtpd2ps {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2PSrm [NoVLX, HasAVX]
vcvtpd2ps{x} {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPD2PSrr [NoVLX, HasAVX]
vcvtpd2ps {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2DQYrm [NoVLX, HasAVX]
vcvtps2dq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2DQYrr [NoVLX, HasAVX]
vcvtps2dq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2DQrm [NoVLX, HasAVX]
vcvtps2dq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2DQrr [NoVLX, HasAVX]
vcvtps2dq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2PDYrm [NoVLX, HasAVX]
vcvtps2pd {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2PDYrr [NoVLX, HasAVX]
vcvtps2pd {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2PDrm [NoVLX, HasAVX]
vcvtps2pd {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2PDrr [NoVLX, HasAVX]
vcvtps2pd {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2DQYrm [NoVLX, HasAVX]
vcvttpd2dq{y} {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2DQYrr [NoVLX, HasAVX]
vcvttpd2dq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2DQrm [NoVLX, HasAVX]
vcvttpd2dq{x} {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPD2DQrr [NoVLX, HasAVX]
vcvttpd2dq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2DQYrm [NoVLX, HasAVX]
vcvttps2dq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2DQYrr [NoVLX, HasAVX]
vcvttps2dq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2DQrm [NoVLX, HasAVX]
vcvttps2dq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTPS2DQrr [NoVLX, HasAVX]
vcvttps2dq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VDIVPDYrm [NoVLX, HasAVX]
vdivpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VDIVPDYrr [NoVLX, HasAVX]
vdivpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VDIVPDrm [NoVLX, HasAVX]
vdivpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VDIVPDrr [NoVLX, HasAVX]
vdivpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VDIVPSYrm [NoVLX, HasAVX]
vdivps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VDIVPSYrr [NoVLX, HasAVX]
vdivps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VDIVPSrm [NoVLX, HasAVX]
vdivps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VDIVPSrr [NoVLX, HasAVX]
vdivps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMAXPDYrm [NoVLX, HasAVX]
vmaxpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMAXPDYrr [NoVLX, HasAVX]
vmaxpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMAXPDrm [NoVLX, HasAVX]
vmaxpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMAXPDrr [NoVLX, HasAVX]
vmaxpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMAXPSYrm [NoVLX, HasAVX]
vmaxps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMAXPSYrr [NoVLX, HasAVX]
vmaxps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMAXPSrm [NoVLX, HasAVX]
vmaxps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMAXPSrr [NoVLX, HasAVX]
vmaxps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMINPDYrm [NoVLX, HasAVX]
vminpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMINPDYrr [NoVLX, HasAVX]
vminpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMINPDrm [NoVLX, HasAVX]
vminpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMINPDrr [NoVLX, HasAVX]
vminpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMINPSYrm [NoVLX, HasAVX]
vminps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMINPSYrr [NoVLX, HasAVX]
vminps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMINPSrm [NoVLX, HasAVX]
vminps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMINPSrr [NoVLX, HasAVX]
vminps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMOVAPDYmr [NoVLX, HasAVX]
vmovapd {src, dst|dst, src}
VMOVAPDYrm [NoVLX, HasAVX]
vmovapd {src, dst|dst, src}
VMOVAPDYrr [NoVLX, HasAVX]
vmovapd {src, dst|dst, src}
|
Note
|
Properties: isMoveReg |
VMOVAPDmr [NoVLX, HasAVX]
vmovapd {src, dst|dst, src}
VMOVAPDrm [NoVLX, HasAVX]
vmovapd {src, dst|dst, src}
VMOVAPDrr [NoVLX, HasAVX]
vmovapd {src, dst|dst, src}
|
Note
|
Properties: isMoveReg |
VMOVAPSYmr [NoVLX, HasAVX]
vmovaps {src, dst|dst, src}
VMOVAPSYrm [NoVLX, HasAVX]
vmovaps {src, dst|dst, src}
VMOVAPSYrr [NoVLX, HasAVX]
vmovaps {src, dst|dst, src}
|
Note
|
Properties: isMoveReg |
VMOVAPSmr [NoVLX, HasAVX]
vmovaps {src, dst|dst, src}
VMOVAPSrm [NoVLX, HasAVX]
vmovaps {src, dst|dst, src}
VMOVAPSrr [NoVLX, HasAVX]
vmovaps {src, dst|dst, src}
|
Note
|
Properties: isMoveReg |
VMOVDDUPYrm [NoVLX, HasAVX]
vmovddup {src, dst|dst, src}
VMOVDDUPYrr [NoVLX, HasAVX]
vmovddup {src, dst|dst, src}
VMOVDDUPrm [NoVLX, HasAVX]
vmovddup {src, dst|dst, src}
VMOVDDUPrr [NoVLX, HasAVX]
vmovddup {src, dst|dst, src}
VMOVDQAYmr [NoVLX, HasAVX]
vmovdqa {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VMOVDQAYrm [NoVLX, HasAVX]
vmovdqa {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
VMOVDQAmr [NoVLX, HasAVX]
vmovdqa {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VMOVDQArm [NoVLX, HasAVX]
vmovdqa {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
VMOVDQUYmr [NoVLX, HasAVX]
vmovdqu {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VMOVDQUYrm [NoVLX, HasAVX]
vmovdqu {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
VMOVDQUmr [NoVLX, HasAVX]
vmovdqu {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VMOVDQUrm [NoVLX, HasAVX]
vmovdqu {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
VMOVNTDQArm [NoVLX, HasAVX]
vmovntdqa {src, dst|dst, src}
VMOVNTDQYmr [NoVLX, HasAVX]
vmovntdq {src, dst|dst, src}
VMOVNTDQmr [NoVLX, HasAVX]
vmovntdq {src, dst|dst, src}
VMOVNTPDYmr [NoVLX, HasAVX]
vmovntpd {src, dst|dst, src}
VMOVNTPDmr [NoVLX, HasAVX]
vmovntpd {src, dst|dst, src}
VMOVNTPSYmr [NoVLX, HasAVX]
vmovntps {src, dst|dst, src}
VMOVNTPSmr [NoVLX, HasAVX]
vmovntps {src, dst|dst, src}
VMOVSHDUPYrm [NoVLX, HasAVX]
vmovshdup {src, dst|dst, src}
VMOVSHDUPYrr [NoVLX, HasAVX]
vmovshdup {src, dst|dst, src}
VMOVSHDUPrm [NoVLX, HasAVX]
vmovshdup {src, dst|dst, src}
VMOVSHDUPrr [NoVLX, HasAVX]
vmovshdup {src, dst|dst, src}
VMOVSLDUPYrm [NoVLX, HasAVX]
vmovsldup {src, dst|dst, src}
VMOVSLDUPYrr [NoVLX, HasAVX]
vmovsldup {src, dst|dst, src}
VMOVSLDUPrm [NoVLX, HasAVX]
vmovsldup {src, dst|dst, src}
VMOVSLDUPrr [NoVLX, HasAVX]
vmovsldup {src, dst|dst, src}
VMOVUPDYmr [NoVLX, HasAVX]
vmovupd {src, dst|dst, src}
VMOVUPDYrm [NoVLX, HasAVX]
vmovupd {src, dst|dst, src}
VMOVUPDYrr [NoVLX, HasAVX]
vmovupd {src, dst|dst, src}
|
Note
|
Properties: isMoveReg |
VMOVUPDmr [NoVLX, HasAVX]
vmovupd {src, dst|dst, src}
VMOVUPDrm [NoVLX, HasAVX]
vmovupd {src, dst|dst, src}
VMOVUPDrr [NoVLX, HasAVX]
vmovupd {src, dst|dst, src}
|
Note
|
Properties: isMoveReg |
VMOVUPSYmr [NoVLX, HasAVX]
vmovups {src, dst|dst, src}
VMOVUPSYrm [NoVLX, HasAVX]
vmovups {src, dst|dst, src}
VMOVUPSYrr [NoVLX, HasAVX]
vmovups {src, dst|dst, src}
|
Note
|
Properties: isMoveReg |
VMOVUPSmr [NoVLX, HasAVX]
vmovups {src, dst|dst, src}
VMOVUPSrm [NoVLX, HasAVX]
vmovups {src, dst|dst, src}
VMOVUPSrr [NoVLX, HasAVX]
vmovups {src, dst|dst, src}
|
Note
|
Properties: isMoveReg |
VMULPDYrm [NoVLX, HasAVX]
vmulpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMULPDYrr [NoVLX, HasAVX]
vmulpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMULPDrm [NoVLX, HasAVX]
vmulpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMULPDrr [NoVLX, HasAVX]
vmulpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMULPSYrm [NoVLX, HasAVX]
vmulps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMULPSYrr [NoVLX, HasAVX]
vmulps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMULPSrm [NoVLX, HasAVX]
vmulps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMULPSrr [NoVLX, HasAVX]
vmulps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VORPDYrm [NoVLX, HasAVX]
vorpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VORPDYrr [NoVLX, HasAVX]
vorpd {src2, src1, dst|dst, src1, src2}
VORPDrm [NoVLX, HasAVX]
vorpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VORPDrr [NoVLX, HasAVX]
vorpd {src2, src1, dst|dst, src1, src2}
VORPSYrm [NoVLX, HasAVX]
vorps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VORPSYrr [NoVLX, HasAVX]
vorps {src2, src1, dst|dst, src1, src2}
VORPSrm [NoVLX, HasAVX]
vorps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VORPSrr [NoVLX, HasAVX]
vorps {src2, src1, dst|dst, src1, src2}
VPABSDrm [NoVLX, HasAVX]
vpabsd {src, dst|dst, src}
VPABSDrr [NoVLX, HasAVX]
vpabsd {src, dst|dst, src}
VPADDDrm [NoVLX, HasAVX]
vpaddd {src2, src1, dst|dst, src1, src2}
VPADDDrr [NoVLX, HasAVX]
vpaddd {src2, src1, dst|dst, src1, src2}
VPADDQrm [NoVLX, HasAVX]
vpaddq {src2, src1, dst|dst, src1, src2}
VPADDQrr [NoVLX, HasAVX]
vpaddq {src2, src1, dst|dst, src1, src2}
VPANDNrm [NoVLX, HasAVX]
vpandn {src2, src1, dst|dst, src1, src2}
VPANDNrr [NoVLX, HasAVX]
vpandn {src2, src1, dst|dst, src1, src2}
VPANDrm [NoVLX, HasAVX]
vpand {src2, src1, dst|dst, src1, src2}
VPANDrr [NoVLX, HasAVX]
vpand {src2, src1, dst|dst, src1, src2}
VPERMILPDYmi [NoVLX, HasAVX]
vpermilpd {src2, src1, dst|dst, src1, src2}
VPERMILPDYri [NoVLX, HasAVX]
vpermilpd {src2, src1, dst|dst, src1, src2}
VPERMILPDYrm [NoVLX, HasAVX]
vpermilpd {src2, src1, dst|dst, src1, src2}
VPERMILPDYrr [NoVLX, HasAVX]
vpermilpd {src2, src1, dst|dst, src1, src2}
VPERMILPDmi [NoVLX, HasAVX]
vpermilpd {src2, src1, dst|dst, src1, src2}
VPERMILPDri [NoVLX, HasAVX]
vpermilpd {src2, src1, dst|dst, src1, src2}
VPERMILPDrm [NoVLX, HasAVX]
vpermilpd {src2, src1, dst|dst, src1, src2}
VPERMILPDrr [NoVLX, HasAVX]
vpermilpd {src2, src1, dst|dst, src1, src2}
VPERMILPSYmi [NoVLX, HasAVX]
vpermilps {src2, src1, dst|dst, src1, src2}
VPERMILPSYri [NoVLX, HasAVX]
vpermilps {src2, src1, dst|dst, src1, src2}
VPERMILPSYrm [NoVLX, HasAVX]
vpermilps {src2, src1, dst|dst, src1, src2}
VPERMILPSYrr [NoVLX, HasAVX]
vpermilps {src2, src1, dst|dst, src1, src2}
VPERMILPSmi [NoVLX, HasAVX]
vpermilps {src2, src1, dst|dst, src1, src2}
VPERMILPSri [NoVLX, HasAVX]
vpermilps {src2, src1, dst|dst, src1, src2}
VPERMILPSrm [NoVLX, HasAVX]
vpermilps {src2, src1, dst|dst, src1, src2}
VPERMILPSrr [NoVLX, HasAVX]
vpermilps {src2, src1, dst|dst, src1, src2}
VPMAXSDrm [NoVLX, HasAVX]
vpmaxsd {src2, src1, dst|dst, src1, src2}
VPMAXSDrr [NoVLX, HasAVX]
vpmaxsd {src2, src1, dst|dst, src1, src2}
VPMAXUDrm [NoVLX, HasAVX]
vpmaxud {src2, src1, dst|dst, src1, src2}
VPMAXUDrr [NoVLX, HasAVX]
vpmaxud {src2, src1, dst|dst, src1, src2}
VPMINSDrm [NoVLX, HasAVX]
vpminsd {src2, src1, dst|dst, src1, src2}
VPMINSDrr [NoVLX, HasAVX]
vpminsd {src2, src1, dst|dst, src1, src2}
VPMINUDrm [NoVLX, HasAVX]
vpminud {src2, src1, dst|dst, src1, src2}
VPMINUDrr [NoVLX, HasAVX]
vpminud {src2, src1, dst|dst, src1, src2}
VPMOVSXBDrm [NoVLX, HasAVX]
vpmovsxbd {src, dst|dst, src}
VPMOVSXBDrr [NoVLX, HasAVX]
vpmovsxbd {src, dst|dst, src}
VPMOVSXBQrm [NoVLX, HasAVX]
vpmovsxbq {src, dst|dst, src}
VPMOVSXBQrr [NoVLX, HasAVX]
vpmovsxbq {src, dst|dst, src}
VPMOVSXDQrm [NoVLX, HasAVX]
vpmovsxdq {src, dst|dst, src}
VPMOVSXDQrr [NoVLX, HasAVX]
vpmovsxdq {src, dst|dst, src}
VPMOVSXWDrm [NoVLX, HasAVX]
vpmovsxwd {src, dst|dst, src}
VPMOVSXWDrr [NoVLX, HasAVX]
vpmovsxwd {src, dst|dst, src}
VPMOVSXWQrm [NoVLX, HasAVX]
vpmovsxwq {src, dst|dst, src}
VPMOVSXWQrr [NoVLX, HasAVX]
vpmovsxwq {src, dst|dst, src}
VPMOVZXBDrm [NoVLX, HasAVX]
vpmovzxbd {src, dst|dst, src}
VPMOVZXBDrr [NoVLX, HasAVX]
vpmovzxbd {src, dst|dst, src}
VPMOVZXBQrm [NoVLX, HasAVX]
vpmovzxbq {src, dst|dst, src}
VPMOVZXBQrr [NoVLX, HasAVX]
vpmovzxbq {src, dst|dst, src}
VPMOVZXDQrm [NoVLX, HasAVX]
vpmovzxdq {src, dst|dst, src}
VPMOVZXDQrr [NoVLX, HasAVX]
vpmovzxdq {src, dst|dst, src}
VPMOVZXWDrm [NoVLX, HasAVX]
vpmovzxwd {src, dst|dst, src}
VPMOVZXWDrr [NoVLX, HasAVX]
vpmovzxwd {src, dst|dst, src}
VPMOVZXWQrm [NoVLX, HasAVX]
vpmovzxwq {src, dst|dst, src}
VPMOVZXWQrr [NoVLX, HasAVX]
vpmovzxwq {src, dst|dst, src}
VPMULDQrm [NoVLX, HasAVX]
vpmuldq {src2, src1, dst|dst, src1, src2}
VPMULDQrr [NoVLX, HasAVX]
vpmuldq {src2, src1, dst|dst, src1, src2}
VPMULLDrm [NoVLX, HasAVX]
vpmulld {src2, src1, dst|dst, src1, src2}
VPMULLDrr [NoVLX, HasAVX]
vpmulld {src2, src1, dst|dst, src1, src2}
VPMULUDQrm [NoVLX, HasAVX]
vpmuludq {src2, src1, dst|dst, src1, src2}
VPMULUDQrr [NoVLX, HasAVX]
vpmuludq {src2, src1, dst|dst, src1, src2}
VPORrm [NoVLX, HasAVX]
vpor {src2, src1, dst|dst, src1, src2}
VPORrr [NoVLX, HasAVX]
vpor {src2, src1, dst|dst, src1, src2}
VPSHUFDmi [NoVLX, HasAVX]
vpshufd {src2, src1, dst|dst, src1, src2}
VPSHUFDri [NoVLX, HasAVX]
vpshufd {src2, src1, dst|dst, src1, src2}
VPSLLDri [NoVLX, HasAVX]
vpslld {src2, src1, dst|dst, src1, src2}
VPSLLDrm [NoVLX, HasAVX]
vpslld {src2, src1, dst|dst, src1, src2}
VPSLLDrr [NoVLX, HasAVX]
vpslld {src2, src1, dst|dst, src1, src2}
VPSLLQri [NoVLX, HasAVX]
vpsllq {src2, src1, dst|dst, src1, src2}
VPSLLQrm [NoVLX, HasAVX]
vpsllq {src2, src1, dst|dst, src1, src2}
VPSLLQrr [NoVLX, HasAVX]
vpsllq {src2, src1, dst|dst, src1, src2}
VPSRADri [NoVLX, HasAVX]
vpsrad {src2, src1, dst|dst, src1, src2}
VPSRADrm [NoVLX, HasAVX]
vpsrad {src2, src1, dst|dst, src1, src2}
VPSRADrr [NoVLX, HasAVX]
vpsrad {src2, src1, dst|dst, src1, src2}
VPSRLDri [NoVLX, HasAVX]
vpsrld {src2, src1, dst|dst, src1, src2}
VPSRLDrm [NoVLX, HasAVX]
vpsrld {src2, src1, dst|dst, src1, src2}
VPSRLDrr [NoVLX, HasAVX]
vpsrld {src2, src1, dst|dst, src1, src2}
VPSRLQri [NoVLX, HasAVX]
vpsrlq {src2, src1, dst|dst, src1, src2}
VPSRLQrm [NoVLX, HasAVX]
vpsrlq {src2, src1, dst|dst, src1, src2}
VPSRLQrr [NoVLX, HasAVX]
vpsrlq {src2, src1, dst|dst, src1, src2}
VPSUBDrm [NoVLX, HasAVX]
vpsubd {src2, src1, dst|dst, src1, src2}
VPSUBDrr [NoVLX, HasAVX]
vpsubd {src2, src1, dst|dst, src1, src2}
VPSUBQrm [NoVLX, HasAVX]
vpsubq {src2, src1, dst|dst, src1, src2}
VPSUBQrr [NoVLX, HasAVX]
vpsubq {src2, src1, dst|dst, src1, src2}
VPUNPCKHDQrm [NoVLX, HasAVX]
vpunpckhdq {src2, src1, dst|dst, src1, src2}
VPUNPCKHDQrr [NoVLX, HasAVX]
vpunpckhdq {src2, src1, dst|dst, src1, src2}
VPUNPCKHQDQrm [NoVLX, HasAVX]
vpunpckhqdq {src2, src1, dst|dst, src1, src2}
VPUNPCKHQDQrr [NoVLX, HasAVX]
vpunpckhqdq {src2, src1, dst|dst, src1, src2}
VPUNPCKLDQrm [NoVLX, HasAVX]
vpunpckldq {src2, src1, dst|dst, src1, src2}
VPUNPCKLDQrr [NoVLX, HasAVX]
vpunpckldq {src2, src1, dst|dst, src1, src2}
VPUNPCKLQDQrm [NoVLX, HasAVX]
vpunpcklqdq {src2, src1, dst|dst, src1, src2}
VPUNPCKLQDQrr [NoVLX, HasAVX]
vpunpcklqdq {src2, src1, dst|dst, src1, src2}
VPXORrm [NoVLX, HasAVX]
vpxor {src2, src1, dst|dst, src1, src2}
VPXORrr [NoVLX, HasAVX]
vpxor {src2, src1, dst|dst, src1, src2}
VROUNDPDYmi [NoVLX, HasAVX]
vroundpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VROUNDPDYri [NoVLX, HasAVX]
vroundpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VROUNDPDmi [NoVLX, HasAVX]
vroundpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VROUNDPDri [NoVLX, HasAVX]
vroundpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VROUNDPSYmi [NoVLX, HasAVX]
vroundps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VROUNDPSYri [NoVLX, HasAVX]
vroundps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VROUNDPSmi [NoVLX, HasAVX]
vroundps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VROUNDPSri [NoVLX, HasAVX]
vroundps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSHUFPDYrmi [NoVLX, HasAVX]
vshufpd {src3, src2, src1, dst|dst, src1, src2, src3}
VSHUFPDYrri [NoVLX, HasAVX]
vshufpd {src3, src2, src1, dst|dst, src1, src2, src3}
VSHUFPDrmi [NoVLX, HasAVX]
vshufpd {src3, src2, src1, dst|dst, src1, src2, src3}
VSHUFPDrri [NoVLX, HasAVX]
vshufpd {src3, src2, src1, dst|dst, src1, src2, src3}
VSHUFPSYrmi [NoVLX, HasAVX]
vshufps {src3, src2, src1, dst|dst, src1, src2, src3}
VSHUFPSYrri [NoVLX, HasAVX]
vshufps {src3, src2, src1, dst|dst, src1, src2, src3}
VSHUFPSrmi [NoVLX, HasAVX]
vshufps {src3, src2, src1, dst|dst, src1, src2, src3}
VSHUFPSrri [NoVLX, HasAVX]
vshufps {src3, src2, src1, dst|dst, src1, src2, src3}
VSQRTPDYm [NoVLX, HasAVX]
vsqrtpd {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VSQRTPDYr [NoVLX, HasAVX]
vsqrtpd {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VSQRTPDm [NoVLX, HasAVX]
vsqrtpd {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VSQRTPDr [NoVLX, HasAVX]
vsqrtpd {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VSQRTPSYm [NoVLX, HasAVX]
vsqrtps {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VSQRTPSYr [NoVLX, HasAVX]
vsqrtps {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VSQRTPSm [NoVLX, HasAVX]
vsqrtps {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VSQRTPSr [NoVLX, HasAVX]
vsqrtps {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VSUBPDYrm [NoVLX, HasAVX]
vsubpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VSUBPDYrr [NoVLX, HasAVX]
vsubpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSUBPDrm [NoVLX, HasAVX]
vsubpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VSUBPDrr [NoVLX, HasAVX]
vsubpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSUBPSYrm [NoVLX, HasAVX]
vsubps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VSUBPSYrr [NoVLX, HasAVX]
vsubps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSUBPSrm [NoVLX, HasAVX]
vsubps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VSUBPSrr [NoVLX, HasAVX]
vsubps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VUNPCKHPDYrm [NoVLX, HasAVX]
vunpckhpd {src2, src1, dst|dst, src1, src2}
VUNPCKHPDYrr [NoVLX, HasAVX]
vunpckhpd {src2, src1, dst|dst, src1, src2}
VUNPCKHPDrm [NoVLX, HasAVX]
vunpckhpd {src2, src1, dst|dst, src1, src2}
VUNPCKHPDrr [NoVLX, HasAVX]
vunpckhpd {src2, src1, dst|dst, src1, src2}
VUNPCKHPSYrm [NoVLX, HasAVX]
vunpckhps {src2, src1, dst|dst, src1, src2}
VUNPCKHPSYrr [NoVLX, HasAVX]
vunpckhps {src2, src1, dst|dst, src1, src2}
VUNPCKHPSrm [NoVLX, HasAVX]
vunpckhps {src2, src1, dst|dst, src1, src2}
VUNPCKHPSrr [NoVLX, HasAVX]
vunpckhps {src2, src1, dst|dst, src1, src2}
VUNPCKLPDYrm [NoVLX, HasAVX]
vunpcklpd {src2, src1, dst|dst, src1, src2}
VUNPCKLPDYrr [NoVLX, HasAVX]
vunpcklpd {src2, src1, dst|dst, src1, src2}
VUNPCKLPDrm [NoVLX, HasAVX]
vunpcklpd {src2, src1, dst|dst, src1, src2}
VUNPCKLPDrr [NoVLX, HasAVX]
vunpcklpd {src2, src1, dst|dst, src1, src2}
VUNPCKLPSYrm [NoVLX, HasAVX]
vunpcklps {src2, src1, dst|dst, src1, src2}
VUNPCKLPSYrr [NoVLX, HasAVX]
vunpcklps {src2, src1, dst|dst, src1, src2}
VUNPCKLPSrm [NoVLX, HasAVX]
vunpcklps {src2, src1, dst|dst, src1, src2}
VUNPCKLPSrr [NoVLX, HasAVX]
vunpcklps {src2, src1, dst|dst, src1, src2}
VXORPDYrm [NoVLX, HasAVX]
vxorpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VXORPDYrr [NoVLX, HasAVX]
vxorpd {src2, src1, dst|dst, src1, src2}
VXORPDrm [NoVLX, HasAVX]
vxorpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VXORPDrr [NoVLX, HasAVX]
vxorpd {src2, src1, dst|dst, src1, src2}
VXORPSYrm [NoVLX, HasAVX]
vxorps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VXORPSYrr [NoVLX, HasAVX]
vxorps {src2, src1, dst|dst, src1, src2}
VXORPSrm [NoVLX, HasAVX]
vxorps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VXORPSrr [NoVLX, HasAVX]
vxorps {src2, src1, dst|dst, src1, src2}
VGF2P8AFFINEINVQBYrmi [NoVLX, HasAVX, HasGFNI]
vgf2p8affineinvqb {src3, src2, src1, dst|dst, src1, src2, src3}
VGF2P8AFFINEINVQBYrri [NoVLX, HasAVX, HasGFNI]
vgf2p8affineinvqb {src3, src2, src1, dst|dst, src1, src2, src3}
VGF2P8AFFINEINVQBrmi [NoVLX, HasAVX, HasGFNI]
vgf2p8affineinvqb {src3, src2, src1, dst|dst, src1, src2, src3}
VGF2P8AFFINEINVQBrri [NoVLX, HasAVX, HasGFNI]
vgf2p8affineinvqb {src3, src2, src1, dst|dst, src1, src2, src3}
VGF2P8AFFINEQBYrmi [NoVLX, HasAVX, HasGFNI]
vgf2p8affineqb {src3, src2, src1, dst|dst, src1, src2, src3}
VGF2P8AFFINEQBYrri [NoVLX, HasAVX, HasGFNI]
vgf2p8affineqb {src3, src2, src1, dst|dst, src1, src2, src3}
VGF2P8AFFINEQBrmi [NoVLX, HasAVX, HasGFNI]
vgf2p8affineqb {src3, src2, src1, dst|dst, src1, src2, src3}
VGF2P8AFFINEQBrri [NoVLX, HasAVX, HasGFNI]
vgf2p8affineqb {src3, src2, src1, dst|dst, src1, src2, src3}
VGF2P8MULBYrm [NoVLX, HasAVX, HasGFNI]
vgf2p8mulb {src2, src1, dst|dst, src1, src2}
VGF2P8MULBYrr [NoVLX, HasAVX, HasGFNI]
vgf2p8mulb {src2, src1, dst|dst, src1, src2}
VGF2P8MULBrm [NoVLX, HasAVX, HasGFNI]
vgf2p8mulb {src2, src1, dst|dst, src1, src2}
VGF2P8MULBrr [NoVLX, HasAVX, HasGFNI]
vgf2p8mulb {src2, src1, dst|dst, src1, src2}
VBROADCASTSDYrr [NoVLX, HasAVX2]
vbroadcastsd {src, dst|dst, src}
VBROADCASTSSYrr [NoVLX, HasAVX2]
vbroadcastss {src, dst|dst, src}
VBROADCASTSSrr [NoVLX, HasAVX2]
vbroadcastss {src, dst|dst, src}
VMOVNTDQAYrm [NoVLX, HasAVX2]
vmovntdqa {src, dst|dst, src}
VPABSDYrm [NoVLX, HasAVX2]
vpabsd {src, dst|dst, src}
VPABSDYrr [NoVLX, HasAVX2]
vpabsd {src, dst|dst, src}
VPADDDYrm [NoVLX, HasAVX2]
vpaddd {src2, src1, dst|dst, src1, src2}
VPADDDYrr [NoVLX, HasAVX2]
vpaddd {src2, src1, dst|dst, src1, src2}
VPADDQYrm [NoVLX, HasAVX2]
vpaddq {src2, src1, dst|dst, src1, src2}
VPADDQYrr [NoVLX, HasAVX2]
vpaddq {src2, src1, dst|dst, src1, src2}
VPANDNYrm [NoVLX, HasAVX2]
vpandn {src2, src1, dst|dst, src1, src2}
VPANDNYrr [NoVLX, HasAVX2]
vpandn {src2, src1, dst|dst, src1, src2}
VPANDYrm [NoVLX, HasAVX2]
vpand {src2, src1, dst|dst, src1, src2}
VPANDYrr [NoVLX, HasAVX2]
vpand {src2, src1, dst|dst, src1, src2}
VPBROADCASTDYrm [NoVLX, HasAVX2]
vpbroadcastd {src, dst|dst, src}
VPBROADCASTDYrr [NoVLX, HasAVX2]
vpbroadcastd {src, dst|dst, src}
VPBROADCASTDrm [NoVLX, HasAVX2]
vpbroadcastd {src, dst|dst, src}
VPBROADCASTDrr [NoVLX, HasAVX2]
vpbroadcastd {src, dst|dst, src}
VPBROADCASTQYrm [NoVLX, HasAVX2]
vpbroadcastq {src, dst|dst, src}
VPBROADCASTQYrr [NoVLX, HasAVX2]
vpbroadcastq {src, dst|dst, src}
VPBROADCASTQrm [NoVLX, HasAVX2]
vpbroadcastq {src, dst|dst, src}
VPBROADCASTQrr [NoVLX, HasAVX2]
vpbroadcastq {src, dst|dst, src}
VPERMDYrm [NoVLX, HasAVX2]
vpermd {src2, src1, dst|dst, src1, src2}
VPERMDYrr [NoVLX, HasAVX2]
vpermd {src2, src1, dst|dst, src1, src2}
VPERMPDYmi [NoVLX, HasAVX2]
vpermpd {src2, src1, dst|dst, src1, src2}
VPERMPDYri [NoVLX, HasAVX2]
vpermpd {src2, src1, dst|dst, src1, src2}
VPERMPSYrm [NoVLX, HasAVX2]
vpermps {src2, src1, dst|dst, src1, src2}
VPERMPSYrr [NoVLX, HasAVX2]
vpermps {src2, src1, dst|dst, src1, src2}
VPERMQYmi [NoVLX, HasAVX2]
vpermq {src2, src1, dst|dst, src1, src2}
VPERMQYri [NoVLX, HasAVX2]
vpermq {src2, src1, dst|dst, src1, src2}
VPMAXSDYrm [NoVLX, HasAVX2]
vpmaxsd {src2, src1, dst|dst, src1, src2}
VPMAXSDYrr [NoVLX, HasAVX2]
vpmaxsd {src2, src1, dst|dst, src1, src2}
VPMAXUDYrm [NoVLX, HasAVX2]
vpmaxud {src2, src1, dst|dst, src1, src2}
VPMAXUDYrr [NoVLX, HasAVX2]
vpmaxud {src2, src1, dst|dst, src1, src2}
VPMINSDYrm [NoVLX, HasAVX2]
vpminsd {src2, src1, dst|dst, src1, src2}
VPMINSDYrr [NoVLX, HasAVX2]
vpminsd {src2, src1, dst|dst, src1, src2}
VPMINUDYrm [NoVLX, HasAVX2]
vpminud {src2, src1, dst|dst, src1, src2}
VPMINUDYrr [NoVLX, HasAVX2]
vpminud {src2, src1, dst|dst, src1, src2}
VPMOVSXBDYrm [NoVLX, HasAVX2]
vpmovsxbd {src, dst|dst, src}
VPMOVSXBDYrr [NoVLX, HasAVX2]
vpmovsxbd {src, dst|dst, src}
VPMOVSXBQYrm [NoVLX, HasAVX2]
vpmovsxbq {src, dst|dst, src}
VPMOVSXBQYrr [NoVLX, HasAVX2]
vpmovsxbq {src, dst|dst, src}
VPMOVSXDQYrm [NoVLX, HasAVX2]
vpmovsxdq {src, dst|dst, src}
VPMOVSXDQYrr [NoVLX, HasAVX2]
vpmovsxdq {src, dst|dst, src}
VPMOVSXWDYrm [NoVLX, HasAVX2]
vpmovsxwd {src, dst|dst, src}
VPMOVSXWDYrr [NoVLX, HasAVX2]
vpmovsxwd {src, dst|dst, src}
VPMOVSXWQYrm [NoVLX, HasAVX2]
vpmovsxwq {src, dst|dst, src}
VPMOVSXWQYrr [NoVLX, HasAVX2]
vpmovsxwq {src, dst|dst, src}
VPMOVZXBDYrm [NoVLX, HasAVX2]
vpmovzxbd {src, dst|dst, src}
VPMOVZXBDYrr [NoVLX, HasAVX2]
vpmovzxbd {src, dst|dst, src}
VPMOVZXBQYrm [NoVLX, HasAVX2]
vpmovzxbq {src, dst|dst, src}
VPMOVZXBQYrr [NoVLX, HasAVX2]
vpmovzxbq {src, dst|dst, src}
VPMOVZXDQYrm [NoVLX, HasAVX2]
vpmovzxdq {src, dst|dst, src}
VPMOVZXDQYrr [NoVLX, HasAVX2]
vpmovzxdq {src, dst|dst, src}
VPMOVZXWDYrm [NoVLX, HasAVX2]
vpmovzxwd {src, dst|dst, src}
VPMOVZXWDYrr [NoVLX, HasAVX2]
vpmovzxwd {src, dst|dst, src}
VPMOVZXWQYrm [NoVLX, HasAVX2]
vpmovzxwq {src, dst|dst, src}
VPMOVZXWQYrr [NoVLX, HasAVX2]
vpmovzxwq {src, dst|dst, src}
VPMULDQYrm [NoVLX, HasAVX2]
vpmuldq {src2, src1, dst|dst, src1, src2}
VPMULDQYrr [NoVLX, HasAVX2]
vpmuldq {src2, src1, dst|dst, src1, src2}
VPMULLDYrm [NoVLX, HasAVX2]
vpmulld {src2, src1, dst|dst, src1, src2}
VPMULLDYrr [NoVLX, HasAVX2]
vpmulld {src2, src1, dst|dst, src1, src2}
VPMULUDQYrm [NoVLX, HasAVX2]
vpmuludq {src2, src1, dst|dst, src1, src2}
VPMULUDQYrr [NoVLX, HasAVX2]
vpmuludq {src2, src1, dst|dst, src1, src2}
VPORYrm [NoVLX, HasAVX2]
vpor {src2, src1, dst|dst, src1, src2}
VPORYrr [NoVLX, HasAVX2]
vpor {src2, src1, dst|dst, src1, src2}
VPSHUFDYmi [NoVLX, HasAVX2]
vpshufd {src2, src1, dst|dst, src1, src2}
VPSHUFDYri [NoVLX, HasAVX2]
vpshufd {src2, src1, dst|dst, src1, src2}
VPSLLDYri [NoVLX, HasAVX2]
vpslld {src2, src1, dst|dst, src1, src2}
VPSLLDYrm [NoVLX, HasAVX2]
vpslld {src2, src1, dst|dst, src1, src2}
VPSLLDYrr [NoVLX, HasAVX2]
vpslld {src2, src1, dst|dst, src1, src2}
VPSLLQYri [NoVLX, HasAVX2]
vpsllq {src2, src1, dst|dst, src1, src2}
VPSLLQYrm [NoVLX, HasAVX2]
vpsllq {src2, src1, dst|dst, src1, src2}
VPSLLQYrr [NoVLX, HasAVX2]
vpsllq {src2, src1, dst|dst, src1, src2}
VPSLLVDYrm [NoVLX, HasAVX2]
vpsllvd {src2, src1, dst|dst, src1, src2}
VPSLLVDYrr [NoVLX, HasAVX2]
vpsllvd {src2, src1, dst|dst, src1, src2}
VPSLLVDrm [NoVLX, HasAVX2]
vpsllvd {src2, src1, dst|dst, src1, src2}
VPSLLVDrr [NoVLX, HasAVX2]
vpsllvd {src2, src1, dst|dst, src1, src2}
VPSLLVQYrm [NoVLX, HasAVX2]
vpsllvq {src2, src1, dst|dst, src1, src2}
VPSLLVQYrr [NoVLX, HasAVX2]
vpsllvq {src2, src1, dst|dst, src1, src2}
VPSLLVQrm [NoVLX, HasAVX2]
vpsllvq {src2, src1, dst|dst, src1, src2}
VPSLLVQrr [NoVLX, HasAVX2]
vpsllvq {src2, src1, dst|dst, src1, src2}
VPSRADYri [NoVLX, HasAVX2]
vpsrad {src2, src1, dst|dst, src1, src2}
VPSRADYrm [NoVLX, HasAVX2]
vpsrad {src2, src1, dst|dst, src1, src2}
VPSRADYrr [NoVLX, HasAVX2]
vpsrad {src2, src1, dst|dst, src1, src2}
VPSRAVDYrm [NoVLX, HasAVX2]
vpsravd {src2, src1, dst|dst, src1, src2}
VPSRAVDYrr [NoVLX, HasAVX2]
vpsravd {src2, src1, dst|dst, src1, src2}
VPSRAVDrm [NoVLX, HasAVX2]
vpsravd {src2, src1, dst|dst, src1, src2}
VPSRAVDrr [NoVLX, HasAVX2]
vpsravd {src2, src1, dst|dst, src1, src2}
VPSRLDYri [NoVLX, HasAVX2]
vpsrld {src2, src1, dst|dst, src1, src2}
VPSRLDYrm [NoVLX, HasAVX2]
vpsrld {src2, src1, dst|dst, src1, src2}
VPSRLDYrr [NoVLX, HasAVX2]
vpsrld {src2, src1, dst|dst, src1, src2}
VPSRLQYri [NoVLX, HasAVX2]
vpsrlq {src2, src1, dst|dst, src1, src2}
VPSRLQYrm [NoVLX, HasAVX2]
vpsrlq {src2, src1, dst|dst, src1, src2}
VPSRLQYrr [NoVLX, HasAVX2]
vpsrlq {src2, src1, dst|dst, src1, src2}
VPSRLVDYrm [NoVLX, HasAVX2]
vpsrlvd {src2, src1, dst|dst, src1, src2}
VPSRLVDYrr [NoVLX, HasAVX2]
vpsrlvd {src2, src1, dst|dst, src1, src2}
VPSRLVDrm [NoVLX, HasAVX2]
vpsrlvd {src2, src1, dst|dst, src1, src2}
VPSRLVDrr [NoVLX, HasAVX2]
vpsrlvd {src2, src1, dst|dst, src1, src2}
VPSRLVQYrm [NoVLX, HasAVX2]
vpsrlvq {src2, src1, dst|dst, src1, src2}
VPSRLVQYrr [NoVLX, HasAVX2]
vpsrlvq {src2, src1, dst|dst, src1, src2}
VPSRLVQrm [NoVLX, HasAVX2]
vpsrlvq {src2, src1, dst|dst, src1, src2}
VPSRLVQrr [NoVLX, HasAVX2]
vpsrlvq {src2, src1, dst|dst, src1, src2}
VPSUBDYrm [NoVLX, HasAVX2]
vpsubd {src2, src1, dst|dst, src1, src2}
VPSUBDYrr [NoVLX, HasAVX2]
vpsubd {src2, src1, dst|dst, src1, src2}
VPSUBQYrm [NoVLX, HasAVX2]
vpsubq {src2, src1, dst|dst, src1, src2}
VPSUBQYrr [NoVLX, HasAVX2]
vpsubq {src2, src1, dst|dst, src1, src2}
VPUNPCKHDQYrm [NoVLX, HasAVX2]
vpunpckhdq {src2, src1, dst|dst, src1, src2}
VPUNPCKHDQYrr [NoVLX, HasAVX2]
vpunpckhdq {src2, src1, dst|dst, src1, src2}
VPUNPCKHQDQYrm [NoVLX, HasAVX2]
vpunpckhqdq {src2, src1, dst|dst, src1, src2}
VPUNPCKHQDQYrr [NoVLX, HasAVX2]
vpunpckhqdq {src2, src1, dst|dst, src1, src2}
VPUNPCKLDQYrm [NoVLX, HasAVX2]
vpunpckldq {src2, src1, dst|dst, src1, src2}
VPUNPCKLDQYrr [NoVLX, HasAVX2]
vpunpckldq {src2, src1, dst|dst, src1, src2}
VPUNPCKLQDQYrm [NoVLX, HasAVX2]
vpunpcklqdq {src2, src1, dst|dst, src1, src2}
VPUNPCKLQDQYrr [NoVLX, HasAVX2]
vpunpcklqdq {src2, src1, dst|dst, src1, src2}
VPXORYrm [NoVLX, HasAVX2]
vpxor {src2, src1, dst|dst, src1, src2}
VPXORYrr [NoVLX, HasAVX2]
vpxor {src2, src1, dst|dst, src1, src2}
VFMADD132PDYm [NoVLX, HasFMA, NoFMA4]
vfmadd132pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PDYr [NoVLX, HasFMA, NoFMA4]
vfmadd132pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PDm [NoVLX, HasFMA, NoFMA4]
vfmadd132pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PDr [NoVLX, HasFMA, NoFMA4]
vfmadd132pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PSYm [NoVLX, HasFMA, NoFMA4]
vfmadd132ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PSYr [NoVLX, HasFMA, NoFMA4]
vfmadd132ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PSm [NoVLX, HasFMA, NoFMA4]
vfmadd132ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132PSr [NoVLX, HasFMA, NoFMA4]
vfmadd132ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PDYm [NoVLX, HasFMA, NoFMA4]
vfmadd213pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PDYr [NoVLX, HasFMA, NoFMA4]
vfmadd213pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PDm [NoVLX, HasFMA, NoFMA4]
vfmadd213pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PDr [NoVLX, HasFMA, NoFMA4]
vfmadd213pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PSYm [NoVLX, HasFMA, NoFMA4]
vfmadd213ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PSYr [NoVLX, HasFMA, NoFMA4]
vfmadd213ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PSm [NoVLX, HasFMA, NoFMA4]
vfmadd213ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213PSr [NoVLX, HasFMA, NoFMA4]
vfmadd213ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PDYm [NoVLX, HasFMA, NoFMA4]
vfmadd231pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PDYr [NoVLX, HasFMA, NoFMA4]
vfmadd231pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PDm [NoVLX, HasFMA, NoFMA4]
vfmadd231pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PDr [NoVLX, HasFMA, NoFMA4]
vfmadd231pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PSYm [NoVLX, HasFMA, NoFMA4]
vfmadd231ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PSYr [NoVLX, HasFMA, NoFMA4]
vfmadd231ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PSm [NoVLX, HasFMA, NoFMA4]
vfmadd231ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231PSr [NoVLX, HasFMA, NoFMA4]
vfmadd231ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PDYm [NoVLX, HasFMA, NoFMA4]
vfmaddsub132pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PDYr [NoVLX, HasFMA, NoFMA4]
vfmaddsub132pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PDm [NoVLX, HasFMA, NoFMA4]
vfmaddsub132pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PDr [NoVLX, HasFMA, NoFMA4]
vfmaddsub132pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PSYm [NoVLX, HasFMA, NoFMA4]
vfmaddsub132ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PSYr [NoVLX, HasFMA, NoFMA4]
vfmaddsub132ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PSm [NoVLX, HasFMA, NoFMA4]
vfmaddsub132ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB132PSr [NoVLX, HasFMA, NoFMA4]
vfmaddsub132ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PDYm [NoVLX, HasFMA, NoFMA4]
vfmaddsub213pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PDYr [NoVLX, HasFMA, NoFMA4]
vfmaddsub213pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PDm [NoVLX, HasFMA, NoFMA4]
vfmaddsub213pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PDr [NoVLX, HasFMA, NoFMA4]
vfmaddsub213pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PSYm [NoVLX, HasFMA, NoFMA4]
vfmaddsub213ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PSYr [NoVLX, HasFMA, NoFMA4]
vfmaddsub213ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PSm [NoVLX, HasFMA, NoFMA4]
vfmaddsub213ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB213PSr [NoVLX, HasFMA, NoFMA4]
vfmaddsub213ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PDYm [NoVLX, HasFMA, NoFMA4]
vfmaddsub231pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PDYr [NoVLX, HasFMA, NoFMA4]
vfmaddsub231pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PDm [NoVLX, HasFMA, NoFMA4]
vfmaddsub231pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PDr [NoVLX, HasFMA, NoFMA4]
vfmaddsub231pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PSYm [NoVLX, HasFMA, NoFMA4]
vfmaddsub231ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PSYr [NoVLX, HasFMA, NoFMA4]
vfmaddsub231ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PSm [NoVLX, HasFMA, NoFMA4]
vfmaddsub231ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSUB231PSr [NoVLX, HasFMA, NoFMA4]
vfmaddsub231ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PDYm [NoVLX, HasFMA, NoFMA4]
vfmsub132pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PDYr [NoVLX, HasFMA, NoFMA4]
vfmsub132pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PDm [NoVLX, HasFMA, NoFMA4]
vfmsub132pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PDr [NoVLX, HasFMA, NoFMA4]
vfmsub132pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PSYm [NoVLX, HasFMA, NoFMA4]
vfmsub132ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PSYr [NoVLX, HasFMA, NoFMA4]
vfmsub132ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PSm [NoVLX, HasFMA, NoFMA4]
vfmsub132ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132PSr [NoVLX, HasFMA, NoFMA4]
vfmsub132ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PDYm [NoVLX, HasFMA, NoFMA4]
vfmsub213pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PDYr [NoVLX, HasFMA, NoFMA4]
vfmsub213pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PDm [NoVLX, HasFMA, NoFMA4]
vfmsub213pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PDr [NoVLX, HasFMA, NoFMA4]
vfmsub213pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PSYm [NoVLX, HasFMA, NoFMA4]
vfmsub213ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PSYr [NoVLX, HasFMA, NoFMA4]
vfmsub213ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PSm [NoVLX, HasFMA, NoFMA4]
vfmsub213ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213PSr [NoVLX, HasFMA, NoFMA4]
vfmsub213ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PDYm [NoVLX, HasFMA, NoFMA4]
vfmsub231pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PDYr [NoVLX, HasFMA, NoFMA4]
vfmsub231pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PDm [NoVLX, HasFMA, NoFMA4]
vfmsub231pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PDr [NoVLX, HasFMA, NoFMA4]
vfmsub231pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PSYm [NoVLX, HasFMA, NoFMA4]
vfmsub231ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PSYr [NoVLX, HasFMA, NoFMA4]
vfmsub231ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PSm [NoVLX, HasFMA, NoFMA4]
vfmsub231ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231PSr [NoVLX, HasFMA, NoFMA4]
vfmsub231ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PDYm [NoVLX, HasFMA, NoFMA4]
vfmsubadd132pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PDYr [NoVLX, HasFMA, NoFMA4]
vfmsubadd132pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PDm [NoVLX, HasFMA, NoFMA4]
vfmsubadd132pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PDr [NoVLX, HasFMA, NoFMA4]
vfmsubadd132pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PSYm [NoVLX, HasFMA, NoFMA4]
vfmsubadd132ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PSYr [NoVLX, HasFMA, NoFMA4]
vfmsubadd132ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PSm [NoVLX, HasFMA, NoFMA4]
vfmsubadd132ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD132PSr [NoVLX, HasFMA, NoFMA4]
vfmsubadd132ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PDYm [NoVLX, HasFMA, NoFMA4]
vfmsubadd213pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PDYr [NoVLX, HasFMA, NoFMA4]
vfmsubadd213pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PDm [NoVLX, HasFMA, NoFMA4]
vfmsubadd213pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PDr [NoVLX, HasFMA, NoFMA4]
vfmsubadd213pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PSYm [NoVLX, HasFMA, NoFMA4]
vfmsubadd213ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PSYr [NoVLX, HasFMA, NoFMA4]
vfmsubadd213ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PSm [NoVLX, HasFMA, NoFMA4]
vfmsubadd213ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD213PSr [NoVLX, HasFMA, NoFMA4]
vfmsubadd213ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PDYm [NoVLX, HasFMA, NoFMA4]
vfmsubadd231pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PDYr [NoVLX, HasFMA, NoFMA4]
vfmsubadd231pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PDm [NoVLX, HasFMA, NoFMA4]
vfmsubadd231pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PDr [NoVLX, HasFMA, NoFMA4]
vfmsubadd231pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PSYm [NoVLX, HasFMA, NoFMA4]
vfmsubadd231ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PSYr [NoVLX, HasFMA, NoFMA4]
vfmsubadd231ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PSm [NoVLX, HasFMA, NoFMA4]
vfmsubadd231ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUBADD231PSr [NoVLX, HasFMA, NoFMA4]
vfmsubadd231ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PDYm [NoVLX, HasFMA, NoFMA4]
vfnmadd132pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PDYr [NoVLX, HasFMA, NoFMA4]
vfnmadd132pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PDm [NoVLX, HasFMA, NoFMA4]
vfnmadd132pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PDr [NoVLX, HasFMA, NoFMA4]
vfnmadd132pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PSYm [NoVLX, HasFMA, NoFMA4]
vfnmadd132ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PSYr [NoVLX, HasFMA, NoFMA4]
vfnmadd132ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PSm [NoVLX, HasFMA, NoFMA4]
vfnmadd132ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132PSr [NoVLX, HasFMA, NoFMA4]
vfnmadd132ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PDYm [NoVLX, HasFMA, NoFMA4]
vfnmadd213pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PDYr [NoVLX, HasFMA, NoFMA4]
vfnmadd213pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PDm [NoVLX, HasFMA, NoFMA4]
vfnmadd213pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PDr [NoVLX, HasFMA, NoFMA4]
vfnmadd213pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PSYm [NoVLX, HasFMA, NoFMA4]
vfnmadd213ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PSYr [NoVLX, HasFMA, NoFMA4]
vfnmadd213ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PSm [NoVLX, HasFMA, NoFMA4]
vfnmadd213ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213PSr [NoVLX, HasFMA, NoFMA4]
vfnmadd213ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PDYm [NoVLX, HasFMA, NoFMA4]
vfnmadd231pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PDYr [NoVLX, HasFMA, NoFMA4]
vfnmadd231pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PDm [NoVLX, HasFMA, NoFMA4]
vfnmadd231pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PDr [NoVLX, HasFMA, NoFMA4]
vfnmadd231pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PSYm [NoVLX, HasFMA, NoFMA4]
vfnmadd231ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PSYr [NoVLX, HasFMA, NoFMA4]
vfnmadd231ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PSm [NoVLX, HasFMA, NoFMA4]
vfnmadd231ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231PSr [NoVLX, HasFMA, NoFMA4]
vfnmadd231ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PDYm [NoVLX, HasFMA, NoFMA4]
vfnmsub132pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PDYr [NoVLX, HasFMA, NoFMA4]
vfnmsub132pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PDm [NoVLX, HasFMA, NoFMA4]
vfnmsub132pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PDr [NoVLX, HasFMA, NoFMA4]
vfnmsub132pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PSYm [NoVLX, HasFMA, NoFMA4]
vfnmsub132ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PSYr [NoVLX, HasFMA, NoFMA4]
vfnmsub132ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PSm [NoVLX, HasFMA, NoFMA4]
vfnmsub132ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132PSr [NoVLX, HasFMA, NoFMA4]
vfnmsub132ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PDYm [NoVLX, HasFMA, NoFMA4]
vfnmsub213pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PDYr [NoVLX, HasFMA, NoFMA4]
vfnmsub213pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PDm [NoVLX, HasFMA, NoFMA4]
vfnmsub213pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PDr [NoVLX, HasFMA, NoFMA4]
vfnmsub213pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PSYm [NoVLX, HasFMA, NoFMA4]
vfnmsub213ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PSYr [NoVLX, HasFMA, NoFMA4]
vfnmsub213ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PSm [NoVLX, HasFMA, NoFMA4]
vfnmsub213ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213PSr [NoVLX, HasFMA, NoFMA4]
vfnmsub213ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PDYm [NoVLX, HasFMA, NoFMA4]
vfnmsub231pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PDYr [NoVLX, HasFMA, NoFMA4]
vfnmsub231pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PDm [NoVLX, HasFMA, NoFMA4]
vfnmsub231pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PDr [NoVLX, HasFMA, NoFMA4]
vfnmsub231pd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PSYm [NoVLX, HasFMA, NoFMA4]
vfnmsub231ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PSYr [NoVLX, HasFMA, NoFMA4]
vfnmsub231ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PSm [NoVLX, HasFMA, NoFMA4]
vfnmsub231ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231PSr [NoVLX, HasFMA, NoFMA4]
vfnmsub231ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDPD4Ymr [NoVLX, HasFMA4]
vfmaddpd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFMADDPD4Yrm [NoVLX, HasFMA4]
vfmaddpd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFMADDPD4Yrr [NoVLX, HasFMA4]
vfmaddpd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFMADDPD4mr [NoVLX, HasFMA4]
vfmaddpd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFMADDPD4rm [NoVLX, HasFMA4]
vfmaddpd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFMADDPD4rr [NoVLX, HasFMA4]
vfmaddpd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFMADDPS4Ymr [NoVLX, HasFMA4]
vfmaddps {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFMADDPS4Yrm [NoVLX, HasFMA4]
vfmaddps {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFMADDPS4Yrr [NoVLX, HasFMA4]
vfmaddps {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFMADDPS4mr [NoVLX, HasFMA4]
vfmaddps {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFMADDPS4rm [NoVLX, HasFMA4]
vfmaddps {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFMADDPS4rr [NoVLX, HasFMA4]
vfmaddps {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFMADDSUBPD4Ymr [NoVLX, HasFMA4]
vfmaddsubpd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFMADDSUBPD4Yrm [NoVLX, HasFMA4]
vfmaddsubpd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFMADDSUBPD4Yrr [NoVLX, HasFMA4]
vfmaddsubpd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFMADDSUBPD4mr [NoVLX, HasFMA4]
vfmaddsubpd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFMADDSUBPD4rm [NoVLX, HasFMA4]
vfmaddsubpd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFMADDSUBPD4rr [NoVLX, HasFMA4]
vfmaddsubpd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFMADDSUBPS4Ymr [NoVLX, HasFMA4]
vfmaddsubps {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFMADDSUBPS4Yrm [NoVLX, HasFMA4]
vfmaddsubps {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFMADDSUBPS4Yrr [NoVLX, HasFMA4]
vfmaddsubps {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFMADDSUBPS4mr [NoVLX, HasFMA4]
vfmaddsubps {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFMADDSUBPS4rm [NoVLX, HasFMA4]
vfmaddsubps {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFMADDSUBPS4rr [NoVLX, HasFMA4]
vfmaddsubps {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFMSUBADDPD4Ymr [NoVLX, HasFMA4]
vfmsubaddpd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFMSUBADDPD4Yrm [NoVLX, HasFMA4]
vfmsubaddpd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFMSUBADDPD4Yrr [NoVLX, HasFMA4]
vfmsubaddpd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFMSUBADDPD4mr [NoVLX, HasFMA4]
vfmsubaddpd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFMSUBADDPD4rm [NoVLX, HasFMA4]
vfmsubaddpd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFMSUBADDPD4rr [NoVLX, HasFMA4]
vfmsubaddpd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFMSUBADDPS4Ymr [NoVLX, HasFMA4]
vfmsubaddps {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFMSUBADDPS4Yrm [NoVLX, HasFMA4]
vfmsubaddps {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFMSUBADDPS4Yrr [NoVLX, HasFMA4]
vfmsubaddps {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFMSUBADDPS4mr [NoVLX, HasFMA4]
vfmsubaddps {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFMSUBADDPS4rm [NoVLX, HasFMA4]
vfmsubaddps {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFMSUBADDPS4rr [NoVLX, HasFMA4]
vfmsubaddps {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFMSUBPD4Ymr [NoVLX, HasFMA4]
vfmsubpd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFMSUBPD4Yrm [NoVLX, HasFMA4]
vfmsubpd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFMSUBPD4Yrr [NoVLX, HasFMA4]
vfmsubpd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFMSUBPD4mr [NoVLX, HasFMA4]
vfmsubpd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFMSUBPD4rm [NoVLX, HasFMA4]
vfmsubpd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFMSUBPD4rr [NoVLX, HasFMA4]
vfmsubpd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFMSUBPS4Ymr [NoVLX, HasFMA4]
vfmsubps {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFMSUBPS4Yrm [NoVLX, HasFMA4]
vfmsubps {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFMSUBPS4Yrr [NoVLX, HasFMA4]
vfmsubps {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFMSUBPS4mr [NoVLX, HasFMA4]
vfmsubps {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFMSUBPS4rm [NoVLX, HasFMA4]
vfmsubps {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFMSUBPS4rr [NoVLX, HasFMA4]
vfmsubps {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFNMADDPD4Ymr [NoVLX, HasFMA4]
vfnmaddpd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFNMADDPD4Yrm [NoVLX, HasFMA4]
vfnmaddpd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFNMADDPD4Yrr [NoVLX, HasFMA4]
vfnmaddpd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFNMADDPD4mr [NoVLX, HasFMA4]
vfnmaddpd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFNMADDPD4rm [NoVLX, HasFMA4]
vfnmaddpd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFNMADDPD4rr [NoVLX, HasFMA4]
vfnmaddpd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFNMADDPS4Ymr [NoVLX, HasFMA4]
vfnmaddps {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFNMADDPS4Yrm [NoVLX, HasFMA4]
vfnmaddps {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFNMADDPS4Yrr [NoVLX, HasFMA4]
vfnmaddps {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFNMADDPS4mr [NoVLX, HasFMA4]
vfnmaddps {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFNMADDPS4rm [NoVLX, HasFMA4]
vfnmaddps {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFNMADDPS4rr [NoVLX, HasFMA4]
vfnmaddps {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFNMSUBPD4Ymr [NoVLX, HasFMA4]
vfnmsubpd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFNMSUBPD4Yrm [NoVLX, HasFMA4]
vfnmsubpd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFNMSUBPD4Yrr [NoVLX, HasFMA4]
vfnmsubpd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFNMSUBPD4mr [NoVLX, HasFMA4]
vfnmsubpd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFNMSUBPD4rm [NoVLX, HasFMA4]
vfnmsubpd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFNMSUBPD4rr [NoVLX, HasFMA4]
vfnmsubpd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFNMSUBPS4Ymr [NoVLX, HasFMA4]
vfnmsubps {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFNMSUBPS4Yrm [NoVLX, HasFMA4]
vfnmsubps {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFNMSUBPS4Yrr [NoVLX, HasFMA4]
vfnmsubps {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFNMSUBPS4mr [NoVLX, HasFMA4]
vfnmsubps {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFNMSUBPS4rm [NoVLX, HasFMA4]
vfnmsubps {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFNMSUBPS4rr [NoVLX, HasFMA4]
vfnmsubps {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VAESDECLASTYrm [NoVLX, HasVAES]
vaesdeclast {src2, src1, dst|dst, src1, src2}
VAESDECLASTYrr [NoVLX, HasVAES]
vaesdeclast {src2, src1, dst|dst, src1, src2}
VAESDECYrm [NoVLX, HasVAES]
vaesdec {src2, src1, dst|dst, src1, src2}
VAESDECYrr [NoVLX, HasVAES]
vaesdec {src2, src1, dst|dst, src1, src2}
VAESENCLASTYrm [NoVLX, HasVAES]
vaesenclast {src2, src1, dst|dst, src1, src2}
VAESENCLASTYrr [NoVLX, HasVAES]
vaesenclast {src2, src1, dst|dst, src1, src2}
VAESENCYrm [NoVLX, HasVAES]
vaesenc {src2, src1, dst|dst, src1, src2}
VAESENCYrr [NoVLX, HasVAES]
vaesenc {src2, src1, dst|dst, src1, src2}
VCVTPH2PSYrm [NoVLX, HasF16C]
vcvtph2ps {src, dst|dst, src}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VCVTPH2PSYrr [NoVLX, HasF16C]
vcvtph2ps {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPH2PSrm [NoVLX, HasF16C]
vcvtph2ps {src, dst|dst, src}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VCVTPH2PSrr [NoVLX, HasF16C]
vcvtph2ps {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2PHYmr [NoVLX, HasF16C]
vcvtps2ph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException, mayStore |
VCVTPS2PHYrr [NoVLX, HasF16C]
vcvtps2ph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VCVTPS2PHmr [NoVLX, HasF16C]
vcvtps2ph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException, mayStore |
VCVTPS2PHrr [NoVLX, HasF16C]
vcvtps2ph {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VPCLMULQDQYrmi [NoVLX, HasVPCLMULQDQ]
vpclmulqdq {src3, src2, src1, dst|dst, src1, src2, src3}
VPCLMULQDQYrri [NoVLX, HasVPCLMULQDQ]
vpclmulqdq {src3, src2, src1, dst|dst, src1, src2, src3}
VADDSUBPDYrm [HasAVX]
vaddsubpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VADDSUBPDYrr [HasAVX]
vaddsubpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VADDSUBPDrm [HasAVX]
vaddsubpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VADDSUBPDrr [HasAVX]
vaddsubpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VADDSUBPSYrm [HasAVX]
vaddsubps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VADDSUBPSYrr [HasAVX]
vaddsubps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VADDSUBPSrm [HasAVX]
vaddsubps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VADDSUBPSrr [HasAVX]
vaddsubps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VBLENDPDYrmi [HasAVX]
vblendpd {src3, src2, src1, dst|dst, src1, src2, src3}
VBLENDPDYrri [HasAVX]
vblendpd {src3, src2, src1, dst|dst, src1, src2, src3}
VBLENDPDrmi [HasAVX]
vblendpd {src3, src2, src1, dst|dst, src1, src2, src3}
VBLENDPDrri [HasAVX]
vblendpd {src3, src2, src1, dst|dst, src1, src2, src3}
VBLENDPSYrmi [HasAVX]
vblendps {src3, src2, src1, dst|dst, src1, src2, src3}
VBLENDPSYrri [HasAVX]
vblendps {src3, src2, src1, dst|dst, src1, src2, src3}
VBLENDPSrmi [HasAVX]
vblendps {src3, src2, src1, dst|dst, src1, src2, src3}
VBLENDPSrri [HasAVX]
vblendps {src3, src2, src1, dst|dst, src1, src2, src3}
VBLENDVPDYrmr [HasAVX]
vblendvpd {src3, src2, src1, dst|dst, src1, src2, src3}
VBLENDVPDYrrr [HasAVX]
vblendvpd {src3, src2, src1, dst|dst, src1, src2, src3}
VBLENDVPDrmr [HasAVX]
vblendvpd {src3, src2, src1, dst|dst, src1, src2, src3}
VBLENDVPDrrr [HasAVX]
vblendvpd {src3, src2, src1, dst|dst, src1, src2, src3}
VBLENDVPSYrmr [HasAVX]
vblendvps {src3, src2, src1, dst|dst, src1, src2, src3}
VBLENDVPSYrrr [HasAVX]
vblendvps {src3, src2, src1, dst|dst, src1, src2, src3}
VBLENDVPSrmr [HasAVX]
vblendvps {src3, src2, src1, dst|dst, src1, src2, src3}
VBLENDVPSrrr [HasAVX]
vblendvps {src3, src2, src1, dst|dst, src1, src2, src3}
VBROADCASTF128rm [HasAVX]
vbroadcastf128 {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
VCMPPDYrmi [HasAVX]
vcmppd {cc, src2, src1, dst|dst, src1, src2, cc}
|
Note
|
Properties: mayRaiseFPException |
VCMPPDYrri [HasAVX]
vcmppd {cc, src2, src1, dst|dst, src1, src2, cc}
|
Note
|
Properties: mayRaiseFPException |
VCMPPDrmi [HasAVX]
vcmppd {cc, src2, src1, dst|dst, src1, src2, cc}
|
Note
|
Properties: mayRaiseFPException |
VCMPPDrri [HasAVX]
vcmppd {cc, src2, src1, dst|dst, src1, src2, cc}
|
Note
|
Properties: mayRaiseFPException |
VCMPPSYrmi [HasAVX]
vcmpps {cc, src2, src1, dst|dst, src1, src2, cc}
|
Note
|
Properties: mayRaiseFPException |
VCMPPSYrri [HasAVX]
vcmpps {cc, src2, src1, dst|dst, src1, src2, cc}
|
Note
|
Properties: mayRaiseFPException |
VCMPPSrmi [HasAVX]
vcmpps {cc, src2, src1, dst|dst, src1, src2, cc}
|
Note
|
Properties: mayRaiseFPException |
VCMPPSrri [HasAVX]
vcmpps {cc, src2, src1, dst|dst, src1, src2, cc}
|
Note
|
Properties: mayRaiseFPException |
VCMPSDrmi_Int [HasAVX]
vcmpsd {cc, src2, src1, dst|dst, src1, src2, cc}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VCMPSDrri_Int [HasAVX]
vcmpsd {cc, src2, src1, dst|dst, src1, src2, cc}
|
Note
|
Properties: mayRaiseFPException |
VCMPSSrmi_Int [HasAVX]
vcmpss {cc, src2, src1, dst|dst, src1, src2, cc}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VCMPSSrri_Int [HasAVX]
vcmpss {cc, src2, src1, dst|dst, src1, src2, cc}
|
Note
|
Properties: mayRaiseFPException |
VCVTSS2SDrm_Int [HasAVX]
vcvtss2sd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VCVTSS2SDrr_Int [HasAVX]
vcvtss2sd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VDPPDrmi [HasAVX]
vdppd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VDPPDrri [HasAVX]
vdppd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VDPPSYrmi [HasAVX]
vdpps {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VDPPSYrri [HasAVX]
vdpps {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VDPPSrmi [HasAVX]
vdpps {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VDPPSrri [HasAVX]
vdpps {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VEXTRACTF128mri [HasAVX]
vextractf128 {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayStore |
VEXTRACTF128rri [HasAVX]
vextractf128 {src2, src1, dst|dst, src1, src2}
VHADDPDYrm [HasAVX]
vhaddpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VHADDPDYrr [HasAVX]
vhaddpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VHADDPDrm [HasAVX]
vhaddpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VHADDPDrr [HasAVX]
vhaddpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VHADDPSYrm [HasAVX]
vhaddps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VHADDPSYrr [HasAVX]
vhaddps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VHADDPSrm [HasAVX]
vhaddps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VHADDPSrr [HasAVX]
vhaddps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VHSUBPDYrm [HasAVX]
vhsubpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VHSUBPDYrr [HasAVX]
vhsubpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VHSUBPDrm [HasAVX]
vhsubpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VHSUBPDrr [HasAVX]
vhsubpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VHSUBPSYrm [HasAVX]
vhsubps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VHSUBPSYrr [HasAVX]
vhsubps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VHSUBPSrm [HasAVX]
vhsubps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VHSUBPSrr [HasAVX]
vhsubps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VINSERTF128rmi [HasAVX]
vinsertf128 {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayLoad |
VINSERTF128rri [HasAVX]
vinsertf128 {src3, src2, src1, dst|dst, src1, src2, src3}
VLDDQUYrm [HasAVX]
vlddqu {src, dst|dst, src}
VLDDQUrm [HasAVX]
vlddqu {src, dst|dst, src}
VLDMXCSR [HasAVX]
vldmxcsr src
|
Note
|
Properties: hasSideEffects, mayLoad |
VMASKMOVDQU [HasAVX]
vmaskmovdqu {mask, src|src, mask}
VMASKMOVPDYmr [HasAVX]
vmaskmovpd {src2, src1, dst|dst, src1, src2}
VMASKMOVPDYrm [HasAVX]
vmaskmovpd {src2, src1, dst|dst, src1, src2}
VMASKMOVPDmr [HasAVX]
vmaskmovpd {src2, src1, dst|dst, src1, src2}
VMASKMOVPDrm [HasAVX]
vmaskmovpd {src2, src1, dst|dst, src1, src2}
VMASKMOVPSYmr [HasAVX]
vmaskmovps {src2, src1, dst|dst, src1, src2}
VMASKMOVPSYrm [HasAVX]
vmaskmovps {src2, src1, dst|dst, src1, src2}
VMASKMOVPSmr [HasAVX]
vmaskmovps {src2, src1, dst|dst, src1, src2}
VMASKMOVPSrm [HasAVX]
vmaskmovps {src2, src1, dst|dst, src1, src2}
VMOVDQAYrr [HasAVX]
vmovdqa {src, dst|dst, src}
VMOVDQArr [HasAVX]
vmovdqa {src, dst|dst, src}
VMOVDQUYrr [HasAVX]
vmovdqu {src, dst|dst, src}
VMOVDQUrr [HasAVX]
vmovdqu {src, dst|dst, src}
VMOVMSKPDYrr [HasAVX]
vmovmskpd {src, dst|dst, src}
VMOVMSKPDrr [HasAVX]
vmovmskpd {src, dst|dst, src}
VMOVMSKPSYrr [HasAVX]
vmovmskps {src, dst|dst, src}
VMOVMSKPSrr [HasAVX]
vmovmskps {src, dst|dst, src}
VPBLENDVBrmr [HasAVX]
vpblendvb {src3, src2, src1, dst|dst, src1, src2, src3}
VPBLENDVBrrr [HasAVX]
vpblendvb {src3, src2, src1, dst|dst, src1, src2, src3}
VPBLENDWrmi [HasAVX]
vpblendw {src3, src2, src1, dst|dst, src1, src2, src3}
VPBLENDWrri [HasAVX]
vpblendw {src3, src2, src1, dst|dst, src1, src2, src3}
VPCMPEQQrm [HasAVX]
vpcmpeqq {src2, src1, dst|dst, src1, src2}
VPCMPEQQrr [HasAVX]
vpcmpeqq {src2, src1, dst|dst, src1, src2}
VPCMPESTRIrmi [HasAVX]
vpcmpestri {src5, src3, src1|src1, src3, src5}
|
Note
|
Properties: mayLoad |
VPCMPESTRIrri [HasAVX]
vpcmpestri {src5, src3, src1|src1, src3, src5}
VPCMPESTRMrmi [HasAVX]
vpcmpestrm {src5, src3, src1|src1, src3, src5}
|
Note
|
Properties: mayLoad |
VPCMPESTRMrri [HasAVX]
vpcmpestrm {src5, src3, src1|src1, src3, src5}
VPCMPGTQrm [HasAVX]
vpcmpgtq {src2, src1, dst|dst, src1, src2}
VPCMPGTQrr [HasAVX]
vpcmpgtq {src2, src1, dst|dst, src1, src2}
VPCMPISTRIrmi [HasAVX]
vpcmpistri {src3, src2, src1|src1, src2, src3}
|
Note
|
Properties: mayLoad |
VPCMPISTRIrri [HasAVX]
vpcmpistri {src3, src2, src1|src1, src2, src3}
VPCMPISTRMrmi [HasAVX]
vpcmpistrm {src3, src2, src1|src1, src2, src3}
|
Note
|
Properties: mayLoad |
VPCMPISTRMrri [HasAVX]
vpcmpistrm {src3, src2, src1|src1, src2, src3}
VPERM2F128rmi [HasAVX]
vperm2f128 {src3, src2, src1, dst|dst, src1, src2, src3}
VPERM2F128rri [HasAVX]
vperm2f128 {src3, src2, src1, dst|dst, src1, src2, src3}
VPHADDDrm [HasAVX]
vphaddd {src2, src1, dst|dst, src1, src2}
VPHADDDrr [HasAVX]
vphaddd {src2, src1, dst|dst, src1, src2}
VPHADDSWrm [HasAVX]
vphaddsw {src2, src1, dst|dst, src1, src2}
VPHADDSWrr [HasAVX]
vphaddsw {src2, src1, dst|dst, src1, src2}
VPHADDWrm [HasAVX]
vphaddw {src2, src1, dst|dst, src1, src2}
VPHADDWrr [HasAVX]
vphaddw {src2, src1, dst|dst, src1, src2}
VPHMINPOSUWrm [HasAVX]
vphminposuw {src, dst|dst, src}
VPHMINPOSUWrr [HasAVX]
vphminposuw {src, dst|dst, src}
VPHSUBDrm [HasAVX]
vphsubd {src2, src1, dst|dst, src1, src2}
VPHSUBDrr [HasAVX]
vphsubd {src2, src1, dst|dst, src1, src2}
VPHSUBSWrm [HasAVX]
vphsubsw {src2, src1, dst|dst, src1, src2}
VPHSUBSWrr [HasAVX]
vphsubsw {src2, src1, dst|dst, src1, src2}
VPHSUBWrm [HasAVX]
vphsubw {src2, src1, dst|dst, src1, src2}
VPHSUBWrr [HasAVX]
vphsubw {src2, src1, dst|dst, src1, src2}
VPMOVMSKBrr [HasAVX]
vpmovmskb {src, dst|dst, src}
VPSIGNBrm [HasAVX]
vpsignb {src2, src1, dst|dst, src1, src2}
VPSIGNBrr [HasAVX]
vpsignb {src2, src1, dst|dst, src1, src2}
VPSIGNDrm [HasAVX]
vpsignd {src2, src1, dst|dst, src1, src2}
VPSIGNDrr [HasAVX]
vpsignd {src2, src1, dst|dst, src1, src2}
VPSIGNWrm [HasAVX]
vpsignw {src2, src1, dst|dst, src1, src2}
VPSIGNWrr [HasAVX]
vpsignw {src2, src1, dst|dst, src1, src2}
VPTESTYrm [HasAVX]
vptest {src2, src1|src1, src2}
VPTESTYrr [HasAVX]
vptest {src2, src1|src1, src2}
VPTESTrm [HasAVX]
vptest {src2, src1|src1, src2}
VPTESTrr [HasAVX]
vptest {src2, src1|src1, src2}
VRCPPSYm [HasAVX]
vrcpps {src, dst|dst, src}
VRCPPSYr [HasAVX]
vrcpps {src, dst|dst, src}
VRCPPSm [HasAVX]
vrcpps {src, dst|dst, src}
VRCPPSr [HasAVX]
vrcpps {src, dst|dst, src}
VRSQRTPSYm [HasAVX]
vrsqrtps {src, dst|dst, src}
VRSQRTPSYr [HasAVX]
vrsqrtps {src, dst|dst, src}
VRSQRTPSm [HasAVX]
vrsqrtps {src, dst|dst, src}
VRSQRTPSr [HasAVX]
vrsqrtps {src, dst|dst, src}
VSTMXCSR [HasAVX]
vstmxcsr dst
|
Note
|
Properties: hasSideEffects, mayStore |
VTESTPDYrm [HasAVX]
vtestpd {src2, src1|src1, src2}
VTESTPDYrr [HasAVX]
vtestpd {src2, src1|src1, src2}
VTESTPDrm [HasAVX]
vtestpd {src2, src1|src1, src2}
VTESTPDrr [HasAVX]
vtestpd {src2, src1|src1, src2}
VTESTPSYrm [HasAVX]
vtestps {src2, src1|src1, src2}
VTESTPSYrr [HasAVX]
vtestps {src2, src1|src1, src2}
VTESTPSrm [HasAVX]
vtestps {src2, src1|src1, src2}
VTESTPSrr [HasAVX]
vtestps {src2, src1|src1, src2}
VZEROALL [HasAVX]
vzeroall
VZEROUPPER [HasAVX]
vzeroupper
VPABSBrm [HasAVX, NoVLX_Or_NoBWI]
vpabsb {src, dst|dst, src}
VPABSBrr [HasAVX, NoVLX_Or_NoBWI]
vpabsb {src, dst|dst, src}
VPABSWrm [HasAVX, NoVLX_Or_NoBWI]
vpabsw {src, dst|dst, src}
VPABSWrr [HasAVX, NoVLX_Or_NoBWI]
vpabsw {src, dst|dst, src}
VPACKSSDWrm [HasAVX, NoVLX_Or_NoBWI]
vpackssdw {src2, src1, dst|dst, src1, src2}
VPACKSSDWrr [HasAVX, NoVLX_Or_NoBWI]
vpackssdw {src2, src1, dst|dst, src1, src2}
VPACKSSWBrm [HasAVX, NoVLX_Or_NoBWI]
vpacksswb {src2, src1, dst|dst, src1, src2}
VPACKSSWBrr [HasAVX, NoVLX_Or_NoBWI]
vpacksswb {src2, src1, dst|dst, src1, src2}
VPACKUSDWrm [HasAVX, NoVLX_Or_NoBWI]
vpackusdw {src2, src1, dst|dst, src1, src2}
VPACKUSDWrr [HasAVX, NoVLX_Or_NoBWI]
vpackusdw {src2, src1, dst|dst, src1, src2}
VPACKUSWBrm [HasAVX, NoVLX_Or_NoBWI]
vpackuswb {src2, src1, dst|dst, src1, src2}
VPACKUSWBrr [HasAVX, NoVLX_Or_NoBWI]
vpackuswb {src2, src1, dst|dst, src1, src2}
VPADDBrm [HasAVX, NoVLX_Or_NoBWI]
vpaddb {src2, src1, dst|dst, src1, src2}
VPADDBrr [HasAVX, NoVLX_Or_NoBWI]
vpaddb {src2, src1, dst|dst, src1, src2}
VPADDSBrm [HasAVX, NoVLX_Or_NoBWI]
vpaddsb {src2, src1, dst|dst, src1, src2}
VPADDSBrr [HasAVX, NoVLX_Or_NoBWI]
vpaddsb {src2, src1, dst|dst, src1, src2}
VPADDSWrm [HasAVX, NoVLX_Or_NoBWI]
vpaddsw {src2, src1, dst|dst, src1, src2}
VPADDSWrr [HasAVX, NoVLX_Or_NoBWI]
vpaddsw {src2, src1, dst|dst, src1, src2}
VPADDUSBrm [HasAVX, NoVLX_Or_NoBWI]
vpaddusb {src2, src1, dst|dst, src1, src2}
VPADDUSBrr [HasAVX, NoVLX_Or_NoBWI]
vpaddusb {src2, src1, dst|dst, src1, src2}
VPADDUSWrm [HasAVX, NoVLX_Or_NoBWI]
vpaddusw {src2, src1, dst|dst, src1, src2}
VPADDUSWrr [HasAVX, NoVLX_Or_NoBWI]
vpaddusw {src2, src1, dst|dst, src1, src2}
VPADDWrm [HasAVX, NoVLX_Or_NoBWI]
vpaddw {src2, src1, dst|dst, src1, src2}
VPADDWrr [HasAVX, NoVLX_Or_NoBWI]
vpaddw {src2, src1, dst|dst, src1, src2}
VPALIGNRrmi [HasAVX, NoVLX_Or_NoBWI]
vpalignr {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayLoad |
VPALIGNRrri [HasAVX, NoVLX_Or_NoBWI]
vpalignr {src3, src2, src1, dst|dst, src1, src2, src3}
VPAVGBrm [HasAVX, NoVLX_Or_NoBWI]
vpavgb {src2, src1, dst|dst, src1, src2}
VPAVGBrr [HasAVX, NoVLX_Or_NoBWI]
vpavgb {src2, src1, dst|dst, src1, src2}
VPAVGWrm [HasAVX, NoVLX_Or_NoBWI]
vpavgw {src2, src1, dst|dst, src1, src2}
VPAVGWrr [HasAVX, NoVLX_Or_NoBWI]
vpavgw {src2, src1, dst|dst, src1, src2}
VPMADDUBSWrm [HasAVX, NoVLX_Or_NoBWI]
vpmaddubsw {src2, src1, dst|dst, src1, src2}
VPMADDUBSWrr [HasAVX, NoVLX_Or_NoBWI]
vpmaddubsw {src2, src1, dst|dst, src1, src2}
VPMADDWDrm [HasAVX, NoVLX_Or_NoBWI]
vpmaddwd {src2, src1, dst|dst, src1, src2}
VPMADDWDrr [HasAVX, NoVLX_Or_NoBWI]
vpmaddwd {src2, src1, dst|dst, src1, src2}
VPMAXSBrm [HasAVX, NoVLX_Or_NoBWI]
vpmaxsb {src2, src1, dst|dst, src1, src2}
VPMAXSBrr [HasAVX, NoVLX_Or_NoBWI]
vpmaxsb {src2, src1, dst|dst, src1, src2}
VPMAXSWrm [HasAVX, NoVLX_Or_NoBWI]
vpmaxsw {src2, src1, dst|dst, src1, src2}
VPMAXSWrr [HasAVX, NoVLX_Or_NoBWI]
vpmaxsw {src2, src1, dst|dst, src1, src2}
VPMAXUBrm [HasAVX, NoVLX_Or_NoBWI]
vpmaxub {src2, src1, dst|dst, src1, src2}
VPMAXUBrr [HasAVX, NoVLX_Or_NoBWI]
vpmaxub {src2, src1, dst|dst, src1, src2}
VPMAXUWrm [HasAVX, NoVLX_Or_NoBWI]
vpmaxuw {src2, src1, dst|dst, src1, src2}
VPMAXUWrr [HasAVX, NoVLX_Or_NoBWI]
vpmaxuw {src2, src1, dst|dst, src1, src2}
VPMINSBrm [HasAVX, NoVLX_Or_NoBWI]
vpminsb {src2, src1, dst|dst, src1, src2}
VPMINSBrr [HasAVX, NoVLX_Or_NoBWI]
vpminsb {src2, src1, dst|dst, src1, src2}
VPMINSWrm [HasAVX, NoVLX_Or_NoBWI]
vpminsw {src2, src1, dst|dst, src1, src2}
VPMINSWrr [HasAVX, NoVLX_Or_NoBWI]
vpminsw {src2, src1, dst|dst, src1, src2}
VPMINUBrm [HasAVX, NoVLX_Or_NoBWI]
vpminub {src2, src1, dst|dst, src1, src2}
VPMINUBrr [HasAVX, NoVLX_Or_NoBWI]
vpminub {src2, src1, dst|dst, src1, src2}
VPMINUWrm [HasAVX, NoVLX_Or_NoBWI]
vpminuw {src2, src1, dst|dst, src1, src2}
VPMINUWrr [HasAVX, NoVLX_Or_NoBWI]
vpminuw {src2, src1, dst|dst, src1, src2}
VPMOVSXBWrm [HasAVX, NoVLX_Or_NoBWI]
vpmovsxbw {src, dst|dst, src}
VPMOVSXBWrr [HasAVX, NoVLX_Or_NoBWI]
vpmovsxbw {src, dst|dst, src}
VPMOVZXBWrm [HasAVX, NoVLX_Or_NoBWI]
vpmovzxbw {src, dst|dst, src}
VPMOVZXBWrr [HasAVX, NoVLX_Or_NoBWI]
vpmovzxbw {src, dst|dst, src}
VPMULHRSWrm [HasAVX, NoVLX_Or_NoBWI]
vpmulhrsw {src2, src1, dst|dst, src1, src2}
VPMULHRSWrr [HasAVX, NoVLX_Or_NoBWI]
vpmulhrsw {src2, src1, dst|dst, src1, src2}
VPMULHUWrm [HasAVX, NoVLX_Or_NoBWI]
vpmulhuw {src2, src1, dst|dst, src1, src2}
VPMULHUWrr [HasAVX, NoVLX_Or_NoBWI]
vpmulhuw {src2, src1, dst|dst, src1, src2}
VPMULHWrm [HasAVX, NoVLX_Or_NoBWI]
vpmulhw {src2, src1, dst|dst, src1, src2}
VPMULHWrr [HasAVX, NoVLX_Or_NoBWI]
vpmulhw {src2, src1, dst|dst, src1, src2}
VPMULLWrm [HasAVX, NoVLX_Or_NoBWI]
vpmullw {src2, src1, dst|dst, src1, src2}
VPMULLWrr [HasAVX, NoVLX_Or_NoBWI]
vpmullw {src2, src1, dst|dst, src1, src2}
VPSADBWrm [HasAVX, NoVLX_Or_NoBWI]
vpsadbw {src2, src1, dst|dst, src1, src2}
VPSADBWrr [HasAVX, NoVLX_Or_NoBWI]
vpsadbw {src2, src1, dst|dst, src1, src2}
VPSHUFBrm [HasAVX, NoVLX_Or_NoBWI]
vpshufb {src2, src1, dst|dst, src1, src2}
VPSHUFBrr [HasAVX, NoVLX_Or_NoBWI]
vpshufb {src2, src1, dst|dst, src1, src2}
VPSHUFHWmi [HasAVX, NoVLX_Or_NoBWI]
vpshufhw {src2, src1, dst|dst, src1, src2}
VPSHUFHWri [HasAVX, NoVLX_Or_NoBWI]
vpshufhw {src2, src1, dst|dst, src1, src2}
VPSHUFLWmi [HasAVX, NoVLX_Or_NoBWI]
vpshuflw {src2, src1, dst|dst, src1, src2}
VPSHUFLWri [HasAVX, NoVLX_Or_NoBWI]
vpshuflw {src2, src1, dst|dst, src1, src2}
VPSLLDQri [HasAVX, NoVLX_Or_NoBWI]
vpslldq {src2, src1, dst|dst, src1, src2}
VPSLLWri [HasAVX, NoVLX_Or_NoBWI]
vpsllw {src2, src1, dst|dst, src1, src2}
VPSLLWrm [HasAVX, NoVLX_Or_NoBWI]
vpsllw {src2, src1, dst|dst, src1, src2}
VPSLLWrr [HasAVX, NoVLX_Or_NoBWI]
vpsllw {src2, src1, dst|dst, src1, src2}
VPSRAWri [HasAVX, NoVLX_Or_NoBWI]
vpsraw {src2, src1, dst|dst, src1, src2}
VPSRAWrm [HasAVX, NoVLX_Or_NoBWI]
vpsraw {src2, src1, dst|dst, src1, src2}
VPSRAWrr [HasAVX, NoVLX_Or_NoBWI]
vpsraw {src2, src1, dst|dst, src1, src2}
VPSRLDQri [HasAVX, NoVLX_Or_NoBWI]
vpsrldq {src2, src1, dst|dst, src1, src2}
VPSRLWri [HasAVX, NoVLX_Or_NoBWI]
vpsrlw {src2, src1, dst|dst, src1, src2}
VPSRLWrm [HasAVX, NoVLX_Or_NoBWI]
vpsrlw {src2, src1, dst|dst, src1, src2}
VPSRLWrr [HasAVX, NoVLX_Or_NoBWI]
vpsrlw {src2, src1, dst|dst, src1, src2}
VPSUBBrm [HasAVX, NoVLX_Or_NoBWI]
vpsubb {src2, src1, dst|dst, src1, src2}
VPSUBBrr [HasAVX, NoVLX_Or_NoBWI]
vpsubb {src2, src1, dst|dst, src1, src2}
VPSUBSBrm [HasAVX, NoVLX_Or_NoBWI]
vpsubsb {src2, src1, dst|dst, src1, src2}
VPSUBSBrr [HasAVX, NoVLX_Or_NoBWI]
vpsubsb {src2, src1, dst|dst, src1, src2}
VPSUBSWrm [HasAVX, NoVLX_Or_NoBWI]
vpsubsw {src2, src1, dst|dst, src1, src2}
VPSUBSWrr [HasAVX, NoVLX_Or_NoBWI]
vpsubsw {src2, src1, dst|dst, src1, src2}
VPSUBUSBrm [HasAVX, NoVLX_Or_NoBWI]
vpsubusb {src2, src1, dst|dst, src1, src2}
VPSUBUSBrr [HasAVX, NoVLX_Or_NoBWI]
vpsubusb {src2, src1, dst|dst, src1, src2}
VPSUBUSWrm [HasAVX, NoVLX_Or_NoBWI]
vpsubusw {src2, src1, dst|dst, src1, src2}
VPSUBUSWrr [HasAVX, NoVLX_Or_NoBWI]
vpsubusw {src2, src1, dst|dst, src1, src2}
VPSUBWrm [HasAVX, NoVLX_Or_NoBWI]
vpsubw {src2, src1, dst|dst, src1, src2}
VPSUBWrr [HasAVX, NoVLX_Or_NoBWI]
vpsubw {src2, src1, dst|dst, src1, src2}
VPUNPCKHBWrm [HasAVX, NoVLX_Or_NoBWI]
vpunpckhbw {src2, src1, dst|dst, src1, src2}
VPUNPCKHBWrr [HasAVX, NoVLX_Or_NoBWI]
vpunpckhbw {src2, src1, dst|dst, src1, src2}
VPUNPCKHWDrm [HasAVX, NoVLX_Or_NoBWI]
vpunpckhwd {src2, src1, dst|dst, src1, src2}
VPUNPCKHWDrr [HasAVX, NoVLX_Or_NoBWI]
vpunpckhwd {src2, src1, dst|dst, src1, src2}
VPUNPCKLBWrm [HasAVX, NoVLX_Or_NoBWI]
vpunpcklbw {src2, src1, dst|dst, src1, src2}
VPUNPCKLBWrr [HasAVX, NoVLX_Or_NoBWI]
vpunpcklbw {src2, src1, dst|dst, src1, src2}
VPUNPCKLWDrm [HasAVX, NoVLX_Or_NoBWI]
vpunpcklwd {src2, src1, dst|dst, src1, src2}
VPUNPCKLWDrr [HasAVX, NoVLX_Or_NoBWI]
vpunpcklwd {src2, src1, dst|dst, src1, src2}
VAESIMCrm [HasAVX, HasAES]
vaesimc {src1, dst|dst, src1}
VAESIMCrr [HasAVX, HasAES]
vaesimc {src1, dst|dst, src1}
VAESKEYGENASSIST128rm [HasAVX, HasAES]
vaeskeygenassist {src2, src1, dst|dst, src1, src2}
VAESKEYGENASSIST128rr [HasAVX, HasAES]
vaeskeygenassist {src2, src1, dst|dst, src1, src2}
VPCMPEQBrm [HasAVX, TruePredicate]
vpcmpeqb {src2, src1, dst|dst, src1, src2}
VPCMPEQBrr [HasAVX, TruePredicate]
vpcmpeqb {src2, src1, dst|dst, src1, src2}
VPCMPEQDrm [HasAVX, TruePredicate]
vpcmpeqd {src2, src1, dst|dst, src1, src2}
VPCMPEQDrr [HasAVX, TruePredicate]
vpcmpeqd {src2, src1, dst|dst, src1, src2}
VPCMPEQWrm [HasAVX, TruePredicate]
vpcmpeqw {src2, src1, dst|dst, src1, src2}
VPCMPEQWrr [HasAVX, TruePredicate]
vpcmpeqw {src2, src1, dst|dst, src1, src2}
VPCMPGTBrm [HasAVX, TruePredicate]
vpcmpgtb {src2, src1, dst|dst, src1, src2}
VPCMPGTBrr [HasAVX, TruePredicate]
vpcmpgtb {src2, src1, dst|dst, src1, src2}
VPCMPGTDrm [HasAVX, TruePredicate]
vpcmpgtd {src2, src1, dst|dst, src1, src2}
VPCMPGTDrr [HasAVX, TruePredicate]
vpcmpgtd {src2, src1, dst|dst, src1, src2}
VPCMPGTWrm [HasAVX, TruePredicate]
vpcmpgtw {src2, src1, dst|dst, src1, src2}
VPCMPGTWrr [HasAVX, TruePredicate]
vpcmpgtw {src2, src1, dst|dst, src1, src2}
VAESDECLASTrm [HasAVX, HasAES, NoVLX_Or_NoVAES]
vaesdeclast {src2, src1, dst|dst, src1, src2}
VAESDECLASTrr [HasAVX, HasAES, NoVLX_Or_NoVAES]
vaesdeclast {src2, src1, dst|dst, src1, src2}
VAESDECrm [HasAVX, HasAES, NoVLX_Or_NoVAES]
vaesdec {src2, src1, dst|dst, src1, src2}
VAESDECrr [HasAVX, HasAES, NoVLX_Or_NoVAES]
vaesdec {src2, src1, dst|dst, src1, src2}
VAESENCLASTrm [HasAVX, HasAES, NoVLX_Or_NoVAES]
vaesenclast {src2, src1, dst|dst, src1, src2}
VAESENCLASTrr [HasAVX, HasAES, NoVLX_Or_NoVAES]
vaesenclast {src2, src1, dst|dst, src1, src2}
VAESENCrm [HasAVX, HasAES, NoVLX_Or_NoVAES]
vaesenc {src2, src1, dst|dst, src1, src2}
VAESENCrr [HasAVX, HasAES, NoVLX_Or_NoVAES]
vaesenc {src2, src1, dst|dst, src1, src2}
VPEXTRBmri [HasAVX, NoBWI]
vpextrb {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayStore |
VPEXTRBrri [HasAVX, NoBWI]
vpextrb {src2, src1, dst|dst, src1, src2}
VPEXTRDmri [HasAVX, NoDQI]
vpextrd {src2, src1, dst|dst, src1, src2}
VPEXTRDrri [HasAVX, NoDQI]
vpextrd {src2, src1, dst|dst, src1, src2}
VPEXTRQmri [HasAVX, NoDQI]
vpextrq {src2, src1, dst|dst, src1, src2}
VPEXTRQrri [HasAVX, NoDQI]
vpextrq {src2, src1, dst|dst, src1, src2}
VPEXTRWmri [HasAVX, NoBWI]
vpextrw {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayStore |
VPEXTRWrri [HasAVX, NoBWI]
vpextrw {src2, src1, dst|dst, src1, src2}
VPINSRBrmi [HasAVX, NoBWI]
vpinsrb {src3, src2, src1, dst|dst, src1, src2, src3}
VPINSRBrri [HasAVX, NoBWI]
vpinsrb {src3, src2, src1, dst|dst, src1, src2, src3}
VPINSRDrmi [HasAVX, NoDQI]
vpinsrd {src3, src2, src1, dst|dst, src1, src2, src3}
VPINSRDrri [HasAVX, NoDQI]
vpinsrd {src3, src2, src1, dst|dst, src1, src2, src3}
VPINSRQrmi [HasAVX, NoDQI]
vpinsrq {src3, src2, src1, dst|dst, src1, src2, src3}
VPINSRQrri [HasAVX, NoDQI]
vpinsrq {src3, src2, src1, dst|dst, src1, src2, src3}
VPINSRWrmi [HasAVX, NoBWI]
vpinsrw {src3, src2, src1, dst|dst, src1, src2, src3}
VPINSRWrri [HasAVX, NoBWI]
vpinsrw {src3, src2, src1, dst|dst, src1, src2, src3}
VMPSADBWrmi [HasAVX, NoAVX10_2]
vmpsadbw {src3, src2, src1, dst|dst, src1, src2, src3}
VMPSADBWrri [HasAVX, NoAVX10_2]
vmpsadbw {src3, src2, src1, dst|dst, src1, src2, src3}
VPCLMULQDQrmi [HasAVX, HasPCLMUL, NoVLX_Or_NoVPCLMULQDQ]
vpclmulqdq {src3, src2, src1, dst|dst, src1, src2, src3}
VPCLMULQDQrri [HasAVX, HasPCLMUL, NoVLX_Or_NoVPCLMULQDQ]
vpclmulqdq {src3, src2, src1, dst|dst, src1, src2, src3}
VPCOMPRESSBZmr [HasVBMI2]
vpcompressb {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VPCOMPRESSBZmrk [HasVBMI2]
vpcompressb {src, dst {mask}|dst {mask}, src}
VPCOMPRESSBZrr [HasVBMI2]
vpcompressb {src1, dst|dst, src1}
VPCOMPRESSBZrrk [HasVBMI2]
vpcompressb {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPCOMPRESSBZrrkz [HasVBMI2]
vpcompressb {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPCOMPRESSWZmr [HasVBMI2]
vpcompressw {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VPCOMPRESSWZmrk [HasVBMI2]
vpcompressw {src, dst {mask}|dst {mask}, src}
VPCOMPRESSWZrr [HasVBMI2]
vpcompressw {src1, dst|dst, src1}
VPCOMPRESSWZrrk [HasVBMI2]
vpcompressw {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPCOMPRESSWZrrkz [HasVBMI2]
vpcompressw {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPEXPANDBZrm [HasVBMI2]
vpexpandb {src1, dst|dst, src1}
VPEXPANDBZrmk [HasVBMI2]
vpexpandb {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPEXPANDBZrmkz [HasVBMI2]
vpexpandb {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPEXPANDBZrr [HasVBMI2]
vpexpandb {src1, dst|dst, src1}
VPEXPANDBZrrk [HasVBMI2]
vpexpandb {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPEXPANDBZrrkz [HasVBMI2]
vpexpandb {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPEXPANDWZrm [HasVBMI2]
vpexpandw {src1, dst|dst, src1}
VPEXPANDWZrmk [HasVBMI2]
vpexpandw {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPEXPANDWZrmkz [HasVBMI2]
vpexpandw {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPEXPANDWZrr [HasVBMI2]
vpexpandw {src1, dst|dst, src1}
VPEXPANDWZrrk [HasVBMI2]
vpexpandw {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPEXPANDWZrrkz [HasVBMI2]
vpexpandw {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPSHLDDZrmbi [HasVBMI2]
vpshldd {src3, src2{1to16}, src1, dst|dst, src1, src2{1to16}, src3}
VPSHLDDZrmbik [HasVBMI2]
vpshldd {src3, src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}, src3}
|
Note
|
Constraints: src0 = dst |
VPSHLDDZrmbikz [HasVBMI2]
vpshldd {src3, src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}, src3}
VPSHLDDZrmi [HasVBMI2]
vpshldd {src3, src2, src1, dst|dst, src1, src2, src3}
VPSHLDDZrmik [HasVBMI2]
vpshldd {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VPSHLDDZrmikz [HasVBMI2]
vpshldd {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VPSHLDDZrri [HasVBMI2]
vpshldd {src3, src2, src1, dst|dst, src1, src2, src3}
VPSHLDDZrrik [HasVBMI2]
vpshldd {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VPSHLDDZrrikz [HasVBMI2]
vpshldd {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VPSHLDQZrmbi [HasVBMI2]
vpshldq {src3, src2{1to8}, src1, dst|dst, src1, src2{1to8}, src3}
VPSHLDQZrmbik [HasVBMI2]
vpshldq {src3, src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}, src3}
|
Note
|
Constraints: src0 = dst |
VPSHLDQZrmbikz [HasVBMI2]
vpshldq {src3, src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}, src3}
VPSHLDQZrmi [HasVBMI2]
vpshldq {src3, src2, src1, dst|dst, src1, src2, src3}
VPSHLDQZrmik [HasVBMI2]
vpshldq {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VPSHLDQZrmikz [HasVBMI2]
vpshldq {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VPSHLDQZrri [HasVBMI2]
vpshldq {src3, src2, src1, dst|dst, src1, src2, src3}
VPSHLDQZrrik [HasVBMI2]
vpshldq {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VPSHLDQZrrikz [HasVBMI2]
vpshldq {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VPSHLDVDZm [HasVBMI2]
vpshldvd {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHLDVDZmb [HasVBMI2]
vpshldvd {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VPSHLDVDZmbk [HasVBMI2]
vpshldvd {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VPSHLDVDZmbkz [HasVBMI2]
vpshldvd {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VPSHLDVDZmk [HasVBMI2]
vpshldvd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHLDVDZmkz [HasVBMI2]
vpshldvd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHLDVDZr [HasVBMI2]
vpshldvd {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHLDVDZrk [HasVBMI2]
vpshldvd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHLDVDZrkz [HasVBMI2]
vpshldvd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHLDVQZm [HasVBMI2]
vpshldvq {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHLDVQZmb [HasVBMI2]
vpshldvq {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPSHLDVQZmbk [HasVBMI2]
vpshldvq {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPSHLDVQZmbkz [HasVBMI2]
vpshldvq {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPSHLDVQZmk [HasVBMI2]
vpshldvq {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHLDVQZmkz [HasVBMI2]
vpshldvq {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHLDVQZr [HasVBMI2]
vpshldvq {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHLDVQZrk [HasVBMI2]
vpshldvq {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHLDVQZrkz [HasVBMI2]
vpshldvq {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHLDVWZm [HasVBMI2]
vpshldvw {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHLDVWZmk [HasVBMI2]
vpshldvw {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHLDVWZmkz [HasVBMI2]
vpshldvw {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHLDVWZr [HasVBMI2]
vpshldvw {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHLDVWZrk [HasVBMI2]
vpshldvw {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHLDVWZrkz [HasVBMI2]
vpshldvw {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHLDWZrmi [HasVBMI2]
vpshldw {src3, src2, src1, dst|dst, src1, src2, src3}
VPSHLDWZrmik [HasVBMI2]
vpshldw {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VPSHLDWZrmikz [HasVBMI2]
vpshldw {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VPSHLDWZrri [HasVBMI2]
vpshldw {src3, src2, src1, dst|dst, src1, src2, src3}
VPSHLDWZrrik [HasVBMI2]
vpshldw {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VPSHLDWZrrikz [HasVBMI2]
vpshldw {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VPSHRDDZrmbi [HasVBMI2]
vpshrdd {src3, src2{1to16}, src1, dst|dst, src1, src2{1to16}, src3}
VPSHRDDZrmbik [HasVBMI2]
vpshrdd {src3, src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}, src3}
|
Note
|
Constraints: src0 = dst |
VPSHRDDZrmbikz [HasVBMI2]
vpshrdd {src3, src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}, src3}
VPSHRDDZrmi [HasVBMI2]
vpshrdd {src3, src2, src1, dst|dst, src1, src2, src3}
VPSHRDDZrmik [HasVBMI2]
vpshrdd {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VPSHRDDZrmikz [HasVBMI2]
vpshrdd {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VPSHRDDZrri [HasVBMI2]
vpshrdd {src3, src2, src1, dst|dst, src1, src2, src3}
VPSHRDDZrrik [HasVBMI2]
vpshrdd {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VPSHRDDZrrikz [HasVBMI2]
vpshrdd {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VPSHRDQZrmbi [HasVBMI2]
vpshrdq {src3, src2{1to8}, src1, dst|dst, src1, src2{1to8}, src3}
VPSHRDQZrmbik [HasVBMI2]
vpshrdq {src3, src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}, src3}
|
Note
|
Constraints: src0 = dst |
VPSHRDQZrmbikz [HasVBMI2]
vpshrdq {src3, src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}, src3}
VPSHRDQZrmi [HasVBMI2]
vpshrdq {src3, src2, src1, dst|dst, src1, src2, src3}
VPSHRDQZrmik [HasVBMI2]
vpshrdq {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VPSHRDQZrmikz [HasVBMI2]
vpshrdq {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VPSHRDQZrri [HasVBMI2]
vpshrdq {src3, src2, src1, dst|dst, src1, src2, src3}
VPSHRDQZrrik [HasVBMI2]
vpshrdq {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VPSHRDQZrrikz [HasVBMI2]
vpshrdq {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VPSHRDVDZm [HasVBMI2]
vpshrdvd {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHRDVDZmb [HasVBMI2]
vpshrdvd {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VPSHRDVDZmbk [HasVBMI2]
vpshrdvd {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VPSHRDVDZmbkz [HasVBMI2]
vpshrdvd {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VPSHRDVDZmk [HasVBMI2]
vpshrdvd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHRDVDZmkz [HasVBMI2]
vpshrdvd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHRDVDZr [HasVBMI2]
vpshrdvd {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHRDVDZrk [HasVBMI2]
vpshrdvd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHRDVDZrkz [HasVBMI2]
vpshrdvd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHRDVQZm [HasVBMI2]
vpshrdvq {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHRDVQZmb [HasVBMI2]
vpshrdvq {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPSHRDVQZmbk [HasVBMI2]
vpshrdvq {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPSHRDVQZmbkz [HasVBMI2]
vpshrdvq {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPSHRDVQZmk [HasVBMI2]
vpshrdvq {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHRDVQZmkz [HasVBMI2]
vpshrdvq {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHRDVQZr [HasVBMI2]
vpshrdvq {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHRDVQZrk [HasVBMI2]
vpshrdvq {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHRDVQZrkz [HasVBMI2]
vpshrdvq {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHRDVWZm [HasVBMI2]
vpshrdvw {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHRDVWZmk [HasVBMI2]
vpshrdvw {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHRDVWZmkz [HasVBMI2]
vpshrdvw {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHRDVWZr [HasVBMI2]
vpshrdvw {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHRDVWZrk [HasVBMI2]
vpshrdvw {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHRDVWZrkz [HasVBMI2]
vpshrdvw {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPSHRDWZrmi [HasVBMI2]
vpshrdw {src3, src2, src1, dst|dst, src1, src2, src3}
VPSHRDWZrmik [HasVBMI2]
vpshrdw {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VPSHRDWZrmikz [HasVBMI2]
vpshrdw {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VPSHRDWZrri [HasVBMI2]
vpshrdw {src3, src2, src1, dst|dst, src1, src2, src3}
VPSHRDWZrrik [HasVBMI2]
vpshrdw {src3, src2, src1, dst {mask}|dst {mask}, src1, src2, src3}
|
Note
|
Constraints: src0 = dst |
VPSHRDWZrrikz [HasVBMI2]
vpshrdw {src3, src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2, src3}
VBROADCASTI128rm [HasAVX2]
vbroadcasti128 {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
VEXTRACTI128mri [HasAVX2]
vextracti128 {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayStore |
VEXTRACTI128rri [HasAVX2]
vextracti128 {src2, src1, dst|dst, src1, src2}
VGATHERDPDYrm [HasAVX2]
vgatherdpd {mask, src2, dst|dst, src2, mask}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst,@earlyclobber mask_wb, src1 = dst, mask = mask_wb |
VGATHERDPDrm [HasAVX2]
vgatherdpd {mask, src2, dst|dst, src2, mask}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst,@earlyclobber mask_wb, src1 = dst, mask = mask_wb |
VGATHERDPSYrm [HasAVX2]
vgatherdps {mask, src2, dst|dst, src2, mask}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst,@earlyclobber mask_wb, src1 = dst, mask = mask_wb |
VGATHERDPSrm [HasAVX2]
vgatherdps {mask, src2, dst|dst, src2, mask}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst,@earlyclobber mask_wb, src1 = dst, mask = mask_wb |
VGATHERQPDYrm [HasAVX2]
vgatherqpd {mask, src2, dst|dst, src2, mask}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst,@earlyclobber mask_wb, src1 = dst, mask = mask_wb |
VGATHERQPDrm [HasAVX2]
vgatherqpd {mask, src2, dst|dst, src2, mask}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst,@earlyclobber mask_wb, src1 = dst, mask = mask_wb |
VGATHERQPSYrm [HasAVX2]
vgatherqps {mask, src2, dst|dst, src2, mask}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst,@earlyclobber mask_wb, src1 = dst, mask = mask_wb |
VGATHERQPSrm [HasAVX2]
vgatherqps {mask, src2, dst|dst, src2, mask}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst,@earlyclobber mask_wb, src1 = dst, mask = mask_wb |
VINSERTI128rmi [HasAVX2]
vinserti128 {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayLoad |
VINSERTI128rri [HasAVX2]
vinserti128 {src3, src2, src1, dst|dst, src1, src2, src3}
VPBLENDDYrmi [HasAVX2]
vpblendd {src3, src2, src1, dst|dst, src1, src2, src3}
VPBLENDDYrri [HasAVX2]
vpblendd {src3, src2, src1, dst|dst, src1, src2, src3}
VPBLENDDrmi [HasAVX2]
vpblendd {src3, src2, src1, dst|dst, src1, src2, src3}
VPBLENDDrri [HasAVX2]
vpblendd {src3, src2, src1, dst|dst, src1, src2, src3}
VPBLENDVBYrmr [HasAVX2]
vpblendvb {src3, src2, src1, dst|dst, src1, src2, src3}
VPBLENDVBYrrr [HasAVX2]
vpblendvb {src3, src2, src1, dst|dst, src1, src2, src3}
VPBLENDWYrmi [HasAVX2]
vpblendw {src3, src2, src1, dst|dst, src1, src2, src3}
VPBLENDWYrri [HasAVX2]
vpblendw {src3, src2, src1, dst|dst, src1, src2, src3}
VPCMPEQQYrm [HasAVX2]
vpcmpeqq {src2, src1, dst|dst, src1, src2}
VPCMPEQQYrr [HasAVX2]
vpcmpeqq {src2, src1, dst|dst, src1, src2}
VPCMPGTQYrm [HasAVX2]
vpcmpgtq {src2, src1, dst|dst, src1, src2}
VPCMPGTQYrr [HasAVX2]
vpcmpgtq {src2, src1, dst|dst, src1, src2}
VPERM2I128rmi [HasAVX2]
vperm2i128 {src3, src2, src1, dst|dst, src1, src2, src3}
VPERM2I128rri [HasAVX2]
vperm2i128 {src3, src2, src1, dst|dst, src1, src2, src3}
VPGATHERDDYrm [HasAVX2]
vpgatherdd {mask, src2, dst|dst, src2, mask}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst,@earlyclobber mask_wb, src1 = dst, mask = mask_wb |
VPGATHERDDrm [HasAVX2]
vpgatherdd {mask, src2, dst|dst, src2, mask}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst,@earlyclobber mask_wb, src1 = dst, mask = mask_wb |
VPGATHERDQYrm [HasAVX2]
vpgatherdq {mask, src2, dst|dst, src2, mask}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst,@earlyclobber mask_wb, src1 = dst, mask = mask_wb |
VPGATHERDQrm [HasAVX2]
vpgatherdq {mask, src2, dst|dst, src2, mask}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst,@earlyclobber mask_wb, src1 = dst, mask = mask_wb |
VPGATHERQDYrm [HasAVX2]
vpgatherqd {mask, src2, dst|dst, src2, mask}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst,@earlyclobber mask_wb, src1 = dst, mask = mask_wb |
VPGATHERQDrm [HasAVX2]
vpgatherqd {mask, src2, dst|dst, src2, mask}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst,@earlyclobber mask_wb, src1 = dst, mask = mask_wb |
VPGATHERQQYrm [HasAVX2]
vpgatherqq {mask, src2, dst|dst, src2, mask}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst,@earlyclobber mask_wb, src1 = dst, mask = mask_wb |
VPGATHERQQrm [HasAVX2]
vpgatherqq {mask, src2, dst|dst, src2, mask}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: @earlyclobber dst,@earlyclobber mask_wb, src1 = dst, mask = mask_wb |
VPHADDDYrm [HasAVX2]
vphaddd {src2, src1, dst|dst, src1, src2}
VPHADDDYrr [HasAVX2]
vphaddd {src2, src1, dst|dst, src1, src2}
VPHADDSWYrm [HasAVX2]
vphaddsw {src2, src1, dst|dst, src1, src2}
VPHADDSWYrr [HasAVX2]
vphaddsw {src2, src1, dst|dst, src1, src2}
VPHADDWYrm [HasAVX2]
vphaddw {src2, src1, dst|dst, src1, src2}
VPHADDWYrr [HasAVX2]
vphaddw {src2, src1, dst|dst, src1, src2}
VPHSUBDYrm [HasAVX2]
vphsubd {src2, src1, dst|dst, src1, src2}
VPHSUBDYrr [HasAVX2]
vphsubd {src2, src1, dst|dst, src1, src2}
VPHSUBSWYrm [HasAVX2]
vphsubsw {src2, src1, dst|dst, src1, src2}
VPHSUBSWYrr [HasAVX2]
vphsubsw {src2, src1, dst|dst, src1, src2}
VPHSUBWYrm [HasAVX2]
vphsubw {src2, src1, dst|dst, src1, src2}
VPHSUBWYrr [HasAVX2]
vphsubw {src2, src1, dst|dst, src1, src2}
VPMASKMOVDYmr [HasAVX2]
vpmaskmovd {src2, src1, dst|dst, src1, src2}
VPMASKMOVDYrm [HasAVX2]
vpmaskmovd {src2, src1, dst|dst, src1, src2}
VPMASKMOVDmr [HasAVX2]
vpmaskmovd {src2, src1, dst|dst, src1, src2}
VPMASKMOVDrm [HasAVX2]
vpmaskmovd {src2, src1, dst|dst, src1, src2}
VPMASKMOVQYmr [HasAVX2]
vpmaskmovq {src2, src1, dst|dst, src1, src2}
VPMASKMOVQYrm [HasAVX2]
vpmaskmovq {src2, src1, dst|dst, src1, src2}
VPMASKMOVQmr [HasAVX2]
vpmaskmovq {src2, src1, dst|dst, src1, src2}
VPMASKMOVQrm [HasAVX2]
vpmaskmovq {src2, src1, dst|dst, src1, src2}
VPMOVMSKBYrr [HasAVX2]
vpmovmskb {src, dst|dst, src}
VPSIGNBYrm [HasAVX2]
vpsignb {src2, src1, dst|dst, src1, src2}
VPSIGNBYrr [HasAVX2]
vpsignb {src2, src1, dst|dst, src1, src2}
VPSIGNDYrm [HasAVX2]
vpsignd {src2, src1, dst|dst, src1, src2}
VPSIGNDYrr [HasAVX2]
vpsignd {src2, src1, dst|dst, src1, src2}
VPSIGNWYrm [HasAVX2]
vpsignw {src2, src1, dst|dst, src1, src2}
VPSIGNWYrr [HasAVX2]
vpsignw {src2, src1, dst|dst, src1, src2}
VPABSBYrm [HasAVX2, NoVLX_Or_NoBWI]
vpabsb {src, dst|dst, src}
VPABSBYrr [HasAVX2, NoVLX_Or_NoBWI]
vpabsb {src, dst|dst, src}
VPABSWYrm [HasAVX2, NoVLX_Or_NoBWI]
vpabsw {src, dst|dst, src}
VPABSWYrr [HasAVX2, NoVLX_Or_NoBWI]
vpabsw {src, dst|dst, src}
VPACKSSDWYrm [HasAVX2, NoVLX_Or_NoBWI]
vpackssdw {src2, src1, dst|dst, src1, src2}
VPACKSSDWYrr [HasAVX2, NoVLX_Or_NoBWI]
vpackssdw {src2, src1, dst|dst, src1, src2}
VPACKSSWBYrm [HasAVX2, NoVLX_Or_NoBWI]
vpacksswb {src2, src1, dst|dst, src1, src2}
VPACKSSWBYrr [HasAVX2, NoVLX_Or_NoBWI]
vpacksswb {src2, src1, dst|dst, src1, src2}
VPACKUSDWYrm [HasAVX2, NoVLX_Or_NoBWI]
vpackusdw {src2, src1, dst|dst, src1, src2}
VPACKUSDWYrr [HasAVX2, NoVLX_Or_NoBWI]
vpackusdw {src2, src1, dst|dst, src1, src2}
VPACKUSWBYrm [HasAVX2, NoVLX_Or_NoBWI]
vpackuswb {src2, src1, dst|dst, src1, src2}
VPACKUSWBYrr [HasAVX2, NoVLX_Or_NoBWI]
vpackuswb {src2, src1, dst|dst, src1, src2}
VPADDBYrm [HasAVX2, NoVLX_Or_NoBWI]
vpaddb {src2, src1, dst|dst, src1, src2}
VPADDBYrr [HasAVX2, NoVLX_Or_NoBWI]
vpaddb {src2, src1, dst|dst, src1, src2}
VPADDSBYrm [HasAVX2, NoVLX_Or_NoBWI]
vpaddsb {src2, src1, dst|dst, src1, src2}
VPADDSBYrr [HasAVX2, NoVLX_Or_NoBWI]
vpaddsb {src2, src1, dst|dst, src1, src2}
VPADDSWYrm [HasAVX2, NoVLX_Or_NoBWI]
vpaddsw {src2, src1, dst|dst, src1, src2}
VPADDSWYrr [HasAVX2, NoVLX_Or_NoBWI]
vpaddsw {src2, src1, dst|dst, src1, src2}
VPADDUSBYrm [HasAVX2, NoVLX_Or_NoBWI]
vpaddusb {src2, src1, dst|dst, src1, src2}
VPADDUSBYrr [HasAVX2, NoVLX_Or_NoBWI]
vpaddusb {src2, src1, dst|dst, src1, src2}
VPADDUSWYrm [HasAVX2, NoVLX_Or_NoBWI]
vpaddusw {src2, src1, dst|dst, src1, src2}
VPADDUSWYrr [HasAVX2, NoVLX_Or_NoBWI]
vpaddusw {src2, src1, dst|dst, src1, src2}
VPADDWYrm [HasAVX2, NoVLX_Or_NoBWI]
vpaddw {src2, src1, dst|dst, src1, src2}
VPADDWYrr [HasAVX2, NoVLX_Or_NoBWI]
vpaddw {src2, src1, dst|dst, src1, src2}
VPALIGNRYrmi [HasAVX2, NoVLX_Or_NoBWI]
vpalignr {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayLoad |
VPALIGNRYrri [HasAVX2, NoVLX_Or_NoBWI]
vpalignr {src3, src2, src1, dst|dst, src1, src2, src3}
VPAVGBYrm [HasAVX2, NoVLX_Or_NoBWI]
vpavgb {src2, src1, dst|dst, src1, src2}
VPAVGBYrr [HasAVX2, NoVLX_Or_NoBWI]
vpavgb {src2, src1, dst|dst, src1, src2}
VPAVGWYrm [HasAVX2, NoVLX_Or_NoBWI]
vpavgw {src2, src1, dst|dst, src1, src2}
VPAVGWYrr [HasAVX2, NoVLX_Or_NoBWI]
vpavgw {src2, src1, dst|dst, src1, src2}
VPBROADCASTBYrm [HasAVX2, NoVLX_Or_NoBWI]
vpbroadcastb {src, dst|dst, src}
VPBROADCASTBYrr [HasAVX2, NoVLX_Or_NoBWI]
vpbroadcastb {src, dst|dst, src}
VPBROADCASTBrm [HasAVX2, NoVLX_Or_NoBWI]
vpbroadcastb {src, dst|dst, src}
VPBROADCASTBrr [HasAVX2, NoVLX_Or_NoBWI]
vpbroadcastb {src, dst|dst, src}
VPBROADCASTWYrm [HasAVX2, NoVLX_Or_NoBWI]
vpbroadcastw {src, dst|dst, src}
VPBROADCASTWYrr [HasAVX2, NoVLX_Or_NoBWI]
vpbroadcastw {src, dst|dst, src}
VPBROADCASTWrm [HasAVX2, NoVLX_Or_NoBWI]
vpbroadcastw {src, dst|dst, src}
VPBROADCASTWrr [HasAVX2, NoVLX_Or_NoBWI]
vpbroadcastw {src, dst|dst, src}
VPMADDUBSWYrm [HasAVX2, NoVLX_Or_NoBWI]
vpmaddubsw {src2, src1, dst|dst, src1, src2}
VPMADDUBSWYrr [HasAVX2, NoVLX_Or_NoBWI]
vpmaddubsw {src2, src1, dst|dst, src1, src2}
VPMADDWDYrm [HasAVX2, NoVLX_Or_NoBWI]
vpmaddwd {src2, src1, dst|dst, src1, src2}
VPMADDWDYrr [HasAVX2, NoVLX_Or_NoBWI]
vpmaddwd {src2, src1, dst|dst, src1, src2}
VPMAXSBYrm [HasAVX2, NoVLX_Or_NoBWI]
vpmaxsb {src2, src1, dst|dst, src1, src2}
VPMAXSBYrr [HasAVX2, NoVLX_Or_NoBWI]
vpmaxsb {src2, src1, dst|dst, src1, src2}
VPMAXSWYrm [HasAVX2, NoVLX_Or_NoBWI]
vpmaxsw {src2, src1, dst|dst, src1, src2}
VPMAXSWYrr [HasAVX2, NoVLX_Or_NoBWI]
vpmaxsw {src2, src1, dst|dst, src1, src2}
VPMAXUBYrm [HasAVX2, NoVLX_Or_NoBWI]
vpmaxub {src2, src1, dst|dst, src1, src2}
VPMAXUBYrr [HasAVX2, NoVLX_Or_NoBWI]
vpmaxub {src2, src1, dst|dst, src1, src2}
VPMAXUWYrm [HasAVX2, NoVLX_Or_NoBWI]
vpmaxuw {src2, src1, dst|dst, src1, src2}
VPMAXUWYrr [HasAVX2, NoVLX_Or_NoBWI]
vpmaxuw {src2, src1, dst|dst, src1, src2}
VPMINSBYrm [HasAVX2, NoVLX_Or_NoBWI]
vpminsb {src2, src1, dst|dst, src1, src2}
VPMINSBYrr [HasAVX2, NoVLX_Or_NoBWI]
vpminsb {src2, src1, dst|dst, src1, src2}
VPMINSWYrm [HasAVX2, NoVLX_Or_NoBWI]
vpminsw {src2, src1, dst|dst, src1, src2}
VPMINSWYrr [HasAVX2, NoVLX_Or_NoBWI]
vpminsw {src2, src1, dst|dst, src1, src2}
VPMINUBYrm [HasAVX2, NoVLX_Or_NoBWI]
vpminub {src2, src1, dst|dst, src1, src2}
VPMINUBYrr [HasAVX2, NoVLX_Or_NoBWI]
vpminub {src2, src1, dst|dst, src1, src2}
VPMINUWYrm [HasAVX2, NoVLX_Or_NoBWI]
vpminuw {src2, src1, dst|dst, src1, src2}
VPMINUWYrr [HasAVX2, NoVLX_Or_NoBWI]
vpminuw {src2, src1, dst|dst, src1, src2}
VPMOVSXBWYrm [HasAVX2, NoVLX_Or_NoBWI]
vpmovsxbw {src, dst|dst, src}
VPMOVSXBWYrr [HasAVX2, NoVLX_Or_NoBWI]
vpmovsxbw {src, dst|dst, src}
VPMOVZXBWYrm [HasAVX2, NoVLX_Or_NoBWI]
vpmovzxbw {src, dst|dst, src}
VPMOVZXBWYrr [HasAVX2, NoVLX_Or_NoBWI]
vpmovzxbw {src, dst|dst, src}
VPMULHRSWYrm [HasAVX2, NoVLX_Or_NoBWI]
vpmulhrsw {src2, src1, dst|dst, src1, src2}
VPMULHRSWYrr [HasAVX2, NoVLX_Or_NoBWI]
vpmulhrsw {src2, src1, dst|dst, src1, src2}
VPMULHUWYrm [HasAVX2, NoVLX_Or_NoBWI]
vpmulhuw {src2, src1, dst|dst, src1, src2}
VPMULHUWYrr [HasAVX2, NoVLX_Or_NoBWI]
vpmulhuw {src2, src1, dst|dst, src1, src2}
VPMULHWYrm [HasAVX2, NoVLX_Or_NoBWI]
vpmulhw {src2, src1, dst|dst, src1, src2}
VPMULHWYrr [HasAVX2, NoVLX_Or_NoBWI]
vpmulhw {src2, src1, dst|dst, src1, src2}
VPMULLWYrm [HasAVX2, NoVLX_Or_NoBWI]
vpmullw {src2, src1, dst|dst, src1, src2}
VPMULLWYrr [HasAVX2, NoVLX_Or_NoBWI]
vpmullw {src2, src1, dst|dst, src1, src2}
VPSADBWYrm [HasAVX2, NoVLX_Or_NoBWI]
vpsadbw {src2, src1, dst|dst, src1, src2}
VPSADBWYrr [HasAVX2, NoVLX_Or_NoBWI]
vpsadbw {src2, src1, dst|dst, src1, src2}
VPSHUFBYrm [HasAVX2, NoVLX_Or_NoBWI]
vpshufb {src2, src1, dst|dst, src1, src2}
VPSHUFBYrr [HasAVX2, NoVLX_Or_NoBWI]
vpshufb {src2, src1, dst|dst, src1, src2}
VPSHUFHWYmi [HasAVX2, NoVLX_Or_NoBWI]
vpshufhw {src2, src1, dst|dst, src1, src2}
VPSHUFHWYri [HasAVX2, NoVLX_Or_NoBWI]
vpshufhw {src2, src1, dst|dst, src1, src2}
VPSHUFLWYmi [HasAVX2, NoVLX_Or_NoBWI]
vpshuflw {src2, src1, dst|dst, src1, src2}
VPSHUFLWYri [HasAVX2, NoVLX_Or_NoBWI]
vpshuflw {src2, src1, dst|dst, src1, src2}
VPSLLDQYri [HasAVX2, NoVLX_Or_NoBWI]
vpslldq {src2, src1, dst|dst, src1, src2}
VPSLLWYri [HasAVX2, NoVLX_Or_NoBWI]
vpsllw {src2, src1, dst|dst, src1, src2}
VPSLLWYrm [HasAVX2, NoVLX_Or_NoBWI]
vpsllw {src2, src1, dst|dst, src1, src2}
VPSLLWYrr [HasAVX2, NoVLX_Or_NoBWI]
vpsllw {src2, src1, dst|dst, src1, src2}
VPSRAWYri [HasAVX2, NoVLX_Or_NoBWI]
vpsraw {src2, src1, dst|dst, src1, src2}
VPSRAWYrm [HasAVX2, NoVLX_Or_NoBWI]
vpsraw {src2, src1, dst|dst, src1, src2}
VPSRAWYrr [HasAVX2, NoVLX_Or_NoBWI]
vpsraw {src2, src1, dst|dst, src1, src2}
VPSRLDQYri [HasAVX2, NoVLX_Or_NoBWI]
vpsrldq {src2, src1, dst|dst, src1, src2}
VPSRLWYri [HasAVX2, NoVLX_Or_NoBWI]
vpsrlw {src2, src1, dst|dst, src1, src2}
VPSRLWYrm [HasAVX2, NoVLX_Or_NoBWI]
vpsrlw {src2, src1, dst|dst, src1, src2}
VPSRLWYrr [HasAVX2, NoVLX_Or_NoBWI]
vpsrlw {src2, src1, dst|dst, src1, src2}
VPSUBBYrm [HasAVX2, NoVLX_Or_NoBWI]
vpsubb {src2, src1, dst|dst, src1, src2}
VPSUBBYrr [HasAVX2, NoVLX_Or_NoBWI]
vpsubb {src2, src1, dst|dst, src1, src2}
VPSUBSBYrm [HasAVX2, NoVLX_Or_NoBWI]
vpsubsb {src2, src1, dst|dst, src1, src2}
VPSUBSBYrr [HasAVX2, NoVLX_Or_NoBWI]
vpsubsb {src2, src1, dst|dst, src1, src2}
VPSUBSWYrm [HasAVX2, NoVLX_Or_NoBWI]
vpsubsw {src2, src1, dst|dst, src1, src2}
VPSUBSWYrr [HasAVX2, NoVLX_Or_NoBWI]
vpsubsw {src2, src1, dst|dst, src1, src2}
VPSUBUSBYrm [HasAVX2, NoVLX_Or_NoBWI]
vpsubusb {src2, src1, dst|dst, src1, src2}
VPSUBUSBYrr [HasAVX2, NoVLX_Or_NoBWI]
vpsubusb {src2, src1, dst|dst, src1, src2}
VPSUBUSWYrm [HasAVX2, NoVLX_Or_NoBWI]
vpsubusw {src2, src1, dst|dst, src1, src2}
VPSUBUSWYrr [HasAVX2, NoVLX_Or_NoBWI]
vpsubusw {src2, src1, dst|dst, src1, src2}
VPSUBWYrm [HasAVX2, NoVLX_Or_NoBWI]
vpsubw {src2, src1, dst|dst, src1, src2}
VPSUBWYrr [HasAVX2, NoVLX_Or_NoBWI]
vpsubw {src2, src1, dst|dst, src1, src2}
VPUNPCKHBWYrm [HasAVX2, NoVLX_Or_NoBWI]
vpunpckhbw {src2, src1, dst|dst, src1, src2}
VPUNPCKHBWYrr [HasAVX2, NoVLX_Or_NoBWI]
vpunpckhbw {src2, src1, dst|dst, src1, src2}
VPUNPCKHWDYrm [HasAVX2, NoVLX_Or_NoBWI]
vpunpckhwd {src2, src1, dst|dst, src1, src2}
VPUNPCKHWDYrr [HasAVX2, NoVLX_Or_NoBWI]
vpunpckhwd {src2, src1, dst|dst, src1, src2}
VPUNPCKLBWYrm [HasAVX2, NoVLX_Or_NoBWI]
vpunpcklbw {src2, src1, dst|dst, src1, src2}
VPUNPCKLBWYrr [HasAVX2, NoVLX_Or_NoBWI]
vpunpcklbw {src2, src1, dst|dst, src1, src2}
VPUNPCKLWDYrm [HasAVX2, NoVLX_Or_NoBWI]
vpunpcklwd {src2, src1, dst|dst, src1, src2}
VPUNPCKLWDYrr [HasAVX2, NoVLX_Or_NoBWI]
vpunpcklwd {src2, src1, dst|dst, src1, src2}
VPCMPEQBYrm [HasAVX2, TruePredicate]
vpcmpeqb {src2, src1, dst|dst, src1, src2}
VPCMPEQBYrr [HasAVX2, TruePredicate]
vpcmpeqb {src2, src1, dst|dst, src1, src2}
VPCMPEQDYrm [HasAVX2, TruePredicate]
vpcmpeqd {src2, src1, dst|dst, src1, src2}
VPCMPEQDYrr [HasAVX2, TruePredicate]
vpcmpeqd {src2, src1, dst|dst, src1, src2}
VPCMPEQWYrm [HasAVX2, TruePredicate]
vpcmpeqw {src2, src1, dst|dst, src1, src2}
VPCMPEQWYrr [HasAVX2, TruePredicate]
vpcmpeqw {src2, src1, dst|dst, src1, src2}
VPCMPGTBYrm [HasAVX2, TruePredicate]
vpcmpgtb {src2, src1, dst|dst, src1, src2}
VPCMPGTBYrr [HasAVX2, TruePredicate]
vpcmpgtb {src2, src1, dst|dst, src1, src2}
VPCMPGTDYrm [HasAVX2, TruePredicate]
vpcmpgtd {src2, src1, dst|dst, src1, src2}
VPCMPGTDYrr [HasAVX2, TruePredicate]
vpcmpgtd {src2, src1, dst|dst, src1, src2}
VPCMPGTWYrm [HasAVX2, TruePredicate]
vpcmpgtw {src2, src1, dst|dst, src1, src2}
VPCMPGTWYrr [HasAVX2, TruePredicate]
vpcmpgtw {src2, src1, dst|dst, src1, src2}
VMPSADBWYrmi [HasAVX2, NoAVX10_2]
vmpsadbw {src3, src2, src1, dst|dst, src1, src2, src3}
VMPSADBWYrri [HasAVX2, NoAVX10_2]
vmpsadbw {src3, src2, src1, dst|dst, src1, src2, src3}
ADDPDrm [UseSSE2]
addpd {src2, dst|dst, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
ADDPDrr [UseSSE2]
addpd {src2, dst|dst, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
ADDSDrm_Int [UseSSE2]
addsd {src2, dst|dst, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
ADDSDrr_Int [UseSSE2]
addsd {src2, dst|dst, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
ANDNPDrm [UseSSE2]
andnpd {src2, dst|dst, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
ANDNPDrr [UseSSE2]
andnpd {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
ANDPDrm [UseSSE2]
andpd {src2, dst|dst, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
ANDPDrr [UseSSE2]
andpd {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
CMPPDrmi [UseSSE2]
cmppd {cc, src2, dst|dst, src2, cc}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
CMPPDrri [UseSSE2]
cmppd {cc, src2, dst|dst, src2, cc}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
CMPSDrmi_Int [UseSSE2]
cmpsd {cc, src2, dst|dst, src2, cc}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
CMPSDrri_Int [UseSSE2]
cmpsd {cc, src2, dst|dst, src2, cc}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
COMISDrm [UseSSE2]
comisd {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
COMISDrr [UseSSE2]
comisd {src2, src1|src1, src2}
|
Note
|
Properties: mayRaiseFPException |
CVTDQ2PDrm [UseSSE2]
cvtdq2pd {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
CVTDQ2PDrr [UseSSE2]
cvtdq2pd {src, dst|dst, src}
CVTDQ2PSrm [UseSSE2]
cvtdq2ps {src, dst|dst, src}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
CVTDQ2PSrr [UseSSE2]
cvtdq2ps {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
CVTPD2DQrm [UseSSE2]
cvtpd2dq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
CVTPD2DQrr [UseSSE2]
cvtpd2dq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
CVTPD2PSrm [UseSSE2]
cvtpd2ps {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
CVTPD2PSrr [UseSSE2]
cvtpd2ps {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
CVTPS2DQrm [UseSSE2]
cvtps2dq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
CVTPS2DQrr [UseSSE2]
cvtps2dq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
CVTPS2PDrm [UseSSE2]
cvtps2pd {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
CVTPS2PDrr [UseSSE2]
cvtps2pd {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
CVTSD2SI64rm_Int [UseSSE2]
cvtsd2si {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
CVTSD2SI64rr_Int [UseSSE2]
cvtsd2si {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
CVTSD2SIrm_Int [UseSSE2]
cvtsd2si {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
CVTSD2SIrr_Int [UseSSE2]
cvtsd2si {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
CVTSD2SSrm_Int [UseSSE2]
cvtsd2ss {src2, dst|dst, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
CVTSD2SSrr_Int [UseSSE2]
cvtsd2ss {src2, dst|dst, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
CVTSI2SDrm_Int [UseSSE2]
cvtsi2sd{l} {src2, dst|dst, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
CVTSI2SDrr_Int [UseSSE2]
cvtsi2sd {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
CVTSI642SDrm_Int [UseSSE2]
cvtsi2sd{q} {src2, dst|dst, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
CVTSI642SDrr_Int [UseSSE2]
cvtsi2sd {src2, dst|dst, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
CVTSS2SDrm_Int [UseSSE2]
cvtss2sd {src2, dst|dst, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
CVTSS2SDrr_Int [UseSSE2]
cvtss2sd {src2, dst|dst, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
CVTTPD2DQrm [UseSSE2]
cvttpd2dq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
CVTTPD2DQrr [UseSSE2]
cvttpd2dq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
CVTTPS2DQrm [UseSSE2]
cvttps2dq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
CVTTPS2DQrr [UseSSE2]
cvttps2dq {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
CVTTSD2SI64rm_Int [UseSSE2]
cvttsd2si {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
CVTTSD2SI64rr_Int [UseSSE2]
cvttsd2si {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
CVTTSD2SIrm_Int [UseSSE2]
cvttsd2si {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
CVTTSD2SIrr_Int [UseSSE2]
cvttsd2si {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
DIVPDrm [UseSSE2]
divpd {src2, dst|dst, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
DIVPDrr [UseSSE2]
divpd {src2, dst|dst, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
DIVSDrm_Int [UseSSE2]
divsd {src2, dst|dst, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
DIVSDrr_Int [UseSSE2]
divsd {src2, dst|dst, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
MASKMOVDQU [UseSSE2]
maskmovdqu {mask, src|src, mask}
MAXPDrm [UseSSE2]
maxpd {src2, dst|dst, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
MAXPDrr [UseSSE2]
maxpd {src2, dst|dst, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
MAXSDrm_Int [UseSSE2]
maxsd {src2, dst|dst, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
MAXSDrr_Int [UseSSE2]
maxsd {src2, dst|dst, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
MINPDrm [UseSSE2]
minpd {src2, dst|dst, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
MINPDrr [UseSSE2]
minpd {src2, dst|dst, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
MINSDrm_Int [UseSSE2]
minsd {src2, dst|dst, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
MINSDrr_Int [UseSSE2]
minsd {src2, dst|dst, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
MOV64toPQIrr [UseSSE2]
movq {src, dst|dst, src}
MOVAPDmr [UseSSE2]
movapd {src, dst|dst, src}
MOVAPDrm [UseSSE2]
movapd {src, dst|dst, src}
MOVAPDrr [UseSSE2]
movapd {src, dst|dst, src}
|
Note
|
Properties: isMoveReg |
MOVDI2PDIrm [UseSSE2]
movd {src, dst|dst, src}
MOVDI2PDIrr [UseSSE2]
movd {src, dst|dst, src}
MOVDQAmr [UseSSE2]
movdqa {src, dst|dst, src}
|
Note
|
Properties: mayStore |
MOVDQArm [UseSSE2]
movdqa {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
MOVDQArr [UseSSE2]
movdqa {src, dst|dst, src}
MOVDQUmr [UseSSE2]
movdqu {src, dst|dst, src}
|
Note
|
Properties: mayStore |
MOVDQUrm [UseSSE2]
movdqu {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
MOVDQUrr [UseSSE2]
movdqu {src, dst|dst, src}
MOVHPDmr [UseSSE2]
movhpd {src, dst|dst, src}
MOVHPDrm [UseSSE2]
movhpd {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MOVLPDmr [UseSSE2]
movlpd {src, dst|dst, src}
MOVLPDrm [UseSSE2]
movlpd {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MOVMSKPDrr [UseSSE2]
movmskpd {src, dst|dst, src}
MOVNTDQmr [UseSSE2]
movntdq {src, dst|dst, src}
MOVNTPDmr [UseSSE2]
movntpd {src, dst|dst, src}
MOVPDI2DImr [UseSSE2]
movd {src, dst|dst, src}
MOVPDI2DIrr [UseSSE2]
movd {src, dst|dst, src}
MOVPQI2QImr [UseSSE2]
movq {src, dst|dst, src}
MOVPQIto64rr [UseSSE2]
movq {src, dst|dst, src}
MOVQI2PQIrm [UseSSE2]
movq {src, dst|dst, src}
MOVSDmr [UseSSE2]
movsd {src, dst|dst, src}
MOVSDrm [UseSSE2]
movsd {src, dst|dst, src}
MOVUPDmr [UseSSE2]
movupd {src, dst|dst, src}
MOVUPDrm [UseSSE2]
movupd {src, dst|dst, src}
MOVUPDrr [UseSSE2]
movupd {src, dst|dst, src}
|
Note
|
Properties: isMoveReg |
MOVZPQILo2PQIrr [UseSSE2]
movq {src, dst|dst, src}
MULPDrm [UseSSE2]
mulpd {src2, dst|dst, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
MULPDrr [UseSSE2]
mulpd {src2, dst|dst, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
MULSDrm_Int [UseSSE2]
mulsd {src2, dst|dst, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
MULSDrr_Int [UseSSE2]
mulsd {src2, dst|dst, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
ORPDrm [UseSSE2]
orpd {src2, dst|dst, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
ORPDrr [UseSSE2]
orpd {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PACKSSDWrm [UseSSE2]
packssdw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PACKSSDWrr [UseSSE2]
packssdw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PACKSSWBrm [UseSSE2]
packsswb {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PACKSSWBrr [UseSSE2]
packsswb {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PACKUSWBrm [UseSSE2]
packuswb {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PACKUSWBrr [UseSSE2]
packuswb {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PADDBrm [UseSSE2]
paddb {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PADDBrr [UseSSE2]
paddb {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PADDDrm [UseSSE2]
paddd {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PADDDrr [UseSSE2]
paddd {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PADDQrm [UseSSE2]
paddq {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PADDQrr [UseSSE2]
paddq {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PADDSBrm [UseSSE2]
paddsb {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PADDSBrr [UseSSE2]
paddsb {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PADDSWrm [UseSSE2]
paddsw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PADDSWrr [UseSSE2]
paddsw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PADDUSBrm [UseSSE2]
paddusb {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PADDUSBrr [UseSSE2]
paddusb {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PADDUSWrm [UseSSE2]
paddusw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PADDUSWrr [UseSSE2]
paddusw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PADDWrm [UseSSE2]
paddw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PADDWrr [UseSSE2]
paddw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PANDNrm [UseSSE2]
pandn {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PANDNrr [UseSSE2]
pandn {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PANDrm [UseSSE2]
pand {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PANDrr [UseSSE2]
pand {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PAVGBrm [UseSSE2]
pavgb {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PAVGBrr [UseSSE2]
pavgb {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PAVGWrm [UseSSE2]
pavgw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PAVGWrr [UseSSE2]
pavgw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PCMPEQBrm [UseSSE2]
pcmpeqb {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PCMPEQBrr [UseSSE2]
pcmpeqb {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PCMPEQDrm [UseSSE2]
pcmpeqd {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PCMPEQDrr [UseSSE2]
pcmpeqd {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PCMPEQWrm [UseSSE2]
pcmpeqw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PCMPEQWrr [UseSSE2]
pcmpeqw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PCMPGTBrm [UseSSE2]
pcmpgtb {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PCMPGTBrr [UseSSE2]
pcmpgtb {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PCMPGTDrm [UseSSE2]
pcmpgtd {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PCMPGTDrr [UseSSE2]
pcmpgtd {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PCMPGTWrm [UseSSE2]
pcmpgtw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PCMPGTWrr [UseSSE2]
pcmpgtw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PEXTRWrri [UseSSE2]
pextrw {src2, src1, dst|dst, src1, src2}
PINSRWrmi [UseSSE2]
pinsrw {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
PINSRWrri [UseSSE2]
pinsrw {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
PMADDWDrm [UseSSE2]
pmaddwd {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PMADDWDrr [UseSSE2]
pmaddwd {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PMAXSWrm [UseSSE2]
pmaxsw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PMAXSWrr [UseSSE2]
pmaxsw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PMAXUBrm [UseSSE2]
pmaxub {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PMAXUBrr [UseSSE2]
pmaxub {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PMINSWrm [UseSSE2]
pminsw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PMINSWrr [UseSSE2]
pminsw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PMINUBrm [UseSSE2]
pminub {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PMINUBrr [UseSSE2]
pminub {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PMOVMSKBrr [UseSSE2]
pmovmskb {src, dst|dst, src}
PMULHUWrm [UseSSE2]
pmulhuw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PMULHUWrr [UseSSE2]
pmulhuw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PMULHWrm [UseSSE2]
pmulhw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PMULHWrr [UseSSE2]
pmulhw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PMULLWrm [UseSSE2]
pmullw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PMULLWrr [UseSSE2]
pmullw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PMULUDQrm [UseSSE2]
pmuludq {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PMULUDQrr [UseSSE2]
pmuludq {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PORrm [UseSSE2]
por {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PORrr [UseSSE2]
por {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PSADBWrm [UseSSE2]
psadbw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PSADBWrr [UseSSE2]
psadbw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PSHUFDmi [UseSSE2]
pshufd {src2, src1, dst|dst, src1, src2}
PSHUFDri [UseSSE2]
pshufd {src2, src1, dst|dst, src1, src2}
PSHUFHWmi [UseSSE2]
pshufhw {src2, src1, dst|dst, src1, src2}
PSHUFHWri [UseSSE2]
pshufhw {src2, src1, dst|dst, src1, src2}
PSHUFLWmi [UseSSE2]
pshuflw {src2, src1, dst|dst, src1, src2}
PSHUFLWri [UseSSE2]
pshuflw {src2, src1, dst|dst, src1, src2}
PSLLDQri [UseSSE2]
pslldq {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PSLLDri [UseSSE2]
pslld {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PSLLDrm [UseSSE2]
pslld {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PSLLDrr [UseSSE2]
pslld {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PSLLQri [UseSSE2]
psllq {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PSLLQrm [UseSSE2]
psllq {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PSLLQrr [UseSSE2]
psllq {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PSLLWri [UseSSE2]
psllw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PSLLWrm [UseSSE2]
psllw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PSLLWrr [UseSSE2]
psllw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PSRADri [UseSSE2]
psrad {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PSRADrm [UseSSE2]
psrad {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PSRADrr [UseSSE2]
psrad {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PSRAWri [UseSSE2]
psraw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PSRAWrm [UseSSE2]
psraw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PSRAWrr [UseSSE2]
psraw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PSRLDQri [UseSSE2]
psrldq {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PSRLDri [UseSSE2]
psrld {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PSRLDrm [UseSSE2]
psrld {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PSRLDrr [UseSSE2]
psrld {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PSRLQri [UseSSE2]
psrlq {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PSRLQrm [UseSSE2]
psrlq {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PSRLQrr [UseSSE2]
psrlq {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PSRLWri [UseSSE2]
psrlw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PSRLWrm [UseSSE2]
psrlw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PSRLWrr [UseSSE2]
psrlw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PSUBBrm [UseSSE2]
psubb {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PSUBBrr [UseSSE2]
psubb {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PSUBDrm [UseSSE2]
psubd {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PSUBDrr [UseSSE2]
psubd {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PSUBQrm [UseSSE2]
psubq {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PSUBQrr [UseSSE2]
psubq {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PSUBSBrm [UseSSE2]
psubsb {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PSUBSBrr [UseSSE2]
psubsb {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PSUBSWrm [UseSSE2]
psubsw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PSUBSWrr [UseSSE2]
psubsw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PSUBUSBrm [UseSSE2]
psubusb {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PSUBUSBrr [UseSSE2]
psubusb {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PSUBUSWrm [UseSSE2]
psubusw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PSUBUSWrr [UseSSE2]
psubusw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PSUBWrm [UseSSE2]
psubw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PSUBWrr [UseSSE2]
psubw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PUNPCKHBWrm [UseSSE2]
punpckhbw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PUNPCKHBWrr [UseSSE2]
punpckhbw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PUNPCKHDQrm [UseSSE2]
punpckhdq {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PUNPCKHDQrr [UseSSE2]
punpckhdq {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PUNPCKHQDQrm [UseSSE2]
punpckhqdq {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PUNPCKHQDQrr [UseSSE2]
punpckhqdq {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PUNPCKHWDrm [UseSSE2]
punpckhwd {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PUNPCKHWDrr [UseSSE2]
punpckhwd {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PUNPCKLBWrm [UseSSE2]
punpcklbw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PUNPCKLBWrr [UseSSE2]
punpcklbw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PUNPCKLDQrm [UseSSE2]
punpckldq {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PUNPCKLDQrr [UseSSE2]
punpckldq {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PUNPCKLQDQrm [UseSSE2]
punpcklqdq {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PUNPCKLQDQrr [UseSSE2]
punpcklqdq {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PUNPCKLWDrm [UseSSE2]
punpcklwd {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PUNPCKLWDrr [UseSSE2]
punpcklwd {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PXORrm [UseSSE2]
pxor {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PXORrr [UseSSE2]
pxor {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
SHUFPDrmi [UseSSE2]
shufpd {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
SHUFPDrri [UseSSE2]
shufpd {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
SQRTPDm [UseSSE2]
sqrtpd {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
SQRTPDr [UseSSE2]
sqrtpd {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
SUBPDrm [UseSSE2]
subpd {src2, dst|dst, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
SUBPDrr [UseSSE2]
subpd {src2, dst|dst, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
SUBSDrm_Int [UseSSE2]
subsd {src2, dst|dst, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
SUBSDrr_Int [UseSSE2]
subsd {src2, dst|dst, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
UCOMISDrm [UseSSE2]
ucomisd {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
UCOMISDrr [UseSSE2]
ucomisd {src2, src1|src1, src2}
|
Note
|
Properties: mayRaiseFPException |
UNPCKHPDrm [UseSSE2]
unpckhpd {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
UNPCKHPDrr [UseSSE2]
unpckhpd {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
UNPCKLPDrm [UseSSE2]
unpcklpd {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
UNPCKLPDrr [UseSSE2]
unpcklpd {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
XORPDrm [UseSSE2]
xorpd {src2, dst|dst, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
XORPDrr [UseSSE2]
xorpd {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
GF2P8AFFINEINVQBrmi [UseSSE2, HasGFNI]
gf2p8affineinvqb {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
GF2P8AFFINEINVQBrri [UseSSE2, HasGFNI]
gf2p8affineinvqb {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
GF2P8AFFINEQBrmi [UseSSE2, HasGFNI]
gf2p8affineqb {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
GF2P8AFFINEQBrri [UseSSE2, HasGFNI]
gf2p8affineqb {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
GF2P8MULBrm [UseSSE2, HasGFNI]
gf2p8mulb {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
GF2P8MULBrr [UseSSE2, HasGFNI]
gf2p8mulb {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MOVSDrr [UseSSE2, NoSSE41_Or_OptForSize]
movsd {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
ADC16ri [NoNDD]
adc{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ADC16ri8 [NoNDD]
adc{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ADC16rm [NoNDD]
adc{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
ADC16rr [NoNDD]
adc{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ADC32ri [NoNDD]
adc{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ADC32ri8 [NoNDD]
adc{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ADC32rm [NoNDD]
adc{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
ADC32rr [NoNDD]
adc{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ADC64ri32 [NoNDD]
adc{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ADC64ri8 [NoNDD]
adc{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ADC64rm [NoNDD]
adc{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
ADC64rr [NoNDD]
adc{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ADC8ri [NoNDD]
adc{b} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ADC8rm [NoNDD]
adc{b} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
ADC8rr [NoNDD]
adc{b} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ADD16ri [NoNDD]
add{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ADD16ri8 [NoNDD]
add{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ADD16rm [NoNDD]
add{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
ADD16rr [NoNDD]
add{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ADD32ri [NoNDD]
add{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ADD32ri8 [NoNDD]
add{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ADD32rm [NoNDD]
add{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
ADD32rr [NoNDD]
add{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ADD64ri32 [NoNDD]
add{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ADD64ri8 [NoNDD]
add{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ADD64rm [NoNDD]
add{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
ADD64rr [NoNDD]
add{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ADD8ri [NoNDD]
add{b} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ADD8rm [NoNDD]
add{b} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
ADD8rr [NoNDD]
add{b} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
AND16ri [NoNDD]
and{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
AND16ri8 [NoNDD]
and{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
AND16rm [NoNDD]
and{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
AND16rr [NoNDD]
and{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
AND32ri [NoNDD]
and{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
AND32ri8 [NoNDD]
and{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
AND32rm [NoNDD]
and{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
AND32rr [NoNDD]
and{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
AND64ri32 [NoNDD]
and{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
AND64ri8 [NoNDD]
and{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
AND64rm [NoNDD]
and{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
AND64rr [NoNDD]
and{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
AND8ri [NoNDD]
and{b} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
AND8rm [NoNDD]
and{b} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
AND8rr [NoNDD]
and{b} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
DEC16r [NoNDD]
dec{w} src1
|
Note
|
Constraints: src1 = dst |
DEC32r [NoNDD]
dec{l} src1
|
Note
|
Constraints: src1 = dst |
DEC64r [NoNDD]
dec{q} src1
|
Note
|
Constraints: src1 = dst |
DEC8r [NoNDD]
dec{b} src1
|
Note
|
Constraints: src1 = dst |
IMUL16rm [NoNDD]
imul{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
IMUL16rr [NoNDD]
imul{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
IMUL32rm [NoNDD]
imul{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
IMUL32rr [NoNDD]
imul{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
IMUL64rm [NoNDD]
imul{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
IMUL64rr [NoNDD]
imul{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
INC16r [NoNDD]
inc{w} src1
|
Note
|
Constraints: src1 = dst |
INC32r [NoNDD]
inc{l} src1
|
Note
|
Constraints: src1 = dst |
INC64r [NoNDD]
inc{q} src1
|
Note
|
Constraints: src1 = dst |
INC8r [NoNDD]
inc{b} src1
|
Note
|
Constraints: src1 = dst |
NEG16r [NoNDD]
neg{w} src1
|
Note
|
Constraints: src1 = dst |
NEG32r [NoNDD]
neg{l} src1
|
Note
|
Constraints: src1 = dst |
NEG64r [NoNDD]
neg{q} src1
|
Note
|
Constraints: src1 = dst |
NEG8r [NoNDD]
neg{b} src1
|
Note
|
Constraints: src1 = dst |
NOT16r [NoNDD]
not{w} src1
|
Note
|
Constraints: src1 = dst |
NOT32r [NoNDD]
not{l} src1
|
Note
|
Constraints: src1 = dst |
NOT64r [NoNDD]
not{q} src1
|
Note
|
Constraints: src1 = dst |
NOT8r [NoNDD]
not{b} src1
|
Note
|
Constraints: src1 = dst |
OR16ri [NoNDD]
or{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
OR16ri8 [NoNDD]
or{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
OR16rm [NoNDD]
or{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
OR16rr [NoNDD]
or{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
OR32ri [NoNDD]
or{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
OR32ri8 [NoNDD]
or{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
OR32rm [NoNDD]
or{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
OR32rr [NoNDD]
or{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
OR64ri32 [NoNDD]
or{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
OR64ri8 [NoNDD]
or{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
OR64rm [NoNDD]
or{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
OR64rr [NoNDD]
or{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
OR8ri [NoNDD]
or{b} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
OR8rm [NoNDD]
or{b} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
OR8rr [NoNDD]
or{b} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
RCL16rCL [NoNDD]
rcl{w} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
RCL16ri [NoNDD]
rcl{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
RCL32rCL [NoNDD]
rcl{l} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
RCL32ri [NoNDD]
rcl{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
RCL64rCL [NoNDD]
rcl{q} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
RCL64ri [NoNDD]
rcl{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
RCL8rCL [NoNDD]
rcl{b} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
RCL8ri [NoNDD]
rcl{b} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
RCR16rCL [NoNDD]
rcr{w} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
RCR16ri [NoNDD]
rcr{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
RCR32rCL [NoNDD]
rcr{l} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
RCR32ri [NoNDD]
rcr{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
RCR64rCL [NoNDD]
rcr{q} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
RCR64ri [NoNDD]
rcr{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
RCR8rCL [NoNDD]
rcr{b} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
RCR8ri [NoNDD]
rcr{b} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ROL16rCL [NoNDD]
rol{w} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
ROL16ri [NoNDD]
rol{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ROL32rCL [NoNDD]
rol{l} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
ROL32ri [NoNDD]
rol{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ROL64rCL [NoNDD]
rol{q} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
ROL64ri [NoNDD]
rol{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ROL8rCL [NoNDD]
rol{b} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
ROL8ri [NoNDD]
rol{b} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ROR16rCL [NoNDD]
ror{w} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
ROR16ri [NoNDD]
ror{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ROR32rCL [NoNDD]
ror{l} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
ROR32ri [NoNDD]
ror{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ROR64rCL [NoNDD]
ror{q} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
ROR64ri [NoNDD]
ror{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ROR8rCL [NoNDD]
ror{b} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
ROR8ri [NoNDD]
ror{b} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
SAR16rCL [NoNDD]
sar{w} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
SAR16ri [NoNDD]
sar{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
SAR32rCL [NoNDD]
sar{l} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
SAR32ri [NoNDD]
sar{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
SAR64rCL [NoNDD]
sar{q} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
SAR64ri [NoNDD]
sar{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
SAR8rCL [NoNDD]
sar{b} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
SAR8ri [NoNDD]
sar{b} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
SBB16ri [NoNDD]
sbb{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
SBB16ri8 [NoNDD]
sbb{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
SBB16rm [NoNDD]
sbb{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
SBB16rr [NoNDD]
sbb{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
SBB32ri [NoNDD]
sbb{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
SBB32ri8 [NoNDD]
sbb{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
SBB32rm [NoNDD]
sbb{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
SBB32rr [NoNDD]
sbb{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
SBB64ri32 [NoNDD]
sbb{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
SBB64ri8 [NoNDD]
sbb{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
SBB64rm [NoNDD]
sbb{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
SBB64rr [NoNDD]
sbb{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
SBB8ri [NoNDD]
sbb{b} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
SBB8rm [NoNDD]
sbb{b} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
SBB8rr [NoNDD]
sbb{b} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
SHL16rCL [NoNDD]
shl{w} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
SHL16ri [NoNDD]
shl{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
SHL32rCL [NoNDD]
shl{l} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
SHL32ri [NoNDD]
shl{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
SHL64rCL [NoNDD]
shl{q} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
SHL64ri [NoNDD]
shl{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
SHL8rCL [NoNDD]
shl{b} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
SHL8ri [NoNDD]
shl{b} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
SHLD16rrCL [NoNDD]
shld{w} {%cl, src2, src1|src1, src2, cl}
|
Note
|
Constraints: src1 = dst |
SHLD16rri8 [NoNDD]
shld{w} {src3, src2, src1|src1, src2, src3}
|
Note
|
Constraints: src1 = dst |
SHLD32rrCL [NoNDD]
shld{l} {%cl, src2, src1|src1, src2, cl}
|
Note
|
Constraints: src1 = dst |
SHLD32rri8 [NoNDD]
shld{l} {src3, src2, src1|src1, src2, src3}
|
Note
|
Constraints: src1 = dst |
SHLD64rrCL [NoNDD]
shld{q} {%cl, src2, src1|src1, src2, cl}
|
Note
|
Constraints: src1 = dst |
SHLD64rri8 [NoNDD]
shld{q} {src3, src2, src1|src1, src2, src3}
|
Note
|
Constraints: src1 = dst |
SHR16rCL [NoNDD]
shr{w} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
SHR16ri [NoNDD]
shr{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
SHR32rCL [NoNDD]
shr{l} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
SHR32ri [NoNDD]
shr{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
SHR64rCL [NoNDD]
shr{q} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
SHR64ri [NoNDD]
shr{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
SHR8rCL [NoNDD]
shr{b} {%cl, src1|src1, cl}
|
Note
|
Constraints: src1 = dst |
SHR8ri [NoNDD]
shr{b} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
SHRD16rrCL [NoNDD]
shrd{w} {%cl, src2, src1|src1, src2, cl}
|
Note
|
Constraints: src1 = dst |
SHRD16rri8 [NoNDD]
shrd{w} {src3, src2, src1|src1, src2, src3}
|
Note
|
Constraints: src1 = dst |
SHRD32rrCL [NoNDD]
shrd{l} {%cl, src2, src1|src1, src2, cl}
|
Note
|
Constraints: src1 = dst |
SHRD32rri8 [NoNDD]
shrd{l} {src3, src2, src1|src1, src2, src3}
|
Note
|
Constraints: src1 = dst |
SHRD64rrCL [NoNDD]
shrd{q} {%cl, src2, src1|src1, src2, cl}
|
Note
|
Constraints: src1 = dst |
SHRD64rri8 [NoNDD]
shrd{q} {src3, src2, src1|src1, src2, src3}
|
Note
|
Constraints: src1 = dst |
SUB16ri [NoNDD]
sub{w} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare |
|
Note
|
Constraints: src1 = dst |
SUB16ri8 [NoNDD]
sub{w} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare |
|
Note
|
Constraints: src1 = dst |
SUB16rm [NoNDD]
sub{w} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare, mayLoad |
|
Note
|
Constraints: src1 = dst |
SUB16rr [NoNDD]
sub{w} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare |
|
Note
|
Constraints: src1 = dst |
SUB32ri [NoNDD]
sub{l} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare |
|
Note
|
Constraints: src1 = dst |
SUB32ri8 [NoNDD]
sub{l} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare |
|
Note
|
Constraints: src1 = dst |
SUB32rm [NoNDD]
sub{l} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare, mayLoad |
|
Note
|
Constraints: src1 = dst |
SUB32rr [NoNDD]
sub{l} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare |
|
Note
|
Constraints: src1 = dst |
SUB64ri32 [NoNDD]
sub{q} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare |
|
Note
|
Constraints: src1 = dst |
SUB64ri8 [NoNDD]
sub{q} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare |
|
Note
|
Constraints: src1 = dst |
SUB64rm [NoNDD]
sub{q} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare, mayLoad |
|
Note
|
Constraints: src1 = dst |
SUB64rr [NoNDD]
sub{q} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare |
|
Note
|
Constraints: src1 = dst |
SUB8ri [NoNDD]
sub{b} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare |
|
Note
|
Constraints: src1 = dst |
SUB8rm [NoNDD]
sub{b} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare, mayLoad |
|
Note
|
Constraints: src1 = dst |
SUB8rr [NoNDD]
sub{b} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare |
|
Note
|
Constraints: src1 = dst |
XOR16ri [NoNDD]
xor{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
XOR16ri8 [NoNDD]
xor{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
XOR16rm [NoNDD]
xor{w} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
XOR16rr [NoNDD]
xor{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
XOR32ri [NoNDD]
xor{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
XOR32ri8 [NoNDD]
xor{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
XOR32rm [NoNDD]
xor{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
XOR32rr [NoNDD]
xor{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
XOR64ri32 [NoNDD]
xor{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
XOR64ri8 [NoNDD]
xor{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
XOR64rm [NoNDD]
xor{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
XOR64rr [NoNDD]
xor{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
XOR8ri [NoNDD]
xor{b} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
XOR8rm [NoNDD]
xor{b} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
XOR8rr [NoNDD]
xor{b} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
VFMADD132SDm_Int [HasFMA, NoAVX512]
vfmadd132sd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132SDr_Int [HasFMA, NoAVX512]
vfmadd132sd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132SSm_Int [HasFMA, NoAVX512]
vfmadd132ss {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD132SSr_Int [HasFMA, NoAVX512]
vfmadd132ss {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213SDm_Int [HasFMA, NoAVX512]
vfmadd213sd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213SDr_Int [HasFMA, NoAVX512]
vfmadd213sd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213SSm_Int [HasFMA, NoAVX512]
vfmadd213ss {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD213SSr_Int [HasFMA, NoAVX512]
vfmadd213ss {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231SDm_Int [HasFMA, NoAVX512]
vfmadd231sd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231SDr_Int [HasFMA, NoAVX512]
vfmadd231sd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231SSm_Int [HasFMA, NoAVX512]
vfmadd231ss {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADD231SSr_Int [HasFMA, NoAVX512]
vfmadd231ss {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132SDm_Int [HasFMA, NoAVX512]
vfmsub132sd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132SDr_Int [HasFMA, NoAVX512]
vfmsub132sd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132SSm_Int [HasFMA, NoAVX512]
vfmsub132ss {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB132SSr_Int [HasFMA, NoAVX512]
vfmsub132ss {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213SDm_Int [HasFMA, NoAVX512]
vfmsub213sd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213SDr_Int [HasFMA, NoAVX512]
vfmsub213sd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213SSm_Int [HasFMA, NoAVX512]
vfmsub213ss {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB213SSr_Int [HasFMA, NoAVX512]
vfmsub213ss {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231SDm_Int [HasFMA, NoAVX512]
vfmsub231sd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231SDr_Int [HasFMA, NoAVX512]
vfmsub231sd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231SSm_Int [HasFMA, NoAVX512]
vfmsub231ss {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMSUB231SSr_Int [HasFMA, NoAVX512]
vfmsub231ss {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132SDm_Int [HasFMA, NoAVX512]
vfnmadd132sd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132SDr_Int [HasFMA, NoAVX512]
vfnmadd132sd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132SSm_Int [HasFMA, NoAVX512]
vfnmadd132ss {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD132SSr_Int [HasFMA, NoAVX512]
vfnmadd132ss {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213SDm_Int [HasFMA, NoAVX512]
vfnmadd213sd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213SDr_Int [HasFMA, NoAVX512]
vfnmadd213sd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213SSm_Int [HasFMA, NoAVX512]
vfnmadd213ss {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD213SSr_Int [HasFMA, NoAVX512]
vfnmadd213ss {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231SDm_Int [HasFMA, NoAVX512]
vfnmadd231sd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231SDr_Int [HasFMA, NoAVX512]
vfnmadd231sd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231SSm_Int [HasFMA, NoAVX512]
vfnmadd231ss {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMADD231SSr_Int [HasFMA, NoAVX512]
vfnmadd231ss {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132SDm_Int [HasFMA, NoAVX512]
vfnmsub132sd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132SDr_Int [HasFMA, NoAVX512]
vfnmsub132sd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132SSm_Int [HasFMA, NoAVX512]
vfnmsub132ss {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB132SSr_Int [HasFMA, NoAVX512]
vfnmsub132ss {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213SDm_Int [HasFMA, NoAVX512]
vfnmsub213sd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213SDr_Int [HasFMA, NoAVX512]
vfnmsub213sd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213SSm_Int [HasFMA, NoAVX512]
vfnmsub213ss {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB213SSr_Int [HasFMA, NoAVX512]
vfnmsub213ss {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231SDm_Int [HasFMA, NoAVX512]
vfnmsub231sd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231SDr_Int [HasFMA, NoAVX512]
vfnmsub231sd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231SSm_Int [HasFMA, NoAVX512]
vfnmsub231ss {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFNMSUB231SSr_Int [HasFMA, NoAVX512]
vfnmsub231ss {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
MMX_EMMS [HasMMX]
emms
MMX_MOVD64grr [HasMMX]
movd {src, dst|dst, src}
MMX_MOVD64mr [HasMMX]
movd {src, dst|dst, src}
|
Note
|
Properties: mayStore |
MMX_MOVD64rm [HasMMX]
movd {src, dst|dst, src}
MMX_MOVD64rr [HasMMX]
movd {src, dst|dst, src}
MMX_MOVQ64mr [HasMMX]
movq {src, dst|dst, src}
MMX_MOVQ64rm [HasMMX]
movq {src, dst|dst, src}
MMX_MOVQ64rr [HasMMX]
movq {src, dst|dst, src}
|
Note
|
Properties: isBitcast, isMoveReg |
MMX_PACKSSDWrm [HasMMX]
packssdw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PACKSSDWrr [HasMMX]
packssdw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PACKSSWBrm [HasMMX]
packsswb {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PACKSSWBrr [HasMMX]
packsswb {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PACKUSWBrm [HasMMX]
packuswb {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PACKUSWBrr [HasMMX]
packuswb {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PADDBrm [HasMMX]
paddb {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PADDBrr [HasMMX]
paddb {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PADDDrm [HasMMX]
paddd {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PADDDrr [HasMMX]
paddd {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PADDSBrm [HasMMX]
paddsb {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PADDSBrr [HasMMX]
paddsb {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PADDSWrm [HasMMX]
paddsw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PADDSWrr [HasMMX]
paddsw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PADDUSBrm [HasMMX]
paddusb {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PADDUSBrr [HasMMX]
paddusb {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PADDUSWrm [HasMMX]
paddusw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PADDUSWrr [HasMMX]
paddusw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PADDWrm [HasMMX]
paddw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PADDWrr [HasMMX]
paddw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PANDNrm [HasMMX]
pandn {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PANDNrr [HasMMX]
pandn {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PANDrm [HasMMX]
pand {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PANDrr [HasMMX]
pand {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PCMPEQBrm [HasMMX]
pcmpeqb {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PCMPEQBrr [HasMMX]
pcmpeqb {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PCMPEQDrm [HasMMX]
pcmpeqd {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PCMPEQDrr [HasMMX]
pcmpeqd {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PCMPEQWrm [HasMMX]
pcmpeqw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PCMPEQWrr [HasMMX]
pcmpeqw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PCMPGTBrm [HasMMX]
pcmpgtb {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PCMPGTBrr [HasMMX]
pcmpgtb {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PCMPGTDrm [HasMMX]
pcmpgtd {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PCMPGTDrr [HasMMX]
pcmpgtd {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PCMPGTWrm [HasMMX]
pcmpgtw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PCMPGTWrr [HasMMX]
pcmpgtw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PMADDWDrm [HasMMX]
pmaddwd {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PMADDWDrr [HasMMX]
pmaddwd {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PMULHWrm [HasMMX]
pmulhw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PMULHWrr [HasMMX]
pmulhw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PMULLWrm [HasMMX]
pmullw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PMULLWrr [HasMMX]
pmullw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PORrm [HasMMX]
por {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PORrr [HasMMX]
por {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PSLLDri [HasMMX]
pslld {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PSLLDrm [HasMMX]
pslld {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PSLLDrr [HasMMX]
pslld {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PSLLQri [HasMMX]
psllq {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PSLLQrm [HasMMX]
psllq {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PSLLQrr [HasMMX]
psllq {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PSLLWri [HasMMX]
psllw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PSLLWrm [HasMMX]
psllw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PSLLWrr [HasMMX]
psllw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PSRADri [HasMMX]
psrad {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PSRADrm [HasMMX]
psrad {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PSRADrr [HasMMX]
psrad {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PSRAWri [HasMMX]
psraw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PSRAWrm [HasMMX]
psraw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PSRAWrr [HasMMX]
psraw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PSRLDri [HasMMX]
psrld {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PSRLDrm [HasMMX]
psrld {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PSRLDrr [HasMMX]
psrld {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PSRLQri [HasMMX]
psrlq {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PSRLQrm [HasMMX]
psrlq {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PSRLQrr [HasMMX]
psrlq {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PSRLWri [HasMMX]
psrlw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PSRLWrm [HasMMX]
psrlw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PSRLWrr [HasMMX]
psrlw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PSUBBrm [HasMMX]
psubb {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PSUBBrr [HasMMX]
psubb {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PSUBDrm [HasMMX]
psubd {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PSUBDrr [HasMMX]
psubd {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PSUBSBrm [HasMMX]
psubsb {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PSUBSBrr [HasMMX]
psubsb {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PSUBSWrm [HasMMX]
psubsw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PSUBSWrr [HasMMX]
psubsw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PSUBUSBrm [HasMMX]
psubusb {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PSUBUSBrr [HasMMX]
psubusb {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PSUBUSWrm [HasMMX]
psubusw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PSUBUSWrr [HasMMX]
psubusw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PSUBWrm [HasMMX]
psubw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PSUBWrr [HasMMX]
psubw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PUNPCKHBWrm [HasMMX]
punpckhbw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PUNPCKHBWrr [HasMMX]
punpckhbw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PUNPCKHDQrm [HasMMX]
punpckhdq {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PUNPCKHDQrr [HasMMX]
punpckhdq {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PUNPCKHWDrm [HasMMX]
punpckhwd {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PUNPCKHWDrr [HasMMX]
punpckhwd {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PUNPCKLBWrm [HasMMX]
punpcklbw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PUNPCKLBWrr [HasMMX]
punpcklbw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PUNPCKLDQrm [HasMMX]
punpckldq {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PUNPCKLDQrr [HasMMX]
punpckldq {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PUNPCKLWDrm [HasMMX]
punpcklwd {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PUNPCKLWDrr [HasMMX]
punpcklwd {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PXORrm [HasMMX]
pxor {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PXORrr [HasMMX]
pxor {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_MASKMOVQ [HasMMX, Not64BitMode, HasSSE1]
maskmovq {mask, src|src, mask}
MMX_CVTPI2PSrm [HasMMX, HasSSE1]
cvtpi2ps {src2, dst|dst, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
MMX_CVTPI2PSrr [HasMMX, HasSSE1]
cvtpi2ps {src2, dst|dst, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
MMX_CVTPS2PIrm [HasMMX, HasSSE1]
cvtps2pi {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
MMX_CVTPS2PIrr [HasMMX, HasSSE1]
cvtps2pi {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
MMX_CVTTPS2PIrm [HasMMX, HasSSE1]
cvttps2pi {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
MMX_CVTTPS2PIrr [HasMMX, HasSSE1]
cvttps2pi {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
MMX_MOVNTQmr [HasMMX, HasSSE1]
movntq {src, dst|dst, src}
MMX_PABSBrm [HasMMX, HasSSSE3]
pabsb {src, dst|dst, src}
MMX_PABSBrr [HasMMX, HasSSSE3]
pabsb {src, dst|dst, src}
MMX_PABSDrm [HasMMX, HasSSSE3]
pabsd {src, dst|dst, src}
MMX_PABSDrr [HasMMX, HasSSSE3]
pabsd {src, dst|dst, src}
MMX_PABSWrm [HasMMX, HasSSSE3]
pabsw {src, dst|dst, src}
MMX_PABSWrr [HasMMX, HasSSSE3]
pabsw {src, dst|dst, src}
MMX_PALIGNRrmi [HasMMX, HasSSSE3]
palignr {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
MMX_PALIGNRrri [HasMMX, HasSSSE3]
palignr {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
MMX_PAVGBrm [HasMMX, HasSSE1]
pavgb {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PAVGBrr [HasMMX, HasSSE1]
pavgb {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PAVGWrm [HasMMX, HasSSE1]
pavgw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PAVGWrr [HasMMX, HasSSE1]
pavgw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PEXTRWrri [HasMMX, HasSSE1]
pextrw {src2, src1, dst|dst, src1, src2}
MMX_PHADDDrm [HasMMX, HasSSSE3]
phaddd {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PHADDDrr [HasMMX, HasSSSE3]
phaddd {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PHADDSWrm [HasMMX, HasSSSE3]
phaddsw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PHADDSWrr [HasMMX, HasSSSE3]
phaddsw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PHADDWrm [HasMMX, HasSSSE3]
phaddw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PHADDWrr [HasMMX, HasSSSE3]
phaddw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PHSUBDrm [HasMMX, HasSSSE3]
phsubd {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PHSUBDrr [HasMMX, HasSSSE3]
phsubd {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PHSUBSWrm [HasMMX, HasSSSE3]
phsubsw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PHSUBSWrr [HasMMX, HasSSSE3]
phsubsw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PHSUBWrm [HasMMX, HasSSSE3]
phsubw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PHSUBWrr [HasMMX, HasSSSE3]
phsubw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PINSRWrmi [HasMMX, HasSSE1]
pinsrw {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
MMX_PINSRWrri [HasMMX, HasSSE1]
pinsrw {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
MMX_PMADDUBSWrm [HasMMX, HasSSSE3]
pmaddubsw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PMADDUBSWrr [HasMMX, HasSSSE3]
pmaddubsw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PMAXSWrm [HasMMX, HasSSE1]
pmaxsw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PMAXSWrr [HasMMX, HasSSE1]
pmaxsw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PMAXUBrm [HasMMX, HasSSE1]
pmaxub {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PMAXUBrr [HasMMX, HasSSE1]
pmaxub {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PMINSWrm [HasMMX, HasSSE1]
pminsw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PMINSWrr [HasMMX, HasSSE1]
pminsw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PMINUBrm [HasMMX, HasSSE1]
pminub {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PMINUBrr [HasMMX, HasSSE1]
pminub {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PMOVMSKBrr [HasMMX, HasSSE1]
pmovmskb {src, dst|dst, src}
MMX_PMULHRSWrm [HasMMX, HasSSSE3]
pmulhrsw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PMULHRSWrr [HasMMX, HasSSSE3]
pmulhrsw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PMULHUWrm [HasMMX, HasSSE1]
pmulhuw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PMULHUWrr [HasMMX, HasSSE1]
pmulhuw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PSADBWrm [HasMMX, HasSSE1]
psadbw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PSADBWrr [HasMMX, HasSSE1]
psadbw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PSHUFBrm [HasMMX, HasSSSE3]
pshufb {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PSHUFBrr [HasMMX, HasSSSE3]
pshufb {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PSHUFWmi [HasMMX, HasSSE1]
pshufw {src2, src1, dst|dst, src1, src2}
MMX_PSHUFWri [HasMMX, HasSSE1]
pshufw {src2, src1, dst|dst, src1, src2}
MMX_PSIGNBrm [HasMMX, HasSSSE3]
psignb {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PSIGNBrr [HasMMX, HasSSSE3]
psignb {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PSIGNDrm [HasMMX, HasSSSE3]
psignd {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PSIGNDrr [HasMMX, HasSSSE3]
psignd {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PSIGNWrm [HasMMX, HasSSSE3]
psignw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PSIGNWrr [HasMMX, HasSSSE3]
psignw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_CVTPD2PIrm [HasMMX, HasSSE2]
cvtpd2pi {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
MMX_CVTPD2PIrr [HasMMX, HasSSE2]
cvtpd2pi {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
MMX_CVTPI2PDrm [HasMMX, HasSSE2]
cvtpi2pd {src, dst|dst, src}
MMX_CVTPI2PDrr [HasMMX, HasSSE2]
cvtpi2pd {src, dst|dst, src}
MMX_CVTTPD2PIrm [HasMMX, HasSSE2]
cvttpd2pi {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
MMX_CVTTPD2PIrr [HasMMX, HasSSE2]
cvttpd2pi {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
MMX_MOVDQ2Qrr [HasMMX, HasSSE2]
movdq2q {src, dst|dst, src}
MMX_MOVQ2DQrr [HasMMX, HasSSE2]
movq2dq {src, dst|dst, src}
MMX_PADDQrm [HasMMX, HasSSE2]
paddq {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PADDQrr [HasMMX, HasSSE2]
paddq {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PMULUDQrm [HasMMX, HasSSE2]
pmuludq {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PMULUDQrr [HasMMX, HasSSE2]
pmuludq {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PSUBQrm [HasMMX, HasSSE2]
psubq {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MMX_PSUBQrr [HasMMX, HasSSE2]
psubq {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
VFRCZPDYrm [HasXOP]
vfrczpd {src, dst|dst, src}
VFRCZPDYrr [HasXOP]
vfrczpd {src, dst|dst, src}
VFRCZPDrm [HasXOP]
vfrczpd {src, dst|dst, src}
VFRCZPDrr [HasXOP]
vfrczpd {src, dst|dst, src}
VFRCZPSYrm [HasXOP]
vfrczps {src, dst|dst, src}
VFRCZPSYrr [HasXOP]
vfrczps {src, dst|dst, src}
VFRCZPSrm [HasXOP]
vfrczps {src, dst|dst, src}
VFRCZPSrr [HasXOP]
vfrczps {src, dst|dst, src}
VFRCZSDrm [HasXOP]
vfrczsd {src, dst|dst, src}
VFRCZSDrr [HasXOP]
vfrczsd {src, dst|dst, src}
VFRCZSSrm [HasXOP]
vfrczss {src, dst|dst, src}
VFRCZSSrr [HasXOP]
vfrczss {src, dst|dst, src}
VPCMOVYrmr [HasXOP]
vpcmov {src3, src2, src1, dst|dst, src1, src2, src3}
VPCMOVYrrm [HasXOP]
vpcmov {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayLoad |
VPCMOVYrrr [HasXOP]
vpcmov {src3, src2, src1, dst|dst, src1, src2, src3}
VPCMOVrmr [HasXOP]
vpcmov {src3, src2, src1, dst|dst, src1, src2, src3}
VPCMOVrrm [HasXOP]
vpcmov {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayLoad |
VPCMOVrrr [HasXOP]
vpcmov {src3, src2, src1, dst|dst, src1, src2, src3}
VPCOMBmi [HasXOP]
vpcomb {cc, src2, src1, dst|dst, src1, src2, cc}
VPCOMBri [HasXOP]
vpcomb {cc, src2, src1, dst|dst, src1, src2, cc}
VPCOMDmi [HasXOP]
vpcomd {cc, src2, src1, dst|dst, src1, src2, cc}
VPCOMDri [HasXOP]
vpcomd {cc, src2, src1, dst|dst, src1, src2, cc}
VPCOMQmi [HasXOP]
vpcomq {cc, src2, src1, dst|dst, src1, src2, cc}
VPCOMQri [HasXOP]
vpcomq {cc, src2, src1, dst|dst, src1, src2, cc}
VPCOMUBmi [HasXOP]
vpcomub {cc, src2, src1, dst|dst, src1, src2, cc}
VPCOMUBri [HasXOP]
vpcomub {cc, src2, src1, dst|dst, src1, src2, cc}
VPCOMUDmi [HasXOP]
vpcomud {cc, src2, src1, dst|dst, src1, src2, cc}
VPCOMUDri [HasXOP]
vpcomud {cc, src2, src1, dst|dst, src1, src2, cc}
VPCOMUQmi [HasXOP]
vpcomuq {cc, src2, src1, dst|dst, src1, src2, cc}
VPCOMUQri [HasXOP]
vpcomuq {cc, src2, src1, dst|dst, src1, src2, cc}
VPCOMUWmi [HasXOP]
vpcomuw {cc, src2, src1, dst|dst, src1, src2, cc}
VPCOMUWri [HasXOP]
vpcomuw {cc, src2, src1, dst|dst, src1, src2, cc}
VPCOMWmi [HasXOP]
vpcomw {cc, src2, src1, dst|dst, src1, src2, cc}
VPCOMWri [HasXOP]
vpcomw {cc, src2, src1, dst|dst, src1, src2, cc}
VPERMIL2PDYmr [HasXOP]
vpermil2pd {src4, src3, src2, src1, dst|dst, src1, src2, src3, src4}
VPERMIL2PDYrm [HasXOP]
vpermil2pd {src4, src3, src2, src1, dst|dst, src1, src2, src3, src4}
VPERMIL2PDYrr [HasXOP]
vpermil2pd {src4, src3, src2, src1, dst|dst, src1, src2, src3, src4}
VPERMIL2PDmr [HasXOP]
vpermil2pd {src4, src3, src2, src1, dst|dst, src1, src2, src3, src4}
VPERMIL2PDrm [HasXOP]
vpermil2pd {src4, src3, src2, src1, dst|dst, src1, src2, src3, src4}
VPERMIL2PDrr [HasXOP]
vpermil2pd {src4, src3, src2, src1, dst|dst, src1, src2, src3, src4}
VPERMIL2PSYmr [HasXOP]
vpermil2ps {src4, src3, src2, src1, dst|dst, src1, src2, src3, src4}
VPERMIL2PSYrm [HasXOP]
vpermil2ps {src4, src3, src2, src1, dst|dst, src1, src2, src3, src4}
VPERMIL2PSYrr [HasXOP]
vpermil2ps {src4, src3, src2, src1, dst|dst, src1, src2, src3, src4}
VPERMIL2PSmr [HasXOP]
vpermil2ps {src4, src3, src2, src1, dst|dst, src1, src2, src3, src4}
VPERMIL2PSrm [HasXOP]
vpermil2ps {src4, src3, src2, src1, dst|dst, src1, src2, src3, src4}
VPERMIL2PSrr [HasXOP]
vpermil2ps {src4, src3, src2, src1, dst|dst, src1, src2, src3, src4}
VPHADDBDrm [HasXOP]
vphaddbd {src, dst|dst, src}
VPHADDBDrr [HasXOP]
vphaddbd {src, dst|dst, src}
VPHADDBQrm [HasXOP]
vphaddbq {src, dst|dst, src}
VPHADDBQrr [HasXOP]
vphaddbq {src, dst|dst, src}
VPHADDBWrm [HasXOP]
vphaddbw {src, dst|dst, src}
VPHADDBWrr [HasXOP]
vphaddbw {src, dst|dst, src}
VPHADDDQrm [HasXOP]
vphadddq {src, dst|dst, src}
VPHADDDQrr [HasXOP]
vphadddq {src, dst|dst, src}
VPHADDUBDrm [HasXOP]
vphaddubd {src, dst|dst, src}
VPHADDUBDrr [HasXOP]
vphaddubd {src, dst|dst, src}
VPHADDUBQrm [HasXOP]
vphaddubq {src, dst|dst, src}
VPHADDUBQrr [HasXOP]
vphaddubq {src, dst|dst, src}
VPHADDUBWrm [HasXOP]
vphaddubw {src, dst|dst, src}
VPHADDUBWrr [HasXOP]
vphaddubw {src, dst|dst, src}
VPHADDUDQrm [HasXOP]
vphaddudq {src, dst|dst, src}
VPHADDUDQrr [HasXOP]
vphaddudq {src, dst|dst, src}
VPHADDUWDrm [HasXOP]
vphadduwd {src, dst|dst, src}
VPHADDUWDrr [HasXOP]
vphadduwd {src, dst|dst, src}
VPHADDUWQrm [HasXOP]
vphadduwq {src, dst|dst, src}
VPHADDUWQrr [HasXOP]
vphadduwq {src, dst|dst, src}
VPHADDWDrm [HasXOP]
vphaddwd {src, dst|dst, src}
VPHADDWDrr [HasXOP]
vphaddwd {src, dst|dst, src}
VPHADDWQrm [HasXOP]
vphaddwq {src, dst|dst, src}
VPHADDWQrr [HasXOP]
vphaddwq {src, dst|dst, src}
VPHSUBBWrm [HasXOP]
vphsubbw {src, dst|dst, src}
VPHSUBBWrr [HasXOP]
vphsubbw {src, dst|dst, src}
VPHSUBDQrm [HasXOP]
vphsubdq {src, dst|dst, src}
VPHSUBDQrr [HasXOP]
vphsubdq {src, dst|dst, src}
VPHSUBWDrm [HasXOP]
vphsubwd {src, dst|dst, src}
VPHSUBWDrr [HasXOP]
vphsubwd {src, dst|dst, src}
VPMACSDDrm [HasXOP]
vpmacsdd {src3, src2, src1, dst|dst, src1, src2, src3}
VPMACSDDrr [HasXOP]
vpmacsdd {src3, src2, src1, dst|dst, src1, src2, src3}
VPMACSDQHrm [HasXOP]
vpmacsdqh {src3, src2, src1, dst|dst, src1, src2, src3}
VPMACSDQHrr [HasXOP]
vpmacsdqh {src3, src2, src1, dst|dst, src1, src2, src3}
VPMACSDQLrm [HasXOP]
vpmacsdql {src3, src2, src1, dst|dst, src1, src2, src3}
VPMACSDQLrr [HasXOP]
vpmacsdql {src3, src2, src1, dst|dst, src1, src2, src3}
VPMACSSDDrm [HasXOP]
vpmacssdd {src3, src2, src1, dst|dst, src1, src2, src3}
VPMACSSDDrr [HasXOP]
vpmacssdd {src3, src2, src1, dst|dst, src1, src2, src3}
VPMACSSDQHrm [HasXOP]
vpmacssdqh {src3, src2, src1, dst|dst, src1, src2, src3}
VPMACSSDQHrr [HasXOP]
vpmacssdqh {src3, src2, src1, dst|dst, src1, src2, src3}
VPMACSSDQLrm [HasXOP]
vpmacssdql {src3, src2, src1, dst|dst, src1, src2, src3}
VPMACSSDQLrr [HasXOP]
vpmacssdql {src3, src2, src1, dst|dst, src1, src2, src3}
VPMACSSWDrm [HasXOP]
vpmacsswd {src3, src2, src1, dst|dst, src1, src2, src3}
VPMACSSWDrr [HasXOP]
vpmacsswd {src3, src2, src1, dst|dst, src1, src2, src3}
VPMACSSWWrm [HasXOP]
vpmacssww {src3, src2, src1, dst|dst, src1, src2, src3}
VPMACSSWWrr [HasXOP]
vpmacssww {src3, src2, src1, dst|dst, src1, src2, src3}
VPMACSWDrm [HasXOP]
vpmacswd {src3, src2, src1, dst|dst, src1, src2, src3}
VPMACSWDrr [HasXOP]
vpmacswd {src3, src2, src1, dst|dst, src1, src2, src3}
VPMACSWWrm [HasXOP]
vpmacsww {src3, src2, src1, dst|dst, src1, src2, src3}
VPMACSWWrr [HasXOP]
vpmacsww {src3, src2, src1, dst|dst, src1, src2, src3}
VPMADCSSWDrm [HasXOP]
vpmadcsswd {src3, src2, src1, dst|dst, src1, src2, src3}
VPMADCSSWDrr [HasXOP]
vpmadcsswd {src3, src2, src1, dst|dst, src1, src2, src3}
VPMADCSWDrm [HasXOP]
vpmadcswd {src3, src2, src1, dst|dst, src1, src2, src3}
VPMADCSWDrr [HasXOP]
vpmadcswd {src3, src2, src1, dst|dst, src1, src2, src3}
VPPERMrmr [HasXOP]
vpperm {src3, src2, src1, dst|dst, src1, src2, src3}
VPPERMrrm [HasXOP]
vpperm {src3, src2, src1, dst|dst, src1, src2, src3}
VPPERMrrr [HasXOP]
vpperm {src3, src2, src1, dst|dst, src1, src2, src3}
VPROTBmi [HasXOP]
vprotb {src2, src1, dst|dst, src1, src2}
VPROTBmr [HasXOP]
vprotb {src2, src1, dst|dst, src1, src2}
VPROTBri [HasXOP]
vprotb {src2, src1, dst|dst, src1, src2}
VPROTBrm [HasXOP]
vprotb {src2, src1, dst|dst, src1, src2}
VPROTBrr [HasXOP]
vprotb {src2, src1, dst|dst, src1, src2}
VPROTDmi [HasXOP]
vprotd {src2, src1, dst|dst, src1, src2}
VPROTDmr [HasXOP]
vprotd {src2, src1, dst|dst, src1, src2}
VPROTDri [HasXOP]
vprotd {src2, src1, dst|dst, src1, src2}
VPROTDrm [HasXOP]
vprotd {src2, src1, dst|dst, src1, src2}
VPROTDrr [HasXOP]
vprotd {src2, src1, dst|dst, src1, src2}
VPROTQmi [HasXOP]
vprotq {src2, src1, dst|dst, src1, src2}
VPROTQmr [HasXOP]
vprotq {src2, src1, dst|dst, src1, src2}
VPROTQri [HasXOP]
vprotq {src2, src1, dst|dst, src1, src2}
VPROTQrm [HasXOP]
vprotq {src2, src1, dst|dst, src1, src2}
VPROTQrr [HasXOP]
vprotq {src2, src1, dst|dst, src1, src2}
VPROTWmi [HasXOP]
vprotw {src2, src1, dst|dst, src1, src2}
VPROTWmr [HasXOP]
vprotw {src2, src1, dst|dst, src1, src2}
VPROTWri [HasXOP]
vprotw {src2, src1, dst|dst, src1, src2}
VPROTWrm [HasXOP]
vprotw {src2, src1, dst|dst, src1, src2}
VPROTWrr [HasXOP]
vprotw {src2, src1, dst|dst, src1, src2}
VPSHABmr [HasXOP]
vpshab {src2, src1, dst|dst, src1, src2}
VPSHABrm [HasXOP]
vpshab {src2, src1, dst|dst, src1, src2}
VPSHABrr [HasXOP]
vpshab {src2, src1, dst|dst, src1, src2}
VPSHADmr [HasXOP]
vpshad {src2, src1, dst|dst, src1, src2}
VPSHADrm [HasXOP]
vpshad {src2, src1, dst|dst, src1, src2}
VPSHADrr [HasXOP]
vpshad {src2, src1, dst|dst, src1, src2}
VPSHAQmr [HasXOP]
vpshaq {src2, src1, dst|dst, src1, src2}
VPSHAQrm [HasXOP]
vpshaq {src2, src1, dst|dst, src1, src2}
VPSHAQrr [HasXOP]
vpshaq {src2, src1, dst|dst, src1, src2}
VPSHAWmr [HasXOP]
vpshaw {src2, src1, dst|dst, src1, src2}
VPSHAWrm [HasXOP]
vpshaw {src2, src1, dst|dst, src1, src2}
VPSHAWrr [HasXOP]
vpshaw {src2, src1, dst|dst, src1, src2}
VPSHLBmr [HasXOP]
vpshlb {src2, src1, dst|dst, src1, src2}
VPSHLBrm [HasXOP]
vpshlb {src2, src1, dst|dst, src1, src2}
VPSHLBrr [HasXOP]
vpshlb {src2, src1, dst|dst, src1, src2}
VPSHLDmr [HasXOP]
vpshld {src2, src1, dst|dst, src1, src2}
VPSHLDrm [HasXOP]
vpshld {src2, src1, dst|dst, src1, src2}
VPSHLDrr [HasXOP]
vpshld {src2, src1, dst|dst, src1, src2}
VPSHLQmr [HasXOP]
vpshlq {src2, src1, dst|dst, src1, src2}
VPSHLQrm [HasXOP]
vpshlq {src2, src1, dst|dst, src1, src2}
VPSHLQrr [HasXOP]
vpshlq {src2, src1, dst|dst, src1, src2}
VPSHLWmr [HasXOP]
vpshlw {src2, src1, dst|dst, src1, src2}
VPSHLWrm [HasXOP]
vpshlw {src2, src1, dst|dst, src1, src2}
VPSHLWrr [HasXOP]
vpshlw {src2, src1, dst|dst, src1, src2}
PDEP32rm_EVEX [HasEGPR, HasBMI2]
pdep{l} {src2, src1, dst|dst, src1, src2}
PDEP32rr_EVEX [HasEGPR, HasBMI2]
pdep{l} {src2, src1, dst|dst, src1, src2}
PDEP64rm_EVEX [HasEGPR, HasBMI2]
pdep{q} {src2, src1, dst|dst, src1, src2}
PDEP64rr_EVEX [HasEGPR, HasBMI2]
pdep{q} {src2, src1, dst|dst, src1, src2}
PEXT32rm_EVEX [HasEGPR, HasBMI2]
pext{l} {src2, src1, dst|dst, src1, src2}
PEXT32rr_EVEX [HasEGPR, HasBMI2]
pext{l} {src2, src1, dst|dst, src1, src2}
PEXT64rm_EVEX [HasEGPR, HasBMI2]
pext{q} {src2, src1, dst|dst, src1, src2}
PEXT64rr_EVEX [HasEGPR, HasBMI2]
pext{q} {src2, src1, dst|dst, src1, src2}
VPBROADCASTMB2QZrr [HasCDI]
vpbroadcastmb2q {src, dst|dst, src}
VPBROADCASTMW2DZrr [HasCDI]
vpbroadcastmw2d {src, dst|dst, src}
VPCONFLICTDZrm [HasCDI]
vpconflictd {src1, dst|dst, src1}
VPCONFLICTDZrmb [HasCDI]
vpconflictd {src1{1to16}, dst|dst, src1{1to16}}
VPCONFLICTDZrmbk [HasCDI]
vpconflictd {src1{1to16}, dst {mask}|dst {mask}, src1{1to16}}
|
Note
|
Constraints: src0 = dst |
VPCONFLICTDZrmbkz [HasCDI]
vpconflictd {src1{1to16}, dst {mask} {z}|dst {mask} {z}, src1{1to16}}
VPCONFLICTDZrmk [HasCDI]
vpconflictd {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPCONFLICTDZrmkz [HasCDI]
vpconflictd {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPCONFLICTDZrr [HasCDI]
vpconflictd {src1, dst|dst, src1}
VPCONFLICTDZrrk [HasCDI]
vpconflictd {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPCONFLICTDZrrkz [HasCDI]
vpconflictd {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPCONFLICTQZrm [HasCDI]
vpconflictq {src1, dst|dst, src1}
VPCONFLICTQZrmb [HasCDI]
vpconflictq {src1{1to8}, dst|dst, src1{1to8}}
VPCONFLICTQZrmbk [HasCDI]
vpconflictq {src1{1to8}, dst {mask}|dst {mask}, src1{1to8}}
|
Note
|
Constraints: src0 = dst |
VPCONFLICTQZrmbkz [HasCDI]
vpconflictq {src1{1to8}, dst {mask} {z}|dst {mask} {z}, src1{1to8}}
VPCONFLICTQZrmk [HasCDI]
vpconflictq {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPCONFLICTQZrmkz [HasCDI]
vpconflictq {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPCONFLICTQZrr [HasCDI]
vpconflictq {src1, dst|dst, src1}
VPCONFLICTQZrrk [HasCDI]
vpconflictq {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPCONFLICTQZrrkz [HasCDI]
vpconflictq {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPLZCNTDZrm [HasCDI]
vplzcntd {src1, dst|dst, src1}
VPLZCNTDZrmb [HasCDI]
vplzcntd {src1{1to16}, dst|dst, src1{1to16}}
VPLZCNTDZrmbk [HasCDI]
vplzcntd {src1{1to16}, dst {mask}|dst {mask}, src1{1to16}}
|
Note
|
Constraints: src0 = dst |
VPLZCNTDZrmbkz [HasCDI]
vplzcntd {src1{1to16}, dst {mask} {z}|dst {mask} {z}, src1{1to16}}
VPLZCNTDZrmk [HasCDI]
vplzcntd {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPLZCNTDZrmkz [HasCDI]
vplzcntd {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPLZCNTDZrr [HasCDI]
vplzcntd {src1, dst|dst, src1}
VPLZCNTDZrrk [HasCDI]
vplzcntd {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPLZCNTDZrrkz [HasCDI]
vplzcntd {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPLZCNTQZrm [HasCDI]
vplzcntq {src1, dst|dst, src1}
VPLZCNTQZrmb [HasCDI]
vplzcntq {src1{1to8}, dst|dst, src1{1to8}}
VPLZCNTQZrmbk [HasCDI]
vplzcntq {src1{1to8}, dst {mask}|dst {mask}, src1{1to8}}
|
Note
|
Constraints: src0 = dst |
VPLZCNTQZrmbkz [HasCDI]
vplzcntq {src1{1to8}, dst {mask} {z}|dst {mask} {z}, src1{1to8}}
VPLZCNTQZrmk [HasCDI]
vplzcntq {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPLZCNTQZrmkz [HasCDI]
vplzcntq {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPLZCNTQZrr [HasCDI]
vplzcntq {src1, dst|dst, src1}
VPLZCNTQZrrk [HasCDI]
vplzcntq {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPLZCNTQZrrkz [HasCDI]
vplzcntq {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPDPBUSDSZm [HasVNNI]
vpdpbusds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUSDSZmb [HasVNNI]
vpdpbusds {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VPDPBUSDSZmbk [HasVNNI]
vpdpbusds {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VPDPBUSDSZmbkz [HasVNNI]
vpdpbusds {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VPDPBUSDSZmk [HasVNNI]
vpdpbusds {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUSDSZmkz [HasVNNI]
vpdpbusds {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUSDSZr [HasVNNI]
vpdpbusds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUSDSZrk [HasVNNI]
vpdpbusds {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUSDSZrkz [HasVNNI]
vpdpbusds {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUSDZm [HasVNNI]
vpdpbusd {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUSDZmb [HasVNNI]
vpdpbusd {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VPDPBUSDZmbk [HasVNNI]
vpdpbusd {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VPDPBUSDZmbkz [HasVNNI]
vpdpbusd {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VPDPBUSDZmk [HasVNNI]
vpdpbusd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUSDZmkz [HasVNNI]
vpdpbusd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUSDZr [HasVNNI]
vpdpbusd {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUSDZrk [HasVNNI]
vpdpbusd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUSDZrkz [HasVNNI]
vpdpbusd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSSDSZm [HasVNNI]
vpdpwssds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSSDSZmb [HasVNNI]
vpdpwssds {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VPDPWSSDSZmbk [HasVNNI]
vpdpwssds {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VPDPWSSDSZmbkz [HasVNNI]
vpdpwssds {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VPDPWSSDSZmk [HasVNNI]
vpdpwssds {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSSDSZmkz [HasVNNI]
vpdpwssds {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSSDSZr [HasVNNI]
vpdpwssds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSSDSZrk [HasVNNI]
vpdpwssds {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSSDSZrkz [HasVNNI]
vpdpwssds {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSSDZm [HasVNNI]
vpdpwssd {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSSDZmb [HasVNNI]
vpdpwssd {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VPDPWSSDZmbk [HasVNNI]
vpdpwssd {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VPDPWSSDZmbkz [HasVNNI]
vpdpwssd {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Constraints: src1 = dst |
VPDPWSSDZmk [HasVNNI]
vpdpwssd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSSDZmkz [HasVNNI]
vpdpwssd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSSDZr [HasVNNI]
vpdpwssd {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSSDZrk [HasVNNI]
vpdpwssd {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSSDZrkz [HasVNNI]
vpdpwssd {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
WRSSD [NoEGPR]
wrssd {src, dst|dst, src}
WRSSQ [NoEGPR]
wrssq {src, dst|dst, src}
WRUSSD [NoEGPR]
wrussd {src, dst|dst, src}
WRUSSQ [NoEGPR]
wrussq {src, dst|dst, src}
BZHI32rm [NoEGPR, HasBMI2]
bzhi{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
BZHI32rr [NoEGPR, HasBMI2]
bzhi{l} {src2, src1, dst|dst, src1, src2}
BZHI64rm [NoEGPR, HasBMI2]
bzhi{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
BZHI64rr [NoEGPR, HasBMI2]
bzhi{q} {src2, src1, dst|dst, src1, src2}
PDEP32rm [NoEGPR, HasBMI2]
pdep{l} {src2, src1, dst|dst, src1, src2}
PDEP32rr [NoEGPR, HasBMI2]
pdep{l} {src2, src1, dst|dst, src1, src2}
PDEP64rm [NoEGPR, HasBMI2]
pdep{q} {src2, src1, dst|dst, src1, src2}
PDEP64rr [NoEGPR, HasBMI2]
pdep{q} {src2, src1, dst|dst, src1, src2}
PEXT32rm [NoEGPR, HasBMI2]
pext{l} {src2, src1, dst|dst, src1, src2}
PEXT32rr [NoEGPR, HasBMI2]
pext{l} {src2, src1, dst|dst, src1, src2}
PEXT64rm [NoEGPR, HasBMI2]
pext{q} {src2, src1, dst|dst, src1, src2}
PEXT64rr [NoEGPR, HasBMI2]
pext{q} {src2, src1, dst|dst, src1, src2}
RORX32mi [NoEGPR, HasBMI2]
rorx{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
RORX32ri [NoEGPR, HasBMI2]
rorx{l} {src2, src1, dst|dst, src1, src2}
RORX64mi [NoEGPR, HasBMI2]
rorx{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
RORX64ri [NoEGPR, HasBMI2]
rorx{q} {src2, src1, dst|dst, src1, src2}
SARX32rm [NoEGPR, HasBMI2]
sarx{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
SARX32rr [NoEGPR, HasBMI2]
sarx{l} {src2, src1, dst|dst, src1, src2}
SARX64rm [NoEGPR, HasBMI2]
sarx{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
SARX64rr [NoEGPR, HasBMI2]
sarx{q} {src2, src1, dst|dst, src1, src2}
SHLX32rm [NoEGPR, HasBMI2]
shlx{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
SHLX32rr [NoEGPR, HasBMI2]
shlx{l} {src2, src1, dst|dst, src1, src2}
SHLX64rm [NoEGPR, HasBMI2]
shlx{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
SHLX64rr [NoEGPR, HasBMI2]
shlx{q} {src2, src1, dst|dst, src1, src2}
SHRX32rm [NoEGPR, HasBMI2]
shrx{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
SHRX32rr [NoEGPR, HasBMI2]
shrx{l} {src2, src1, dst|dst, src1, src2}
SHRX64rm [NoEGPR, HasBMI2]
shrx{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
SHRX64rr [NoEGPR, HasBMI2]
shrx{q} {src2, src1, dst|dst, src1, src2}
ANDN32rm [NoEGPR, HasBMI]
andn{l} {src2, src1, dst|dst, src1, src2}
ANDN32rr [NoEGPR, HasBMI]
andn{l} {src2, src1, dst|dst, src1, src2}
ANDN64rm [NoEGPR, HasBMI]
andn{q} {src2, src1, dst|dst, src1, src2}
ANDN64rr [NoEGPR, HasBMI]
andn{q} {src2, src1, dst|dst, src1, src2}
BEXTR32rm [NoEGPR, HasBMI]
bextr{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
BEXTR32rr [NoEGPR, HasBMI]
bextr{l} {src2, src1, dst|dst, src1, src2}
BEXTR64rm [NoEGPR, HasBMI]
bextr{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
BEXTR64rr [NoEGPR, HasBMI]
bextr{q} {src2, src1, dst|dst, src1, src2}
CRC32r32m16 [NoEGPR, HasCRC32]
crc32{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
CRC32r32m32 [NoEGPR, HasCRC32]
crc32{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
CRC32r32m8 [NoEGPR, HasCRC32]
crc32{b} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
CRC32r32r16 [NoEGPR, HasCRC32]
crc32{w} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
CRC32r32r32 [NoEGPR, HasCRC32]
crc32{l} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
CRC32r32r8 [NoEGPR, HasCRC32]
crc32{b} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
CRC32r64m64 [NoEGPR, HasCRC32]
crc32{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
CRC32r64m8 [NoEGPR, HasCRC32]
crc32{b} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
CRC32r64r64 [NoEGPR, HasCRC32]
crc32{q} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
CRC32r64r8 [NoEGPR, HasCRC32]
crc32{b} {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
AADD32mr [NoEGPR, HasRAOINT]
aadd{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
AADD64mr [NoEGPR, HasRAOINT]
aadd{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
AAND32mr [NoEGPR, HasRAOINT]
aand{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
AAND64mr [NoEGPR, HasRAOINT]
aand{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
AOR32mr [NoEGPR, HasRAOINT]
aor{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
AOR64mr [NoEGPR, HasRAOINT]
aor{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
AXOR32mr [NoEGPR, HasRAOINT]
axor{l} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
AXOR64mr [NoEGPR, HasRAOINT]
axor{q} {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayStore |
MOVBE16mr [NoEGPR, HasMOVBE]
movbe{w} {src1, dst|dst, src1}
MOVBE16rm [NoEGPR, HasMOVBE]
movbe{w} {src1, dst|dst, src1}
MOVBE32mr [NoEGPR, HasMOVBE]
movbe{l} {src1, dst|dst, src1}
MOVBE32rm [NoEGPR, HasMOVBE]
movbe{l} {src1, dst|dst, src1}
MOVBE64mr [NoEGPR, HasMOVBE]
movbe{q} {src1, dst|dst, src1}
MOVBE64rm [NoEGPR, HasMOVBE]
movbe{q} {src1, dst|dst, src1}
RDMSRri [NoEGPR, HasUSERMSR]
rdmsr {imm, dst|dst, imm}
|
Note
|
Properties: mayLoad |
URDMSRri [NoEGPR, HasUSERMSR]
urdmsr {imm, dst|dst, imm}
|
Note
|
Properties: mayLoad |
URDMSRrr [NoEGPR, HasUSERMSR]
urdmsr {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
UWRMSRir [NoEGPR, HasUSERMSR]
uwrmsr {src, imm|imm, src}
|
Note
|
Properties: mayStore |
UWRMSRrr [NoEGPR, HasUSERMSR]
uwrmsr {src2, src1|src1, src2}
|
Note
|
Properties: mayStore |
WRMSRNSir [NoEGPR, HasUSERMSR]
wrmsrns {src, imm|imm, src}
|
Note
|
Properties: mayStore |
ENQCMD32 [NoEGPR, HasENQCMD]
enqcmd {src, dst|dst, src}
ENQCMD64 [NoEGPR, HasENQCMD]
enqcmd {src, dst|dst, src}
ENQCMDS32 [NoEGPR, HasENQCMD]
enqcmds {src, dst|dst, src}
ENQCMDS64 [NoEGPR, HasENQCMD]
enqcmds {src, dst|dst, src}
MOVDIR64B32 [NoEGPR, HasMOVDIR64B]
movdir64b {src, dst|dst, src}
MOVDIRI32 [NoEGPR, HasMOVDIRI]
movdiri {src, dst|dst, src}
AAA [Not64BitMode]
aaa
AAD8i8 [Not64BitMode]
aad src
AAM8i8 [Not64BitMode]
aam src
AAS [Not64BitMode]
aas
ARPL16mr [Not64BitMode]
arpl {src, dst|dst, src}
|
Note
|
Properties: mayStore |
ARPL16rr [Not64BitMode]
arpl {src, dst|dst, src}
BOUNDS16rm [Not64BitMode]
bound dst, src
BOUNDS32rm [Not64BitMode]
bound dst, src
CALL16r [Not64BitMode]
call{w} {*}dst
|
Note
|
Properties: isCall |
CALLpcrel16 [Not64BitMode]
call{w} dst
|
Note
|
Properties: isCall |
CALLpcrel32 [Not64BitMode]
call{l} dst
|
Note
|
Properties: isCall |
CMP8mi8 [Not64BitMode]
cmp{b} {src2, src1|src1, src2}
|
Note
|
Properties: isCompare, mayLoad |
DAA [Not64BitMode]
daa
DAS [Not64BitMode]
das
DEC16r_alt [Not64BitMode]
dec{w} src1
|
Note
|
Constraints: src1 = dst |
DEC32r_alt [Not64BitMode]
dec{l} src1
|
Note
|
Constraints: src1 = dst |
FARCALL16i [Not64BitMode]
lcall{w} seg, off
|
Note
|
Properties: isCall |
FARCALL32i [Not64BitMode]
lcall{l} seg, off
|
Note
|
Properties: isCall |
FARJMP16i [Not64BitMode]
ljmp{w} seg, off
|
Note
|
Properties: isBarrier, isBranch, isIndirectBranch, isTerminator |
FARJMP32i [Not64BitMode]
ljmp{l} seg, off
|
Note
|
Properties: isBarrier, isBranch, isIndirectBranch, isTerminator |
INC16r_alt [Not64BitMode]
inc{w} src1
|
Note
|
Constraints: src1 = dst |
INC32r_alt [Not64BitMode]
inc{l} src1
|
Note
|
Constraints: src1 = dst |
INTO [Not64BitMode]
into
INVEPT32 [Not64BitMode]
invept {src2, src1|src1, src2}
INVLPGA32 [Not64BitMode]
invlpga
INVLPGB32 [Not64BitMode]
invlpgb
INVVPID32 [Not64BitMode]
invvpid {src2, src1|src1, src2}
JCXZ [Not64BitMode]
jcxz dst
|
Note
|
Properties: isBranch, isTerminator |
JMP16m [Not64BitMode]
jmp{w} {*}dst
|
Note
|
Properties: isBarrier, isBranch, isIndirectBranch, isTerminator |
JMP16r [Not64BitMode]
jmp{w} {*}dst
|
Note
|
Properties: isBarrier, isBranch, isIndirectBranch, isTerminator |
JMP32m [Not64BitMode]
jmp{l} {*}dst
|
Note
|
Properties: isBarrier, isBranch, isIndirectBranch, isTerminator |
JMP32r [Not64BitMode]
jmp{l} {*}dst
|
Note
|
Properties: isBarrier, isBranch, isIndirectBranch, isTerminator |
LDS16rm [Not64BitMode]
lds{w} {src, dst|dst, src}
LDS32rm [Not64BitMode]
lds{l} {src, dst|dst, src}
LEA32r [Not64BitMode]
lea{l} {src|dst}, {dst|src}
LEAVE [Not64BitMode]
leave
|
Note
|
Properties: mayLoad |
LES16rm [Not64BitMode]
les{w} {src, dst|dst, src}
LES32rm [Not64BitMode]
les{l} {src, dst|dst, src}
LGDT16m [Not64BitMode]
lgdtw src
LGDT32m [Not64BitMode]
lgdt{l|d} src
LIDT16m [Not64BitMode]
lidtw src
LIDT32m [Not64BitMode]
lidt{l|d} src
MOV32cr [Not64BitMode]
mov{l} {src, dst|dst, src}
MOV32dr [Not64BitMode]
mov{l} {src, dst|dst, src}
MOV32rc [Not64BitMode]
mov{l} {src, dst|dst, src}
MOV32rd [Not64BitMode]
mov{l} {src, dst|dst, src}
POP32r [Not64BitMode]
pop{l} reg
|
Note
|
Properties: mayLoad |
POP32rmm [Not64BitMode]
pop{l} dst
|
Note
|
Properties: mayLoad, mayStore |
POPA16 [Not64BitMode]
popaw
|
Note
|
Properties: mayLoad |
POPA32 [Not64BitMode]
popal
|
Note
|
Properties: mayLoad |
POPDS16 [Not64BitMode]
pop{w} {%ds|ds}
POPDS32 [Not64BitMode]
pop{l} {%ds|ds}
POPES16 [Not64BitMode]
pop{w} {%es|es}
POPES32 [Not64BitMode]
pop{l} {%es|es}
POPF32 [Not64BitMode]
popf{l|d}
|
Note
|
Properties: mayLoad |
POPFS32 [Not64BitMode]
pop{l} {%fs|fs}
POPGS32 [Not64BitMode]
pop{l} {%gs|gs}
POPSS16 [Not64BitMode]
pop{w} {%ss|ss}
POPSS32 [Not64BitMode]
pop{l} {%ss|ss}
PUSH32i [Not64BitMode]
push{l} imm
|
Note
|
Properties: mayStore |
PUSH32i8 [Not64BitMode]
push{l} imm
|
Note
|
Properties: mayStore |
PUSH32r [Not64BitMode]
push{l} reg
|
Note
|
Properties: mayStore |
PUSH32rmm [Not64BitMode]
push{l} src
|
Note
|
Properties: mayLoad, mayStore |
PUSHA16 [Not64BitMode]
pushaw
|
Note
|
Properties: mayStore |
PUSHA32 [Not64BitMode]
pushal
|
Note
|
Properties: mayStore |
PUSHCS16 [Not64BitMode]
push{w} {%cs|cs}
PUSHCS32 [Not64BitMode]
push{l} {%cs|cs}
PUSHDS16 [Not64BitMode]
push{w} {%ds|ds}
PUSHDS32 [Not64BitMode]
push{l} {%ds|ds}
PUSHES16 [Not64BitMode]
push{w} {%es|es}
PUSHES32 [Not64BitMode]
push{l} {%es|es}
PUSHF32 [Not64BitMode]
pushf{l|d}
|
Note
|
Properties: mayStore |
PUSHFS32 [Not64BitMode]
push{l} {%fs|fs}
PUSHGS32 [Not64BitMode]
push{l} {%gs|gs}
PUSHSS16 [Not64BitMode]
push{w} {%ss|ss}
PUSHSS32 [Not64BitMode]
push{l} {%ss|ss}
PVALIDATE32 [Not64BitMode]
pvalidate
RET32 [Not64BitMode]
ret{l}
|
Note
|
Properties: hasCtrlDep, isBarrier, isReturn, isTerminator |
RETI32 [Not64BitMode]
ret{l} amt
|
Note
|
Properties: hasCtrlDep, isBarrier, isReturn, isTerminator |
SALC [Not64BitMode]
salc
SGDT16m [Not64BitMode]
sgdtw dst
SGDT32m [Not64BitMode]
sgdt{l|d} dst
SIDT16m [Not64BitMode]
sidtw dst
SIDT32m [Not64BitMode]
sidt{l|d} dst
VMLOAD32 [Not64BitMode]
vmload
VMREAD32mr [Not64BitMode]
vmread{l} {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VMREAD32rr [Not64BitMode]
vmread{l} {src, dst|dst, src}
VMRUN32 [Not64BitMode]
vmrun
VMSAVE32 [Not64BitMode]
vmsave
VMWRITE32rm [Not64BitMode]
vmwrite{l} {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
VMWRITE32rr [Not64BitMode]
vmwrite{l} {src, dst|dst, src}
ENQCMD16 [Not64BitMode, HasENQCMD]
enqcmd {src, dst|dst, src}
ENQCMDS16 [Not64BitMode, HasENQCMD]
enqcmds {src, dst|dst, src}
MOVDIR64B16 [Not64BitMode, HasMOVDIR64B]
movdir64b {src, dst|dst, src}
UMONITOR16 [Not64BitMode, HasWAITPKG]
umonitor src
CALL32r [Not64BitMode, NotUseIndirectThunkCalls]
call{l} {*}dst
|
Note
|
Properties: isCall |
CALL32m [Not64BitMode, NotUseIndirectThunkCalls, FavorMemIndirectCall]
call{l} {*}dst
|
Note
|
Properties: isCall |
CALL16m [Not64BitMode, FavorMemIndirectCall]
call{w} {*}dst
|
Note
|
Properties: isCall |
MONITOR32rrr [Not64BitMode, HasSSE3]
monitor
MONITORX32rrr [Not64BitMode, HasMWAITX]
monitorx
CLZERO32r [Not64BitMode, HasCLZERO]
clzero
RDPID32 [Not64BitMode, HasRDPID]
rdpid dst
INVPCID32 [Not64BitMode, HasINVPCID]
invpcid {src2, src1|src1, src2}
ABS_F [HasX87]
fabs
ADD_F32m [HasX87]
fadd{s} src
|
Note
|
Properties: mayLoad, mayRaiseFPException |
ADD_F64m [HasX87]
fadd{l} src
|
Note
|
Properties: mayLoad, mayRaiseFPException |
ADD_FI16m [HasX87]
fiadd{s} src
|
Note
|
Properties: mayLoad, mayRaiseFPException |
ADD_FI32m [HasX87]
fiadd{l} src
|
Note
|
Properties: mayLoad, mayRaiseFPException |
ADD_FPrST0 [HasX87]
faddp {%st, op|op, st}
|
Note
|
Properties: mayRaiseFPException |
ADD_FST0r [HasX87]
fadd {op, %st|st, op}
|
Note
|
Properties: mayRaiseFPException |
ADD_FrST0 [HasX87]
fadd {%st, op|op, st}
|
Note
|
Properties: mayRaiseFPException |
CHS_F [HasX87]
fchs
COMP_FST0r [HasX87]
fcomp op
|
Note
|
Properties: mayRaiseFPException |
COM_FIPr [HasX87]
fcompi {reg, %st|st, reg}
|
Note
|
Properties: mayRaiseFPException |
COM_FIr [HasX87]
fcomi {reg, %st|st, reg}
|
Note
|
Properties: mayRaiseFPException |
COM_FST0r [HasX87]
fcom op
|
Note
|
Properties: mayRaiseFPException |
DIVR_F32m [HasX87]
fdivr{s} src
|
Note
|
Properties: mayLoad, mayRaiseFPException |
DIVR_F64m [HasX87]
fdivr{l} src
|
Note
|
Properties: mayLoad, mayRaiseFPException |
DIVR_FI16m [HasX87]
fidivr{s} src
|
Note
|
Properties: mayLoad, mayRaiseFPException |
DIVR_FI32m [HasX87]
fidivr{l} src
|
Note
|
Properties: mayLoad, mayRaiseFPException |
DIVR_FPrST0 [HasX87]
fdiv{|r}p {%st, op|op, st}
|
Note
|
Properties: mayRaiseFPException |
DIVR_FST0r [HasX87]
fdivr {op, %st|st, op}
|
Note
|
Properties: mayRaiseFPException |
DIVR_FrST0 [HasX87]
fdiv{|r} {%st, op|op, st}
|
Note
|
Properties: mayRaiseFPException |
DIV_F32m [HasX87]
fdiv{s} src
|
Note
|
Properties: mayLoad, mayRaiseFPException |
DIV_F64m [HasX87]
fdiv{l} src
|
Note
|
Properties: mayLoad, mayRaiseFPException |
DIV_FI16m [HasX87]
fidiv{s} src
|
Note
|
Properties: mayLoad, mayRaiseFPException |
DIV_FI32m [HasX87]
fidiv{l} src
|
Note
|
Properties: mayLoad, mayRaiseFPException |
DIV_FPrST0 [HasX87]
fdiv{r}p {%st, op|op, st}
|
Note
|
Properties: mayRaiseFPException |
DIV_FST0r [HasX87]
fdiv {op, %st|st, op}
|
Note
|
Properties: mayRaiseFPException |
DIV_FrST0 [HasX87]
fdiv{r} {%st, op|op, st}
|
Note
|
Properties: mayRaiseFPException |
FBLDm [HasX87]
fbld src
|
Note
|
Properties: mayLoad |
FBSTPm [HasX87]
fbstp dst
|
Note
|
Properties: mayRaiseFPException, mayStore |
FCOM32m [HasX87]
fcom{s} src
|
Note
|
Properties: mayLoad, mayRaiseFPException |
FCOM64m [HasX87]
fcom{l} src
|
Note
|
Properties: mayLoad, mayRaiseFPException |
FCOMP32m [HasX87]
fcomp{s} src
|
Note
|
Properties: mayLoad, mayRaiseFPException |
FCOMP64m [HasX87]
fcomp{l} src
|
Note
|
Properties: mayLoad, mayRaiseFPException |
FFREE [HasX87]
ffree reg
FFREEP [HasX87]
ffreep reg
FICOM16m [HasX87]
ficom{s} src
|
Note
|
Properties: mayLoad, mayRaiseFPException |
FICOM32m [HasX87]
ficom{l} src
|
Note
|
Properties: mayLoad, mayRaiseFPException |
FICOMP16m [HasX87]
ficomp{s} src
|
Note
|
Properties: mayLoad, mayRaiseFPException |
FICOMP32m [HasX87]
ficomp{l} src
|
Note
|
Properties: mayLoad, mayRaiseFPException |
FLDENVm [HasX87]
fldenv src
|
Note
|
Properties: mayLoad |
FNSTSWm [HasX87]
fnstsw dst
|
Note
|
Properties: mayStore |
FRSTORm [HasX87]
frstor src
|
Note
|
Properties: mayLoad |
FSAVEm [HasX87]
fnsave dst
|
Note
|
Properties: mayStore |
FSTENVm [HasX87]
fnstenv dst
|
Note
|
Properties: mayStore |
ILD_F16m [HasX87]
fild{s} src
|
Note
|
Properties: mayLoad |
ILD_F32m [HasX87]
fild{l} src
|
Note
|
Properties: mayLoad |
ILD_F64m [HasX87]
fild{ll} src
|
Note
|
Properties: mayLoad |
ISTT_FP16m [HasX87]
fisttp{s} dst
|
Note
|
Properties: mayRaiseFPException, mayStore |
ISTT_FP32m [HasX87]
fisttp{l} dst
|
Note
|
Properties: mayRaiseFPException, mayStore |
ISTT_FP64m [HasX87]
fisttp{ll} dst
|
Note
|
Properties: mayRaiseFPException, mayStore |
IST_F16m [HasX87]
fist{s} dst
|
Note
|
Properties: mayRaiseFPException, mayStore |
IST_F32m [HasX87]
fist{l} dst
|
Note
|
Properties: mayRaiseFPException, mayStore |
IST_FP16m [HasX87]
fistp{s} dst
|
Note
|
Properties: mayRaiseFPException, mayStore |
IST_FP32m [HasX87]
fistp{l} dst
|
Note
|
Properties: mayRaiseFPException, mayStore |
IST_FP64m [HasX87]
fistp{ll} dst
|
Note
|
Properties: mayRaiseFPException, mayStore |
LD_F0 [HasX87]
fldz
LD_F1 [HasX87]
fld1
LD_F32m [HasX87]
fld{s} src
|
Note
|
Properties: mayLoad, mayRaiseFPException |
LD_F64m [HasX87]
fld{l} src
|
Note
|
Properties: mayLoad, mayRaiseFPException |
LD_F80m [HasX87]
fld{t} src
|
Note
|
Properties: mayLoad, mayRaiseFPException |
LD_Frr [HasX87]
fld op
|
Note
|
Properties: mayRaiseFPException |
MUL_F32m [HasX87]
fmul{s} src
|
Note
|
Properties: mayLoad, mayRaiseFPException |
MUL_F64m [HasX87]
fmul{l} src
|
Note
|
Properties: mayLoad, mayRaiseFPException |
MUL_FI16m [HasX87]
fimul{s} src
|
Note
|
Properties: mayLoad, mayRaiseFPException |
MUL_FI32m [HasX87]
fimul{l} src
|
Note
|
Properties: mayLoad, mayRaiseFPException |
MUL_FPrST0 [HasX87]
fmulp {%st, op|op, st}
|
Note
|
Properties: mayRaiseFPException |
MUL_FST0r [HasX87]
fmul {op, %st|st, op}
|
Note
|
Properties: mayRaiseFPException |
MUL_FrST0 [HasX87]
fmul {%st, op|op, st}
|
Note
|
Properties: mayRaiseFPException |
SQRT_F [HasX87]
fsqrt
|
Note
|
Properties: mayRaiseFPException |
ST_F32m [HasX87]
fst{s} dst
|
Note
|
Properties: mayRaiseFPException, mayStore |
ST_F64m [HasX87]
fst{l} dst
|
Note
|
Properties: mayRaiseFPException, mayStore |
ST_FP32m [HasX87]
fstp{s} dst
|
Note
|
Properties: mayRaiseFPException, mayStore |
ST_FP64m [HasX87]
fstp{l} dst
|
Note
|
Properties: mayRaiseFPException, mayStore |
ST_FP80m [HasX87]
fstp{t} dst
|
Note
|
Properties: mayRaiseFPException, mayStore |
ST_FPrr [HasX87]
fstp op
|
Note
|
Properties: mayRaiseFPException |
ST_Frr [HasX87]
fst op
|
Note
|
Properties: mayRaiseFPException |
SUBR_F32m [HasX87]
fsubr{s} src
|
Note
|
Properties: mayLoad, mayRaiseFPException |
SUBR_F64m [HasX87]
fsubr{l} src
|
Note
|
Properties: mayLoad, mayRaiseFPException |
SUBR_FI16m [HasX87]
fisubr{s} src
|
Note
|
Properties: mayLoad, mayRaiseFPException |
SUBR_FI32m [HasX87]
fisubr{l} src
|
Note
|
Properties: mayLoad, mayRaiseFPException |
SUBR_FPrST0 [HasX87]
fsub{|r}p {%st, op|op, st}
|
Note
|
Properties: mayRaiseFPException |
SUBR_FST0r [HasX87]
fsubr {op, %st|st, op}
|
Note
|
Properties: mayRaiseFPException |
SUBR_FrST0 [HasX87]
fsub{|r} {%st, op|op, st}
|
Note
|
Properties: mayRaiseFPException |
SUB_F32m [HasX87]
fsub{s} src
|
Note
|
Properties: mayLoad, mayRaiseFPException |
SUB_F64m [HasX87]
fsub{l} src
|
Note
|
Properties: mayLoad, mayRaiseFPException |
SUB_FI16m [HasX87]
fisub{s} src
|
Note
|
Properties: mayLoad, mayRaiseFPException |
SUB_FI32m [HasX87]
fisub{l} src
|
Note
|
Properties: mayLoad, mayRaiseFPException |
SUB_FPrST0 [HasX87]
fsub{r}p {%st, op|op, st}
|
Note
|
Properties: mayRaiseFPException |
SUB_FST0r [HasX87]
fsub {op, %st|st, op}
|
Note
|
Properties: mayRaiseFPException |
SUB_FrST0 [HasX87]
fsub{r} {%st, op|op, st}
|
Note
|
Properties: mayRaiseFPException |
TST_F [HasX87]
ftst
|
Note
|
Properties: mayRaiseFPException |
UCOM_FIPr [HasX87]
fucompi {reg, %st|st, reg}
|
Note
|
Properties: mayRaiseFPException |
UCOM_FIr [HasX87]
fucomi {reg, %st|st, reg}
|
Note
|
Properties: mayRaiseFPException |
UCOM_FPPr [HasX87]
fucompp
|
Note
|
Properties: mayRaiseFPException |
UCOM_FPr [HasX87]
fucomp reg
|
Note
|
Properties: mayRaiseFPException |
UCOM_Fr [HasX87]
fucom reg
|
Note
|
Properties: mayRaiseFPException |
XAM_F [HasX87]
fxam
XCH_F [HasX87]
fxch op
BLENDPDrmi [UseSSE41]
blendpd {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
BLENDPDrri [UseSSE41]
blendpd {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
BLENDPSrmi [UseSSE41]
blendps {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
BLENDPSrri [UseSSE41]
blendps {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
BLENDVPDrm0 [UseSSE41]
blendvpd {%xmm0, src2, dst|dst, src2, xmm0}
|
Note
|
Constraints: src1 = dst |
BLENDVPDrr0 [UseSSE41]
blendvpd {%xmm0, src2, dst|dst, src2, xmm0}
|
Note
|
Constraints: src1 = dst |
BLENDVPSrm0 [UseSSE41]
blendvps {%xmm0, src2, dst|dst, src2, xmm0}
|
Note
|
Constraints: src1 = dst |
BLENDVPSrr0 [UseSSE41]
blendvps {%xmm0, src2, dst|dst, src2, xmm0}
|
Note
|
Constraints: src1 = dst |
DPPDrmi [UseSSE41]
dppd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
DPPDrri [UseSSE41]
dppd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
DPPSrmi [UseSSE41]
dpps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
DPPSrri [UseSSE41]
dpps {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
EXTRACTPSmri [UseSSE41]
extractps {src2, src1, dst|dst, src1, src2}
EXTRACTPSrri [UseSSE41]
extractps {src2, src1, dst|dst, src1, src2}
INSERTPSrmi [UseSSE41]
insertps {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
INSERTPSrri [UseSSE41]
insertps {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
MOVNTDQArm [UseSSE41]
movntdqa {src, dst|dst, src}
MPSADBWrmi [UseSSE41]
mpsadbw {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
MPSADBWrri [UseSSE41]
mpsadbw {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
PACKUSDWrm [UseSSE41]
packusdw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PACKUSDWrr [UseSSE41]
packusdw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PBLENDVBrm0 [UseSSE41]
pblendvb {%xmm0, src2, dst|dst, src2, xmm0}
|
Note
|
Constraints: src1 = dst |
PBLENDVBrr0 [UseSSE41]
pblendvb {%xmm0, src2, dst|dst, src2, xmm0}
|
Note
|
Constraints: src1 = dst |
PBLENDWrmi [UseSSE41]
pblendw {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
PBLENDWrri [UseSSE41]
pblendw {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
PCMPEQQrm [UseSSE41]
pcmpeqq {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PCMPEQQrr [UseSSE41]
pcmpeqq {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PEXTRBmri [UseSSE41]
pextrb {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayStore |
PEXTRBrri [UseSSE41]
pextrb {src2, src1, dst|dst, src1, src2}
PEXTRDmri [UseSSE41]
pextrd {src2, src1, dst|dst, src1, src2}
PEXTRDrri [UseSSE41]
pextrd {src2, src1, dst|dst, src1, src2}
PEXTRQmri [UseSSE41]
pextrq {src2, src1, dst|dst, src1, src2}
PEXTRQrri [UseSSE41]
pextrq {src2, src1, dst|dst, src1, src2}
PEXTRWmri [UseSSE41]
pextrw {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayStore |
PHMINPOSUWrm [UseSSE41]
phminposuw {src, dst|dst, src}
PHMINPOSUWrr [UseSSE41]
phminposuw {src, dst|dst, src}
PINSRBrmi [UseSSE41]
pinsrb {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
PINSRBrri [UseSSE41]
pinsrb {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
PINSRDrmi [UseSSE41]
pinsrd {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
PINSRDrri [UseSSE41]
pinsrd {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
PINSRQrmi [UseSSE41]
pinsrq {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
PINSRQrri [UseSSE41]
pinsrq {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
PMAXSBrm [UseSSE41]
pmaxsb {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PMAXSBrr [UseSSE41]
pmaxsb {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PMAXSDrm [UseSSE41]
pmaxsd {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PMAXSDrr [UseSSE41]
pmaxsd {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PMAXUDrm [UseSSE41]
pmaxud {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PMAXUDrr [UseSSE41]
pmaxud {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PMAXUWrm [UseSSE41]
pmaxuw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PMAXUWrr [UseSSE41]
pmaxuw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PMINSBrm [UseSSE41]
pminsb {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PMINSBrr [UseSSE41]
pminsb {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PMINSDrm [UseSSE41]
pminsd {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PMINSDrr [UseSSE41]
pminsd {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PMINUDrm [UseSSE41]
pminud {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PMINUDrr [UseSSE41]
pminud {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PMINUWrm [UseSSE41]
pminuw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PMINUWrr [UseSSE41]
pminuw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PMOVSXBDrm [UseSSE41]
pmovsxbd {src, dst|dst, src}
PMOVSXBDrr [UseSSE41]
pmovsxbd {src, dst|dst, src}
PMOVSXBQrm [UseSSE41]
pmovsxbq {src, dst|dst, src}
PMOVSXBQrr [UseSSE41]
pmovsxbq {src, dst|dst, src}
PMOVSXBWrm [UseSSE41]
pmovsxbw {src, dst|dst, src}
PMOVSXBWrr [UseSSE41]
pmovsxbw {src, dst|dst, src}
PMOVSXDQrm [UseSSE41]
pmovsxdq {src, dst|dst, src}
PMOVSXDQrr [UseSSE41]
pmovsxdq {src, dst|dst, src}
PMOVSXWDrm [UseSSE41]
pmovsxwd {src, dst|dst, src}
PMOVSXWDrr [UseSSE41]
pmovsxwd {src, dst|dst, src}
PMOVSXWQrm [UseSSE41]
pmovsxwq {src, dst|dst, src}
PMOVSXWQrr [UseSSE41]
pmovsxwq {src, dst|dst, src}
PMOVZXBDrm [UseSSE41]
pmovzxbd {src, dst|dst, src}
PMOVZXBDrr [UseSSE41]
pmovzxbd {src, dst|dst, src}
PMOVZXBQrm [UseSSE41]
pmovzxbq {src, dst|dst, src}
PMOVZXBQrr [UseSSE41]
pmovzxbq {src, dst|dst, src}
PMOVZXBWrm [UseSSE41]
pmovzxbw {src, dst|dst, src}
PMOVZXBWrr [UseSSE41]
pmovzxbw {src, dst|dst, src}
PMOVZXDQrm [UseSSE41]
pmovzxdq {src, dst|dst, src}
PMOVZXDQrr [UseSSE41]
pmovzxdq {src, dst|dst, src}
PMOVZXWDrm [UseSSE41]
pmovzxwd {src, dst|dst, src}
PMOVZXWDrr [UseSSE41]
pmovzxwd {src, dst|dst, src}
PMOVZXWQrm [UseSSE41]
pmovzxwq {src, dst|dst, src}
PMOVZXWQrr [UseSSE41]
pmovzxwq {src, dst|dst, src}
PMULDQrm [UseSSE41]
pmuldq {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PMULDQrr [UseSSE41]
pmuldq {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PMULLDrm [UseSSE41]
pmulld {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PMULLDrr [UseSSE41]
pmulld {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PTESTrm [UseSSE41]
ptest {src2, src1|src1, src2}
PTESTrr [UseSSE41]
ptest {src2, src1|src1, src2}
ROUNDPDmi [UseSSE41]
roundpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
ROUNDPDri [UseSSE41]
roundpd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
ROUNDPSmi [UseSSE41]
roundps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
ROUNDPSri [UseSSE41]
roundps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
ROUNDSDmi_Int [UseSSE41]
roundsd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
ROUNDSDri_Int [UseSSE41]
roundsd {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
ROUNDSSmi_Int [UseSSE41]
roundss {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
ROUNDSSri_Int [UseSSE41]
roundss {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
VFMADDSD4mr [HasFMA4, NoAVX512]
vfmaddsd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFMADDSD4rm [HasFMA4, NoAVX512]
vfmaddsd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFMADDSD4rr [HasFMA4, NoAVX512]
vfmaddsd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFMADDSS4mr [HasFMA4, NoAVX512]
vfmaddss {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFMADDSS4rm [HasFMA4, NoAVX512]
vfmaddss {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFMADDSS4rr [HasFMA4, NoAVX512]
vfmaddss {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFMSUBSD4mr [HasFMA4, NoAVX512]
vfmsubsd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFMSUBSD4rm [HasFMA4, NoAVX512]
vfmsubsd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFMSUBSD4rr [HasFMA4, NoAVX512]
vfmsubsd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFMSUBSS4mr [HasFMA4, NoAVX512]
vfmsubss {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFMSUBSS4rm [HasFMA4, NoAVX512]
vfmsubss {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFMSUBSS4rr [HasFMA4, NoAVX512]
vfmsubss {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFNMADDSD4mr [HasFMA4, NoAVX512]
vfnmaddsd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFNMADDSD4rm [HasFMA4, NoAVX512]
vfnmaddsd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFNMADDSD4rr [HasFMA4, NoAVX512]
vfnmaddsd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFNMADDSS4mr [HasFMA4, NoAVX512]
vfnmaddss {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFNMADDSS4rm [HasFMA4, NoAVX512]
vfnmaddss {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFNMADDSS4rr [HasFMA4, NoAVX512]
vfnmaddss {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFNMSUBSD4mr [HasFMA4, NoAVX512]
vfnmsubsd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFNMSUBSD4rm [HasFMA4, NoAVX512]
vfnmsubsd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFNMSUBSD4rr [HasFMA4, NoAVX512]
vfnmsubsd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFNMSUBSS4mr [HasFMA4, NoAVX512]
vfnmsubss {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFNMSUBSS4rm [HasFMA4, NoAVX512]
vfnmsubss {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VFNMSUBSS4rr [HasFMA4, NoAVX512]
vfnmsubss {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VADDSDrm_Int [UseAVX]
vaddsd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VADDSDrr_Int [UseAVX]
vaddsd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VADDSSrm_Int [UseAVX]
vaddss {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VADDSSrr_Int [UseAVX]
vaddss {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VCOMISDrm [UseAVX]
vcomisd {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VCOMISDrr [UseAVX]
vcomisd {src2, src1|src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VCOMISSrm [UseAVX]
vcomiss {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VCOMISSrr [UseAVX]
vcomiss {src2, src1|src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VCVTSD2SI64rm_Int [UseAVX]
vcvtsd2si {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTSD2SI64rr_Int [UseAVX]
vcvtsd2si {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTSD2SIrm_Int [UseAVX]
vcvtsd2si {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTSD2SIrr_Int [UseAVX]
vcvtsd2si {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTSD2SSrm_Int [UseAVX]
vcvtsd2ss {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VCVTSD2SSrr_Int [UseAVX]
vcvtsd2ss {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VCVTSI2SDrm_Int [UseAVX]
vcvtsi2sd{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VCVTSI2SDrr_Int [UseAVX]
vcvtsi2sd {src2, src1, dst|dst, src1, src2}
VCVTSI2SSrm_Int [UseAVX]
vcvtsi2ss{l} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VCVTSI2SSrr_Int [UseAVX]
vcvtsi2ss {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VCVTSI642SDrm_Int [UseAVX]
vcvtsi2sd{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VCVTSI642SDrr_Int [UseAVX]
vcvtsi2sd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VCVTSI642SSrm_Int [UseAVX]
vcvtsi2ss{q} {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VCVTSI642SSrr_Int [UseAVX]
vcvtsi2ss {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VCVTSS2SI64rm_Int [UseAVX]
vcvtss2si {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTSS2SI64rr_Int [UseAVX]
vcvtss2si {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTSS2SIrm_Int [UseAVX]
vcvtss2si {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTSS2SIrr_Int [UseAVX]
vcvtss2si {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTSD2SI64rm_Int [UseAVX]
vcvttsd2si {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTSD2SI64rr_Int [UseAVX]
vcvttsd2si {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTSD2SIrm_Int [UseAVX]
vcvttsd2si {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTSD2SIrr_Int [UseAVX]
vcvttsd2si {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTSS2SI64rm_Int [UseAVX]
vcvttss2si {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTSS2SI64rr_Int [UseAVX]
vcvttss2si {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTSS2SIrm_Int [UseAVX]
vcvttss2si {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VCVTTSS2SIrr_Int [UseAVX]
vcvttss2si {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
VDIVSDrm_Int [UseAVX]
vdivsd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VDIVSDrr_Int [UseAVX]
vdivsd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VDIVSSrm_Int [UseAVX]
vdivss {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VDIVSSrr_Int [UseAVX]
vdivss {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VEXTRACTPSmri [UseAVX]
vextractps {src2, src1, dst|dst, src1, src2}
VEXTRACTPSrri [UseAVX]
vextractps {src2, src1, dst|dst, src1, src2}
VINSERTPSrmi [UseAVX]
vinsertps {src3, src2, src1, dst|dst, src1, src2, src3}
VINSERTPSrri [UseAVX]
vinsertps {src3, src2, src1, dst|dst, src1, src2, src3}
VMAXSDrm_Int [UseAVX]
vmaxsd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMAXSDrr_Int [UseAVX]
vmaxsd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMAXSSrm_Int [UseAVX]
vmaxss {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMAXSSrr_Int [UseAVX]
vmaxss {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMINSDrm_Int [UseAVX]
vminsd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMINSDrr_Int [UseAVX]
vminsd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMINSSrm_Int [UseAVX]
vminss {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMINSSrr_Int [UseAVX]
vminss {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMOV64toPQIrr [UseAVX]
vmovq {src, dst|dst, src}
VMOVDI2PDIrm [UseAVX]
vmovd {src, dst|dst, src}
VMOVDI2PDIrr [UseAVX]
vmovd {src, dst|dst, src}
VMOVHLPSrr [UseAVX]
vmovhlps {src2, src1, dst|dst, src1, src2}
VMOVHPDmr [UseAVX]
vmovhpd {src, dst|dst, src}
VMOVHPDrm [UseAVX]
vmovhpd {src2, src1, dst|dst, src1, src2}
VMOVHPSmr [UseAVX]
vmovhps {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VMOVHPSrm [UseAVX]
vmovhps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VMOVLHPSrr [UseAVX]
vmovlhps {src2, src1, dst|dst, src1, src2}
VMOVLPDmr [UseAVX]
vmovlpd {src, dst|dst, src}
VMOVLPDrm [UseAVX]
vmovlpd {src2, src1, dst|dst, src1, src2}
VMOVLPSmr [UseAVX]
vmovlps {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VMOVLPSrm [UseAVX]
vmovlps {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad |
VMOVPDI2DImr [UseAVX]
vmovd {src, dst|dst, src}
VMOVPDI2DIrr [UseAVX]
vmovd {src, dst|dst, src}
VMOVPQI2QImr [UseAVX]
vmovq {src, dst|dst, src}
VMOVPQIto64rr [UseAVX]
vmovq {src, dst|dst, src}
VMOVQI2PQIrm [UseAVX]
vmovq {src, dst|dst, src}
VMOVSDmr [UseAVX]
vmovsd {src, dst|dst, src}
VMOVSDrm [UseAVX]
vmovsd {src, dst|dst, src}
VMOVSSmr [UseAVX]
vmovss {src, dst|dst, src}
VMOVSSrm [UseAVX]
vmovss {src, dst|dst, src}
VMOVZPQILo2PQIrr [UseAVX]
vmovq {src, dst|dst, src}
VMULSDrm_Int [UseAVX]
vmulsd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMULSDrr_Int [UseAVX]
vmulsd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMULSSrm_Int [UseAVX]
vmulss {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VMULSSrr_Int [UseAVX]
vmulss {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VROUNDSDmi_Int [UseAVX]
vroundsd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VROUNDSDri_Int [UseAVX]
vroundsd {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VROUNDSSmi_Int [UseAVX]
vroundss {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VROUNDSSri_Int [UseAVX]
vroundss {src3, src2, src1, dst|dst, src1, src2, src3}
|
Note
|
Properties: mayRaiseFPException |
VSUBSDrm_Int [UseAVX]
vsubsd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VSUBSDrr_Int [UseAVX]
vsubsd {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VSUBSSrm_Int [UseAVX]
vsubss {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VSUBSSrr_Int [UseAVX]
vsubss {src2, src1, dst|dst, src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VUCOMISDrm [UseAVX]
vucomisd {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VUCOMISDrr [UseAVX]
vucomisd {src2, src1|src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VUCOMISSrm [UseAVX]
vucomiss {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
VUCOMISSrr [UseAVX]
vucomiss {src2, src1|src1, src2}
|
Note
|
Properties: mayRaiseFPException |
VMOVSDrr [UseAVX, OptForSize]
vmovsd {src2, src1, dst|dst, src1, src2}
VMOVSSrr [UseAVX, OptForSize]
vmovss {src2, src1, dst|dst, src1, src2}
ADDPSrm [UseSSE1]
addps {src2, dst|dst, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
ADDPSrr [UseSSE1]
addps {src2, dst|dst, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
ADDSSrm_Int [UseSSE1]
addss {src2, dst|dst, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
ADDSSrr_Int [UseSSE1]
addss {src2, dst|dst, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
ANDNPSrm [UseSSE1]
andnps {src2, dst|dst, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
ANDNPSrr [UseSSE1]
andnps {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
ANDPSrm [UseSSE1]
andps {src2, dst|dst, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
ANDPSrr [UseSSE1]
andps {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
CMPPSrmi [UseSSE1]
cmpps {cc, src2, dst|dst, src2, cc}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
CMPPSrri [UseSSE1]
cmpps {cc, src2, dst|dst, src2, cc}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
CMPSSrmi_Int [UseSSE1]
cmpss {cc, src2, dst|dst, src2, cc}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
CMPSSrri_Int [UseSSE1]
cmpss {cc, src2, dst|dst, src2, cc}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
COMISSrm [UseSSE1]
comiss {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
COMISSrr [UseSSE1]
comiss {src2, src1|src1, src2}
|
Note
|
Properties: mayRaiseFPException |
CVTSI2SSrm_Int [UseSSE1]
cvtsi2ss{l} {src2, dst|dst, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
CVTSI2SSrr_Int [UseSSE1]
cvtsi2ss {src2, dst|dst, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
CVTSI642SSrm_Int [UseSSE1]
cvtsi2ss{q} {src2, dst|dst, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
CVTSI642SSrr_Int [UseSSE1]
cvtsi2ss {src2, dst|dst, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
CVTSS2SI64rm_Int [UseSSE1]
cvtss2si {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
CVTSS2SI64rr_Int [UseSSE1]
cvtss2si {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
CVTSS2SIrm_Int [UseSSE1]
cvtss2si {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
CVTSS2SIrr_Int [UseSSE1]
cvtss2si {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
CVTTSS2SI64rm_Int [UseSSE1]
cvttss2si {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
CVTTSS2SI64rr_Int [UseSSE1]
cvttss2si {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
CVTTSS2SIrm_Int [UseSSE1]
cvttss2si {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
CVTTSS2SIrr_Int [UseSSE1]
cvttss2si {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
DIVPSrm [UseSSE1]
divps {src2, dst|dst, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
DIVPSrr [UseSSE1]
divps {src2, dst|dst, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
DIVSSrm_Int [UseSSE1]
divss {src2, dst|dst, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
DIVSSrr_Int [UseSSE1]
divss {src2, dst|dst, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
MAXPSrm [UseSSE1]
maxps {src2, dst|dst, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
MAXPSrr [UseSSE1]
maxps {src2, dst|dst, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
MAXSSrm_Int [UseSSE1]
maxss {src2, dst|dst, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
MAXSSrr_Int [UseSSE1]
maxss {src2, dst|dst, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
MINPSrm [UseSSE1]
minps {src2, dst|dst, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
MINPSrr [UseSSE1]
minps {src2, dst|dst, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
MINSSrm_Int [UseSSE1]
minss {src2, dst|dst, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
MINSSrr_Int [UseSSE1]
minss {src2, dst|dst, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
MOVAPSmr [UseSSE1]
movaps {src, dst|dst, src}
MOVAPSrm [UseSSE1]
movaps {src, dst|dst, src}
MOVAPSrr [UseSSE1]
movaps {src, dst|dst, src}
|
Note
|
Properties: isMoveReg |
MOVHLPSrr [UseSSE1]
movhlps {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MOVHPSmr [UseSSE1]
movhps {src, dst|dst, src}
|
Note
|
Properties: mayStore |
MOVHPSrm [UseSSE1]
movhps {src2, dst|dst, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
MOVLHPSrr [UseSSE1]
movlhps {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MOVLPSmr [UseSSE1]
movlps {src, dst|dst, src}
|
Note
|
Properties: mayStore |
MOVLPSrm [UseSSE1]
movlps {src2, dst|dst, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
MOVMSKPSrr [UseSSE1]
movmskps {src, dst|dst, src}
MOVNTPSmr [UseSSE1]
movntps {src, dst|dst, src}
MOVSSmr [UseSSE1]
movss {src, dst|dst, src}
MOVSSrm [UseSSE1]
movss {src, dst|dst, src}
MOVUPSmr [UseSSE1]
movups {src, dst|dst, src}
MOVUPSrm [UseSSE1]
movups {src, dst|dst, src}
MOVUPSrr [UseSSE1]
movups {src, dst|dst, src}
|
Note
|
Properties: isMoveReg |
MULPSrm [UseSSE1]
mulps {src2, dst|dst, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
MULPSrr [UseSSE1]
mulps {src2, dst|dst, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
MULSSrm_Int [UseSSE1]
mulss {src2, dst|dst, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
MULSSrr_Int [UseSSE1]
mulss {src2, dst|dst, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
ORPSrm [UseSSE1]
orps {src2, dst|dst, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
ORPSrr [UseSSE1]
orps {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
RCPPSm [UseSSE1]
rcpps {src, dst|dst, src}
RCPPSr [UseSSE1]
rcpps {src, dst|dst, src}
RSQRTPSm [UseSSE1]
rsqrtps {src, dst|dst, src}
RSQRTPSr [UseSSE1]
rsqrtps {src, dst|dst, src}
SHUFPSrmi [UseSSE1]
shufps {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
SHUFPSrri [UseSSE1]
shufps {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
SQRTPSm [UseSSE1]
sqrtps {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
SQRTPSr [UseSSE1]
sqrtps {src, dst|dst, src}
|
Note
|
Properties: mayRaiseFPException |
SUBPSrm [UseSSE1]
subps {src2, dst|dst, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
SUBPSrr [UseSSE1]
subps {src2, dst|dst, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
SUBSSrm_Int [UseSSE1]
subss {src2, dst|dst, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
SUBSSrr_Int [UseSSE1]
subss {src2, dst|dst, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
UCOMISSrm [UseSSE1]
ucomiss {src2, src1|src1, src2}
|
Note
|
Properties: mayLoad, mayRaiseFPException |
UCOMISSrr [UseSSE1]
ucomiss {src2, src1|src1, src2}
|
Note
|
Properties: mayRaiseFPException |
UNPCKHPSrm [UseSSE1]
unpckhps {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
UNPCKHPSrr [UseSSE1]
unpckhps {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
UNPCKLPSrm [UseSSE1]
unpcklps {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
UNPCKLPSrr [UseSSE1]
unpcklps {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
VCVTNE2PS2BF16Zrm [HasBF16]
vcvtne2ps2bf16 {src2, src1, dst|dst, src1, src2}
VCVTNE2PS2BF16Zrmb [HasBF16]
vcvtne2ps2bf16 {src2{1to16}, src1, dst|dst, src1, src2{1to16}}
VCVTNE2PS2BF16Zrmbk [HasBF16]
vcvtne2ps2bf16 {src2{1to16}, src1, dst {mask}|dst {mask}, src1, src2{1to16}}
|
Note
|
Constraints: src0 = dst |
VCVTNE2PS2BF16Zrmbkz [HasBF16]
vcvtne2ps2bf16 {src2{1to16}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to16}}
VCVTNE2PS2BF16Zrmk [HasBF16]
vcvtne2ps2bf16 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VCVTNE2PS2BF16Zrmkz [HasBF16]
vcvtne2ps2bf16 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VCVTNE2PS2BF16Zrr [HasBF16]
vcvtne2ps2bf16 {src2, src1, dst|dst, src1, src2}
VCVTNE2PS2BF16Zrrk [HasBF16]
vcvtne2ps2bf16 {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VCVTNE2PS2BF16Zrrkz [HasBF16]
vcvtne2ps2bf16 {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VCVTNEPS2BF16Zrm [HasBF16]
vcvtneps2bf16 {src, dst|dst, src}
VCVTNEPS2BF16Zrmb [HasBF16]
vcvtneps2bf16 {src{1to16}, dst|dst, src{1to16}}
VCVTNEPS2BF16Zrmbk [HasBF16]
vcvtneps2bf16 {src{1to16}, dst {mask}|dst {mask}, src{1to16}}
|
Note
|
Constraints: src0 = dst |
VCVTNEPS2BF16Zrmbkz [HasBF16]
vcvtneps2bf16 {src{1to16}, dst {mask} {z}|dst {mask} {z}, src{1to16}}
VCVTNEPS2BF16Zrmk [HasBF16]
vcvtneps2bf16 {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTNEPS2BF16Zrmkz [HasBF16]
vcvtneps2bf16 {src, dst {mask} {z}|dst {mask} {z}, src}
VCVTNEPS2BF16Zrr [HasBF16]
vcvtneps2bf16 {src, dst|dst, src}
VCVTNEPS2BF16Zrrk [HasBF16]
vcvtneps2bf16 {src, dst {mask}|dst {mask}, src}
|
Note
|
Constraints: src0 = dst |
VCVTNEPS2BF16Zrrkz [HasBF16]
vcvtneps2bf16 {src, dst {mask} {z}|dst {mask} {z}, src}
VDPBF16PSZm [HasBF16]
vdpbf16ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VDPBF16PSZmb [HasBF16]
vdpbf16ps {src3{1to16}, src2, dst|dst, src2, src3{1to16}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VDPBF16PSZmbk [HasBF16]
vdpbf16ps {src3{1to16}, src2, dst {mask}|dst {mask}, src2, src3{1to16}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VDPBF16PSZmbkz [HasBF16]
vdpbf16ps {src3{1to16}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to16}}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VDPBF16PSZmk [HasBF16]
vdpbf16ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VDPBF16PSZmkz [HasBF16]
vdpbf16ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VDPBF16PSZr [HasBF16]
vdpbf16ps {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VDPBF16PSZrk [HasBF16]
vdpbf16ps {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VDPBF16PSZrkz [HasBF16]
vdpbf16ps {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMBZrm [HasVBMI]
vpermb {src2, src1, dst|dst, src1, src2}
VPERMBZrmk [HasVBMI]
vpermb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPERMBZrmkz [HasVBMI]
vpermb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPERMBZrr [HasVBMI]
vpermb {src2, src1, dst|dst, src1, src2}
VPERMBZrrk [HasVBMI]
vpermb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPERMBZrrkz [HasVBMI]
vpermb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPERMI2BZrm [HasVBMI]
vpermi2b {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2BZrmk [HasVBMI]
vpermi2b {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2BZrmkz [HasVBMI]
vpermi2b {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
VPERMI2BZrr [HasVBMI]
vpermi2b {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMI2BZrrk [HasVBMI]
vpermi2b {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMI2BZrrkz [HasVBMI]
vpermi2b {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2BZrm [HasVBMI]
vpermt2b {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2BZrmk [HasVBMI]
vpermt2b {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2BZrmkz [HasVBMI]
vpermt2b {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2BZrr [HasVBMI]
vpermt2b {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2BZrrk [HasVBMI]
vpermt2b {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPERMT2BZrrkz [HasVBMI]
vpermt2b {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPMULTISHIFTQBZrm [HasVBMI]
vpmultishiftqb {src2, src1, dst|dst, src1, src2}
VPMULTISHIFTQBZrmb [HasVBMI]
vpmultishiftqb {src2{1to8}, src1, dst|dst, src1, src2{1to8}}
VPMULTISHIFTQBZrmbk [HasVBMI]
vpmultishiftqb {src2{1to8}, src1, dst {mask}|dst {mask}, src1, src2{1to8}}
|
Note
|
Constraints: src0 = dst |
VPMULTISHIFTQBZrmbkz [HasVBMI]
vpmultishiftqb {src2{1to8}, src1, dst {mask} {z}|dst {mask} {z}, src1, src2{1to8}}
VPMULTISHIFTQBZrmk [HasVBMI]
vpmultishiftqb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMULTISHIFTQBZrmkz [HasVBMI]
vpmultishiftqb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
VPMULTISHIFTQBZrr [HasVBMI]
vpmultishiftqb {src2, src1, dst|dst, src1, src2}
VPMULTISHIFTQBZrrk [HasVBMI]
vpmultishiftqb {src2, src1, dst {mask}|dst {mask}, src1, src2}
|
Note
|
Constraints: src0 = dst |
VPMULTISHIFTQBZrrkz [HasVBMI]
vpmultishiftqb {src2, src1, dst {mask} {z}|dst {mask} {z}, src1, src2}
XORPSrm [UseSSE1]
xorps {src2, dst|dst, src2}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
XORPSrr [UseSSE1]
xorps {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
MOVSSrr [UseSSE1, NoSSE41_Or_OptForSize]
movss {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
VPMADD52HUQZm [HasIFMA]
vpmadd52huq {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPMADD52HUQZmb [HasIFMA]
vpmadd52huq {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPMADD52HUQZmbk [HasIFMA]
vpmadd52huq {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPMADD52HUQZmbkz [HasIFMA]
vpmadd52huq {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPMADD52HUQZmk [HasIFMA]
vpmadd52huq {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPMADD52HUQZmkz [HasIFMA]
vpmadd52huq {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPMADD52HUQZr [HasIFMA]
vpmadd52huq {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPMADD52HUQZrk [HasIFMA]
vpmadd52huq {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPMADD52HUQZrkz [HasIFMA]
vpmadd52huq {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPMADD52LUQZm [HasIFMA]
vpmadd52luq {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPMADD52LUQZmb [HasIFMA]
vpmadd52luq {src3{1to8}, src2, dst|dst, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPMADD52LUQZmbk [HasIFMA]
vpmadd52luq {src3{1to8}, src2, dst {mask}|dst {mask}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPMADD52LUQZmbkz [HasIFMA]
vpmadd52luq {src3{1to8}, src2, dst {mask} {z}|dst {mask} {z}, src2, src3{1to8}}
|
Note
|
Constraints: src1 = dst |
VPMADD52LUQZmk [HasIFMA]
vpmadd52luq {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPMADD52LUQZmkz [HasIFMA]
vpmadd52luq {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPMADD52LUQZr [HasIFMA]
vpmadd52luq {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPMADD52LUQZrk [HasIFMA]
vpmadd52luq {src3, src2, dst {mask}|dst {mask}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPMADD52LUQZrkz [HasIFMA]
vpmadd52luq {src3, src2, dst {mask} {z}|dst {mask} {z}, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPOPCNTDZrm [HasVPOPCNTDQ]
vpopcntd {src1, dst|dst, src1}
VPOPCNTDZrmb [HasVPOPCNTDQ]
vpopcntd {src1{1to16}, dst|dst, src1{1to16}}
VPOPCNTDZrmbk [HasVPOPCNTDQ]
vpopcntd {src1{1to16}, dst {mask}|dst {mask}, src1{1to16}}
|
Note
|
Constraints: src0 = dst |
VPOPCNTDZrmbkz [HasVPOPCNTDQ]
vpopcntd {src1{1to16}, dst {mask} {z}|dst {mask} {z}, src1{1to16}}
VPOPCNTDZrmk [HasVPOPCNTDQ]
vpopcntd {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPOPCNTDZrmkz [HasVPOPCNTDQ]
vpopcntd {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPOPCNTDZrr [HasVPOPCNTDQ]
vpopcntd {src1, dst|dst, src1}
VPOPCNTDZrrk [HasVPOPCNTDQ]
vpopcntd {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPOPCNTDZrrkz [HasVPOPCNTDQ]
vpopcntd {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPOPCNTQZrm [HasVPOPCNTDQ]
vpopcntq {src1, dst|dst, src1}
VPOPCNTQZrmb [HasVPOPCNTDQ]
vpopcntq {src1{1to8}, dst|dst, src1{1to8}}
VPOPCNTQZrmbk [HasVPOPCNTDQ]
vpopcntq {src1{1to8}, dst {mask}|dst {mask}, src1{1to8}}
|
Note
|
Constraints: src0 = dst |
VPOPCNTQZrmbkz [HasVPOPCNTDQ]
vpopcntq {src1{1to8}, dst {mask} {z}|dst {mask} {z}, src1{1to8}}
VPOPCNTQZrmk [HasVPOPCNTDQ]
vpopcntq {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPOPCNTQZrmkz [HasVPOPCNTDQ]
vpopcntq {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPOPCNTQZrr [HasVPOPCNTDQ]
vpopcntq {src1, dst|dst, src1}
VPOPCNTQZrrk [HasVPOPCNTDQ]
vpopcntq {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPOPCNTQZrrkz [HasVPOPCNTDQ]
vpopcntq {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPOPCNTBZrm [HasBITALG]
vpopcntb {src1, dst|dst, src1}
VPOPCNTBZrmk [HasBITALG]
vpopcntb {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPOPCNTBZrmkz [HasBITALG]
vpopcntb {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPOPCNTBZrr [HasBITALG]
vpopcntb {src1, dst|dst, src1}
VPOPCNTBZrrk [HasBITALG]
vpopcntb {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPOPCNTBZrrkz [HasBITALG]
vpopcntb {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPOPCNTWZrm [HasBITALG]
vpopcntw {src1, dst|dst, src1}
VPOPCNTWZrmk [HasBITALG]
vpopcntw {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPOPCNTWZrmkz [HasBITALG]
vpopcntw {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPOPCNTWZrr [HasBITALG]
vpopcntw {src1, dst|dst, src1}
VPOPCNTWZrrk [HasBITALG]
vpopcntw {src1, dst {mask}|dst {mask}, src1}
|
Note
|
Constraints: src0 = dst |
VPOPCNTWZrrkz [HasBITALG]
vpopcntw {src1, dst {mask} {z}|dst {mask} {z}, src1}
VPSHUFBITQMBZrm [HasBITALG]
vpshufbitqmb {src2, src1, dst|dst, src1, src2}
VPSHUFBITQMBZrmk [HasBITALG]
vpshufbitqmb {src2, src1, dst {mask}|dst {mask}, src1, src2}
VPSHUFBITQMBZrr [HasBITALG]
vpshufbitqmb {src2, src1, dst|dst, src1, src2}
VPSHUFBITQMBZrrk [HasBITALG]
vpshufbitqmb {src2, src1, dst {mask}|dst {mask}, src1, src2}
PREFETCHRST2 [HasMOVRS]
prefetchrst2 src
BEXTRI32mi [HasTBM]
bextr{l} {cntl, src1, dst|dst, src1, cntl}
BEXTRI32ri [HasTBM]
bextr{l} {cntl, src1, dst|dst, src1, cntl}
BEXTRI64mi [HasTBM]
bextr{q} {cntl, src1, dst|dst, src1, cntl}
BEXTRI64ri [HasTBM]
bextr{q} {cntl, src1, dst|dst, src1, cntl}
BLCFILL32rm [HasTBM]
blcfill{l} {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
BLCFILL32rr [HasTBM]
blcfill{l} {src, dst|dst, src}
BLCFILL64rm [HasTBM]
blcfill{q} {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
BLCFILL64rr [HasTBM]
blcfill{q} {src, dst|dst, src}
BLCI32rm [HasTBM]
blci{l} {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
BLCI32rr [HasTBM]
blci{l} {src, dst|dst, src}
BLCI64rm [HasTBM]
blci{q} {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
BLCI64rr [HasTBM]
blci{q} {src, dst|dst, src}
BLCIC32rm [HasTBM]
blcic{l} {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
BLCIC32rr [HasTBM]
blcic{l} {src, dst|dst, src}
BLCIC64rm [HasTBM]
blcic{q} {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
BLCIC64rr [HasTBM]
blcic{q} {src, dst|dst, src}
BLCMSK32rm [HasTBM]
blcmsk{l} {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
BLCMSK32rr [HasTBM]
blcmsk{l} {src, dst|dst, src}
BLCMSK64rm [HasTBM]
blcmsk{q} {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
BLCMSK64rr [HasTBM]
blcmsk{q} {src, dst|dst, src}
BLCS32rm [HasTBM]
blcs{l} {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
BLCS32rr [HasTBM]
blcs{l} {src, dst|dst, src}
BLCS64rm [HasTBM]
blcs{q} {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
BLCS64rr [HasTBM]
blcs{q} {src, dst|dst, src}
BLSFILL32rm [HasTBM]
blsfill{l} {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
BLSFILL32rr [HasTBM]
blsfill{l} {src, dst|dst, src}
BLSFILL64rm [HasTBM]
blsfill{q} {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
BLSFILL64rr [HasTBM]
blsfill{q} {src, dst|dst, src}
BLSIC32rm [HasTBM]
blsic{l} {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
BLSIC32rr [HasTBM]
blsic{l} {src, dst|dst, src}
BLSIC64rm [HasTBM]
blsic{q} {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
BLSIC64rr [HasTBM]
blsic{q} {src, dst|dst, src}
T1MSKC32rm [HasTBM]
t1mskc{l} {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
T1MSKC32rr [HasTBM]
t1mskc{l} {src, dst|dst, src}
T1MSKC64rm [HasTBM]
t1mskc{q} {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
T1MSKC64rr [HasTBM]
t1mskc{q} {src, dst|dst, src}
TZMSK32rm [HasTBM]
tzmsk{l} {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
TZMSK32rr [HasTBM]
tzmsk{l} {src, dst|dst, src}
TZMSK64rm [HasTBM]
tzmsk{q} {src, dst|dst, src}
|
Note
|
Properties: mayLoad |
TZMSK64rr [HasTBM]
tzmsk{q} {src, dst|dst, src}
PABSBrm [UseSSSE3]
pabsb {src, dst|dst, src}
PABSBrr [UseSSSE3]
pabsb {src, dst|dst, src}
PABSDrm [UseSSSE3]
pabsd {src, dst|dst, src}
PABSDrr [UseSSSE3]
pabsd {src, dst|dst, src}
PABSWrm [UseSSSE3]
pabsw {src, dst|dst, src}
PABSWrr [UseSSSE3]
pabsw {src, dst|dst, src}
PALIGNRrmi [UseSSSE3]
palignr {src3, src2, dst|dst, src2, src3}
|
Note
|
Properties: mayLoad |
|
Note
|
Constraints: src1 = dst |
PALIGNRrri [UseSSSE3]
palignr {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
PHADDDrm [UseSSSE3]
phaddd {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PHADDDrr [UseSSSE3]
phaddd {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PHADDSWrm [UseSSSE3]
phaddsw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PHADDSWrr [UseSSSE3]
phaddsw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PHADDWrm [UseSSSE3]
phaddw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PHADDWrr [UseSSSE3]
phaddw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PHSUBDrm [UseSSSE3]
phsubd {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PHSUBDrr [UseSSSE3]
phsubd {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PHSUBSWrm [UseSSSE3]
phsubsw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PHSUBSWrr [UseSSSE3]
phsubsw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PHSUBWrm [UseSSSE3]
phsubw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PHSUBWrr [UseSSSE3]
phsubw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PMADDUBSWrm [UseSSSE3]
pmaddubsw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PMADDUBSWrr [UseSSSE3]
pmaddubsw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PMULHRSWrm [UseSSSE3]
pmulhrsw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PMULHRSWrr [UseSSSE3]
pmulhrsw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PSHUFBrm [UseSSSE3]
pshufb {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PSHUFBrr [UseSSSE3]
pshufb {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PSIGNBrm [UseSSSE3]
psignb {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PSIGNBrr [UseSSSE3]
psignb {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PSIGNDrm [UseSSSE3]
psignd {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PSIGNDrr [UseSSSE3]
psignd {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PSIGNWrm [UseSSSE3]
psignw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PSIGNWrr [UseSSSE3]
psignw {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
SFENCE [HasSSE1]
sfence
TZCNT16rm [HasBMI]
tzcnt{w} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
TZCNT16rm_EVEX [HasBMI]
tzcnt{w} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
TZCNT16rr [HasBMI]
tzcnt{w} {src1, dst|dst, src1}
TZCNT16rr_EVEX [HasBMI]
tzcnt{w} {src1, dst|dst, src1}
TZCNT32rm [HasBMI]
tzcnt{l} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
TZCNT32rm_EVEX [HasBMI]
tzcnt{l} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
TZCNT32rr [HasBMI]
tzcnt{l} {src1, dst|dst, src1}
TZCNT32rr_EVEX [HasBMI]
tzcnt{l} {src1, dst|dst, src1}
TZCNT64rm [HasBMI]
tzcnt{q} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
TZCNT64rm_EVEX [HasBMI]
tzcnt{q} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
TZCNT64rr [HasBMI]
tzcnt{q} {src1, dst|dst, src1}
TZCNT64rr_EVEX [HasBMI]
tzcnt{q} {src1, dst|dst, src1}
VPDPBSSDSYrm [HasAVXVNNIINT8]
vpdpbssds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSSDSYrr [HasAVXVNNIINT8]
vpdpbssds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSSDSrm [HasAVXVNNIINT8]
vpdpbssds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSSDSrr [HasAVXVNNIINT8]
vpdpbssds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSSDYrm [HasAVXVNNIINT8]
vpdpbssd {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSSDYrr [HasAVXVNNIINT8]
vpdpbssd {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSSDrm [HasAVXVNNIINT8]
vpdpbssd {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSSDrr [HasAVXVNNIINT8]
vpdpbssd {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSUDSYrm [HasAVXVNNIINT8]
vpdpbsuds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSUDSYrr [HasAVXVNNIINT8]
vpdpbsuds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSUDSrm [HasAVXVNNIINT8]
vpdpbsuds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSUDSrr [HasAVXVNNIINT8]
vpdpbsuds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSUDYrm [HasAVXVNNIINT8]
vpdpbsud {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSUDYrr [HasAVXVNNIINT8]
vpdpbsud {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSUDrm [HasAVXVNNIINT8]
vpdpbsud {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBSUDrr [HasAVXVNNIINT8]
vpdpbsud {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUUDSYrm [HasAVXVNNIINT8]
vpdpbuuds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUUDSYrr [HasAVXVNNIINT8]
vpdpbuuds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUUDSrm [HasAVXVNNIINT8]
vpdpbuuds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUUDSrr [HasAVXVNNIINT8]
vpdpbuuds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUUDYrm [HasAVXVNNIINT8]
vpdpbuud {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUUDYrr [HasAVXVNNIINT8]
vpdpbuud {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUUDrm [HasAVXVNNIINT8]
vpdpbuud {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUUDrr [HasAVXVNNIINT8]
vpdpbuud {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSUDSYrm [HasAVXVNNIINT16]
vpdpwsuds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSUDSYrr [HasAVXVNNIINT16]
vpdpwsuds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSUDSrm [HasAVXVNNIINT16]
vpdpwsuds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSUDSrr [HasAVXVNNIINT16]
vpdpwsuds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSUDYrm [HasAVXVNNIINT16]
vpdpwsud {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSUDYrr [HasAVXVNNIINT16]
vpdpwsud {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSUDrm [HasAVXVNNIINT16]
vpdpwsud {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSUDrr [HasAVXVNNIINT16]
vpdpwsud {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUSDSYrm [HasAVXVNNIINT16]
vpdpwusds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUSDSYrr [HasAVXVNNIINT16]
vpdpwusds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUSDSrm [HasAVXVNNIINT16]
vpdpwusds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUSDSrr [HasAVXVNNIINT16]
vpdpwusds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUSDYrm [HasAVXVNNIINT16]
vpdpwusd {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUSDYrr [HasAVXVNNIINT16]
vpdpwusd {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUSDrm [HasAVXVNNIINT16]
vpdpwusd {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUSDrr [HasAVXVNNIINT16]
vpdpwusd {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUUDSYrm [HasAVXVNNIINT16]
vpdpwuuds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUUDSYrr [HasAVXVNNIINT16]
vpdpwuuds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUUDSrm [HasAVXVNNIINT16]
vpdpwuuds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUUDSrr [HasAVXVNNIINT16]
vpdpwuuds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUUDYrm [HasAVXVNNIINT16]
vpdpwuud {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUUDYrr [HasAVXVNNIINT16]
vpdpwuud {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUUDrm [HasAVXVNNIINT16]
vpdpwuud {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWUUDrr [HasAVXVNNIINT16]
vpdpwuud {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
AESDECLASTrm [HasAES, NoAVX]
aesdeclast {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
AESDECLASTrr [HasAES, NoAVX]
aesdeclast {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
AESDECrm [HasAES, NoAVX]
aesdec {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
AESDECrr [HasAES, NoAVX]
aesdec {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
AESENCLASTrm [HasAES, NoAVX]
aesenclast {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
AESENCLASTrr [HasAES, NoAVX]
aesenclast {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
AESENCrm [HasAES, NoAVX]
aesenc {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
AESENCrr [HasAES, NoAVX]
aesenc {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
AESIMCrm [HasAES, NoAVX]
aesimc {src1, dst|dst, src1}
AESIMCrr [HasAES, NoAVX]
aesimc {src1, dst|dst, src1}
AESKEYGENASSIST128rm [HasAES, NoAVX]
aeskeygenassist {src2, src1, dst|dst, src1, src2}
AESKEYGENASSIST128rr [HasAES, NoAVX]
aeskeygenassist {src2, src1, dst|dst, src1, src2}
VSM4KEY4Yrm [HasSM4]
vsm4key4 {src2, src1, dst|dst, src1, src2}
VSM4KEY4Yrr [HasSM4]
vsm4key4 {src2, src1, dst|dst, src1, src2}
VSM4KEY4rm [HasSM4]
vsm4key4 {src2, src1, dst|dst, src1, src2}
VSM4KEY4rr [HasSM4]
vsm4key4 {src2, src1, dst|dst, src1, src2}
VSM4RNDS4Yrm [HasSM4]
vsm4rnds4 {src2, src1, dst|dst, src1, src2}
VSM4RNDS4Yrr [HasSM4]
vsm4rnds4 {src2, src1, dst|dst, src1, src2}
VSM4RNDS4rm [HasSM4]
vsm4rnds4 {src2, src1, dst|dst, src1, src2}
VSM4RNDS4rr [HasSM4]
vsm4rnds4 {src2, src1, dst|dst, src1, src2}
ADDSUBPDrm [UseSSE3]
addsubpd {src2, dst|dst, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
ADDSUBPDrr [UseSSE3]
addsubpd {src2, dst|dst, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
ADDSUBPSrm [UseSSE3]
addsubps {src2, dst|dst, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
ADDSUBPSrr [UseSSE3]
addsubps {src2, dst|dst, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
HADDPDrm [UseSSE3]
haddpd {src2, dst|dst, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
HADDPDrr [UseSSE3]
haddpd {src2, dst|dst, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
HADDPSrm [UseSSE3]
haddps {src2, dst|dst, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
HADDPSrr [UseSSE3]
haddps {src2, dst|dst, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
HSUBPDrm [UseSSE3]
hsubpd {src2, dst|dst, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
HSUBPDrr [UseSSE3]
hsubpd {src2, dst|dst, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
HSUBPSrm [UseSSE3]
hsubps {src2, dst|dst, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
HSUBPSrr [UseSSE3]
hsubps {src2, dst|dst, src2}
|
Note
|
Properties: mayRaiseFPException |
|
Note
|
Constraints: src1 = dst |
LDDQUrm [UseSSE3]
lddqu {src, dst|dst, src}
MOVDDUPrm [UseSSE3]
movddup {src, dst|dst, src}
MOVDDUPrr [UseSSE3]
movddup {src, dst|dst, src}
MOVSHDUPrm [UseSSE3]
movshdup {src, dst|dst, src}
MOVSHDUPrr [UseSSE3]
movshdup {src, dst|dst, src}
MOVSLDUPrm [UseSSE3]
movsldup {src, dst|dst, src}
MOVSLDUPrr [UseSSE3]
movsldup {src, dst|dst, src}
LFENCE [HasSSE2]
lfence
MOVNTI_64mr [HasSSE2]
movnti{q} {src, dst|dst, src}
MOVNTImr [HasSSE2]
movnti{l} {src, dst|dst, src}
DEC16m [UseIncDec]
dec{w} src1
|
Note
|
Properties: mayLoad, mayStore |
DEC32m [UseIncDec]
dec{l} src1
|
Note
|
Properties: mayLoad, mayStore |
DEC8m [UseIncDec]
dec{b} src1
|
Note
|
Properties: mayLoad, mayStore |
INC16m [UseIncDec]
inc{w} src1
|
Note
|
Properties: mayLoad, mayStore |
INC32m [UseIncDec]
inc{l} src1
|
Note
|
Properties: mayLoad, mayStore |
INC8m [UseIncDec]
inc{b} src1
|
Note
|
Properties: mayLoad, mayStore |
VBCSTNEBF162PSYrm [HasAVXNECONVERT]
vbcstnebf162ps {src, dst|dst, src}
VBCSTNEBF162PSrm [HasAVXNECONVERT]
vbcstnebf162ps {src, dst|dst, src}
VBCSTNESH2PSYrm [HasAVXNECONVERT]
vbcstnesh2ps {src, dst|dst, src}
VBCSTNESH2PSrm [HasAVXNECONVERT]
vbcstnesh2ps {src, dst|dst, src}
VCVTNEEBF162PSYrm [HasAVXNECONVERT]
vcvtneebf162ps {src, dst|dst, src}
VCVTNEEBF162PSrm [HasAVXNECONVERT]
vcvtneebf162ps {src, dst|dst, src}
VCVTNEEPH2PSYrm [HasAVXNECONVERT]
vcvtneeph2ps {src, dst|dst, src}
VCVTNEEPH2PSrm [HasAVXNECONVERT]
vcvtneeph2ps {src, dst|dst, src}
VCVTNEOBF162PSYrm [HasAVXNECONVERT]
vcvtneobf162ps {src, dst|dst, src}
VCVTNEOBF162PSrm [HasAVXNECONVERT]
vcvtneobf162ps {src, dst|dst, src}
VCVTNEOPH2PSYrm [HasAVXNECONVERT]
vcvtneoph2ps {src, dst|dst, src}
VCVTNEOPH2PSrm [HasAVXNECONVERT]
vcvtneoph2ps {src, dst|dst, src}
VCVTNEPS2BF16Yrm [HasAVXNECONVERT]
vcvtneps2bf16{y} {src, dst|dst, src}
VCVTNEPS2BF16Yrr [HasAVXNECONVERT]
vcvtneps2bf16 {src, dst|dst, src}
VCVTNEPS2BF16rm [HasAVXNECONVERT]
vcvtneps2bf16{x} {src, dst|dst, src}
VCVTNEPS2BF16rr [HasAVXNECONVERT]
vcvtneps2bf16 {src, dst|dst, src}
VPDPBUSDSYrm [NoVLX_Or_NoVNNI, HasAVXVNNI]
vpdpbusds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUSDSYrr [NoVLX_Or_NoVNNI, HasAVXVNNI]
vpdpbusds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUSDSrm [NoVLX_Or_NoVNNI, HasAVXVNNI]
vpdpbusds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUSDSrr [NoVLX_Or_NoVNNI, HasAVXVNNI]
vpdpbusds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUSDYrm [NoVLX_Or_NoVNNI, HasAVXVNNI]
vpdpbusd {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUSDYrr [NoVLX_Or_NoVNNI, HasAVXVNNI]
vpdpbusd {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUSDrm [NoVLX_Or_NoVNNI, HasAVXVNNI]
vpdpbusd {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPBUSDrr [NoVLX_Or_NoVNNI, HasAVXVNNI]
vpdpbusd {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSSDSYrm [NoVLX_Or_NoVNNI, HasAVXVNNI]
vpdpwssds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSSDSYrr [NoVLX_Or_NoVNNI, HasAVXVNNI]
vpdpwssds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSSDSrm [NoVLX_Or_NoVNNI, HasAVXVNNI]
vpdpwssds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSSDSrr [NoVLX_Or_NoVNNI, HasAVXVNNI]
vpdpwssds {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSSDYrm [NoVLX_Or_NoVNNI, HasAVXVNNI]
vpdpwssd {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSSDYrr [NoVLX_Or_NoVNNI, HasAVXVNNI]
vpdpwssd {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSSDrm [NoVLX_Or_NoVNNI, HasAVXVNNI]
vpdpwssd {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPDPWSSDrr [NoVLX_Or_NoVNNI, HasAVXVNNI]
vpdpwssd {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
SHA1MSG1rm [HasSHA]
sha1msg1 {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
SHA1MSG1rr [HasSHA]
sha1msg1 {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
SHA1MSG2rm [HasSHA]
sha1msg2 {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
SHA1MSG2rr [HasSHA]
sha1msg2 {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
SHA1NEXTErm [HasSHA]
sha1nexte {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
SHA1NEXTErr [HasSHA]
sha1nexte {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
SHA1RNDS4rmi [HasSHA]
sha1rnds4 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
SHA1RNDS4rri [HasSHA]
sha1rnds4 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
SHA256MSG1rm [HasSHA]
sha256msg1 {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
SHA256MSG1rr [HasSHA]
sha256msg1 {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
SHA256MSG2rm [HasSHA]
sha256msg2 {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
SHA256MSG2rr [HasSHA]
sha256msg2 {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
SHA256RNDS2rm [HasSHA]
sha256rnds2 {%xmm0, src2, dst|dst, src2, xmm0}
|
Note
|
Constraints: src1 = dst |
SHA256RNDS2rr [HasSHA]
sha256rnds2 {%xmm0, src2, dst|dst, src2, xmm0}
|
Note
|
Constraints: src1 = dst |
PCLMULQDQrmi [NoAVX, HasPCLMUL]
pclmulqdq {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
PCLMULQDQrri [NoAVX, HasPCLMUL]
pclmulqdq {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
LLWPCB [HasLWP]
llwpcb src
LLWPCB64 [HasLWP]
llwpcb src
LWPINS32rmi [HasLWP]
lwpins {cntl, src1, src0|src0, src1, cntl}
|
Note
|
Properties: mayLoad |
LWPINS32rri [HasLWP]
lwpins {cntl, src1, src0|src0, src1, cntl}
LWPINS64rmi [HasLWP]
lwpins {cntl, src1, src0|src0, src1, cntl}
|
Note
|
Properties: mayLoad |
LWPINS64rri [HasLWP]
lwpins {cntl, src1, src0|src0, src1, cntl}
LWPVAL32rmi [HasLWP]
lwpval {cntl, src1, src0|src0, src1, cntl}
|
Note
|
Properties: mayLoad |
LWPVAL32rri [HasLWP]
lwpval {cntl, src1, src0|src0, src1, cntl}
LWPVAL64rmi [HasLWP]
lwpval {cntl, src1, src0|src0, src1, cntl}
|
Note
|
Properties: mayLoad |
LWPVAL64rri [HasLWP]
lwpval {cntl, src1, src0|src0, src1, cntl}
LZCNT16rm [HasLZCNT]
lzcnt{w} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
LZCNT16rm_EVEX [HasLZCNT]
lzcnt{w} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
LZCNT16rr [HasLZCNT]
lzcnt{w} {src1, dst|dst, src1}
LZCNT16rr_EVEX [HasLZCNT]
lzcnt{w} {src1, dst|dst, src1}
LZCNT32rm [HasLZCNT]
lzcnt{l} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
LZCNT32rm_EVEX [HasLZCNT]
lzcnt{l} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
LZCNT32rr [HasLZCNT]
lzcnt{l} {src1, dst|dst, src1}
LZCNT32rr_EVEX [HasLZCNT]
lzcnt{l} {src1, dst|dst, src1}
LZCNT64rm [HasLZCNT]
lzcnt{q} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
LZCNT64rm_EVEX [HasLZCNT]
lzcnt{q} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
LZCNT64rr [HasLZCNT]
lzcnt{q} {src1, dst|dst, src1}
LZCNT64rr_EVEX [HasLZCNT]
lzcnt{q} {src1, dst|dst, src1}
POPCNT16rm [HasPOPCNT]
popcnt{w} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
POPCNT16rm_EVEX [HasPOPCNT]
popcnt{w} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
POPCNT16rr [HasPOPCNT]
popcnt{w} {src1, dst|dst, src1}
POPCNT16rr_EVEX [HasPOPCNT]
popcnt{w} {src1, dst|dst, src1}
POPCNT32rm [HasPOPCNT]
popcnt{l} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
POPCNT32rm_EVEX [HasPOPCNT]
popcnt{l} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
POPCNT32rr [HasPOPCNT]
popcnt{l} {src1, dst|dst, src1}
POPCNT32rr_EVEX [HasPOPCNT]
popcnt{l} {src1, dst|dst, src1}
POPCNT64rm [HasPOPCNT]
popcnt{q} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
POPCNT64rm_EVEX [HasPOPCNT]
popcnt{q} {src1, dst|dst, src1}
|
Note
|
Properties: mayLoad |
POPCNT64rr [HasPOPCNT]
popcnt{q} {src1, dst|dst, src1}
POPCNT64rr_EVEX [HasPOPCNT]
popcnt{q} {src1, dst|dst, src1}
SLWPCB [HasLWP]
slwpcb dst
SLWPCB64 [HasLWP]
slwpcb dst
PCMPESTRIrmi [UseSSE42]
pcmpestri {src5, src3, src1|src1, src3, src5}
|
Note
|
Properties: mayLoad |
PCMPESTRIrri [UseSSE42]
pcmpestri {src5, src3, src1|src1, src3, src5}
PCMPESTRMrmi [UseSSE42]
pcmpestrm {src5, src3, src1|src1, src3, src5}
|
Note
|
Properties: mayLoad |
PCMPESTRMrri [UseSSE42]
pcmpestrm {src5, src3, src1|src1, src3, src5}
PCMPGTQrm [UseSSE42]
pcmpgtq {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PCMPGTQrr [UseSSE42]
pcmpgtq {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
PCMPISTRIrmi [UseSSE42]
pcmpistri {src3, src2, src1|src1, src2, src3}
|
Note
|
Properties: mayLoad |
PCMPISTRIrri [UseSSE42]
pcmpistri {src3, src2, src1|src1, src2, src3}
PCMPISTRMrmi [UseSSE42]
pcmpistrm {src3, src2, src1|src1, src2, src3}
|
Note
|
Properties: mayLoad |
PCMPISTRMrri [UseSSE42]
pcmpistrm {src3, src2, src1|src1, src2, src3}
CMOVBE_F [HasCMOV]
fcmovbe {op, %st|st, op}
CMOVB_F [HasCMOV]
fcmovb {op, %st|st, op}
CMOVE_F [HasCMOV]
fcmove {op, %st|st, op}
CMOVNBE_F [HasCMOV]
fcmovnbe {op, %st|st, op}
CMOVNB_F [HasCMOV]
fcmovnb {op, %st|st, op}
CMOVNE_F [HasCMOV]
fcmovne {op, %st|st, op}
CMOVNP_F [HasCMOV]
fcmovnu {op, %st|st, op}
CMOVP_F [HasCMOV]
fcmovu {op, %st|st, op}
VPMADD52HUQYrm [NoVLX_Or_NoIFMA, HasAVXIFMA]
vpmadd52huq {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPMADD52HUQYrr [NoVLX_Or_NoIFMA, HasAVXIFMA]
vpmadd52huq {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPMADD52HUQrm [NoVLX_Or_NoIFMA, HasAVXIFMA]
vpmadd52huq {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPMADD52HUQrr [NoVLX_Or_NoIFMA, HasAVXIFMA]
vpmadd52huq {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPMADD52LUQYrm [NoVLX_Or_NoIFMA, HasAVXIFMA]
vpmadd52luq {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPMADD52LUQYrr [NoVLX_Or_NoIFMA, HasAVXIFMA]
vpmadd52luq {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPMADD52LUQrm [NoVLX_Or_NoIFMA, HasAVXIFMA]
vpmadd52luq {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VPMADD52LUQrr [NoVLX_Or_NoIFMA, HasAVXIFMA]
vpmadd52luq {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
AESDEC128KL [HasKL]
aesdec128kl {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
AESDEC256KL [HasKL]
aesdec256kl {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
AESENC128KL [HasKL]
aesenc128kl {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
AESENC256KL [HasKL]
aesenc256kl {src2, src1|src1, src2}
|
Note
|
Constraints: src1 = dst |
ENCODEKEY128 [HasKL]
encodekey128 {src, dst|dst, src}
ENCODEKEY256 [HasKL]
encodekey256 {src, dst|dst, src}
LOADIWKEY [HasKL]
loadiwkey {src2, src1|src1, src2}
EXTRQ [HasSSE4A]
extrq {mask, src|src, mask}
|
Note
|
Constraints: src = dst |
EXTRQI [HasSSE4A]
extrq {idx, len, src|src, len, idx}
|
Note
|
Constraints: src = dst |
INSERTQ [HasSSE4A]
insertq {mask, src|src, mask}
|
Note
|
Constraints: src = dst |
INSERTQI [HasSSE4A]
insertq {idx, len, src2, src|src, src2, len, idx}
|
Note
|
Constraints: src = dst |
MOVNTSD [HasSSE4A]
movntsd {src, dst|dst, src}
|
Note
|
Properties: mayStore |
MOVNTSS [HasSSE4A]
movntss {src, dst|dst, src}
|
Note
|
Properties: mayStore |
VSM3MSG1rm [HasSM3]
vsm3msg1 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VSM3MSG1rr [HasSM3]
vsm3msg1 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VSM3MSG2rm [HasSM3]
vsm3msg2 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VSM3MSG2rr [HasSM3]
vsm3msg2 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
VSM3RNDS2rmi [HasSM3]
vsm3rnds2 {src4, src3, src2, dst|dst, src2, src3, src4}
|
Note
|
Constraints: src1 = dst |
VSM3RNDS2rri [HasSM3]
vsm3rnds2 {src4, src3, src2, dst|dst, src2, src3, src4}
|
Note
|
Constraints: src1 = dst |
TPAUSE [HasWAITPKG]
tpause src
UMONITOR32 [HasWAITPKG]
umonitor src
UMWAIT [HasWAITPKG]
umwait src
XRSTOR [HasXSAVE]
xrstor dst
XSAVE [HasXSAVE]
xsave dst
AESDECWIDE128KL [HasWIDEKL]
aesdecwide128kl src
|
Note
|
Properties: mayLoad |
AESDECWIDE256KL [HasWIDEKL]
aesdecwide256kl src
|
Note
|
Properties: mayLoad |
AESENCWIDE128KL [HasWIDEKL]
aesencwide128kl src
|
Note
|
Properties: mayLoad |
AESENCWIDE256KL [HasWIDEKL]
aesencwide256kl src
|
Note
|
Properties: mayLoad |
FXRSTOR [HasFXSR]
fxrstor src
FXSAVE [HasFXSR]
fxsave dst
PREFETCHNTA [HasSSEPrefetch]
prefetchnta src
PREFETCHT0 [HasSSEPrefetch]
prefetcht0 src
PREFETCHT1 [HasSSEPrefetch]
prefetcht1 src
PREFETCHT2 [HasSSEPrefetch]
prefetcht2 src
PTWRITEm [HasPTWRITE]
ptwrite{l} dst
PTWRITEr [HasPTWRITE]
ptwrite{l} dst
ENCLS [HasSGX]
encls
ENCLU [HasSGX]
enclu
ENCLV [HasSGX]
enclv
MWAITXrrr [HasMWAITX]
mwaitx
MWAITrr [HasSSE3]
mwait
RDRAND16r [HasRDRAND]
rdrand{w} dst
RDRAND32r [HasRDRAND]
rdrand{l} dst
RDRAND64r [HasRDRAND]
rdrand{q} dst
RDSEED16r [HasRDSEED]
rdseed{w} dst
RDSEED32r [HasRDSEED]
rdseed{l} dst
RDSEED64r [HasRDSEED]
rdseed{q} dst
VSHA512MSG1rr [HasSHA512]
vsha512msg1 {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
VSHA512MSG2rr [HasSHA512]
vsha512msg2 {src2, dst|dst, src2}
|
Note
|
Constraints: src1 = dst |
VSHA512RNDS2rr [HasSHA512]
vsha512rnds2 {src3, src2, dst|dst, src2, src3}
|
Note
|
Constraints: src1 = dst |
XABORT [HasRTM]
xabort imm
XEND [HasRTM]
xend
XRSTORS [HasXSAVES]
xrstors dst
XSAVES [HasXSAVES]
xsaves dst
XTEST [HasRTM]
xtest
BSWAP32r [NoNDD_Or_NoMOVBE]
bswap{l} dst
|
Note
|
Constraints: src = dst |
BSWAP64r [NoNDD_Or_NoMOVBE]
bswap{q} dst
|
Note
|
Constraints: src = dst |
LAHF [HasLAHFSAHF]
lahf
SAHF [HasLAHFSAHF]
sahf
XRESLDTRK [HasTSXLDTRK]
xresldtrk
XSAVEC [HasXSAVEC]
xsavec dst
XSAVEOPT [HasXSAVEOPT]
xsaveopt dst
XSUSLDTRK [HasTSXLDTRK]
xsusldtrk
ADDR16_PREFIX [In32BitMode]
addr16
CLDEMOTE [HasCLDEMOTE]
cldemote src
CLFLUSH [HasCLFLUSH]
clflush src
CLFLUSHOPT [HasCLFLUSHOPT]
clflushopt src
CLWB [HasCLWB]
clwb src
CMPXCHG8B [HasCX8]
cmpxchg8b dst
|
Note
|
Properties: mayLoad, mayStore |
HRESET [HasHRESET]
hreset imm
MFENCE [HasMFence]
mfence
PCONFIG [HasPCONFIG]
pconfig
PREFETCHW [HasPrefetchW]
prefetchw addr
|
Note
|
Properties: mayLoad, mayStore |
RDPRU [HasRDPRU]
rdpru
SERIALIZE [HasSERIALIZE]
serialize
WBNOINVD [HasWBNOINVD]
wbnoinvd