BPF Target

ADDR_SPACE_CAST

dst = addr_space_cast(src, dst_as, src_as)

ADD_ri

dst += imm

Note	Properties: isAsCheapAsAMove

Note	Constraints: dst = src2

ADD_ri_32

dst += imm

Note	Properties: isAsCheapAsAMove

Note	Constraints: dst = src2

ADD_rr

dst += src

Note	Properties: isAsCheapAsAMove

Note	Constraints: dst = src2

ADD_rr_32

dst += src

Note	Properties: isAsCheapAsAMove

Note	Constraints: dst = src2

AND_ri

dst &= imm

Note	Properties: isAsCheapAsAMove

Note	Constraints: dst = src2

AND_ri_32

dst &= imm

Note	Properties: isAsCheapAsAMove

Note	Constraints: dst = src2

AND_rr

dst &= src

Note	Properties: isAsCheapAsAMove

Note	Constraints: dst = src2

AND_rr_32

dst &= src

Note	Properties: isAsCheapAsAMove

Note	Constraints: dst = src2

CMPXCHGD

r0 = cmpxchg_64(addr, r0, new)

DIV_ri

dst /= imm

Note	Constraints: dst = src2

DIV_ri_32

dst /= imm

Note	Constraints: dst = src2

DIV_rr

dst /= src

Note	Constraints: dst = src2

DIV_rr_32

dst /= src

Note	Constraints: dst = src2

JAL

call BrDst

Note	Properties: isCall

JALX

callx BrDst

Note	Properties: isCall

JCOND

may_goto BrDst

Note	Properties: isBranch, isTerminator

JEQ_ri

if dst == imm goto BrDst

Note	Properties: isBranch, isTerminator

JEQ_ri_32

if dst == imm goto BrDst

Note	Properties: isBranch, isTerminator

JEQ_rr

if dst == src goto BrDst

Note	Properties: isBranch, isTerminator

JEQ_rr_32

if dst == src goto BrDst

Note	Properties: isBranch, isTerminator

JMP

goto BrDst

Note	Properties: isBarrier, isBranch, isTerminator

JMPL

gotol BrDst

Note	Properties: isBarrier, isBranch, isTerminator

JNE_ri

if dst != imm goto BrDst

Note	Properties: isBranch, isTerminator

JNE_ri_32

if dst != imm goto BrDst

Note	Properties: isBranch, isTerminator

JNE_rr

if dst != src goto BrDst

Note	Properties: isBranch, isTerminator

JNE_rr_32

if dst != src goto BrDst

Note	Properties: isBranch, isTerminator

JSET_ri

if dst & imm goto BrDst

Note	Properties: isBranch, isTerminator

JSET_ri_32

if dst & imm goto BrDst

Note	Properties: isBranch, isTerminator

JSET_rr

if dst & src goto BrDst

Note	Properties: isBranch, isTerminator

JSET_rr_32

if dst & src goto BrDst

Note	Properties: isBranch, isTerminator

JSGE_ri

if dst s>= imm goto BrDst

Note	Properties: isBranch, isTerminator

JSGE_ri_32

if dst s>= imm goto BrDst

Note	Properties: isBranch, isTerminator

JSGE_rr

if dst s>= src goto BrDst

Note	Properties: isBranch, isTerminator

JSGE_rr_32

if dst s>= src goto BrDst

Note	Properties: isBranch, isTerminator

JSGT_ri

if dst s> imm goto BrDst

Note	Properties: isBranch, isTerminator

JSGT_ri_32

if dst s> imm goto BrDst

Note	Properties: isBranch, isTerminator

JSGT_rr

if dst s> src goto BrDst

Note	Properties: isBranch, isTerminator

JSGT_rr_32

if dst s> src goto BrDst

Note	Properties: isBranch, isTerminator

JSLE_ri

if dst s<= imm goto BrDst

Note	Properties: isBranch, isTerminator

JSLE_ri_32

if dst s<= imm goto BrDst

Note	Properties: isBranch, isTerminator

JSLE_rr

if dst s<= src goto BrDst

Note	Properties: isBranch, isTerminator

JSLE_rr_32

if dst s<= src goto BrDst

Note	Properties: isBranch, isTerminator

JSLT_ri

if dst s< imm goto BrDst

Note	Properties: isBranch, isTerminator

JSLT_ri_32

if dst s< imm goto BrDst

Note	Properties: isBranch, isTerminator

JSLT_rr

if dst s< src goto BrDst

Note	Properties: isBranch, isTerminator

JSLT_rr_32

if dst s< src goto BrDst

Note	Properties: isBranch, isTerminator

JUGE_ri

if dst >= imm goto BrDst

Note	Properties: isBranch, isTerminator

JUGE_ri_32

if dst >= imm goto BrDst

Note	Properties: isBranch, isTerminator

JUGE_rr

if dst >= src goto BrDst

Note	Properties: isBranch, isTerminator

JUGE_rr_32

if dst >= src goto BrDst

Note	Properties: isBranch, isTerminator

JUGT_ri

if dst > imm goto BrDst

Note	Properties: isBranch, isTerminator

JUGT_ri_32

if dst > imm goto BrDst

Note	Properties: isBranch, isTerminator

JUGT_rr

if dst > src goto BrDst

Note	Properties: isBranch, isTerminator

JUGT_rr_32

if dst > src goto BrDst

Note	Properties: isBranch, isTerminator

JULE_ri

if dst <= imm goto BrDst

Note	Properties: isBranch, isTerminator

JULE_ri_32

if dst <= imm goto BrDst

Note	Properties: isBranch, isTerminator

JULE_rr

if dst <= src goto BrDst

Note	Properties: isBranch, isTerminator

JULE_rr_32

if dst <= src goto BrDst

Note	Properties: isBranch, isTerminator

JULT_ri

if dst < imm goto BrDst

Note	Properties: isBranch, isTerminator

JULT_ri_32

if dst < imm goto BrDst

Note	Properties: isBranch, isTerminator

JULT_rr

if dst < src goto BrDst

Note	Properties: isBranch, isTerminator

JULT_rr_32

if dst < src goto BrDst

Note	Properties: isBranch, isTerminator

LDD

dst = *(u64 *)(addr)

LD_ABS_B

r0 = *(u8 *)skb[imm]

Note	Properties: hasSideEffects, mayLoad

LD_ABS_H

r0 = *(u16 *)skb[imm]

Note	Properties: hasSideEffects, mayLoad

LD_ABS_W

r0 = *(u32 *)skb[imm]

Note	Properties: hasSideEffects, mayLoad

LD_IND_B

r0 = *(u8 *)skb[val]

Note	Properties: hasSideEffects, mayLoad

LD_IND_H

r0 = *(u16 *)skb[val]

Note	Properties: hasSideEffects, mayLoad

LD_IND_W

r0 = *(u32 *)skb[val]

Note	Properties: hasSideEffects, mayLoad

LD_imm64

dst = imm ll

Note	Properties: isAsCheapAsAMove

LD_pseudo

ld_pseudo	dst, pseudo, imm

MOD_ri

dst %= imm

Note	Constraints: dst = src2

MOD_ri_32

dst %= imm

Note	Constraints: dst = src2

MOD_rr

dst %= src

Note	Constraints: dst = src2

MOD_rr_32

dst %= src

Note	Constraints: dst = src2

MOV_ri

dst = imm

Note	Properties: isAsCheapAsAMove

MOV_ri_32

dst = imm

Note	Properties: isAsCheapAsAMove

MOV_rr

dst = src

Note	Properties: isAsCheapAsAMove

MOV_rr_32

dst = src

Note	Properties: isAsCheapAsAMove

MUL_ri

dst *= imm

Note	Constraints: dst = src2

MUL_ri_32

dst *= imm

Note	Constraints: dst = src2

MUL_rr

dst *= src

Note	Constraints: dst = src2

MUL_rr_32

dst *= src

Note	Constraints: dst = src2

NEG_32

dst = -src

Note	Properties: isAsCheapAsAMove

Note	Constraints: dst = src

NEG_64

dst = -src

Note	Properties: isAsCheapAsAMove

Note	Constraints: dst = src

OR_ri

dst |= imm

Note	Properties: isAsCheapAsAMove

Note	Constraints: dst = src2

OR_ri_32

dst |= imm

Note	Properties: isAsCheapAsAMove

Note	Constraints: dst = src2

OR_rr

dst |= src

Note	Properties: isAsCheapAsAMove

Note	Constraints: dst = src2

OR_rr_32

dst |= src

Note	Properties: isAsCheapAsAMove

Note	Constraints: dst = src2

RET

exit

Note	Properties: isBarrier, isNotDuplicable, isReturn, isTerminator

SLL_ri

dst <<= imm

Note	Properties: isAsCheapAsAMove

Note	Constraints: dst = src2

SLL_ri_32

dst <<= imm

Note	Properties: isAsCheapAsAMove

Note	Constraints: dst = src2

SLL_rr

dst <<= src

Note	Properties: isAsCheapAsAMove

Note	Constraints: dst = src2

SLL_rr_32

dst <<= src

Note	Properties: isAsCheapAsAMove

Note	Constraints: dst = src2

SRA_ri

dst s>>= imm

Note	Properties: isAsCheapAsAMove

Note	Constraints: dst = src2

SRA_ri_32

dst s>>= imm

Note	Properties: isAsCheapAsAMove

Note	Constraints: dst = src2

SRA_rr

dst s>>= src

Note	Properties: isAsCheapAsAMove

Note	Constraints: dst = src2

SRA_rr_32

dst s>>= src

Note	Properties: isAsCheapAsAMove

Note	Constraints: dst = src2

SRL_ri

dst >>= imm

Note	Properties: isAsCheapAsAMove

Note	Constraints: dst = src2

SRL_ri_32

dst >>= imm

Note	Properties: isAsCheapAsAMove

Note	Constraints: dst = src2

SRL_rr

dst >>= src

Note	Properties: isAsCheapAsAMove

Note	Constraints: dst = src2

SRL_rr_32

dst >>= src

Note	Properties: isAsCheapAsAMove

Note	Constraints: dst = src2

STD

*(u64 *)(addr) = src

SUB_ri

dst -= imm

Note	Properties: isAsCheapAsAMove

Note	Constraints: dst = src2

SUB_ri_32

dst -= imm

Note	Properties: isAsCheapAsAMove

Note	Constraints: dst = src2

SUB_rr

dst -= src

Note	Properties: isAsCheapAsAMove

Note	Constraints: dst = src2

SUB_rr_32

dst -= src

Note	Properties: isAsCheapAsAMove

Note	Constraints: dst = src2

XADDD

lock *(u64 *)(addr) += val

Note	Constraints: dst = val

XADDW

lock *(u32 *)(addr) += val

Note	Constraints: dst = val

XANDD

lock *(u64 *)(addr) &= val

Note	Constraints: dst = val

XCHGD

dst = xchg_64(addr, val)

Note	Constraints: dst = val

XFANDD

dst = atomic_fetch_and((u64 *)(addr), val)

Note	Constraints: dst = val

XFORD

dst = atomic_fetch_or((u64 *)(addr), val)

Note	Constraints: dst = val

XFXORD

dst = atomic_fetch_xor((u64 *)(addr), val)

Note	Constraints: dst = val

XORD

lock *(u64 *)(addr) |= val

Note	Constraints: dst = val

XOR_ri

dst ^= imm

Note	Properties: isAsCheapAsAMove

Note	Constraints: dst = src2

XOR_ri_32

dst ^= imm

Note	Properties: isAsCheapAsAMove

Note	Constraints: dst = src2

XOR_rr

dst ^= src

Note	Properties: isAsCheapAsAMove

Note	Constraints: dst = src2

XOR_rr_32

dst ^= src

Note	Properties: isAsCheapAsAMove

Note	Constraints: dst = src2

XXORD

lock *(u64 *)(addr) ^= val

Note	Constraints: dst = val

CMPXCHGW32 [BPFHasALU32]

w0 = cmpxchg32_32(addr, w0, new)

LDB32 [BPFHasALU32]

dst = *(u8 *)(addr)

LDH32 [BPFHasALU32]

dst = *(u16 *)(addr)

LDW32 [BPFHasALU32]

dst = *(u32 *)(addr)

STB32 [BPFHasALU32]

*(u8 *)(addr) = src

STH32 [BPFHasALU32]

*(u16 *)(addr) = src

STW32 [BPFHasALU32]

*(u32 *)(addr) = src

XADDW32 [BPFHasALU32]

lock *(u32 *)(addr) += val

Note	Constraints: dst = val

XANDW32 [BPFHasALU32]

lock *(u32 *)(addr) &= val

Note	Constraints: dst = val

XCHGW32 [BPFHasALU32]

dst = xchg32_32(addr, val)

Note	Constraints: dst = val

XFADDD [BPFHasALU32]

dst = atomic_fetch_add((u64 *)(addr), val)

Note	Constraints: dst = val

XFADDW32 [BPFHasALU32]

dst = atomic_fetch_add((u32 *)(addr), val)

Note	Constraints: dst = val

XFANDW32 [BPFHasALU32]

dst = atomic_fetch_and((u32 *)(addr), val)

Note	Constraints: dst = val

XFORW32 [BPFHasALU32]

dst = atomic_fetch_or((u32 *)(addr), val)

Note	Constraints: dst = val

XFXORW32 [BPFHasALU32]

dst = atomic_fetch_xor((u32 *)(addr), val)

Note	Constraints: dst = val

XORW32 [BPFHasALU32]

lock *(u32 *)(addr) |= val

Note	Constraints: dst = val

XXORW32 [BPFHasALU32]

lock *(u32 *)(addr) ^= val

Note	Constraints: dst = val

LDBACQ32 [BPFHasLoadAcqStoreRel]

dst = load_acquire((u8 *)(addr))

LDDACQ [BPFHasLoadAcqStoreRel]

dst = load_acquire((u64 *)(addr))

LDHACQ32 [BPFHasLoadAcqStoreRel]

dst = load_acquire((u16 *)(addr))

LDWACQ32 [BPFHasLoadAcqStoreRel]

dst = load_acquire((u32 *)(addr))

SDIV_ri [BPFHasSdivSmod]

dst s/= imm

Note	Constraints: dst = src2

SDIV_ri_32 [BPFHasSdivSmod]

dst s/= imm

Note	Constraints: dst = src2

SDIV_rr [BPFHasSdivSmod]

dst s/= src

Note	Constraints: dst = src2

SDIV_rr_32 [BPFHasSdivSmod]

dst s/= src

Note	Constraints: dst = src2

SMOD_ri [BPFHasSdivSmod]

dst s%= imm

Note	Constraints: dst = src2

SMOD_ri_32 [BPFHasSdivSmod]

dst s%= imm

Note	Constraints: dst = src2

SMOD_rr [BPFHasSdivSmod]

dst s%= src

Note	Constraints: dst = src2

SMOD_rr_32 [BPFHasSdivSmod]

dst s%= src

Note	Constraints: dst = src2

STBREL32 [BPFHasLoadAcqStoreRel]

store_release((u8 *)(addr), src)

STDREL [BPFHasLoadAcqStoreRel]

store_release((u64 *)(addr), src)

STHREL32 [BPFHasLoadAcqStoreRel]

store_release((u16 *)(addr), src)

STWREL32 [BPFHasLoadAcqStoreRel]

store_release((u32 *)(addr), src)

LDB [BPFNoALU32]

dst = *(u8 *)(addr)

LDH [BPFNoALU32]

dst = *(u16 *)(addr)

LDW [BPFNoALU32]

dst = *(u32 *)(addr)

STB [BPFNoALU32]

*(u8 *)(addr) = src

STH [BPFNoALU32]

*(u16 *)(addr) = src

STW [BPFNoALU32]

*(u32 *)(addr) = src

MOVSX_rr_16 [BPFHasMovsx]

dst = (s16)src

Note	Properties: isAsCheapAsAMove

MOVSX_rr_32 [BPFHasMovsx]

dst = (s32)src

Note	Properties: isAsCheapAsAMove

MOVSX_rr_32_16 [BPFHasMovsx]

dst = (s16)src

Note	Properties: isAsCheapAsAMove

MOVSX_rr_32_8 [BPFHasMovsx]

dst = (s8)src

Note	Properties: isAsCheapAsAMove

MOVSX_rr_8 [BPFHasMovsx]

dst = (s8)src

Note	Properties: isAsCheapAsAMove

STB_imm [BPFHasStoreImm]

*(u8 *)(addr) = imm

STD_imm [BPFHasStoreImm]

*(u64 *)(addr) = imm

STH_imm [BPFHasStoreImm]

*(u16 *)(addr) = imm

STW_imm [BPFHasStoreImm]

*(u32 *)(addr) = imm

BE16 [BPFIsLittleEndian]

dst = be16 src

Note	Constraints: dst = src

BE32 [BPFIsLittleEndian]

dst = be32 src

Note	Constraints: dst = src

BE64 [BPFIsLittleEndian]

dst = be64 src

Note	Constraints: dst = src

BSWAP16 [BPFHasBswap]

dst = bswap16 src

Note	Constraints: dst = src

BSWAP32 [BPFHasBswap]

dst = bswap32 src

Note	Constraints: dst = src

BSWAP64 [BPFHasBswap]

dst = bswap64 src

Note	Constraints: dst = src

LDBSX [BPFHasLdsx]

dst = *(s8 *)(addr)

LDHSX [BPFHasLdsx]

dst = *(s16 *)(addr)

LDWSX [BPFHasLdsx]

dst = *(s32 *)(addr)

LE16 [BPFIsBigEndian]

dst = le16 src

Note	Constraints: dst = src

LE32 [BPFIsBigEndian]

dst = le32 src

Note	Constraints: dst = src

LE64 [BPFIsBigEndian]

dst = le64 src

Note	Constraints: dst = src

BPF Target

Instructions

ADDR_SPACE_CAST

ADD_ri

ADD_ri_32

ADD_rr

ADD_rr_32

AND_ri

AND_ri_32

AND_rr

AND_rr_32

CMPXCHGD

DIV_ri

DIV_ri_32

DIV_rr

DIV_rr_32

JAL

JALX

JCOND

JEQ_ri

JEQ_ri_32

JEQ_rr

JEQ_rr_32

JMP

JMPL

JNE_ri

JNE_ri_32

JNE_rr

JNE_rr_32

JSET_ri

JSET_ri_32

JSET_rr

JSET_rr_32

JSGE_ri

JSGE_ri_32

JSGE_rr

JSGE_rr_32

JSGT_ri

JSGT_ri_32

JSGT_rr

JSGT_rr_32

JSLE_ri

JSLE_ri_32

JSLE_rr

JSLE_rr_32

JSLT_ri

JSLT_ri_32

JSLT_rr

JSLT_rr_32

JUGE_ri

JUGE_ri_32

JUGE_rr

JUGE_rr_32

JUGT_ri

JUGT_ri_32

JUGT_rr

JUGT_rr_32

JULE_ri

JULE_ri_32

JULE_rr

JULE_rr_32

JULT_ri

JULT_ri_32

JULT_rr

JULT_rr_32

LDD

LD_ABS_B

LD_ABS_H

LD_ABS_W

LD_IND_B

LD_IND_H

LD_IND_W

LD_imm64

LD_pseudo

MOD_ri

MOD_ri_32

MOD_rr

MOD_rr_32

MOV_ri

MOV_ri_32